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ivshmem: remove unnecessary dup()
[qemu/ar7.git] / hw / display / vmware_vga.c
blob9354037852d631e636d017c89648b0fd55486ce2
1 /*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/loader.h"
26 #include "trace.h"
27 #include "ui/console.h"
28 #include "ui/vnc.h"
29 #include "hw/pci/pci.h"
30
31 #undef VERBOSE
32 #define HW_RECT_ACCEL
33 #define HW_FILL_ACCEL
34 #define HW_MOUSE_ACCEL
35
36 #include "vga_int.h"
37
38 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
39
40 struct vmsvga_state_s {
41 VGACommonState vga;
42
43 int invalidated;
44 int enable;
45 int config;
46 struct {
47 int id;
48 int x;
49 int y;
50 int on;
51 } cursor;
52
53 int index;
54 int scratch_size;
55 uint32_t *scratch;
56 int new_width;
57 int new_height;
58 int new_depth;
59 uint32_t guest;
60 uint32_t svgaid;
61 int syncing;
62
63 MemoryRegion fifo_ram;
64 uint8_t *fifo_ptr;
65 unsigned int fifo_size;
66
67 union {
68 uint32_t *fifo;
69 struct QEMU_PACKED {
70 uint32_t min;
71 uint32_t max;
72 uint32_t next_cmd;
73 uint32_t stop;
74 /* Add registers here when adding capabilities. */
75 uint32_t fifo[0];
76 } *cmd;
77 };
78
79 #define REDRAW_FIFO_LEN 512
80 struct vmsvga_rect_s {
81 int x, y, w, h;
82 } redraw_fifo[REDRAW_FIFO_LEN];
83 int redraw_fifo_first, redraw_fifo_last;
84 };
85
86 #define TYPE_VMWARE_SVGA "vmware-svga"
87
88 #define VMWARE_SVGA(obj) \
89 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
90
91 struct pci_vmsvga_state_s {
92 /*< private >*/
93 PCIDevice parent_obj;
94 /*< public >*/
95
96 struct vmsvga_state_s chip;
97 MemoryRegion io_bar;
98 };
99
100 #define SVGA_MAGIC 0x900000UL
101 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
102 #define SVGA_ID_0 SVGA_MAKE_ID(0)
103 #define SVGA_ID_1 SVGA_MAKE_ID(1)
104 #define SVGA_ID_2 SVGA_MAKE_ID(2)
105
106 #define SVGA_LEGACY_BASE_PORT 0x4560
107 #define SVGA_INDEX_PORT 0x0
108 #define SVGA_VALUE_PORT 0x1
109 #define SVGA_BIOS_PORT 0x2
110
111 #define SVGA_VERSION_2
112
113 #ifdef SVGA_VERSION_2
114 # define SVGA_ID SVGA_ID_2
115 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
116 # define SVGA_IO_MUL 1
117 # define SVGA_FIFO_SIZE 0x10000
118 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
119 #else
120 # define SVGA_ID SVGA_ID_1
121 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
122 # define SVGA_IO_MUL 4
123 # define SVGA_FIFO_SIZE 0x10000
124 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
125 #endif
126
127 enum {
128 /* ID 0, 1 and 2 registers */
129 SVGA_REG_ID = 0,
130 SVGA_REG_ENABLE = 1,
131 SVGA_REG_WIDTH = 2,
132 SVGA_REG_HEIGHT = 3,
133 SVGA_REG_MAX_WIDTH = 4,
134 SVGA_REG_MAX_HEIGHT = 5,
135 SVGA_REG_DEPTH = 6,
136 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
137 SVGA_REG_PSEUDOCOLOR = 8,
138 SVGA_REG_RED_MASK = 9,
139 SVGA_REG_GREEN_MASK = 10,
140 SVGA_REG_BLUE_MASK = 11,
141 SVGA_REG_BYTES_PER_LINE = 12,
142 SVGA_REG_FB_START = 13,
143 SVGA_REG_FB_OFFSET = 14,
144 SVGA_REG_VRAM_SIZE = 15,
145 SVGA_REG_FB_SIZE = 16,
146
147 /* ID 1 and 2 registers */
148 SVGA_REG_CAPABILITIES = 17,
149 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
150 SVGA_REG_MEM_SIZE = 19,
151 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
152 SVGA_REG_SYNC = 21, /* Write to force synchronization */
153 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
154 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
155 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
156 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
157 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
158 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
159 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
160 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
161 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
162 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
163 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
164
165 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
166 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
167 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
168 };
169
170 #define SVGA_CAP_NONE 0
171 #define SVGA_CAP_RECT_FILL (1 << 0)
172 #define SVGA_CAP_RECT_COPY (1 << 1)
173 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
174 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
175 #define SVGA_CAP_RASTER_OP (1 << 4)
176 #define SVGA_CAP_CURSOR (1 << 5)
177 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
178 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
179 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
180 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
181 #define SVGA_CAP_GLYPH (1 << 10)
182 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
183 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
184 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
185 #define SVGA_CAP_3D (1 << 14)
186 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
187 #define SVGA_CAP_MULTIMON (1 << 16)
188 #define SVGA_CAP_PITCHLOCK (1 << 17)
189
190 /*
191 * FIFO offsets (seen as an array of 32-bit words)
192 */
193 enum {
194 /*
195 * The original defined FIFO offsets
196 */
197 SVGA_FIFO_MIN = 0,
198 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
199 SVGA_FIFO_NEXT_CMD,
200 SVGA_FIFO_STOP,
201
202 /*
203 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
204 */
205 SVGA_FIFO_CAPABILITIES = 4,
206 SVGA_FIFO_FLAGS,
207 SVGA_FIFO_FENCE,
208 SVGA_FIFO_3D_HWVERSION,
209 SVGA_FIFO_PITCHLOCK,
210 };
211
212 #define SVGA_FIFO_CAP_NONE 0
213 #define SVGA_FIFO_CAP_FENCE (1 << 0)
214 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
215 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
216
217 #define SVGA_FIFO_FLAG_NONE 0
218 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
219
220 /* These values can probably be changed arbitrarily. */
221 #define SVGA_SCRATCH_SIZE 0x8000
222 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT)
223 #define SVGA_MAX_HEIGHT 1770
224
225 #ifdef VERBOSE
226 # define GUEST_OS_BASE 0x5001
227 static const char *vmsvga_guest_id[] = {
228 [0x00] = "Dos",
229 [0x01] = "Windows 3.1",
230 [0x02] = "Windows 95",
231 [0x03] = "Windows 98",
232 [0x04] = "Windows ME",
233 [0x05] = "Windows NT",
234 [0x06] = "Windows 2000",
235 [0x07] = "Linux",
236 [0x08] = "OS/2",
237 [0x09] = "an unknown OS",
238 [0x0a] = "BSD",
239 [0x0b] = "Whistler",
240 [0x0c] = "an unknown OS",
241 [0x0d] = "an unknown OS",
242 [0x0e] = "an unknown OS",
243 [0x0f] = "an unknown OS",
244 [0x10] = "an unknown OS",
245 [0x11] = "an unknown OS",
246 [0x12] = "an unknown OS",
247 [0x13] = "an unknown OS",
248 [0x14] = "an unknown OS",
249 [0x15] = "Windows 2003",
250 };
251 #endif
252
253 enum {
254 SVGA_CMD_INVALID_CMD = 0,
255 SVGA_CMD_UPDATE = 1,
256 SVGA_CMD_RECT_FILL = 2,
257 SVGA_CMD_RECT_COPY = 3,
258 SVGA_CMD_DEFINE_BITMAP = 4,
259 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
260 SVGA_CMD_DEFINE_PIXMAP = 6,
261 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
262 SVGA_CMD_RECT_BITMAP_FILL = 8,
263 SVGA_CMD_RECT_PIXMAP_FILL = 9,
264 SVGA_CMD_RECT_BITMAP_COPY = 10,
265 SVGA_CMD_RECT_PIXMAP_COPY = 11,
266 SVGA_CMD_FREE_OBJECT = 12,
267 SVGA_CMD_RECT_ROP_FILL = 13,
268 SVGA_CMD_RECT_ROP_COPY = 14,
269 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
270 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
271 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
272 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
273 SVGA_CMD_DEFINE_CURSOR = 19,
274 SVGA_CMD_DISPLAY_CURSOR = 20,
275 SVGA_CMD_MOVE_CURSOR = 21,
276 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
277 SVGA_CMD_DRAW_GLYPH = 23,
278 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
279 SVGA_CMD_UPDATE_VERBOSE = 25,
280 SVGA_CMD_SURFACE_FILL = 26,
281 SVGA_CMD_SURFACE_COPY = 27,
282 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
283 SVGA_CMD_FRONT_ROP_FILL = 29,
284 SVGA_CMD_FENCE = 30,
285 };
286
287 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
288 enum {
289 SVGA_CURSOR_ON_HIDE = 0,
290 SVGA_CURSOR_ON_SHOW = 1,
291 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
292 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
293 };
294
295 static inline bool vmsvga_verify_rect(DisplaySurface *surface,
296 const char *name,
297 int x, int y, int w, int h)
298 {
299 if (x < 0) {
300 fprintf(stderr, "%s: x was < 0 (%d)\n", name, x);
301 return false;
302 }
303 if (x > SVGA_MAX_WIDTH) {
304 fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x);
305 return false;
306 }
307 if (w < 0) {
308 fprintf(stderr, "%s: w was < 0 (%d)\n", name, w);
309 return false;
310 }
311 if (w > SVGA_MAX_WIDTH) {
312 fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w);
313 return false;
314 }
315 if (x + w > surface_width(surface)) {
316 fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n",
317 name, surface_width(surface), x, w);
318 return false;
319 }
320
321 if (y < 0) {
322 fprintf(stderr, "%s: y was < 0 (%d)\n", name, y);
323 return false;
324 }
325 if (y > SVGA_MAX_HEIGHT) {
326 fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y);
327 return false;
328 }
329 if (h < 0) {
330 fprintf(stderr, "%s: h was < 0 (%d)\n", name, h);
331 return false;
332 }
333 if (h > SVGA_MAX_HEIGHT) {
334 fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h);
335 return false;
336 }
337 if (y + h > surface_height(surface)) {
338 fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n",
339 name, surface_height(surface), y, h);
340 return false;
341 }
342
343 return true;
344 }
345
346 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
347 int x, int y, int w, int h)
348 {
349 DisplaySurface *surface = qemu_console_surface(s->vga.con);
350 int line;
351 int bypl;
352 int width;
353 int start;
354 uint8_t *src;
355 uint8_t *dst;
356
357 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
358 /* go for a fullscreen update as fallback */
359 x = 0;
360 y = 0;
361 w = surface_width(surface);
362 h = surface_height(surface);
363 }
364
365 bypl = surface_stride(surface);
366 width = surface_bytes_per_pixel(surface) * w;
367 start = surface_bytes_per_pixel(surface) * x + bypl * y;
368 src = s->vga.vram_ptr + start;
369 dst = surface_data(surface) + start;
370
371 for (line = h; line > 0; line--, src += bypl, dst += bypl) {
372 memcpy(dst, src, width);
373 }
374 dpy_gfx_update(s->vga.con, x, y, w, h);
375 }
376
377 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
378 int x, int y, int w, int h)
379 {
380 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
381
382 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
383 rect->x = x;
384 rect->y = y;
385 rect->w = w;
386 rect->h = h;
387 }
388
389 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
390 {
391 struct vmsvga_rect_s *rect;
392
393 if (s->invalidated) {
394 s->redraw_fifo_first = s->redraw_fifo_last;
395 return;
396 }
397 /* Overlapping region updates can be optimised out here - if someone
398 * knows a smart algorithm to do that, please share. */
399 while (s->redraw_fifo_first != s->redraw_fifo_last) {
400 rect = &s->redraw_fifo[s->redraw_fifo_first++];
401 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
402 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
403 }
404 }
405
406 #ifdef HW_RECT_ACCEL
407 static inline int vmsvga_copy_rect(struct vmsvga_state_s *s,
408 int x0, int y0, int x1, int y1, int w, int h)
409 {
410 DisplaySurface *surface = qemu_console_surface(s->vga.con);
411 uint8_t *vram = s->vga.vram_ptr;
412 int bypl = surface_stride(surface);
413 int bypp = surface_bytes_per_pixel(surface);
414 int width = bypp * w;
415 int line = h;
416 uint8_t *ptr[2];
417
418 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) {
419 return -1;
420 }
421 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) {
422 return -1;
423 }
424
425 if (y1 > y0) {
426 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
427 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
428 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
429 memmove(ptr[1], ptr[0], width);
430 }
431 } else {
432 ptr[0] = vram + bypp * x0 + bypl * y0;
433 ptr[1] = vram + bypp * x1 + bypl * y1;
434 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
435 memmove(ptr[1], ptr[0], width);
436 }
437 }
438
439 vmsvga_update_rect_delayed(s, x1, y1, w, h);
440 return 0;
441 }
442 #endif
443
444 #ifdef HW_FILL_ACCEL
445 static inline int vmsvga_fill_rect(struct vmsvga_state_s *s,
446 uint32_t c, int x, int y, int w, int h)
447 {
448 DisplaySurface *surface = qemu_console_surface(s->vga.con);
449 int bypl = surface_stride(surface);
450 int width = surface_bytes_per_pixel(surface) * w;
451 int line = h;
452 int column;
453 uint8_t *fst;
454 uint8_t *dst;
455 uint8_t *src;
456 uint8_t col[4];
457
458 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
459 return -1;
460 }
461
462 col[0] = c;
463 col[1] = c >> 8;
464 col[2] = c >> 16;
465 col[3] = c >> 24;
466
467 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
468
469 if (line--) {
470 dst = fst;
471 src = col;
472 for (column = width; column > 0; column--) {
473 *(dst++) = *(src++);
474 if (src - col == surface_bytes_per_pixel(surface)) {
475 src = col;
476 }
477 }
478 dst = fst;
479 for (; line > 0; line--) {
480 dst += bypl;
481 memcpy(dst, fst, width);
482 }
483 }
484
485 vmsvga_update_rect_delayed(s, x, y, w, h);
486 return 0;
487 }
488 #endif
489
490 struct vmsvga_cursor_definition_s {
491 uint32_t width;
492 uint32_t height;
493 int id;
494 uint32_t bpp;
495 int hot_x;
496 int hot_y;
497 uint32_t mask[1024];
498 uint32_t image[4096];
499 };
500
501 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
502 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
503
504 #ifdef HW_MOUSE_ACCEL
505 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
506 struct vmsvga_cursor_definition_s *c)
507 {
508 QEMUCursor *qc;
509 int i, pixels;
510
511 qc = cursor_alloc(c->width, c->height);
512 qc->hot_x = c->hot_x;
513 qc->hot_y = c->hot_y;
514 switch (c->bpp) {
515 case 1:
516 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
517 1, (void *)c->mask);
518 #ifdef DEBUG
519 cursor_print_ascii_art(qc, "vmware/mono");
520 #endif
521 break;
522 case 32:
523 /* fill alpha channel from mask, set color to zero */
524 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
525 1, (void *)c->mask);
526 /* add in rgb values */
527 pixels = c->width * c->height;
528 for (i = 0; i < pixels; i++) {
529 qc->data[i] |= c->image[i] & 0xffffff;
530 }
531 #ifdef DEBUG
532 cursor_print_ascii_art(qc, "vmware/32bit");
533 #endif
534 break;
535 default:
536 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
537 __func__, c->bpp);
538 cursor_put(qc);
539 qc = cursor_builtin_left_ptr();
540 }
541
542 dpy_cursor_define(s->vga.con, qc);
543 cursor_put(qc);
544 }
545 #endif
546
547 #define CMD(f) le32_to_cpu(s->cmd->f)
548
549 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
550 {
551 int num;
552
553 if (!s->config || !s->enable) {
554 return 0;
555 }
556 num = CMD(next_cmd) - CMD(stop);
557 if (num < 0) {
558 num += CMD(max) - CMD(min);
559 }
560 return num >> 2;
561 }
562
563 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
564 {
565 uint32_t cmd = s->fifo[CMD(stop) >> 2];
566
567 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
568 if (CMD(stop) >= CMD(max)) {
569 s->cmd->stop = s->cmd->min;
570 }
571 return cmd;
572 }
573
574 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
575 {
576 return le32_to_cpu(vmsvga_fifo_read_raw(s));
577 }
578
579 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
580 {
581 uint32_t cmd, colour;
582 int args, len;
583 int x, y, dx, dy, width, height;
584 struct vmsvga_cursor_definition_s cursor;
585 uint32_t cmd_start;
586
587 len = vmsvga_fifo_length(s);
588 while (len > 0) {
589 /* May need to go back to the start of the command if incomplete */
590 cmd_start = s->cmd->stop;
591
592 switch (cmd = vmsvga_fifo_read(s)) {
593 case SVGA_CMD_UPDATE:
594 case SVGA_CMD_UPDATE_VERBOSE:
595 len -= 5;
596 if (len < 0) {
597 goto rewind;
598 }
599
600 x = vmsvga_fifo_read(s);
601 y = vmsvga_fifo_read(s);
602 width = vmsvga_fifo_read(s);
603 height = vmsvga_fifo_read(s);
604 vmsvga_update_rect_delayed(s, x, y, width, height);
605 break;
606
607 case SVGA_CMD_RECT_FILL:
608 len -= 6;
609 if (len < 0) {
610 goto rewind;
611 }
612
613 colour = vmsvga_fifo_read(s);
614 x = vmsvga_fifo_read(s);
615 y = vmsvga_fifo_read(s);
616 width = vmsvga_fifo_read(s);
617 height = vmsvga_fifo_read(s);
618 #ifdef HW_FILL_ACCEL
619 if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) {
620 break;
621 }
622 #endif
623 args = 0;
624 goto badcmd;
625
626 case SVGA_CMD_RECT_COPY:
627 len -= 7;
628 if (len < 0) {
629 goto rewind;
630 }
631
632 x = vmsvga_fifo_read(s);
633 y = vmsvga_fifo_read(s);
634 dx = vmsvga_fifo_read(s);
635 dy = vmsvga_fifo_read(s);
636 width = vmsvga_fifo_read(s);
637 height = vmsvga_fifo_read(s);
638 #ifdef HW_RECT_ACCEL
639 if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) {
640 break;
641 }
642 #endif
643 args = 0;
644 goto badcmd;
645
646 case SVGA_CMD_DEFINE_CURSOR:
647 len -= 8;
648 if (len < 0) {
649 goto rewind;
650 }
651
652 cursor.id = vmsvga_fifo_read(s);
653 cursor.hot_x = vmsvga_fifo_read(s);
654 cursor.hot_y = vmsvga_fifo_read(s);
655 cursor.width = x = vmsvga_fifo_read(s);
656 cursor.height = y = vmsvga_fifo_read(s);
657 vmsvga_fifo_read(s);
658 cursor.bpp = vmsvga_fifo_read(s);
659
660 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
661 if (cursor.width > 256 ||
662 cursor.height > 256 ||
663 cursor.bpp > 32 ||
664 SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
665 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
666 goto badcmd;
667 }
668
669 len -= args;
670 if (len < 0) {
671 goto rewind;
672 }
673
674 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
675 cursor.mask[args] = vmsvga_fifo_read_raw(s);
676 }
677 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
678 cursor.image[args] = vmsvga_fifo_read_raw(s);
679 }
680 #ifdef HW_MOUSE_ACCEL
681 vmsvga_cursor_define(s, &cursor);
682 break;
683 #else
684 args = 0;
685 goto badcmd;
686 #endif
687
688 /*
689 * Other commands that we at least know the number of arguments
690 * for so we can avoid FIFO desync if driver uses them illegally.
691 */
692 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
693 len -= 6;
694 if (len < 0) {
695 goto rewind;
696 }
697 vmsvga_fifo_read(s);
698 vmsvga_fifo_read(s);
699 vmsvga_fifo_read(s);
700 x = vmsvga_fifo_read(s);
701 y = vmsvga_fifo_read(s);
702 args = x * y;
703 goto badcmd;
704 case SVGA_CMD_RECT_ROP_FILL:
705 args = 6;
706 goto badcmd;
707 case SVGA_CMD_RECT_ROP_COPY:
708 args = 7;
709 goto badcmd;
710 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
711 len -= 4;
712 if (len < 0) {
713 goto rewind;
714 }
715 vmsvga_fifo_read(s);
716 vmsvga_fifo_read(s);
717 args = 7 + (vmsvga_fifo_read(s) >> 2);
718 goto badcmd;
719 case SVGA_CMD_SURFACE_ALPHA_BLEND:
720 args = 12;
721 goto badcmd;
722
723 /*
724 * Other commands that are not listed as depending on any
725 * CAPABILITIES bits, but are not described in the README either.
726 */
727 case SVGA_CMD_SURFACE_FILL:
728 case SVGA_CMD_SURFACE_COPY:
729 case SVGA_CMD_FRONT_ROP_FILL:
730 case SVGA_CMD_FENCE:
731 case SVGA_CMD_INVALID_CMD:
732 break; /* Nop */
733
734 default:
735 args = 0;
736 badcmd:
737 len -= args;
738 if (len < 0) {
739 goto rewind;
740 }
741 while (args--) {
742 vmsvga_fifo_read(s);
743 }
744 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
745 __func__, cmd);
746 break;
747
748 rewind:
749 s->cmd->stop = cmd_start;
750 break;
751 }
752 }
753
754 s->syncing = 0;
755 }
756
757 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
758 {
759 struct vmsvga_state_s *s = opaque;
760
761 return s->index;
762 }
763
764 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
765 {
766 struct vmsvga_state_s *s = opaque;
767
768 s->index = index;
769 }
770
771 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
772 {
773 uint32_t caps;
774 struct vmsvga_state_s *s = opaque;
775 DisplaySurface *surface = qemu_console_surface(s->vga.con);
776 PixelFormat pf;
777 uint32_t ret;
778
779 switch (s->index) {
780 case SVGA_REG_ID:
781 ret = s->svgaid;
782 break;
783
784 case SVGA_REG_ENABLE:
785 ret = s->enable;
786 break;
787
788 case SVGA_REG_WIDTH:
789 ret = s->new_width ? s->new_width : surface_width(surface);
790 break;
791
792 case SVGA_REG_HEIGHT:
793 ret = s->new_height ? s->new_height : surface_height(surface);
794 break;
795
796 case SVGA_REG_MAX_WIDTH:
797 ret = SVGA_MAX_WIDTH;
798 break;
799
800 case SVGA_REG_MAX_HEIGHT:
801 ret = SVGA_MAX_HEIGHT;
802 break;
803
804 case SVGA_REG_DEPTH:
805 ret = (s->new_depth == 32) ? 24 : s->new_depth;
806 break;
807
808 case SVGA_REG_BITS_PER_PIXEL:
809 case SVGA_REG_HOST_BITS_PER_PIXEL:
810 ret = s->new_depth;
811 break;
812
813 case SVGA_REG_PSEUDOCOLOR:
814 ret = 0x0;
815 break;
816
817 case SVGA_REG_RED_MASK:
818 pf = qemu_default_pixelformat(s->new_depth);
819 ret = pf.rmask;
820 break;
821
822 case SVGA_REG_GREEN_MASK:
823 pf = qemu_default_pixelformat(s->new_depth);
824 ret = pf.gmask;
825 break;
826
827 case SVGA_REG_BLUE_MASK:
828 pf = qemu_default_pixelformat(s->new_depth);
829 ret = pf.bmask;
830 break;
831
832 case SVGA_REG_BYTES_PER_LINE:
833 if (s->new_width) {
834 ret = (s->new_depth * s->new_width) / 8;
835 } else {
836 ret = surface_stride(surface);
837 }
838 break;
839
840 case SVGA_REG_FB_START: {
841 struct pci_vmsvga_state_s *pci_vmsvga
842 = container_of(s, struct pci_vmsvga_state_s, chip);
843 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
844 break;
845 }
846
847 case SVGA_REG_FB_OFFSET:
848 ret = 0x0;
849 break;
850
851 case SVGA_REG_VRAM_SIZE:
852 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */
853 break;
854
855 case SVGA_REG_FB_SIZE:
856 ret = s->vga.vram_size;
857 break;
858
859 case SVGA_REG_CAPABILITIES:
860 caps = SVGA_CAP_NONE;
861 #ifdef HW_RECT_ACCEL
862 caps |= SVGA_CAP_RECT_COPY;
863 #endif
864 #ifdef HW_FILL_ACCEL
865 caps |= SVGA_CAP_RECT_FILL;
866 #endif
867 #ifdef HW_MOUSE_ACCEL
868 if (dpy_cursor_define_supported(s->vga.con)) {
869 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
870 SVGA_CAP_CURSOR_BYPASS;
871 }
872 #endif
873 ret = caps;
874 break;
875
876 case SVGA_REG_MEM_START: {
877 struct pci_vmsvga_state_s *pci_vmsvga
878 = container_of(s, struct pci_vmsvga_state_s, chip);
879 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
880 break;
881 }
882
883 case SVGA_REG_MEM_SIZE:
884 ret = s->fifo_size;
885 break;
886
887 case SVGA_REG_CONFIG_DONE:
888 ret = s->config;
889 break;
890
891 case SVGA_REG_SYNC:
892 case SVGA_REG_BUSY:
893 ret = s->syncing;
894 break;
895
896 case SVGA_REG_GUEST_ID:
897 ret = s->guest;
898 break;
899
900 case SVGA_REG_CURSOR_ID:
901 ret = s->cursor.id;
902 break;
903
904 case SVGA_REG_CURSOR_X:
905 ret = s->cursor.x;
906 break;
907
908 case SVGA_REG_CURSOR_Y:
909 ret = s->cursor.y;
910 break;
911
912 case SVGA_REG_CURSOR_ON:
913 ret = s->cursor.on;
914 break;
915
916 case SVGA_REG_SCRATCH_SIZE:
917 ret = s->scratch_size;
918 break;
919
920 case SVGA_REG_MEM_REGS:
921 case SVGA_REG_NUM_DISPLAYS:
922 case SVGA_REG_PITCHLOCK:
923 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
924 ret = 0;
925 break;
926
927 default:
928 if (s->index >= SVGA_SCRATCH_BASE &&
929 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
930 ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
931 break;
932 }
933 printf("%s: Bad register %02x\n", __func__, s->index);
934 ret = 0;
935 break;
936 }
937
938 if (s->index >= SVGA_SCRATCH_BASE) {
939 trace_vmware_scratch_read(s->index, ret);
940 } else if (s->index >= SVGA_PALETTE_BASE) {
941 trace_vmware_palette_read(s->index, ret);
942 } else {
943 trace_vmware_value_read(s->index, ret);
944 }
945 return ret;
946 }
947
948 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
949 {
950 struct vmsvga_state_s *s = opaque;
951
952 if (s->index >= SVGA_SCRATCH_BASE) {
953 trace_vmware_scratch_write(s->index, value);
954 } else if (s->index >= SVGA_PALETTE_BASE) {
955 trace_vmware_palette_write(s->index, value);
956 } else {
957 trace_vmware_value_write(s->index, value);
958 }
959 switch (s->index) {
960 case SVGA_REG_ID:
961 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
962 s->svgaid = value;
963 }
964 break;
965
966 case SVGA_REG_ENABLE:
967 s->enable = !!value;
968 s->invalidated = 1;
969 s->vga.hw_ops->invalidate(&s->vga);
970 if (s->enable && s->config) {
971 vga_dirty_log_stop(&s->vga);
972 } else {
973 vga_dirty_log_start(&s->vga);
974 }
975 break;
976
977 case SVGA_REG_WIDTH:
978 if (value <= SVGA_MAX_WIDTH) {
979 s->new_width = value;
980 s->invalidated = 1;
981 } else {
982 printf("%s: Bad width: %i\n", __func__, value);
983 }
984 break;
985
986 case SVGA_REG_HEIGHT:
987 if (value <= SVGA_MAX_HEIGHT) {
988 s->new_height = value;
989 s->invalidated = 1;
990 } else {
991 printf("%s: Bad height: %i\n", __func__, value);
992 }
993 break;
994
995 case SVGA_REG_BITS_PER_PIXEL:
996 if (value != 32) {
997 printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
998 s->config = 0;
999 s->invalidated = 1;
1000 }
1001 break;
1002
1003 case SVGA_REG_CONFIG_DONE:
1004 if (value) {
1005 s->fifo = (uint32_t *) s->fifo_ptr;
1006 /* Check range and alignment. */
1007 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
1008 break;
1009 }
1010 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
1011 break;
1012 }
1013 if (CMD(max) > SVGA_FIFO_SIZE) {
1014 break;
1015 }
1016 if (CMD(max) < CMD(min) + 10 * 1024) {
1017 break;
1018 }
1019 vga_dirty_log_stop(&s->vga);
1020 }
1021 s->config = !!value;
1022 break;
1023
1024 case SVGA_REG_SYNC:
1025 s->syncing = 1;
1026 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
1027 break;
1028
1029 case SVGA_REG_GUEST_ID:
1030 s->guest = value;
1031 #ifdef VERBOSE
1032 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
1033 ARRAY_SIZE(vmsvga_guest_id)) {
1034 printf("%s: guest runs %s.\n", __func__,
1035 vmsvga_guest_id[value - GUEST_OS_BASE]);
1036 }
1037 #endif
1038 break;
1039
1040 case SVGA_REG_CURSOR_ID:
1041 s->cursor.id = value;
1042 break;
1043
1044 case SVGA_REG_CURSOR_X:
1045 s->cursor.x = value;
1046 break;
1047
1048 case SVGA_REG_CURSOR_Y:
1049 s->cursor.y = value;
1050 break;
1051
1052 case SVGA_REG_CURSOR_ON:
1053 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
1054 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
1055 #ifdef HW_MOUSE_ACCEL
1056 if (value <= SVGA_CURSOR_ON_SHOW) {
1057 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
1058 }
1059 #endif
1060 break;
1061
1062 case SVGA_REG_DEPTH:
1063 case SVGA_REG_MEM_REGS:
1064 case SVGA_REG_NUM_DISPLAYS:
1065 case SVGA_REG_PITCHLOCK:
1066 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
1067 break;
1068
1069 default:
1070 if (s->index >= SVGA_SCRATCH_BASE &&
1071 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
1072 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
1073 break;
1074 }
1075 printf("%s: Bad register %02x\n", __func__, s->index);
1076 }
1077 }
1078
1079 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
1080 {
1081 printf("%s: what are we supposed to return?\n", __func__);
1082 return 0xcafe;
1083 }
1084
1085 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
1086 {
1087 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
1088 }
1089
1090 static inline void vmsvga_check_size(struct vmsvga_state_s *s)
1091 {
1092 DisplaySurface *surface = qemu_console_surface(s->vga.con);
1093
1094 if (s->new_width != surface_width(surface) ||
1095 s->new_height != surface_height(surface) ||
1096 s->new_depth != surface_bits_per_pixel(surface)) {
1097 int stride = (s->new_depth * s->new_width) / 8;
1098 pixman_format_code_t format =
1099 qemu_default_pixman_format(s->new_depth, true);
1100 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth);
1101 surface = qemu_create_displaysurface_from(s->new_width, s->new_height,
1102 format, stride,
1103 s->vga.vram_ptr);
1104 dpy_gfx_replace_surface(s->vga.con, surface);
1105 s->invalidated = 1;
1106 }
1107 }
1108
1109 static void vmsvga_update_display(void *opaque)
1110 {
1111 struct vmsvga_state_s *s = opaque;
1112 DisplaySurface *surface;
1113 bool dirty = false;
1114
1115 if (!s->enable) {
1116 s->vga.hw_ops->gfx_update(&s->vga);
1117 return;
1118 }
1119
1120 vmsvga_check_size(s);
1121 surface = qemu_console_surface(s->vga.con);
1122
1123 vmsvga_fifo_run(s);
1124 vmsvga_update_rect_flush(s);
1125
1126 /*
1127 * Is it more efficient to look at vram VGA-dirty bits or wait
1128 * for the driver to issue SVGA_CMD_UPDATE?
1129 */
1130 if (memory_region_is_logging(&s->vga.vram, DIRTY_MEMORY_VGA)) {
1131 vga_sync_dirty_bitmap(&s->vga);
1132 dirty = memory_region_get_dirty(&s->vga.vram, 0,
1133 surface_stride(surface) * surface_height(surface),
1134 DIRTY_MEMORY_VGA);
1135 }
1136 if (s->invalidated || dirty) {
1137 s->invalidated = 0;
1138 dpy_gfx_update(s->vga.con, 0, 0,
1139 surface_width(surface), surface_height(surface));
1140 }
1141 if (dirty) {
1142 memory_region_reset_dirty(&s->vga.vram, 0,
1143 surface_stride(surface) * surface_height(surface),
1144 DIRTY_MEMORY_VGA);
1145 }
1146 }
1147
1148 static void vmsvga_reset(DeviceState *dev)
1149 {
1150 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev);
1151 struct vmsvga_state_s *s = &pci->chip;
1152
1153 s->index = 0;
1154 s->enable = 0;
1155 s->config = 0;
1156 s->svgaid = SVGA_ID;
1157 s->cursor.on = 0;
1158 s->redraw_fifo_first = 0;
1159 s->redraw_fifo_last = 0;
1160 s->syncing = 0;
1161
1162 vga_dirty_log_start(&s->vga);
1163 }
1164
1165 static void vmsvga_invalidate_display(void *opaque)
1166 {
1167 struct vmsvga_state_s *s = opaque;
1168 if (!s->enable) {
1169 s->vga.hw_ops->invalidate(&s->vga);
1170 return;
1171 }
1172
1173 s->invalidated = 1;
1174 }
1175
1176 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1177 {
1178 struct vmsvga_state_s *s = opaque;
1179
1180 if (s->vga.hw_ops->text_update) {
1181 s->vga.hw_ops->text_update(&s->vga, chardata);
1182 }
1183 }
1184
1185 static int vmsvga_post_load(void *opaque, int version_id)
1186 {
1187 struct vmsvga_state_s *s = opaque;
1188
1189 s->invalidated = 1;
1190 if (s->config) {
1191 s->fifo = (uint32_t *) s->fifo_ptr;
1192 }
1193 return 0;
1194 }
1195
1196 static const VMStateDescription vmstate_vmware_vga_internal = {
1197 .name = "vmware_vga_internal",
1198 .version_id = 0,
1199 .minimum_version_id = 0,
1200 .post_load = vmsvga_post_load,
1201 .fields = (VMStateField[]) {
1202 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s),
1203 VMSTATE_INT32(enable, struct vmsvga_state_s),
1204 VMSTATE_INT32(config, struct vmsvga_state_s),
1205 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1206 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1207 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1208 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1209 VMSTATE_INT32(index, struct vmsvga_state_s),
1210 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1211 scratch_size, 0, vmstate_info_uint32, uint32_t),
1212 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1213 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1214 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1215 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1216 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1217 VMSTATE_UNUSED(4), /* was fb_size */
1218 VMSTATE_END_OF_LIST()
1219 }
1220 };
1221
1222 static const VMStateDescription vmstate_vmware_vga = {
1223 .name = "vmware_vga",
1224 .version_id = 0,
1225 .minimum_version_id = 0,
1226 .fields = (VMStateField[]) {
1227 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
1228 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1229 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1230 VMSTATE_END_OF_LIST()
1231 }
1232 };
1233
1234 static const GraphicHwOps vmsvga_ops = {
1235 .invalidate = vmsvga_invalidate_display,
1236 .gfx_update = vmsvga_update_display,
1237 .text_update = vmsvga_text_update,
1238 };
1239
1240 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
1241 MemoryRegion *address_space, MemoryRegion *io)
1242 {
1243 s->scratch_size = SVGA_SCRATCH_SIZE;
1244 s->scratch = g_malloc(s->scratch_size * 4);
1245
1246 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s);
1247
1248 s->fifo_size = SVGA_FIFO_SIZE;
1249 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size,
1250 &error_fatal);
1251 vmstate_register_ram_global(&s->fifo_ram);
1252 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1253
1254 vga_common_init(&s->vga, OBJECT(dev), true);
1255 vga_init(&s->vga, OBJECT(dev), address_space, io, true);
1256 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1257 s->new_depth = 32;
1258 }
1259
1260 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
1261 {
1262 struct vmsvga_state_s *s = opaque;
1263
1264 switch (addr) {
1265 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1266 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1267 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1268 default: return -1u;
1269 }
1270 }
1271
1272 static void vmsvga_io_write(void *opaque, hwaddr addr,
1273 uint64_t data, unsigned size)
1274 {
1275 struct vmsvga_state_s *s = opaque;
1276
1277 switch (addr) {
1278 case SVGA_IO_MUL * SVGA_INDEX_PORT:
1279 vmsvga_index_write(s, addr, data);
1280 break;
1281 case SVGA_IO_MUL * SVGA_VALUE_PORT:
1282 vmsvga_value_write(s, addr, data);
1283 break;
1284 case SVGA_IO_MUL * SVGA_BIOS_PORT:
1285 vmsvga_bios_write(s, addr, data);
1286 break;
1287 }
1288 }
1289
1290 static const MemoryRegionOps vmsvga_io_ops = {
1291 .read = vmsvga_io_read,
1292 .write = vmsvga_io_write,
1293 .endianness = DEVICE_LITTLE_ENDIAN,
1294 .valid = {
1295 .min_access_size = 4,
1296 .max_access_size = 4,
1297 .unaligned = true,
1298 },
1299 .impl = {
1300 .unaligned = true,
1301 },
1302 };
1303
1304 static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
1305 {
1306 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
1307
1308 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
1309 dev->config[PCI_LATENCY_TIMER] = 0x40;
1310 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
1311
1312 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
1313 "vmsvga-io", 0x10);
1314 memory_region_set_flush_coalesced(&s->io_bar);
1315 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1316
1317 vmsvga_init(DEVICE(dev), &s->chip,
1318 pci_address_space(dev), pci_address_space_io(dev));
1319
1320 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
1321 &s->chip.vga.vram);
1322 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1323 &s->chip.fifo_ram);
1324
1325 if (!dev->rom_bar) {
1326 /* compatibility with pc-0.13 and older */
1327 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev));
1328 }
1329 }
1330
1331 static Property vga_vmware_properties[] = {
1332 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1333 chip.vga.vram_size_mb, 16),
1334 DEFINE_PROP_END_OF_LIST(),
1335 };
1336
1337 static void vmsvga_class_init(ObjectClass *klass, void *data)
1338 {
1339 DeviceClass *dc = DEVICE_CLASS(klass);
1340 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1341
1342 k->realize = pci_vmsvga_realize;
1343 k->romfile = "vgabios-vmware.bin";
1344 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1345 k->device_id = SVGA_PCI_DEVICE_ID;
1346 k->class_id = PCI_CLASS_DISPLAY_VGA;
1347 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1348 k->subsystem_id = SVGA_PCI_DEVICE_ID;
1349 dc->reset = vmsvga_reset;
1350 dc->vmsd = &vmstate_vmware_vga;
1351 dc->props = vga_vmware_properties;
1352 dc->hotpluggable = false;
1353 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1354 }
1355
1356 static const TypeInfo vmsvga_info = {
1357 .name = TYPE_VMWARE_SVGA,
1358 .parent = TYPE_PCI_DEVICE,
1359 .instance_size = sizeof(struct pci_vmsvga_state_s),
1360 .class_init = vmsvga_class_init,
1361 };
1362
1363 static void vmsvga_register_types(void)
1364 {
1365 type_register_static(&vmsvga_info);
1366 }
1367
1368 type_init(vmsvga_register_types)
AR7 emulation for QEMU