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1 # AArch64 SVE instruction descriptions
2 #
3 # Copyright (c) 2017 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
19 # This file is processed by scripts/decodetree.py
20 #
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
25 %imm4_16_p1 16:4 !function=plus1
26 %imm6_22_5 22:1 5:5
27 %imm7_22_16 22:2 16:5
28 %imm8_16_10 16:5 10:3
29 %imm9_16_10 16:s6 10:3
30 %size_23 23:2
31 %dtype_23_13 23:2 13:2
33 # A combination of tsz:imm3 -- extract esize.
34 %tszimm_esz 22:2 5:5 !function=tszimm_esz
35 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
36 %tszimm_shr 22:2 5:5 !function=tszimm_shr
37 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
38 %tszimm_shl 22:2 5:5 !function=tszimm_shl
40 # Similarly for the tszh/tszl pair at 22/16 for zzi
41 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
42 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
43 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
45 # Signed 8-bit immediate, optionally shifted left by 8.
46 %sh8_i8s 5:9 !function=expand_imm_sh8s
47 # Unsigned 8-bit immediate, optionally shifted left by 8.
48 %sh8_i8u 5:9 !function=expand_imm_sh8u
50 # Unsigned load of msz into esz=2, represented as a dtype.
51 %msz_dtype 23:2 !function=msz_dtype
53 # Either a copy of rd (at bit 0), or a different source
54 # as propagated via the MOVPRFX instruction.
55 %reg_movprfx 0:5
57 ###########################################################################
58 # Named attribute sets. These are used to make nice(er) names
59 # when creating helpers common to those for the individual
60 # instruction patterns.
62 &rr_esz rd rn esz
63 &rri rd rn imm
64 &rr_dbm rd rn dbm
65 &rrri rd rn rm imm
66 &rri_esz rd rn imm esz
67 &rrr_esz rd rn rm esz
68 &rpr_esz rd pg rn esz
69 &rpr_s rd pg rn s
70 &rprr_s rd pg rn rm s
71 &rprr_esz rd pg rn rm esz
72 &rprrr_esz rd pg rn rm ra esz
73 &rpri_esz rd pg rn imm esz
74 &ptrue rd esz pat s
75 &incdec_cnt rd pat esz imm d u
76 &incdec2_cnt rd rn pat esz imm d u
77 &incdec_pred rd pg esz d u
78 &incdec2_pred rd rn pg esz d u
79 &rprr_load rd pg rn rm dtype nreg
80 &rpri_load rd pg rn imm dtype nreg
81 &rprr_store rd pg rn rm msz esz nreg
82 &rpri_store rd pg rn imm msz esz nreg
83 &rprr_scatter_store rd pg rn rm esz msz xs scale
85 ###########################################################################
86 # Named instruction formats. These are generally used to
87 # reduce the amount of duplication between instruction patterns.
89 # Two operand with unused vector element size
90 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
92 # Two operand
93 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
94 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
96 # Two operand with governing predicate, flags setting
97 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
99 # Three operand with unused vector element size
100 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
102 # Three predicate operand, with governing predicate, flag setting
103 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
105 # Three operand, vector element size
106 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
107 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
108 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
109 &rrr_esz rn=%reg_movprfx
110 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
111 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
112 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
113 &rri_esz rn=%reg_movprfx
114 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
115 &rri_esz rn=%reg_movprfx
117 # Three operand with "memory" size, aka immediate left shift
118 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
120 # Two register operand, with governing predicate, vector element size
121 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
122 &rprr_esz rn=%reg_movprfx
123 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
124 &rprr_esz rm=%reg_movprfx
125 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
126 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
128 # Three register operand, with governing predicate, vector element size
129 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
130 &rprrr_esz ra=%reg_movprfx
131 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
132 &rprrr_esz rn=%reg_movprfx
133 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
134 &rprrr_esz rn=%reg_movprfx
136 # One register operand, with governing predicate, vector element size
137 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
138 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
140 # One register operand, with governing predicate, no vector element size
141 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
143 # Two register operands with a 6-bit signed immediate.
144 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
146 # Two register operand, one immediate operand, with predicate,
147 # element size encoded as TSZHL. User must fill in imm.
148 @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
149 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
151 # Similarly without predicate.
152 @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
153 &rri_esz esz=%tszimm16_esz
155 # Two register operand, one immediate operand, with 4-bit predicate.
156 # User must fill in imm.
157 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
158 &rpri_esz rn=%reg_movprfx
160 # Two register operand, one encoded bitmask.
161 @rdn_dbm ........ .. .... dbm:13 rd:5 \
162 &rr_dbm rn=%reg_movprfx
164 # Predicate output, vector and immediate input,
165 # controlling predicate, element size.
166 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
167 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
169 # Basic Load/Store with 9-bit immediate offset
170 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
171 &rri imm=%imm9_16_10
172 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
173 &rri imm=%imm9_16_10
175 # One register, pattern, and uint4+1.
176 # User must fill in U and D.
177 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
178 &incdec_cnt imm=%imm4_16_p1
179 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
180 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
182 # One register, predicate.
183 # User must fill in U and D.
184 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
185 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
186 &incdec2_pred rn=%reg_movprfx
188 # Loads; user must fill in NREG.
189 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
190 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
192 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
193 &rprr_load dtype=%msz_dtype
194 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
195 &rpri_load dtype=%msz_dtype
197 # Stores; user must fill in ESZ, MSZ, NREG as needed.
198 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
199 @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
200 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
201 &rprr_store nreg=0
202 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
203 &rprr_scatter_store
205 ###########################################################################
206 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
208 ### SVE Integer Arithmetic - Binary Predicated Group
210 # SVE bitwise logical vector operations (predicated)
211 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
212 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
213 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
214 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
216 # SVE integer add/subtract vectors (predicated)
217 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
218 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
219 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
221 # SVE integer min/max/difference (predicated)
222 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
223 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
224 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
225 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
226 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
227 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
229 # SVE integer multiply/divide (predicated)
230 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
231 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
232 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
233 # Note that divide requires size >= 2; below 2 is unallocated.
234 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
235 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
236 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
237 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
239 ### SVE Integer Reduction Group
241 # SVE bitwise logical reduction (predicated)
242 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
243 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
244 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
246 # SVE integer add reduction (predicated)
247 # Note that saddv requires size != 3.
248 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
249 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
251 # SVE integer min/max reduction (predicated)
252 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
253 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
254 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
255 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
257 ### SVE Shift by Immediate - Predicated Group
259 # SVE bitwise shift by immediate (predicated)
260 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
261 @rdn_pg_tszimm imm=%tszimm_shr
262 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
263 @rdn_pg_tszimm imm=%tszimm_shr
264 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
265 @rdn_pg_tszimm imm=%tszimm_shl
266 ASRD 00000100 .. 000 100 100 ... .. ... ..... \
267 @rdn_pg_tszimm imm=%tszimm_shr
269 # SVE bitwise shift by vector (predicated)
270 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
271 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
272 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
273 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
274 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
275 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
277 # SVE bitwise shift by wide elements (predicated)
278 # Note these require size != 3.
279 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
280 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
281 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
283 ### SVE Integer Arithmetic - Unary Predicated Group
285 # SVE unary bit operations (predicated)
286 # Note esz != 0 for FABS and FNEG.
287 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
288 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
289 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
290 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
291 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
292 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
293 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
295 # SVE integer unary operations (predicated)
296 # Note esz > original size for extensions.
297 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
298 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
299 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
300 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
301 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
302 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
303 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
304 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
306 ### SVE Integer Multiply-Add Group
308 # SVE integer multiply-add writing addend (predicated)
309 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
310 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
312 # SVE integer multiply-add writing multiplicand (predicated)
313 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
314 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
316 ### SVE Integer Arithmetic - Unpredicated Group
318 # SVE integer add/subtract vectors (unpredicated)
319 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
320 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
321 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
322 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
323 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
324 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
326 ### SVE Logical - Unpredicated Group
328 # SVE bitwise logical operations (unpredicated)
329 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
330 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
331 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
332 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
334 ### SVE Index Generation Group
336 # SVE index generation (immediate start, immediate increment)
337 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
339 # SVE index generation (immediate start, register increment)
340 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
342 # SVE index generation (register start, immediate increment)
343 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
345 # SVE index generation (register start, register increment)
346 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
348 ### SVE Stack Allocation Group
350 # SVE stack frame adjustment
351 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
352 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
354 # SVE stack frame size
355 RDVL 00000100 101 11111 01010 imm:s6 rd:5
357 ### SVE Bitwise Shift - Unpredicated Group
359 # SVE bitwise shift by immediate (unpredicated)
360 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
361 @rd_rn_tszimm imm=%tszimm16_shr
362 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
363 @rd_rn_tszimm imm=%tszimm16_shr
364 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
365 @rd_rn_tszimm imm=%tszimm16_shl
367 # SVE bitwise shift by wide elements (unpredicated)
368 # Note esz != 3
369 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
370 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
371 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
373 ### SVE Compute Vector Address Group
375 # SVE vector address generation
376 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
377 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
378 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
379 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
381 ### SVE Integer Misc - Unpredicated Group
383 # SVE floating-point exponential accelerator
384 # Note esz != 0
385 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
387 # SVE floating-point trig select coefficient
388 # Note esz != 0
389 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
391 ### SVE Element Count Group
393 # SVE element count
394 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
396 # SVE inc/dec register by element count
397 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
399 # SVE saturating inc/dec register by element count
400 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
401 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
403 # SVE inc/dec vector by element count
404 # Note this requires esz != 0.
405 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
407 # SVE saturating inc/dec vector by element count
408 # Note these require esz != 0.
409 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
411 ### SVE Bitwise Immediate Group
413 # SVE bitwise logical with immediate (unpredicated)
414 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
415 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
416 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
418 # SVE broadcast bitmask immediate
419 DUPM 00000101 11 0000 dbm:13 rd:5
421 ### SVE Integer Wide Immediate - Predicated Group
423 # SVE copy floating-point immediate (predicated)
424 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
426 # SVE copy integer immediate (predicated)
427 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
428 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
430 ### SVE Permute - Extract Group
432 # SVE extract vector (immediate offset)
433 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
434 &rrri rn=%reg_movprfx imm=%imm8_16_10
436 ### SVE Permute - Unpredicated Group
438 # SVE broadcast general register
439 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
441 # SVE broadcast indexed element
442 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
443 &rri imm=%imm7_22_16
445 # SVE insert SIMD&FP scalar register
446 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
448 # SVE insert general register
449 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
451 # SVE reverse vector elements
452 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
454 # SVE vector table lookup
455 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
457 # SVE unpack vector elements
458 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
460 ### SVE Permute - Predicates Group
462 # SVE permute predicate elements
463 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
464 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
465 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
466 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
467 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
468 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
470 # SVE reverse predicate elements
471 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
473 # SVE unpack predicate elements
474 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
475 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
477 ### SVE Permute - Interleaving Group
479 # SVE permute vector elements
480 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
481 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
482 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
483 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
484 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
485 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
487 ### SVE Permute - Predicated Group
489 # SVE compress active elements
490 # Note esz >= 2
491 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
493 # SVE conditionally broadcast element to vector
494 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
495 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
497 # SVE conditionally copy element to SIMD&FP scalar
498 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
499 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
501 # SVE conditionally copy element to general register
502 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
503 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
505 # SVE copy element to SIMD&FP scalar register
506 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
507 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
509 # SVE copy element to general register
510 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
511 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
513 # SVE copy element from SIMD&FP scalar register
514 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
516 # SVE copy element from general register to vector (predicated)
517 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
519 # SVE reverse within elements
520 # Note esz >= operation size
521 REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
522 REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
523 REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
524 RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
526 # SVE vector splice (predicated)
527 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
529 ### SVE Select Vectors Group
531 # SVE select vector elements (predicated)
532 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
534 ### SVE Integer Compare - Vectors Group
536 # SVE integer compare_vectors
537 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
538 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
539 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
540 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
541 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
542 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
544 # SVE integer compare with wide elements
545 # Note these require esz != 3.
546 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
547 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
548 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
549 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
550 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
551 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
552 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
553 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
554 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
555 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
557 ### SVE Integer Compare - Unsigned Immediate Group
559 # SVE integer compare with unsigned immediate
560 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
561 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
562 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
563 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
565 ### SVE Integer Compare - Signed Immediate Group
567 # SVE integer compare with signed immediate
568 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
569 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
570 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
571 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
572 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
573 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
575 ### SVE Predicate Logical Operations Group
577 # SVE predicate logical operations
578 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
579 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
580 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
581 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
582 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
583 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
584 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
585 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
587 ### SVE Predicate Misc Group
589 # SVE predicate test
590 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
592 # SVE predicate initialize
593 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
595 # SVE initialize FFR
596 SETFFR 00100101 0010 1100 1001 0000 0000 0000
598 # SVE zero predicate register
599 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
601 # SVE predicate read from FFR (predicated)
602 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
604 # SVE predicate read from FFR (unpredicated)
605 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
607 # SVE FFR write from predicate (WRFFR)
608 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
610 # SVE predicate first active
611 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
613 # SVE predicate next active
614 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
616 ### SVE Partition Break Group
618 # SVE propagate break from previous partition
619 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
620 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
622 # SVE partition break condition
623 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
624 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
625 BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
626 BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
628 # SVE propagate break to next partition
629 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
631 ### SVE Predicate Count Group
633 # SVE predicate count
634 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
636 # SVE inc/dec register by predicate count
637 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
639 # SVE inc/dec vector by predicate count
640 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
642 # SVE saturating inc/dec register by predicate count
643 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
644 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
646 # SVE saturating inc/dec vector by predicate count
647 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
649 ### SVE Integer Compare - Scalars Group
651 # SVE conditionally terminate scalars
652 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
654 # SVE integer compare scalar count and limit
655 WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
657 ### SVE Integer Wide Immediate - Unpredicated Group
659 # SVE broadcast floating-point immediate (unpredicated)
660 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
662 # SVE broadcast integer immediate (unpredicated)
663 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
665 # SVE integer add/subtract immediate (unpredicated)
666 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
667 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
668 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
669 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
670 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
671 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
672 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
674 # SVE integer min/max immediate (unpredicated)
675 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
676 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
677 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
678 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
680 # SVE integer multiply immediate (unpredicated)
681 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
683 ### SVE FP Accumulating Reduction Group
685 # SVE floating-point serial reduction (predicated)
686 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
688 ### SVE Floating Point Arithmetic - Unpredicated Group
690 # SVE floating-point arithmetic (unpredicated)
691 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
692 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
693 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
694 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
695 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
696 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
698 ### SVE FP Arithmetic Predicated Group
700 # SVE floating-point arithmetic (predicated)
701 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
702 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
703 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
704 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
705 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
706 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
707 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
708 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
709 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
710 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
711 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
712 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
713 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
715 ### SVE FP Multiply-Add Group
717 # SVE floating-point multiply-accumulate writing addend
718 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
719 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
720 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
721 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
723 # SVE floating-point multiply-accumulate writing multiplicand
724 # Alter the operand extraction order and reuse the helpers from above.
725 # FMAD, FMSB, FNMAD, FNMS
726 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
727 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
728 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
729 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
731 ### SVE FP Unary Operations Predicated Group
733 # SVE integer convert to floating-point
734 SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
735 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
736 SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
737 SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
738 SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
739 SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
740 SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
742 UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
743 UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
744 UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
745 UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
746 UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
747 UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
748 UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
750 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
752 # SVE load predicate register
753 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
755 # SVE load vector register
756 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
758 # SVE load and broadcast element
759 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
760 &rpri_load dtype=%dtype_23_13 nreg=0
762 ### SVE Memory Contiguous Load Group
764 # SVE contiguous load (scalar plus scalar)
765 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
767 # SVE contiguous first-fault load (scalar plus scalar)
768 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
770 # SVE contiguous load (scalar plus immediate)
771 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
773 # SVE contiguous non-fault load (scalar plus immediate)
774 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
776 # SVE contiguous non-temporal load (scalar plus scalar)
777 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
778 # SVE load multiple structures (scalar plus scalar)
779 # LD2B, LD2H, LD2W, LD2D; etc.
780 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
782 # SVE contiguous non-temporal load (scalar plus immediate)
783 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
784 # SVE load multiple structures (scalar plus immediate)
785 # LD2B, LD2H, LD2W, LD2D; etc.
786 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
788 # SVE load and broadcast quadword (scalar plus scalar)
789 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
790 @rprr_load_msz nreg=0
792 # SVE load and broadcast quadword (scalar plus immediate)
793 # LD1RQB, LD1RQH, LD1RQS, LD1RQD
794 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
795 @rpri_load_msz nreg=0
797 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
798 PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
800 # SVE 32-bit gather prefetch (vector plus immediate)
801 PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
803 # SVE contiguous prefetch (scalar plus immediate)
804 PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
806 # SVE contiguous prefetch (scalar plus scalar)
807 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
809 ### SVE Memory 64-bit Gather Group
811 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
812 PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
814 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
815 PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
817 # SVE 64-bit gather prefetch (vector plus immediate)
818 PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
820 ### SVE Memory Store Group
822 # SVE store predicate register
823 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
825 # SVE store vector register
826 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
828 # SVE contiguous store (scalar plus immediate)
829 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
830 ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \
831 @rpri_store_msz nreg=0
833 # SVE contiguous store (scalar plus scalar)
834 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
835 # Enumerate msz lest we conflict with STR_zri.
836 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
837 @rprr_store_esz_n0 msz=0
838 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
839 @rprr_store_esz_n0 msz=1
840 ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \
841 @rprr_store_esz_n0 msz=2
842 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
843 @rprr_store msz=3 esz=3 nreg=0
845 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
846 # SVE store multiple structures (scalar plus immediate) (nreg != 0)
847 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
848 @rpri_store_msz esz=%size_23
850 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
851 # SVE store multiple structures (scalar plus scalar) (nreg != 0)
852 ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
853 @rprr_store esz=%size_23
855 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
856 # Require msz > 0 && msz <= esz.
857 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
858 @rprr_scatter_store xs=0 esz=2 scale=1
859 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
860 @rprr_scatter_store xs=1 esz=2 scale=1
862 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
863 # Require msz <= esz.
864 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
865 @rprr_scatter_store xs=0 esz=2 scale=0
866 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
867 @rprr_scatter_store xs=1 esz=2 scale=0
869 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
870 # Require msz > 0
871 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
872 @rprr_scatter_store xs=2 esz=3 scale=1
874 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
875 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
876 @rprr_scatter_store xs=2 esz=3 scale=0
878 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
879 # Require msz > 0
880 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
881 @rprr_scatter_store xs=0 esz=3 scale=1
882 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
883 @rprr_scatter_store xs=1 esz=3 scale=1
885 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
886 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
887 @rprr_scatter_store xs=0 esz=3 scale=0
888 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
889 @rprr_scatter_store xs=1 esz=3 scale=0