4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
25 #include "qemu-common.h"
26 #include "exec/exec-all.h"
27 #include "fpu/softfloat.h"
30 static void hppa_cpu_set_pc(CPUState
*cs
, vaddr value
)
32 HPPACPU
*cpu
= HPPA_CPU(cs
);
34 cpu
->env
.iaoq_f
= value
;
35 cpu
->env
.iaoq_b
= value
+ 4;
38 static void hppa_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
40 HPPACPU
*cpu
= HPPA_CPU(cs
);
42 #ifdef CONFIG_USER_ONLY
43 cpu
->env
.iaoq_f
= tb
->pc
;
44 cpu
->env
.iaoq_b
= tb
->cs_base
;
46 /* Recover the IAOQ values from the GVA + PRIV. */
47 uint32_t priv
= (tb
->flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
48 target_ulong cs_base
= tb
->cs_base
;
49 target_ulong iasq_f
= cs_base
& ~0xffffffffull
;
50 int32_t diff
= cs_base
;
52 cpu
->env
.iasq_f
= iasq_f
;
53 cpu
->env
.iaoq_f
= (tb
->pc
& ~iasq_f
) + priv
;
55 cpu
->env
.iaoq_b
= cpu
->env
.iaoq_f
+ diff
;
59 cpu
->env
.psw_n
= (tb
->flags
& PSW_N
) != 0;
62 static bool hppa_cpu_has_work(CPUState
*cs
)
64 return cs
->interrupt_request
& CPU_INTERRUPT_HARD
;
67 static void hppa_cpu_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
69 info
->mach
= bfd_mach_hppa20
;
70 info
->print_insn
= print_insn_hppa
;
73 static void hppa_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
74 MMUAccessType access_type
,
75 int mmu_idx
, uintptr_t retaddr
)
77 HPPACPU
*cpu
= HPPA_CPU(cs
);
78 CPUHPPAState
*env
= &cpu
->env
;
80 cs
->exception_index
= EXCP_UNALIGN
;
81 if (env
->psw
& PSW_Q
) {
82 /* ??? Needs tweaking for hppa64. */
83 env
->cr
[CR_IOR
] = addr
;
84 env
->cr
[CR_ISR
] = addr
>> 32;
87 cpu_loop_exit_restore(cs
, retaddr
);
90 static void hppa_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
92 CPUState
*cs
= CPU(dev
);
93 HPPACPUClass
*acc
= HPPA_CPU_GET_CLASS(dev
);
94 Error
*local_err
= NULL
;
96 cpu_exec_realizefn(cs
, &local_err
);
97 if (local_err
!= NULL
) {
98 error_propagate(errp
, local_err
);
103 acc
->parent_realize(dev
, errp
);
105 #ifndef CONFIG_USER_ONLY
107 HPPACPU
*cpu
= HPPA_CPU(cs
);
108 cpu
->alarm_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
109 hppa_cpu_alarm_timer
, cpu
);
114 static void hppa_cpu_list_entry(gpointer data
, gpointer user_data
)
116 ObjectClass
*oc
= data
;
118 qemu_printf(" %s\n", object_class_get_name(oc
));
121 void hppa_cpu_list(void)
125 list
= object_class_get_list_sorted(TYPE_HPPA_CPU
, false);
126 qemu_printf("Available CPUs:\n");
127 g_slist_foreach(list
, hppa_cpu_list_entry
, NULL
);
131 static void hppa_cpu_initfn(Object
*obj
)
133 CPUState
*cs
= CPU(obj
);
134 HPPACPU
*cpu
= HPPA_CPU(obj
);
135 CPUHPPAState
*env
= &cpu
->env
;
138 cs
->exception_index
= -1;
139 cpu_hppa_loaded_fr0(env
);
140 cpu_hppa_put_psw(env
, PSW_W
);
143 static ObjectClass
*hppa_cpu_class_by_name(const char *cpu_model
)
145 return object_class_by_name(TYPE_HPPA_CPU
);
148 static void hppa_cpu_class_init(ObjectClass
*oc
, void *data
)
150 DeviceClass
*dc
= DEVICE_CLASS(oc
);
151 CPUClass
*cc
= CPU_CLASS(oc
);
152 HPPACPUClass
*acc
= HPPA_CPU_CLASS(oc
);
154 device_class_set_parent_realize(dc
, hppa_cpu_realizefn
,
155 &acc
->parent_realize
);
157 cc
->class_by_name
= hppa_cpu_class_by_name
;
158 cc
->has_work
= hppa_cpu_has_work
;
159 cc
->do_interrupt
= hppa_cpu_do_interrupt
;
160 cc
->cpu_exec_interrupt
= hppa_cpu_exec_interrupt
;
161 cc
->dump_state
= hppa_cpu_dump_state
;
162 cc
->set_pc
= hppa_cpu_set_pc
;
163 cc
->synchronize_from_tb
= hppa_cpu_synchronize_from_tb
;
164 cc
->gdb_read_register
= hppa_cpu_gdb_read_register
;
165 cc
->gdb_write_register
= hppa_cpu_gdb_write_register
;
166 cc
->tlb_fill
= hppa_cpu_tlb_fill
;
167 #ifndef CONFIG_USER_ONLY
168 cc
->get_phys_page_debug
= hppa_cpu_get_phys_page_debug
;
169 dc
->vmsd
= &vmstate_hppa_cpu
;
171 cc
->do_unaligned_access
= hppa_cpu_do_unaligned_access
;
172 cc
->disas_set_info
= hppa_cpu_disas_set_info
;
173 cc
->tcg_initialize
= hppa_translate_init
;
175 cc
->gdb_num_core_regs
= 128;
178 static const TypeInfo hppa_cpu_type_info
= {
179 .name
= TYPE_HPPA_CPU
,
181 .instance_size
= sizeof(HPPACPU
),
182 .instance_init
= hppa_cpu_initfn
,
184 .class_size
= sizeof(HPPACPUClass
),
185 .class_init
= hppa_cpu_class_init
,
188 static void hppa_cpu_register_types(void)
190 type_register_static(&hppa_cpu_type_info
);
193 type_init(hppa_cpu_register_types
)