4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2011-2013 Andreas Färber
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/i386/pc.h"
31 #include "exec/address-spaces.h"
33 #define TYPE_RAVEN_PCI_DEVICE "raven"
34 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
36 #define RAVEN_PCI_DEVICE(obj) \
37 OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
39 typedef struct RavenPCIState
{
43 #define RAVEN_PCI_HOST_BRIDGE(obj) \
44 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
46 typedef struct PRePPCIState
{
47 PCIHostState parent_obj
;
50 qemu_irq irq
[PCI_NUM_PINS
];
52 RavenPCIState pci_dev
;
55 static inline uint32_t PPC_PCIIO_config(hwaddr addr
)
59 for (i
= 0; i
< 11; i
++) {
60 if ((addr
& (1 << (11 + i
))) != 0) {
64 return (addr
& 0x7ff) | (i
<< 11);
67 static void ppc_pci_io_write(void *opaque
, hwaddr addr
,
68 uint64_t val
, unsigned int size
)
70 PREPPCIState
*s
= opaque
;
71 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
72 pci_data_write(phb
->bus
, PPC_PCIIO_config(addr
), val
, size
);
75 static uint64_t ppc_pci_io_read(void *opaque
, hwaddr addr
,
78 PREPPCIState
*s
= opaque
;
79 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
80 return pci_data_read(phb
->bus
, PPC_PCIIO_config(addr
), size
);
83 static const MemoryRegionOps PPC_PCIIO_ops
= {
84 .read
= ppc_pci_io_read
,
85 .write
= ppc_pci_io_write
,
86 .endianness
= DEVICE_LITTLE_ENDIAN
,
89 static uint64_t ppc_intack_read(void *opaque
, hwaddr addr
,
92 return pic_read_irq(isa_pic
);
95 static const MemoryRegionOps PPC_intack_ops
= {
96 .read
= ppc_intack_read
,
102 static int prep_map_irq(PCIDevice
*pci_dev
, int irq_num
)
104 return (irq_num
+ (pci_dev
->devfn
>> 3)) & 1;
107 static void prep_set_irq(void *opaque
, int irq_num
, int level
)
109 qemu_irq
*pic
= opaque
;
111 qemu_set_irq(pic
[irq_num
] , level
);
114 static void raven_pcihost_realizefn(DeviceState
*d
, Error
**errp
)
116 SysBusDevice
*dev
= SYS_BUS_DEVICE(d
);
117 PCIHostState
*h
= PCI_HOST_BRIDGE(dev
);
118 PREPPCIState
*s
= RAVEN_PCI_HOST_BRIDGE(dev
);
119 MemoryRegion
*address_space_mem
= get_system_memory();
122 isa_mem_base
= 0xc0000000;
124 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
125 sysbus_init_irq(dev
, &s
->irq
[i
]);
128 pci_bus_irqs(&s
->pci_bus
, prep_set_irq
, prep_map_irq
, s
->irq
, PCI_NUM_PINS
);
130 memory_region_init_io(&h
->conf_mem
, OBJECT(h
), &pci_host_conf_be_ops
, s
,
132 sysbus_add_io(dev
, 0xcf8, &h
->conf_mem
);
133 sysbus_init_ioports(&h
->busdev
, 0xcf8, 1);
135 memory_region_init_io(&h
->data_mem
, OBJECT(h
), &pci_host_data_be_ops
, s
,
137 sysbus_add_io(dev
, 0xcfc, &h
->data_mem
);
138 sysbus_init_ioports(&h
->busdev
, 0xcfc, 1);
140 memory_region_init_io(&h
->mmcfg
, OBJECT(s
), &PPC_PCIIO_ops
, s
, "pciio", 0x00400000);
141 memory_region_add_subregion(address_space_mem
, 0x80800000, &h
->mmcfg
);
143 memory_region_init_io(&s
->intack
, OBJECT(s
), &PPC_intack_ops
, s
, "pci-intack", 1);
144 memory_region_add_subregion(address_space_mem
, 0xbffffff0, &s
->intack
);
146 /* TODO Remove once realize propagates to child devices. */
147 object_property_set_bool(OBJECT(&s
->pci_dev
), true, "realized", errp
);
150 static void raven_pcihost_initfn(Object
*obj
)
152 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
153 PREPPCIState
*s
= RAVEN_PCI_HOST_BRIDGE(obj
);
154 MemoryRegion
*address_space_mem
= get_system_memory();
155 MemoryRegion
*address_space_io
= get_system_io();
156 DeviceState
*pci_dev
;
158 pci_bus_new_inplace(&s
->pci_bus
, sizeof(s
->pci_bus
), DEVICE(obj
), NULL
,
159 address_space_mem
, address_space_io
, 0, TYPE_PCI_BUS
);
160 h
->bus
= &s
->pci_bus
;
162 object_initialize(&s
->pci_dev
, sizeof(s
->pci_dev
), TYPE_RAVEN_PCI_DEVICE
);
163 pci_dev
= DEVICE(&s
->pci_dev
);
164 qdev_set_parent_bus(pci_dev
, BUS(&s
->pci_bus
));
165 object_property_set_int(OBJECT(&s
->pci_dev
), PCI_DEVFN(0, 0), "addr",
167 qdev_prop_set_bit(pci_dev
, "multifunction", false);
170 static int raven_init(PCIDevice
*d
)
172 d
->config
[0x0C] = 0x08; // cache_line_size
173 d
->config
[0x0D] = 0x10; // latency_timer
174 d
->config
[0x34] = 0x00; // capabilities_pointer
179 static const VMStateDescription vmstate_raven
= {
182 .minimum_version_id
= 0,
183 .fields
= (VMStateField
[]) {
184 VMSTATE_PCI_DEVICE(dev
, RavenPCIState
),
185 VMSTATE_END_OF_LIST()
189 static void raven_class_init(ObjectClass
*klass
, void *data
)
191 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
192 DeviceClass
*dc
= DEVICE_CLASS(klass
);
194 k
->init
= raven_init
;
195 k
->vendor_id
= PCI_VENDOR_ID_MOTOROLA
;
196 k
->device_id
= PCI_DEVICE_ID_MOTOROLA_RAVEN
;
198 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
199 dc
->desc
= "PReP Host Bridge - Motorola Raven";
200 dc
->vmsd
= &vmstate_raven
;
202 * PCI-facing part of the host bridge, not usable without the
203 * host-facing part, which can't be device_add'ed, yet.
205 dc
->cannot_instantiate_with_device_add_yet
= true;
208 static const TypeInfo raven_info
= {
209 .name
= TYPE_RAVEN_PCI_DEVICE
,
210 .parent
= TYPE_PCI_DEVICE
,
211 .instance_size
= sizeof(RavenPCIState
),
212 .class_init
= raven_class_init
,
215 static void raven_pcihost_class_init(ObjectClass
*klass
, void *data
)
217 DeviceClass
*dc
= DEVICE_CLASS(klass
);
219 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
220 dc
->realize
= raven_pcihost_realizefn
;
224 static const TypeInfo raven_pcihost_info
= {
225 .name
= TYPE_RAVEN_PCI_HOST_BRIDGE
,
226 .parent
= TYPE_PCI_HOST_BRIDGE
,
227 .instance_size
= sizeof(PREPPCIState
),
228 .instance_init
= raven_pcihost_initfn
,
229 .class_init
= raven_pcihost_class_init
,
232 static void raven_register_types(void)
234 type_register_static(&raven_pcihost_info
);
235 type_register_static(&raven_info
);
238 type_init(raven_register_types
)