hw/intc/arm_gic_common.c

   1 /*
   2  * ARM GIC support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "gic_internal.h"
  22
  23 static void gic_pre_save(void *opaque)
  24 {
  25     GICState *s = (GICState *)opaque;
  26     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  27
  28     if (c->pre_save) {
  29         c->pre_save(s);
  30     }
  31 }
  32
  33 static int gic_post_load(void *opaque, int version_id)
  34 {
  35     GICState *s = (GICState *)opaque;
  36     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  37
  38     if (c->post_load) {
  39         c->post_load(s);
  40     }
  41     return 0;
  42 }
  43
  44 static const VMStateDescription vmstate_gic_irq_state = {
  45     .name = "arm_gic_irq_state",
  46     .version_id = 1,
  47     .minimum_version_id = 1,
  48     .fields = (VMStateField[]) {
  49         VMSTATE_UINT8(enabled, gic_irq_state),
  50         VMSTATE_UINT8(pending, gic_irq_state),
  51         VMSTATE_UINT8(active, gic_irq_state),
  52         VMSTATE_UINT8(level, gic_irq_state),
  53         VMSTATE_BOOL(model, gic_irq_state),
  54         VMSTATE_BOOL(edge_trigger, gic_irq_state),
  55         VMSTATE_END_OF_LIST()
  56     }
  57 };
  58
  59 static const VMStateDescription vmstate_gic = {
  60     .name = "arm_gic",
  61     .version_id = 7,
  62     .minimum_version_id = 7,
  63     .pre_save = gic_pre_save,
  64     .post_load = gic_post_load,
  65     .fields = (VMStateField[]) {
  66         VMSTATE_BOOL(enabled, GICState),
  67         VMSTATE_BOOL_ARRAY(cpu_enabled, GICState, GIC_NCPU),
  68         VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
  69                              vmstate_gic_irq_state, gic_irq_state),
  70         VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
  71         VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
  72         VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
  73         VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU),
  74         VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
  75         VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
  76         VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU),
  77         VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
  78         VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
  79         VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
  80         VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
  81         VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
  82         VMSTATE_END_OF_LIST()
  83     }
  84 };
  85
  86 static void arm_gic_common_realize(DeviceState *dev, Error **errp)
  87 {
  88     GICState *s = ARM_GIC_COMMON(dev);
  89     int num_irq = s->num_irq;
  90
  91     if (s->num_cpu > GIC_NCPU) {
  92         error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
  93                    s->num_cpu, GIC_NCPU);
  94         return;
  95     }
  96     s->num_irq += GIC_BASE_IRQ;
  97     if (s->num_irq > GIC_MAXIRQ) {
  98         error_setg(errp,
  99                    "requested %u interrupt lines exceeds GIC maximum %d",
 100                    num_irq, GIC_MAXIRQ);
 101         return;
 102     }
 103     /* ITLinesNumber is represented as (N / 32) - 1 (see
 104      * gic_dist_readb) so this is an implementation imposed
 105      * restriction, not an architectural one:
 106      */
 107     if (s->num_irq < 32 || (s->num_irq % 32)) {
 108         error_setg(errp,
 109                    "%d interrupt lines unsupported: not divisible by 32",
 110                    num_irq);
 111         return;
 112     }
 113 }
 114
 115 static void arm_gic_common_reset(DeviceState *dev)
 116 {
 117     GICState *s = ARM_GIC_COMMON(dev);
 118     int i;
 119     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
 120     for (i = 0 ; i < s->num_cpu; i++) {
 121         if (s->revision == REV_11MPCORE) {
 122             s->priority_mask[i] = 0xf0;
 123         } else {
 124             s->priority_mask[i] = 0;
 125         }
 126         s->current_pending[i] = 1023;
 127         s->running_irq[i] = 1023;
 128         s->running_priority[i] = 0x100;
 129         s->cpu_enabled[i] = false;
 130     }
 131     for (i = 0; i < 16; i++) {
 132         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 133         GIC_SET_EDGE_TRIGGER(i);
 134     }
 135     if (s->num_cpu == 1) {
 136         /* For uniprocessor GICs all interrupts always target the sole CPU */
 137         for (i = 0; i < GIC_MAXIRQ; i++) {
 138             s->irq_target[i] = 1;
 139         }
 140     }
 141     s->enabled = false;
 142 }
 143
 144 static Property arm_gic_common_properties[] = {
 145     DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
 146     DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
 147     /* Revision can be 1 or 2 for GIC architecture specification
 148      * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
 149      * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
 150      */
 151     DEFINE_PROP_UINT32("revision", GICState, revision, 1),
 152     DEFINE_PROP_END_OF_LIST(),
 153 };
 154
 155 static void arm_gic_common_class_init(ObjectClass *klass, void *data)
 156 {
 157     DeviceClass *dc = DEVICE_CLASS(klass);
 158
 159     dc->reset = arm_gic_common_reset;
 160     dc->realize = arm_gic_common_realize;
 161     dc->props = arm_gic_common_properties;
 162     dc->vmsd = &vmstate_gic;
 163 }
 164
 165 static const TypeInfo arm_gic_common_type = {
 166     .name = TYPE_ARM_GIC_COMMON,
 167     .parent = TYPE_SYS_BUS_DEVICE,
 168     .instance_size = sizeof(GICState),
 169     .class_size = sizeof(ARMGICCommonClass),
 170     .class_init = arm_gic_common_class_init,
 171     .abstract = true,
 172 };
 173
 174 static void register_types(void)
 175 {
 176     type_register_static(&arm_gic_common_type);
 177 }
 178
 179 type_init(register_types)