hw/timer/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/ptimer.h"
  28 #include "qemu/log.h"
  29 #include "qemu/main-loop.h"
  30
  31 #define D(x)
  32
  33 #define R_TCSR     0
  34 #define R_TLR      1
  35 #define R_TCR      2
  36 #define R_MAX      4
  37
  38 #define TCSR_MDT        (1<<0)
  39 #define TCSR_UDT        (1<<1)
  40 #define TCSR_GENT       (1<<2)
  41 #define TCSR_CAPT       (1<<3)
  42 #define TCSR_ARHT       (1<<4)
  43 #define TCSR_LOAD       (1<<5)
  44 #define TCSR_ENIT       (1<<6)
  45 #define TCSR_ENT        (1<<7)
  46 #define TCSR_TINT       (1<<8)
  47 #define TCSR_PWMA       (1<<9)
  48 #define TCSR_ENALL      (1<<10)
  49
  50 struct xlx_timer
  51 {
  52     QEMUBH *bh;
  53     ptimer_state *ptimer;
  54     void *parent;
  55     int nr; /* for debug.  */
  56
  57     unsigned long timer_div;
  58
  59     uint32_t regs[R_MAX];
  60 };
  61
  62 #define TYPE_XILINX_TIMER "xlnx.xps-timer"
  63 #define XILINX_TIMER(obj) \
  64     OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
  65
  66 struct timerblock
  67 {
  68     SysBusDevice parent_obj;
  69
  70     MemoryRegion mmio;
  71     qemu_irq irq;
  72     uint8_t one_timer_only;
  73     uint32_t freq_hz;
  74     struct xlx_timer *timers;
  75 };
  76
  77 static inline unsigned int num_timers(struct timerblock *t)
  78 {
  79     return 2 - t->one_timer_only;
  80 }
  81
  82 static inline unsigned int timer_from_addr(hwaddr addr)
  83 {
  84     /* Timers get a 4x32bit control reg area each.  */
  85     return addr >> 2;
  86 }
  87
  88 static void timer_update_irq(struct timerblock *t)
  89 {
  90     unsigned int i, irq = 0;
  91     uint32_t csr;
  92
  93     for (i = 0; i < num_timers(t); i++) {
  94         csr = t->timers[i].regs[R_TCSR];
  95         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  96     }
  97
  98     /* All timers within the same slave share a single IRQ line.  */
  99     qemu_set_irq(t->irq, !!irq);
 100 }
 101
 102 static uint64_t
 103 timer_read(void *opaque, hwaddr addr, unsigned int size)
 104 {
 105     struct timerblock *t = opaque;
 106     struct xlx_timer *xt;
 107     uint32_t r = 0;
 108     unsigned int timer;
 109
 110     addr >>= 2;
 111     timer = timer_from_addr(addr);
 112     xt = &t->timers[timer];
 113     /* Further decoding to address a specific timers reg.  */
 114     addr &= 0x3;
 115     switch (addr)
 116     {
 117         case R_TCR:
 118                 r = ptimer_get_count(xt->ptimer);
 119                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 120                     r = ~r;
 121                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 122                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 123             break;
 124         default:
 125             if (addr < ARRAY_SIZE(xt->regs))
 126                 r = xt->regs[addr];
 127             break;
 128
 129     }
 130     D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 131     return r;
 132 }
 133
 134 static void timer_enable(struct xlx_timer *xt)
 135 {
 136     uint64_t count;
 137
 138     D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
 139               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 140
 141     ptimer_stop(xt->ptimer);
 142
 143     if (xt->regs[R_TCSR] & TCSR_UDT)
 144         count = xt->regs[R_TLR];
 145     else
 146         count = ~0 - xt->regs[R_TLR];
 147     ptimer_set_limit(xt->ptimer, count, 1);
 148     ptimer_run(xt->ptimer, 1);
 149 }
 150
 151 static void
 152 timer_write(void *opaque, hwaddr addr,
 153             uint64_t val64, unsigned int size)
 154 {
 155     struct timerblock *t = opaque;
 156     struct xlx_timer *xt;
 157     unsigned int timer;
 158     uint32_t value = val64;
 159
 160     addr >>= 2;
 161     timer = timer_from_addr(addr);
 162     xt = &t->timers[timer];
 163     D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
 164              __func__, addr * 4, value, timer, addr & 3));
 165     /* Further decoding to address a specific timers reg.  */
 166     addr &= 3;
 167     switch (addr)
 168     {
 169         case R_TCSR:
 170             if (value & TCSR_TINT)
 171                 value &= ~TCSR_TINT;
 172
 173             xt->regs[addr] = value & 0x7ff;
 174             if (value & TCSR_ENT)
 175                 timer_enable(xt);
 176             break;
 177
 178         default:
 179             if (addr < ARRAY_SIZE(xt->regs))
 180                 xt->regs[addr] = value;
 181             break;
 182     }
 183     timer_update_irq(t);
 184 }
 185
 186 static const MemoryRegionOps timer_ops = {
 187     .read = timer_read,
 188     .write = timer_write,
 189     .endianness = DEVICE_NATIVE_ENDIAN,
 190     .valid = {
 191         .min_access_size = 4,
 192         .max_access_size = 4
 193     }
 194 };
 195
 196 static void timer_hit(void *opaque)
 197 {
 198     struct xlx_timer *xt = opaque;
 199     struct timerblock *t = xt->parent;
 200     D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
 201     xt->regs[R_TCSR] |= TCSR_TINT;
 202
 203     if (xt->regs[R_TCSR] & TCSR_ARHT)
 204         timer_enable(xt);
 205     timer_update_irq(t);
 206 }
 207
 208 static void xilinx_timer_realize(DeviceState *dev, Error **errp)
 209 {
 210     struct timerblock *t = XILINX_TIMER(dev);
 211     unsigned int i;
 212
 213     /* Init all the ptimers.  */
 214     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
 215     for (i = 0; i < num_timers(t); i++) {
 216         struct xlx_timer *xt = &t->timers[i];
 217
 218         xt->parent = t;
 219         xt->nr = i;
 220         xt->bh = qemu_bh_new(timer_hit, xt);
 221         xt->ptimer = ptimer_init(xt->bh);
 222         ptimer_set_freq(xt->ptimer, t->freq_hz);
 223     }
 224
 225     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
 226                           R_MAX * 4 * num_timers(t));
 227     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
 228 }
 229
 230 static void xilinx_timer_init(Object *obj)
 231 {
 232     struct timerblock *t = XILINX_TIMER(obj);
 233
 234     /* All timers share a single irq line.  */
 235     sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
 236 }
 237
 238 static Property xilinx_timer_properties[] = {
 239     DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
 240                                                                 62 * 1000000),
 241     DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
 242     DEFINE_PROP_END_OF_LIST(),
 243 };
 244
 245 static void xilinx_timer_class_init(ObjectClass *klass, void *data)
 246 {
 247     DeviceClass *dc = DEVICE_CLASS(klass);
 248
 249     dc->realize = xilinx_timer_realize;
 250     dc->props = xilinx_timer_properties;
 251 }
 252
 253 static const TypeInfo xilinx_timer_info = {
 254     .name          = TYPE_XILINX_TIMER,
 255     .parent        = TYPE_SYS_BUS_DEVICE,
 256     .instance_size = sizeof(struct timerblock),
 257     .instance_init = xilinx_timer_init,
 258     .class_init    = xilinx_timer_class_init,
 259 };
 260
 261 static void xilinx_timer_register_types(void)
 262 {
 263     type_register_static(&xilinx_timer_info);
 264 }
 265
 266 type_init(xilinx_timer_register_types)