rfifolock: no need to get thread identifier when nesting
[qemu/ar7.git] / hw / display / vga_int.h
blobbdb43a5a3476cd5cf23528c9253e75eca665f9d9
1 /*
2 * QEMU internal VGA defines.
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #ifndef HW_VGA_INT_H
25 #define HW_VGA_INT_H 1
27 #include <hw/hw.h>
28 #include "exec/memory.h"
30 #define ST01_V_RETRACE 0x08
31 #define ST01_DISP_ENABLE 0x01
33 #define VBE_DISPI_MAX_XRES 16000
34 #define VBE_DISPI_MAX_YRES 12000
35 #define VBE_DISPI_MAX_BPP 32
37 #define VBE_DISPI_INDEX_ID 0x0
38 #define VBE_DISPI_INDEX_XRES 0x1
39 #define VBE_DISPI_INDEX_YRES 0x2
40 #define VBE_DISPI_INDEX_BPP 0x3
41 #define VBE_DISPI_INDEX_ENABLE 0x4
42 #define VBE_DISPI_INDEX_BANK 0x5
43 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
44 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
45 #define VBE_DISPI_INDEX_X_OFFSET 0x8
46 #define VBE_DISPI_INDEX_Y_OFFSET 0x9
47 #define VBE_DISPI_INDEX_NB 0xa /* size of vbe_regs[] */
48 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */
50 #define VBE_DISPI_ID0 0xB0C0
51 #define VBE_DISPI_ID1 0xB0C1
52 #define VBE_DISPI_ID2 0xB0C2
53 #define VBE_DISPI_ID3 0xB0C3
54 #define VBE_DISPI_ID4 0xB0C4
55 #define VBE_DISPI_ID5 0xB0C5
57 #define VBE_DISPI_DISABLED 0x00
58 #define VBE_DISPI_ENABLED 0x01
59 #define VBE_DISPI_GETCAPS 0x02
60 #define VBE_DISPI_8BIT_DAC 0x20
61 #define VBE_DISPI_LFB_ENABLED 0x40
62 #define VBE_DISPI_NOCLEARMEM 0x80
64 #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
66 #define CH_ATTR_SIZE (160 * 100)
67 #define VGA_MAX_HEIGHT 2048
69 struct vga_precise_retrace {
70 int64_t ticks_per_char;
71 int64_t total_chars;
72 int htotal;
73 int hstart;
74 int hend;
75 int vstart;
76 int vend;
77 int freq;
80 union vga_retrace {
81 struct vga_precise_retrace precise;
84 struct VGACommonState;
85 typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
86 typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
88 typedef struct VGACommonState {
89 MemoryRegion *legacy_address_space;
90 uint8_t *vram_ptr;
91 MemoryRegion vram;
92 MemoryRegion vram_vbe;
93 uint32_t vram_size;
94 uint32_t vram_size_mb; /* property */
95 uint32_t vbe_size;
96 uint32_t latch;
97 bool has_chain4_alias;
98 MemoryRegion chain4_alias;
99 uint8_t sr_index;
100 uint8_t sr[256];
101 uint8_t gr_index;
102 uint8_t gr[256];
103 uint8_t ar_index;
104 uint8_t ar[21];
105 int ar_flip_flop;
106 uint8_t cr_index;
107 uint8_t cr[256]; /* CRT registers */
108 uint8_t msr; /* Misc Output Register */
109 uint8_t fcr; /* Feature Control Register */
110 uint8_t st00; /* status 0 */
111 uint8_t st01; /* status 1 */
112 uint8_t dac_state;
113 uint8_t dac_sub_index;
114 uint8_t dac_read_index;
115 uint8_t dac_write_index;
116 uint8_t dac_cache[3]; /* used when writing */
117 int dac_8bit;
118 uint8_t palette[768];
119 int32_t bank_offset;
120 int (*get_bpp)(struct VGACommonState *s);
121 void (*get_offsets)(struct VGACommonState *s,
122 uint32_t *pline_offset,
123 uint32_t *pstart_addr,
124 uint32_t *pline_compare);
125 void (*get_resolution)(struct VGACommonState *s,
126 int *pwidth,
127 int *pheight);
128 PortioList vga_port_list;
129 PortioList vbe_port_list;
130 /* bochs vbe state */
131 uint16_t vbe_index;
132 uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
133 uint32_t vbe_start_addr;
134 uint32_t vbe_line_offset;
135 uint32_t vbe_bank_mask;
136 int vbe_mapped;
137 /* display refresh support */
138 QemuConsole *con;
139 uint32_t font_offsets[2];
140 int graphic_mode;
141 uint8_t shift_control;
142 uint8_t double_scan;
143 uint32_t line_offset;
144 uint32_t line_compare;
145 uint32_t start_addr;
146 uint32_t plane_updated;
147 uint32_t last_line_offset;
148 uint8_t last_cw, last_ch;
149 uint32_t last_width, last_height; /* in chars or pixels */
150 uint32_t last_scr_width, last_scr_height; /* in pixels */
151 uint32_t last_depth; /* in bits */
152 bool last_byteswap;
153 bool force_shadow;
154 uint8_t cursor_start, cursor_end;
155 bool cursor_visible_phase;
156 int64_t cursor_blink_time;
157 uint32_t cursor_offset;
158 const GraphicHwOps *hw_ops;
159 bool full_update_text;
160 bool full_update_gfx;
161 bool big_endian_fb;
162 bool default_endian_fb;
163 /* hardware mouse cursor support */
164 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
165 uint32_t hw_cursor_x;
166 uint32_t hw_cursor_y;
167 void (*cursor_invalidate)(struct VGACommonState *s);
168 void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
169 /* tell for each page if it has been updated since the last time */
170 uint32_t last_palette[256];
171 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
172 /* retrace */
173 vga_retrace_fn retrace;
174 vga_update_retrace_info_fn update_retrace_info;
175 union vga_retrace retrace_info;
176 uint8_t is_vbe_vmstate;
177 } VGACommonState;
179 static inline int c6_to_8(int v)
181 int b;
182 v &= 0x3f;
183 b = v & 1;
184 return (v << 2) | (b << 1) | b;
187 void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate);
188 void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
189 MemoryRegion *address_space_io, bool init_vga_ports);
190 MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
191 const MemoryRegionPortio **vga_ports,
192 const MemoryRegionPortio **vbe_ports);
193 void vga_common_reset(VGACommonState *s);
195 void vga_sync_dirty_bitmap(VGACommonState *s);
196 void vga_dirty_log_start(VGACommonState *s);
197 void vga_dirty_log_stop(VGACommonState *s);
199 extern const VMStateDescription vmstate_vga_common;
200 uint32_t vga_ioport_read(void *opaque, uint32_t addr);
201 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
202 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr);
203 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val);
204 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
206 int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
208 void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *address_space);
209 uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr);
210 void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val);
211 void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val);
213 extern const uint8_t sr_mask[8];
214 extern const uint8_t gr_mask[16];
216 #define VGABIOS_FILENAME "vgabios.bin"
217 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
219 extern const MemoryRegionOps vga_mem_ops;
221 /* vga-pci.c */
222 void pci_std_vga_mmio_region_init(VGACommonState *s,
223 MemoryRegion *parent,
224 MemoryRegion *subs,
225 bool qext);
227 #endif