2 * Arm SSE (Subsystems for Embedded): IoTKit
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "qapi/error.h"
16 #include "hw/sysbus.h"
17 #include "hw/registerfields.h"
18 #include "hw/arm/armsse.h"
19 #include "hw/arm/arm.h"
21 /* Format of the System Information block SYS_CONFIG register */
22 typedef enum SysConfigFormat
{
32 SysConfigFormat sys_config_format
;
35 static const ARMSSEInfo armsse_variants
[] = {
40 .sys_version
= 0x41743,
41 .sys_config_format
= IoTKitFormat
,
45 static uint32_t armsse_sys_config_value(ARMSSE
*s
, const ARMSSEInfo
*info
)
47 /* Return the SYS_CONFIG value for this SSE */
50 switch (info
->sys_config_format
) {
53 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
54 sys_config
= deposit32(sys_config
, 4, 4, s
->sram_addr_width
- 12);
58 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
59 sys_config
= deposit32(sys_config
, 4, 5, s
->sram_addr_width
);
60 sys_config
= deposit32(sys_config
, 24, 4, 2);
61 if (info
->num_cpus
> 1) {
62 sys_config
= deposit32(sys_config
, 10, 1, 1);
63 sys_config
= deposit32(sys_config
, 20, 4, info
->sram_banks
- 1);
64 sys_config
= deposit32(sys_config
, 28, 4, 2);
68 g_assert_not_reached();
73 /* Clock frequency in HZ of the 32KHz "slow clock" */
74 #define S32KCLK (32 * 1000)
76 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
77 static bool irq_is_common
[32] = {
79 /* 6, 7: per-CPU MHU interrupts */
81 /* 13: per-CPU icache interrupt */
87 /* 28, 29: per-CPU CTI interrupts */
88 /* 30, 31: reserved */
91 /* Create an alias region of @size bytes starting at @base
92 * which mirrors the memory starting at @orig.
94 static void make_alias(ARMSSE
*s
, MemoryRegion
*mr
, const char *name
,
95 hwaddr base
, hwaddr size
, hwaddr orig
)
97 memory_region_init_alias(mr
, NULL
, name
, &s
->container
, orig
, size
);
98 /* The alias is even lower priority than unimplemented_device regions */
99 memory_region_add_subregion_overlap(&s
->container
, base
, mr
, -1500);
102 static void irq_status_forwarder(void *opaque
, int n
, int level
)
104 qemu_irq destirq
= opaque
;
106 qemu_set_irq(destirq
, level
);
109 static void nsccfg_handler(void *opaque
, int n
, int level
)
111 ARMSSE
*s
= ARMSSE(opaque
);
116 static void armsse_forward_ppc(ARMSSE
*s
, const char *ppcname
, int ppcnum
)
118 /* Each of the 4 AHB and 4 APB PPCs that might be present in a
119 * system using the ARMSSE has a collection of control lines which
120 * are provided by the security controller and which we want to
121 * expose as control lines on the ARMSSE device itself, so the
122 * code using the ARMSSE can wire them up to the PPCs.
124 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[ppcnum
];
125 DeviceState
*armssedev
= DEVICE(s
);
126 DeviceState
*dev_secctl
= DEVICE(&s
->secctl
);
127 DeviceState
*dev_splitter
= DEVICE(splitter
);
130 name
= g_strdup_printf("%s_nonsec", ppcname
);
131 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
133 name
= g_strdup_printf("%s_ap", ppcname
);
134 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
136 name
= g_strdup_printf("%s_irq_enable", ppcname
);
137 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
139 name
= g_strdup_printf("%s_irq_clear", ppcname
);
140 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
143 /* irq_status is a little more tricky, because we need to
144 * split it so we can send it both to the security controller
145 * and to our OR gate for the NVIC interrupt line.
146 * Connect up the splitter's outputs, and create a GPIO input
147 * which will pass the line state to the input splitter.
149 name
= g_strdup_printf("%s_irq_status", ppcname
);
150 qdev_connect_gpio_out(dev_splitter
, 0,
151 qdev_get_gpio_in_named(dev_secctl
,
153 qdev_connect_gpio_out(dev_splitter
, 1,
154 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), ppcnum
));
155 s
->irq_status_in
[ppcnum
] = qdev_get_gpio_in(dev_splitter
, 0);
156 qdev_init_gpio_in_named_with_opaque(armssedev
, irq_status_forwarder
,
157 s
->irq_status_in
[ppcnum
], name
, 1);
161 static void armsse_forward_sec_resp_cfg(ARMSSE
*s
)
163 /* Forward the 3rd output from the splitter device as a
164 * named GPIO output of the armsse object.
166 DeviceState
*dev
= DEVICE(s
);
167 DeviceState
*dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
169 qdev_init_gpio_out_named(dev
, &s
->sec_resp_cfg
, "sec_resp_cfg", 1);
170 s
->sec_resp_cfg_in
= qemu_allocate_irq(irq_status_forwarder
,
172 qdev_connect_gpio_out(dev_splitter
, 2, s
->sec_resp_cfg_in
);
175 static void armsse_init(Object
*obj
)
177 ARMSSE
*s
= ARMSSE(obj
);
178 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(obj
);
179 const ARMSSEInfo
*info
= asc
->info
;
182 assert(info
->sram_banks
<= MAX_SRAM_BANKS
);
183 assert(info
->num_cpus
<= SSE_MAX_CPUS
);
185 memory_region_init(&s
->container
, obj
, "armsse-container", UINT64_MAX
);
187 for (i
= 0; i
< info
->num_cpus
; i
++) {
189 * We put each CPU in its own cluster as they are logically
190 * distinct and may be configured differently.
194 name
= g_strdup_printf("cluster%d", i
);
195 object_initialize_child(obj
, name
, &s
->cluster
[i
],
196 sizeof(s
->cluster
[i
]), TYPE_CPU_CLUSTER
,
198 qdev_prop_set_uint32(DEVICE(&s
->cluster
[i
]), "cluster-id", i
);
201 name
= g_strdup_printf("armv7m%d", i
);
202 sysbus_init_child_obj(OBJECT(&s
->cluster
[i
]), name
,
203 &s
->armv7m
[i
], sizeof(s
->armv7m
), TYPE_ARMV7M
);
204 qdev_prop_set_string(DEVICE(&s
->armv7m
[i
]), "cpu-type",
205 ARM_CPU_TYPE_NAME("cortex-m33"));
207 name
= g_strdup_printf("arm-sse-cpu-container%d", i
);
208 memory_region_init(&s
->cpu_container
[i
], obj
, name
, UINT64_MAX
);
211 name
= g_strdup_printf("arm-sse-container-alias%d", i
);
212 memory_region_init_alias(&s
->container_alias
[i
- 1], obj
,
213 name
, &s
->container
, 0, UINT64_MAX
);
218 sysbus_init_child_obj(obj
, "secctl", &s
->secctl
, sizeof(s
->secctl
),
220 sysbus_init_child_obj(obj
, "apb-ppc0", &s
->apb_ppc0
, sizeof(s
->apb_ppc0
),
222 sysbus_init_child_obj(obj
, "apb-ppc1", &s
->apb_ppc1
, sizeof(s
->apb_ppc1
),
224 for (i
= 0; i
< info
->sram_banks
; i
++) {
225 char *name
= g_strdup_printf("mpc%d", i
);
226 sysbus_init_child_obj(obj
, name
, &s
->mpc
[i
],
227 sizeof(s
->mpc
[i
]), TYPE_TZ_MPC
);
230 object_initialize_child(obj
, "mpc-irq-orgate", &s
->mpc_irq_orgate
,
231 sizeof(s
->mpc_irq_orgate
), TYPE_OR_IRQ
,
234 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
235 char *name
= g_strdup_printf("mpc-irq-splitter-%d", i
);
236 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
238 object_initialize_child(obj
, name
, splitter
, sizeof(*splitter
),
239 TYPE_SPLIT_IRQ
, &error_abort
, NULL
);
242 sysbus_init_child_obj(obj
, "timer0", &s
->timer0
, sizeof(s
->timer0
),
243 TYPE_CMSDK_APB_TIMER
);
244 sysbus_init_child_obj(obj
, "timer1", &s
->timer1
, sizeof(s
->timer1
),
245 TYPE_CMSDK_APB_TIMER
);
246 sysbus_init_child_obj(obj
, "s32ktimer", &s
->s32ktimer
, sizeof(s
->s32ktimer
),
247 TYPE_CMSDK_APB_TIMER
);
248 sysbus_init_child_obj(obj
, "dualtimer", &s
->dualtimer
, sizeof(s
->dualtimer
),
249 TYPE_CMSDK_APB_DUALTIMER
);
250 sysbus_init_child_obj(obj
, "s32kwatchdog", &s
->s32kwatchdog
,
251 sizeof(s
->s32kwatchdog
), TYPE_CMSDK_APB_WATCHDOG
);
252 sysbus_init_child_obj(obj
, "nswatchdog", &s
->nswatchdog
,
253 sizeof(s
->nswatchdog
), TYPE_CMSDK_APB_WATCHDOG
);
254 sysbus_init_child_obj(obj
, "swatchdog", &s
->swatchdog
,
255 sizeof(s
->swatchdog
), TYPE_CMSDK_APB_WATCHDOG
);
256 sysbus_init_child_obj(obj
, "armsse-sysctl", &s
->sysctl
,
257 sizeof(s
->sysctl
), TYPE_IOTKIT_SYSCTL
);
258 sysbus_init_child_obj(obj
, "armsse-sysinfo", &s
->sysinfo
,
259 sizeof(s
->sysinfo
), TYPE_IOTKIT_SYSINFO
);
260 object_initialize_child(obj
, "nmi-orgate", &s
->nmi_orgate
,
261 sizeof(s
->nmi_orgate
), TYPE_OR_IRQ
,
263 object_initialize_child(obj
, "ppc-irq-orgate", &s
->ppc_irq_orgate
,
264 sizeof(s
->ppc_irq_orgate
), TYPE_OR_IRQ
,
266 object_initialize_child(obj
, "sec-resp-splitter", &s
->sec_resp_splitter
,
267 sizeof(s
->sec_resp_splitter
), TYPE_SPLIT_IRQ
,
269 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
270 char *name
= g_strdup_printf("ppc-irq-splitter-%d", i
);
271 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[i
];
273 object_initialize_child(obj
, name
, splitter
, sizeof(*splitter
),
274 TYPE_SPLIT_IRQ
, &error_abort
, NULL
);
277 if (info
->num_cpus
> 1) {
278 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
279 if (irq_is_common
[i
]) {
280 char *name
= g_strdup_printf("cpu-irq-splitter%d", i
);
281 SplitIRQ
*splitter
= &s
->cpu_irq_splitter
[i
];
283 object_initialize_child(obj
, name
, splitter
, sizeof(*splitter
),
284 TYPE_SPLIT_IRQ
, &error_abort
, NULL
);
291 static void armsse_exp_irq(void *opaque
, int n
, int level
)
293 qemu_irq
*irqarray
= opaque
;
295 qemu_set_irq(irqarray
[n
], level
);
298 static void armsse_mpcexp_status(void *opaque
, int n
, int level
)
300 ARMSSE
*s
= ARMSSE(opaque
);
301 qemu_set_irq(s
->mpcexp_status_in
[n
], level
);
304 static qemu_irq
armsse_get_common_irq_in(ARMSSE
*s
, int irqno
)
307 * Return a qemu_irq which can be used to signal IRQ n to
308 * all CPUs in the SSE.
310 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(s
);
311 const ARMSSEInfo
*info
= asc
->info
;
313 assert(irq_is_common
[irqno
]);
315 if (info
->num_cpus
== 1) {
316 /* Only one CPU -- just connect directly to it */
317 return qdev_get_gpio_in(DEVICE(&s
->armv7m
[0]), irqno
);
319 /* Connect to the splitter which feeds all CPUs */
320 return qdev_get_gpio_in(DEVICE(&s
->cpu_irq_splitter
[irqno
]), 0);
324 static void armsse_realize(DeviceState
*dev
, Error
**errp
)
326 ARMSSE
*s
= ARMSSE(dev
);
327 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(dev
);
328 const ARMSSEInfo
*info
= asc
->info
;
332 SysBusDevice
*sbd_apb_ppc0
;
333 SysBusDevice
*sbd_secctl
;
334 DeviceState
*dev_apb_ppc0
;
335 DeviceState
*dev_apb_ppc1
;
336 DeviceState
*dev_secctl
;
337 DeviceState
*dev_splitter
;
338 uint32_t addr_width_max
;
340 if (!s
->board_memory
) {
341 error_setg(errp
, "memory property was not set");
345 if (!s
->mainclk_frq
) {
346 error_setg(errp
, "MAINCLK property was not set");
350 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
351 assert(is_power_of_2(info
->sram_banks
));
352 addr_width_max
= 24 - ctz32(info
->sram_banks
);
353 if (s
->sram_addr_width
< 1 || s
->sram_addr_width
> addr_width_max
) {
354 error_setg(errp
, "SRAM_ADDR_WIDTH must be between 1 and %d",
359 /* Handling of which devices should be available only to secure
360 * code is usually done differently for M profile than for A profile.
361 * Instead of putting some devices only into the secure address space,
362 * devices exist in both address spaces but with hard-wired security
363 * permissions that will cause the CPU to fault for non-secure accesses.
365 * The ARMSSE has an IDAU (Implementation Defined Access Unit),
366 * which specifies hard-wired security permissions for different
367 * areas of the physical address space. For the ARMSSE IDAU, the
368 * top 4 bits of the physical address are the IDAU region ID, and
369 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
370 * region, otherwise it is an S region.
372 * The various devices and RAMs are generally all mapped twice,
373 * once into a region that the IDAU defines as secure and once
374 * into a non-secure region. They sit behind either a Memory
375 * Protection Controller (for RAM) or a Peripheral Protection
376 * Controller (for devices), which allow a more fine grained
377 * configuration of whether non-secure accesses are permitted.
379 * (The other place that guest software can configure security
380 * permissions is in the architected SAU (Security Attribution
381 * Unit), which is entirely inside the CPU. The IDAU can upgrade
382 * the security attributes for a region to more restrictive than
383 * the SAU specifies, but cannot downgrade them.)
385 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
386 * 0x20000000..0x2007ffff 32KB FPGA block RAM
387 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
388 * 0x40000000..0x4000ffff base peripheral region 1
389 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
390 * 0x40020000..0x4002ffff system control element peripherals
391 * 0x40080000..0x400fffff base peripheral region 2
392 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
395 memory_region_add_subregion_overlap(&s
->container
, 0, s
->board_memory
, -2);
397 for (i
= 0; i
< info
->num_cpus
; i
++) {
398 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[i
]);
399 Object
*cpuobj
= OBJECT(&s
->armv7m
[i
]);
403 qdev_prop_set_uint32(cpudev
, "num-irq", s
->exp_numirq
+ 32);
405 * In real hardware the initial Secure VTOR is set from the INITSVTOR0
406 * register in the IoT Kit System Control Register block, and the
407 * initial value of that is in turn specifiable by the FPGA that
408 * instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
409 * and simply set the CPU's init-svtor to the IoT Kit default value.
410 * In SSE-200 the situation is similar, except that the default value
411 * is a reset-time signal input. Typically a board using the SSE-200
412 * will have a system control processor whose boot firmware initializes
413 * the INITSVTOR* registers before powering up the CPUs in any case,
414 * so the hardware's default value doesn't matter. QEMU doesn't emulate
415 * the control processor, so instead we behave in the way that the
416 * firmware does. All boards currently known about have firmware that
417 * sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, like the
418 * IoTKit default. We can make this more configurable if necessary.
420 qdev_prop_set_uint32(cpudev
, "init-svtor", 0x10000000);
422 * Start all CPUs except CPU0 powered down. In real hardware it is
423 * a configurable property of the SSE-200 which CPUs start powered up
424 * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
425 * the boards we care about start CPU0 and leave CPU1 powered off,
426 * we hard-code that for now. We can add QOM properties for this
427 * later if necessary.
430 object_property_set_bool(cpuobj
, true, "start-powered-off", &err
);
432 error_propagate(errp
, err
);
438 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
439 &s
->container_alias
[i
- 1], -1);
441 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
444 object_property_set_link(cpuobj
, OBJECT(&s
->cpu_container
[i
]),
447 error_propagate(errp
, err
);
450 object_property_set_link(cpuobj
, OBJECT(s
), "idau", &err
);
452 error_propagate(errp
, err
);
455 object_property_set_bool(cpuobj
, true, "realized", &err
);
457 error_propagate(errp
, err
);
461 * The cluster must be realized after the armv7m container, as
462 * the container's CPU object is only created on realize, and the
463 * CPU must exist and have been parented into the cluster before
464 * the cluster is realized.
466 object_property_set_bool(OBJECT(&s
->cluster
[i
]),
467 true, "realized", &err
);
469 error_propagate(errp
, err
);
473 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
474 s
->exp_irqs
[i
] = g_new(qemu_irq
, s
->exp_numirq
);
475 for (j
= 0; j
< s
->exp_numirq
; j
++) {
476 s
->exp_irqs
[i
][j
] = qdev_get_gpio_in(cpudev
, i
+ 32);
479 gpioname
= g_strdup("EXP_IRQ");
481 gpioname
= g_strdup_printf("EXP_CPU%d_IRQ", i
);
483 qdev_init_gpio_in_named_with_opaque(dev
, armsse_exp_irq
,
485 gpioname
, s
->exp_numirq
);
489 /* Wire up the splitters that connect common IRQs to all CPUs */
490 if (info
->num_cpus
> 1) {
491 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
492 if (irq_is_common
[i
]) {
493 Object
*splitter
= OBJECT(&s
->cpu_irq_splitter
[i
]);
494 DeviceState
*devs
= DEVICE(splitter
);
497 object_property_set_int(splitter
, info
->num_cpus
,
500 error_propagate(errp
, err
);
503 object_property_set_bool(splitter
, true, "realized", &err
);
505 error_propagate(errp
, err
);
508 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
509 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
511 qdev_connect_gpio_out(devs
, cpunum
,
512 qdev_get_gpio_in(cpudev
, i
));
518 /* Set up the big aliases first */
519 make_alias(s
, &s
->alias1
, "alias 1", 0x10000000, 0x10000000, 0x00000000);
520 make_alias(s
, &s
->alias2
, "alias 2", 0x30000000, 0x10000000, 0x20000000);
521 /* The 0x50000000..0x5fffffff region is not a pure alias: it has
522 * a few extra devices that only appear there (generally the
523 * control interfaces for the protection controllers).
524 * We implement this by mapping those devices over the top of this
525 * alias MR at a higher priority.
527 make_alias(s
, &s
->alias3
, "alias 3", 0x50000000, 0x10000000, 0x40000000);
530 /* Security controller */
531 object_property_set_bool(OBJECT(&s
->secctl
), true, "realized", &err
);
533 error_propagate(errp
, err
);
536 sbd_secctl
= SYS_BUS_DEVICE(&s
->secctl
);
537 dev_secctl
= DEVICE(&s
->secctl
);
538 sysbus_mmio_map(sbd_secctl
, 0, 0x50080000);
539 sysbus_mmio_map(sbd_secctl
, 1, 0x40080000);
541 s
->nsc_cfg_in
= qemu_allocate_irq(nsccfg_handler
, s
, 1);
542 qdev_connect_gpio_out_named(dev_secctl
, "nsc_cfg", 0, s
->nsc_cfg_in
);
544 /* The sec_resp_cfg output from the security controller must be split into
545 * multiple lines, one for each of the PPCs within the ARMSSE and one
546 * that will be an output from the ARMSSE to the system.
548 object_property_set_int(OBJECT(&s
->sec_resp_splitter
), 3,
551 error_propagate(errp
, err
);
554 object_property_set_bool(OBJECT(&s
->sec_resp_splitter
), true,
557 error_propagate(errp
, err
);
560 dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
561 qdev_connect_gpio_out_named(dev_secctl
, "sec_resp_cfg", 0,
562 qdev_get_gpio_in(dev_splitter
, 0));
564 /* Each SRAM bank lives behind its own Memory Protection Controller */
565 for (i
= 0; i
< info
->sram_banks
; i
++) {
566 char *ramname
= g_strdup_printf("armsse.sram%d", i
);
567 SysBusDevice
*sbd_mpc
;
568 uint32_t sram_bank_size
= 1 << s
->sram_addr_width
;
570 memory_region_init_ram(&s
->sram
[i
], NULL
, ramname
,
571 sram_bank_size
, &err
);
574 error_propagate(errp
, err
);
577 object_property_set_link(OBJECT(&s
->mpc
[i
]), OBJECT(&s
->sram
[i
]),
580 error_propagate(errp
, err
);
583 object_property_set_bool(OBJECT(&s
->mpc
[i
]), true, "realized", &err
);
585 error_propagate(errp
, err
);
588 /* Map the upstream end of the MPC into the right place... */
589 sbd_mpc
= SYS_BUS_DEVICE(&s
->mpc
[i
]);
590 memory_region_add_subregion(&s
->container
,
591 0x20000000 + i
* sram_bank_size
,
592 sysbus_mmio_get_region(sbd_mpc
, 1));
593 /* ...and its register interface */
594 memory_region_add_subregion(&s
->container
, 0x50083000 + i
* 0x1000,
595 sysbus_mmio_get_region(sbd_mpc
, 0));
598 /* We must OR together lines from the MPC splitters to go to the NVIC */
599 object_property_set_int(OBJECT(&s
->mpc_irq_orgate
),
600 IOTS_NUM_EXP_MPC
+ info
->sram_banks
,
603 error_propagate(errp
, err
);
606 object_property_set_bool(OBJECT(&s
->mpc_irq_orgate
), true,
609 error_propagate(errp
, err
);
612 qdev_connect_gpio_out(DEVICE(&s
->mpc_irq_orgate
), 0,
613 armsse_get_common_irq_in(s
, 9));
615 /* Devices behind APB PPC0:
618 * 0x40002000: dual timer
619 * We must configure and realize each downstream device and connect
620 * it to the appropriate PPC port; then we can realize the PPC and
621 * map its upstream ends to the right place in the container.
623 qdev_prop_set_uint32(DEVICE(&s
->timer0
), "pclk-frq", s
->mainclk_frq
);
624 object_property_set_bool(OBJECT(&s
->timer0
), true, "realized", &err
);
626 error_propagate(errp
, err
);
629 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer0
), 0,
630 armsse_get_common_irq_in(s
, 3));
631 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer0
), 0);
632 object_property_set_link(OBJECT(&s
->apb_ppc0
), OBJECT(mr
), "port[0]", &err
);
634 error_propagate(errp
, err
);
638 qdev_prop_set_uint32(DEVICE(&s
->timer1
), "pclk-frq", s
->mainclk_frq
);
639 object_property_set_bool(OBJECT(&s
->timer1
), true, "realized", &err
);
641 error_propagate(errp
, err
);
644 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer1
), 0,
645 armsse_get_common_irq_in(s
, 4));
646 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer1
), 0);
647 object_property_set_link(OBJECT(&s
->apb_ppc0
), OBJECT(mr
), "port[1]", &err
);
649 error_propagate(errp
, err
);
654 qdev_prop_set_uint32(DEVICE(&s
->dualtimer
), "pclk-frq", s
->mainclk_frq
);
655 object_property_set_bool(OBJECT(&s
->dualtimer
), true, "realized", &err
);
657 error_propagate(errp
, err
);
660 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dualtimer
), 0,
661 armsse_get_common_irq_in(s
, 5));
662 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->dualtimer
), 0);
663 object_property_set_link(OBJECT(&s
->apb_ppc0
), OBJECT(mr
), "port[2]", &err
);
665 error_propagate(errp
, err
);
669 object_property_set_bool(OBJECT(&s
->apb_ppc0
), true, "realized", &err
);
671 error_propagate(errp
, err
);
675 sbd_apb_ppc0
= SYS_BUS_DEVICE(&s
->apb_ppc0
);
676 dev_apb_ppc0
= DEVICE(&s
->apb_ppc0
);
678 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 0);
679 memory_region_add_subregion(&s
->container
, 0x40000000, mr
);
680 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 1);
681 memory_region_add_subregion(&s
->container
, 0x40001000, mr
);
682 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 2);
683 memory_region_add_subregion(&s
->container
, 0x40002000, mr
);
684 for (i
= 0; i
< IOTS_APB_PPC0_NUM_PORTS
; i
++) {
685 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_nonsec", i
,
686 qdev_get_gpio_in_named(dev_apb_ppc0
,
688 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_ap", i
,
689 qdev_get_gpio_in_named(dev_apb_ppc0
,
692 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_enable", 0,
693 qdev_get_gpio_in_named(dev_apb_ppc0
,
695 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_clear", 0,
696 qdev_get_gpio_in_named(dev_apb_ppc0
,
698 qdev_connect_gpio_out(dev_splitter
, 0,
699 qdev_get_gpio_in_named(dev_apb_ppc0
,
702 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external
703 * ones) are sent individually to the security controller, and also
704 * ORed together to give a single combined PPC interrupt to the NVIC.
706 object_property_set_int(OBJECT(&s
->ppc_irq_orgate
),
707 NUM_PPCS
, "num-lines", &err
);
709 error_propagate(errp
, err
);
712 object_property_set_bool(OBJECT(&s
->ppc_irq_orgate
), true,
715 error_propagate(errp
, err
);
718 qdev_connect_gpio_out(DEVICE(&s
->ppc_irq_orgate
), 0,
719 armsse_get_common_irq_in(s
, 10));
721 /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */
723 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
724 /* Devices behind APB PPC1:
725 * 0x4002f000: S32K timer
727 qdev_prop_set_uint32(DEVICE(&s
->s32ktimer
), "pclk-frq", S32KCLK
);
728 object_property_set_bool(OBJECT(&s
->s32ktimer
), true, "realized", &err
);
730 error_propagate(errp
, err
);
733 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32ktimer
), 0,
734 armsse_get_common_irq_in(s
, 2));
735 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->s32ktimer
), 0);
736 object_property_set_link(OBJECT(&s
->apb_ppc1
), OBJECT(mr
), "port[0]", &err
);
738 error_propagate(errp
, err
);
742 object_property_set_bool(OBJECT(&s
->apb_ppc1
), true, "realized", &err
);
744 error_propagate(errp
, err
);
747 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->apb_ppc1
), 0);
748 memory_region_add_subregion(&s
->container
, 0x4002f000, mr
);
750 dev_apb_ppc1
= DEVICE(&s
->apb_ppc1
);
751 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_nonsec", 0,
752 qdev_get_gpio_in_named(dev_apb_ppc1
,
754 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_ap", 0,
755 qdev_get_gpio_in_named(dev_apb_ppc1
,
757 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_enable", 0,
758 qdev_get_gpio_in_named(dev_apb_ppc1
,
760 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_clear", 0,
761 qdev_get_gpio_in_named(dev_apb_ppc1
,
763 qdev_connect_gpio_out(dev_splitter
, 1,
764 qdev_get_gpio_in_named(dev_apb_ppc1
,
767 object_property_set_int(OBJECT(&s
->sysinfo
), info
->sys_version
,
768 "SYS_VERSION", &err
);
770 error_propagate(errp
, err
);
773 object_property_set_int(OBJECT(&s
->sysinfo
),
774 armsse_sys_config_value(s
, info
),
777 error_propagate(errp
, err
);
780 object_property_set_bool(OBJECT(&s
->sysinfo
), true, "realized", &err
);
782 error_propagate(errp
, err
);
785 /* System information registers */
786 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysinfo
), 0, 0x40020000);
787 /* System control registers */
788 object_property_set_bool(OBJECT(&s
->sysctl
), true, "realized", &err
);
790 error_propagate(errp
, err
);
793 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysctl
), 0, 0x50021000);
795 /* This OR gate wires together outputs from the secure watchdogs to NMI */
796 object_property_set_int(OBJECT(&s
->nmi_orgate
), 2, "num-lines", &err
);
798 error_propagate(errp
, err
);
801 object_property_set_bool(OBJECT(&s
->nmi_orgate
), true, "realized", &err
);
803 error_propagate(errp
, err
);
806 qdev_connect_gpio_out(DEVICE(&s
->nmi_orgate
), 0,
807 qdev_get_gpio_in_named(DEVICE(&s
->armv7m
), "NMI", 0));
809 qdev_prop_set_uint32(DEVICE(&s
->s32kwatchdog
), "wdogclk-frq", S32KCLK
);
810 object_property_set_bool(OBJECT(&s
->s32kwatchdog
), true, "realized", &err
);
812 error_propagate(errp
, err
);
815 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0,
816 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 0));
817 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0, 0x5002e000);
819 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
821 qdev_prop_set_uint32(DEVICE(&s
->nswatchdog
), "wdogclk-frq", s
->mainclk_frq
);
822 object_property_set_bool(OBJECT(&s
->nswatchdog
), true, "realized", &err
);
824 error_propagate(errp
, err
);
827 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->nswatchdog
), 0,
828 armsse_get_common_irq_in(s
, 1));
829 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->nswatchdog
), 0, 0x40081000);
831 qdev_prop_set_uint32(DEVICE(&s
->swatchdog
), "wdogclk-frq", s
->mainclk_frq
);
832 object_property_set_bool(OBJECT(&s
->swatchdog
), true, "realized", &err
);
834 error_propagate(errp
, err
);
837 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->swatchdog
), 0,
838 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 1));
839 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->swatchdog
), 0, 0x50081000);
841 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
842 Object
*splitter
= OBJECT(&s
->ppc_irq_splitter
[i
]);
844 object_property_set_int(splitter
, 2, "num-lines", &err
);
846 error_propagate(errp
, err
);
849 object_property_set_bool(splitter
, true, "realized", &err
);
851 error_propagate(errp
, err
);
856 for (i
= 0; i
< IOTS_NUM_AHB_EXP_PPC
; i
++) {
857 char *ppcname
= g_strdup_printf("ahb_ppcexp%d", i
);
859 armsse_forward_ppc(s
, ppcname
, i
);
863 for (i
= 0; i
< IOTS_NUM_APB_EXP_PPC
; i
++) {
864 char *ppcname
= g_strdup_printf("apb_ppcexp%d", i
);
866 armsse_forward_ppc(s
, ppcname
, i
+ IOTS_NUM_AHB_EXP_PPC
);
870 for (i
= NUM_EXTERNAL_PPCS
; i
< NUM_PPCS
; i
++) {
871 /* Wire up IRQ splitter for internal PPCs */
872 DeviceState
*devs
= DEVICE(&s
->ppc_irq_splitter
[i
]);
873 char *gpioname
= g_strdup_printf("apb_ppc%d_irq_status",
874 i
- NUM_EXTERNAL_PPCS
);
875 TZPPC
*ppc
= (i
== NUM_EXTERNAL_PPCS
) ? &s
->apb_ppc0
: &s
->apb_ppc1
;
877 qdev_connect_gpio_out(devs
, 0,
878 qdev_get_gpio_in_named(dev_secctl
, gpioname
, 0));
879 qdev_connect_gpio_out(devs
, 1,
880 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), i
));
881 qdev_connect_gpio_out_named(DEVICE(ppc
), "irq", 0,
882 qdev_get_gpio_in(devs
, 0));
886 /* Wire up the splitters for the MPC IRQs */
887 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
888 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
889 DeviceState
*dev_splitter
= DEVICE(splitter
);
891 object_property_set_int(OBJECT(splitter
), 2, "num-lines", &err
);
893 error_propagate(errp
, err
);
896 object_property_set_bool(OBJECT(splitter
), true, "realized", &err
);
898 error_propagate(errp
, err
);
902 if (i
< IOTS_NUM_EXP_MPC
) {
903 /* Splitter input is from GPIO input line */
904 s
->mpcexp_status_in
[i
] = qdev_get_gpio_in(dev_splitter
, 0);
905 qdev_connect_gpio_out(dev_splitter
, 0,
906 qdev_get_gpio_in_named(dev_secctl
,
907 "mpcexp_status", i
));
909 /* Splitter input is from our own MPC */
910 qdev_connect_gpio_out_named(DEVICE(&s
->mpc
[i
- IOTS_NUM_EXP_MPC
]),
912 qdev_get_gpio_in(dev_splitter
, 0));
913 qdev_connect_gpio_out(dev_splitter
, 0,
914 qdev_get_gpio_in_named(dev_secctl
,
918 qdev_connect_gpio_out(dev_splitter
, 1,
919 qdev_get_gpio_in(DEVICE(&s
->mpc_irq_orgate
), i
));
921 /* Create GPIO inputs which will pass the line state for our
922 * mpcexp_irq inputs to the correct splitter devices.
924 qdev_init_gpio_in_named(dev
, armsse_mpcexp_status
, "mpcexp_status",
927 armsse_forward_sec_resp_cfg(s
);
929 /* Forward the MSC related signals */
930 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_status");
931 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_clear");
932 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_ns");
933 qdev_connect_gpio_out_named(dev_secctl
, "msc_irq", 0,
934 armsse_get_common_irq_in(s
, 11));
937 * Expose our container region to the board model; this corresponds
938 * to the AHB Slave Expansion ports which allow bus master devices
939 * (eg DMA controllers) in the board model to make transactions into
940 * devices in the ARMSSE.
942 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->container
);
944 system_clock_scale
= NANOSECONDS_PER_SECOND
/ s
->mainclk_frq
;
947 static void armsse_idau_check(IDAUInterface
*ii
, uint32_t address
,
948 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
951 * For ARMSSE systems the IDAU responses are simple logical functions
952 * of the address bits. The NSC attribute is guest-adjustable via the
953 * NSCCFG register in the security controller.
955 ARMSSE
*s
= ARMSSE(ii
);
956 int region
= extract32(address
, 28, 4);
959 *nsc
= (region
== 1 && (s
->nsccfg
& 1)) || (region
== 3 && (s
->nsccfg
& 2));
960 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
961 *exempt
= (address
& 0xeff00000) == 0xe0000000;
965 static const VMStateDescription armsse_vmstate
= {
968 .minimum_version_id
= 1,
969 .fields
= (VMStateField
[]) {
970 VMSTATE_UINT32(nsccfg
, ARMSSE
),
971 VMSTATE_END_OF_LIST()
975 static Property armsse_properties
[] = {
976 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
978 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
979 DEFINE_PROP_UINT32("MAINCLK", ARMSSE
, mainclk_frq
, 0),
980 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
981 DEFINE_PROP_END_OF_LIST()
984 static void armsse_reset(DeviceState
*dev
)
986 ARMSSE
*s
= ARMSSE(dev
);
991 static void armsse_class_init(ObjectClass
*klass
, void *data
)
993 DeviceClass
*dc
= DEVICE_CLASS(klass
);
994 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(klass
);
995 ARMSSEClass
*asc
= ARMSSE_CLASS(klass
);
997 dc
->realize
= armsse_realize
;
998 dc
->vmsd
= &armsse_vmstate
;
999 dc
->props
= armsse_properties
;
1000 dc
->reset
= armsse_reset
;
1001 iic
->check
= armsse_idau_check
;
1005 static const TypeInfo armsse_info
= {
1006 .name
= TYPE_ARMSSE
,
1007 .parent
= TYPE_SYS_BUS_DEVICE
,
1008 .instance_size
= sizeof(ARMSSE
),
1009 .instance_init
= armsse_init
,
1011 .interfaces
= (InterfaceInfo
[]) {
1012 { TYPE_IDAU_INTERFACE
},
1017 static void armsse_register_types(void)
1021 type_register_static(&armsse_info
);
1023 for (i
= 0; i
< ARRAY_SIZE(armsse_variants
); i
++) {
1025 .name
= armsse_variants
[i
].name
,
1026 .parent
= TYPE_ARMSSE
,
1027 .class_init
= armsse_class_init
,
1028 .class_data
= (void *)&armsse_variants
[i
],
1034 type_init(armsse_register_types
);