4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
132 fprintf_function cpu_fprintf
, int flags
)
134 ARMCPU
*cpu
= ARM_CPU(cs
);
135 CPUARMState
*env
= &cpu
->env
;
136 uint32_t psr
= pstate_read(env
);
138 int el
= arm_current_el(env
);
139 const char *ns_status
;
141 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
142 for (i
= 0; i
< 32; i
++) {
144 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
146 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
147 (i
+ 2) % 3 ? " " : "\n");
151 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
152 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
156 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
158 psr
& PSTATE_N
? 'N' : '-',
159 psr
& PSTATE_Z
? 'Z' : '-',
160 psr
& PSTATE_C
? 'C' : '-',
161 psr
& PSTATE_V
? 'V' : '-',
164 psr
& PSTATE_SP
? 'h' : 't');
166 if (!(flags
& CPU_DUMP_FPU
)) {
167 cpu_fprintf(f
, "\n");
170 if (fp_exception_el(env
, el
) != 0) {
171 cpu_fprintf(f
, " FPU disabled\n");
174 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
175 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
177 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
178 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
180 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
182 if (i
== FFR_PRED_NUM
) {
183 cpu_fprintf(f
, "FFR=");
184 /* It's last, so end the line. */
187 cpu_fprintf(f
, "P%02d=", i
);
200 /* More than one quadword per predicate. */
205 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
207 if (j
* 4 + 4 <= zcr_len
+ 1) {
210 digits
= (zcr_len
% 4 + 1) * 4;
212 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
213 env
->vfp
.pregs
[i
].p
[j
],
214 j
? ":" : eol
? "\n" : " ");
218 for (i
= 0; i
< 32; i
++) {
220 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
221 i
, env
->vfp
.zregs
[i
].d
[1],
222 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
223 } else if (zcr_len
== 1) {
224 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
225 ":%016" PRIx64
":%016" PRIx64
"\n",
226 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
227 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
229 for (j
= zcr_len
; j
>= 0; j
--) {
230 bool odd
= (zcr_len
- j
) % 2 != 0;
232 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
235 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
237 cpu_fprintf(f
, " [%x]=", j
);
240 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
241 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
242 env
->vfp
.zregs
[i
].d
[j
* 2],
243 odd
|| j
== 0 ? "\n" : ":");
248 for (i
= 0; i
< 32; i
++) {
249 uint64_t *q
= aa64_vfp_qreg(env
, i
);
250 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
251 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
256 void gen_a64_set_pc_im(uint64_t val
)
258 tcg_gen_movi_i64(cpu_pc
, val
);
261 /* Load the PC from a generic TCG variable.
263 * If address tagging is enabled via the TCR TBI bits, then loading
264 * an address into the PC will clear out any tag in it:
265 * + for EL2 and EL3 there is only one TBI bit, and if it is set
266 * then the address is zero-extended, clearing bits [63:56]
267 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
268 * and TBI1 controls addressses with bit 55 == 1.
269 * If the appropriate TBI bit is set for the address then
270 * the address is sign-extended from bit 55 into bits [63:56]
272 * We can avoid doing this for relative-branches, because the
273 * PC + offset can never overflow into the tag bits (assuming
274 * that virtual addresses are less than 56 bits wide, as they
275 * are currently), but we must handle it for branch-to-register.
277 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
279 /* Note that TBII is TBI1:TBI0. */
282 if (s
->current_el
<= 1) {
284 /* Sign-extend from bit 55. */
285 tcg_gen_sextract_i64(cpu_pc
, src
, 0, 56);
288 TCGv_i64 tcg_zero
= tcg_const_i64(0);
291 * The two TBI bits differ.
292 * If tbi0, then !tbi1: only use the extension if positive.
293 * if !tbi0, then tbi1: only use the extension if negative.
295 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
296 cpu_pc
, cpu_pc
, tcg_zero
, cpu_pc
, src
);
297 tcg_temp_free_i64(tcg_zero
);
303 /* Force tag byte to all zero */
304 tcg_gen_extract_i64(cpu_pc
, src
, 0, 56);
309 /* Load unmodified address */
310 tcg_gen_mov_i64(cpu_pc
, src
);
313 typedef struct DisasCompare64
{
318 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
322 arm_test_cc(&c32
, cc
);
324 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
325 * properly. The NE/EQ comparisons are also fine with this choice. */
326 c64
->cond
= c32
.cond
;
327 c64
->value
= tcg_temp_new_i64();
328 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
333 static void a64_free_cc(DisasCompare64
*c64
)
335 tcg_temp_free_i64(c64
->value
);
338 static void gen_exception_internal(int excp
)
340 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
342 assert(excp_is_internal(excp
));
343 gen_helper_exception_internal(cpu_env
, tcg_excp
);
344 tcg_temp_free_i32(tcg_excp
);
347 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
349 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
350 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
351 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
353 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
355 tcg_temp_free_i32(tcg_el
);
356 tcg_temp_free_i32(tcg_syn
);
357 tcg_temp_free_i32(tcg_excp
);
360 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
362 gen_a64_set_pc_im(s
->pc
- offset
);
363 gen_exception_internal(excp
);
364 s
->base
.is_jmp
= DISAS_NORETURN
;
367 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
368 uint32_t syndrome
, uint32_t target_el
)
370 gen_a64_set_pc_im(s
->pc
- offset
);
371 gen_exception(excp
, syndrome
, target_el
);
372 s
->base
.is_jmp
= DISAS_NORETURN
;
375 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
380 gen_a64_set_pc_im(s
->pc
- offset
);
381 tcg_syn
= tcg_const_i32(syndrome
);
382 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
383 tcg_temp_free_i32(tcg_syn
);
384 s
->base
.is_jmp
= DISAS_NORETURN
;
387 static void gen_ss_advance(DisasContext
*s
)
389 /* If the singlestep state is Active-not-pending, advance to
394 gen_helper_clear_pstate_ss(cpu_env
);
398 static void gen_step_complete_exception(DisasContext
*s
)
400 /* We just completed step of an insn. Move from Active-not-pending
401 * to Active-pending, and then also take the swstep exception.
402 * This corresponds to making the (IMPDEF) choice to prioritize
403 * swstep exceptions over asynchronous exceptions taken to an exception
404 * level where debug is disabled. This choice has the advantage that
405 * we do not need to maintain internal state corresponding to the
406 * ISV/EX syndrome bits between completion of the step and generation
407 * of the exception, and our syndrome information is always correct.
410 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
411 default_exception_el(s
));
412 s
->base
.is_jmp
= DISAS_NORETURN
;
415 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
417 /* No direct tb linking with singlestep (either QEMU's or the ARM
418 * debug architecture kind) or deterministic io
420 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
421 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
425 #ifndef CONFIG_USER_ONLY
426 /* Only link tbs from inside the same guest page */
427 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
435 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
437 TranslationBlock
*tb
;
440 if (use_goto_tb(s
, n
, dest
)) {
442 gen_a64_set_pc_im(dest
);
443 tcg_gen_exit_tb(tb
, n
);
444 s
->base
.is_jmp
= DISAS_NORETURN
;
446 gen_a64_set_pc_im(dest
);
448 gen_step_complete_exception(s
);
449 } else if (s
->base
.singlestep_enabled
) {
450 gen_exception_internal(EXCP_DEBUG
);
452 tcg_gen_lookup_and_goto_ptr();
453 s
->base
.is_jmp
= DISAS_NORETURN
;
458 void unallocated_encoding(DisasContext
*s
)
460 /* Unallocated and reserved encodings are uncategorized */
461 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
462 default_exception_el(s
));
465 static void init_tmp_a64_array(DisasContext
*s
)
467 #ifdef CONFIG_DEBUG_TCG
468 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
470 s
->tmp_a64_count
= 0;
473 static void free_tmp_a64(DisasContext
*s
)
476 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
477 tcg_temp_free_i64(s
->tmp_a64
[i
]);
479 init_tmp_a64_array(s
);
482 TCGv_i64
new_tmp_a64(DisasContext
*s
)
484 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
485 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
488 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
490 TCGv_i64 t
= new_tmp_a64(s
);
491 tcg_gen_movi_i64(t
, 0);
496 * Register access functions
498 * These functions are used for directly accessing a register in where
499 * changes to the final register value are likely to be made. If you
500 * need to use a register for temporary calculation (e.g. index type
501 * operations) use the read_* form.
503 * B1.2.1 Register mappings
505 * In instruction register encoding 31 can refer to ZR (zero register) or
506 * the SP (stack pointer) depending on context. In QEMU's case we map SP
507 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
508 * This is the point of the _sp forms.
510 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
513 return new_tmp_a64_zero(s
);
519 /* register access for when 31 == SP */
520 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
525 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
526 * representing the register contents. This TCGv is an auto-freed
527 * temporary so it need not be explicitly freed, and may be modified.
529 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
531 TCGv_i64 v
= new_tmp_a64(s
);
534 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
536 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
539 tcg_gen_movi_i64(v
, 0);
544 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
546 TCGv_i64 v
= new_tmp_a64(s
);
548 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
550 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
555 /* Return the offset into CPUARMState of a slice (from
556 * the least significant end) of FP register Qn (ie
558 * (Note that this is not the same mapping as for A32; see cpu.h)
560 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
562 return vec_reg_offset(s
, regno
, 0, size
);
565 /* Offset of the high half of the 128 bit vector Qn */
566 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
568 return vec_reg_offset(s
, regno
, 1, MO_64
);
571 /* Convenience accessors for reading and writing single and double
572 * FP registers. Writing clears the upper parts of the associated
573 * 128 bit vector register, as required by the architecture.
574 * Note that unlike the GP register accessors, the values returned
575 * by the read functions must be manually freed.
577 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
579 TCGv_i64 v
= tcg_temp_new_i64();
581 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
585 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
587 TCGv_i32 v
= tcg_temp_new_i32();
589 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
593 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
595 TCGv_i32 v
= tcg_temp_new_i32();
597 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
601 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
602 * If SVE is not enabled, then there are only 128 bits in the vector.
604 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
606 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
607 unsigned vsz
= vec_full_reg_size(s
);
610 TCGv_i64 tcg_zero
= tcg_const_i64(0);
611 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
612 tcg_temp_free_i64(tcg_zero
);
615 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
619 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
621 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
623 tcg_gen_st_i64(v
, cpu_env
, ofs
);
624 clear_vec_high(s
, false, reg
);
627 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
629 TCGv_i64 tmp
= tcg_temp_new_i64();
631 tcg_gen_extu_i32_i64(tmp
, v
);
632 write_fp_dreg(s
, reg
, tmp
);
633 tcg_temp_free_i64(tmp
);
636 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
638 TCGv_ptr statusptr
= tcg_temp_new_ptr();
641 /* In A64 all instructions (both FP and Neon) use the FPCR; there
642 * is no equivalent of the A32 Neon "standard FPSCR value".
643 * However half-precision operations operate under a different
644 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
647 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
649 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
651 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
655 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
656 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
657 GVecGen2Fn
*gvec_fn
, int vece
)
659 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
660 is_q
? 16 : 8, vec_full_reg_size(s
));
663 /* Expand a 2-operand + immediate AdvSIMD vector operation using
664 * an expander function.
666 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
667 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
669 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
670 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
673 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
674 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
675 GVecGen3Fn
*gvec_fn
, int vece
)
677 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
678 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
681 /* Expand a 2-operand + immediate AdvSIMD vector operation using
684 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
685 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
687 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
688 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
691 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
692 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
693 int rn
, int rm
, const GVecGen3
*gvec_op
)
695 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
696 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
697 vec_full_reg_size(s
), gvec_op
);
700 /* Expand a 3-operand operation using an out-of-line helper. */
701 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
702 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
704 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
705 vec_full_reg_offset(s
, rn
),
706 vec_full_reg_offset(s
, rm
),
707 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
710 /* Expand a 3-operand + env pointer operation using
711 * an out-of-line helper.
713 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
714 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
716 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
717 vec_full_reg_offset(s
, rn
),
718 vec_full_reg_offset(s
, rm
), cpu_env
,
719 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
722 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
723 * an out-of-line helper.
725 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
726 int rm
, bool is_fp16
, int data
,
727 gen_helper_gvec_3_ptr
*fn
)
729 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
730 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
731 vec_full_reg_offset(s
, rn
),
732 vec_full_reg_offset(s
, rm
), fpst
,
733 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
734 tcg_temp_free_ptr(fpst
);
737 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
738 * than the 32 bit equivalent.
740 static inline void gen_set_NZ64(TCGv_i64 result
)
742 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
743 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
746 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
747 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
750 gen_set_NZ64(result
);
752 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
753 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
755 tcg_gen_movi_i32(cpu_CF
, 0);
756 tcg_gen_movi_i32(cpu_VF
, 0);
759 /* dest = T0 + T1; compute C, N, V and Z flags */
760 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
763 TCGv_i64 result
, flag
, tmp
;
764 result
= tcg_temp_new_i64();
765 flag
= tcg_temp_new_i64();
766 tmp
= tcg_temp_new_i64();
768 tcg_gen_movi_i64(tmp
, 0);
769 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
771 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
773 gen_set_NZ64(result
);
775 tcg_gen_xor_i64(flag
, result
, t0
);
776 tcg_gen_xor_i64(tmp
, t0
, t1
);
777 tcg_gen_andc_i64(flag
, flag
, tmp
);
778 tcg_temp_free_i64(tmp
);
779 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
781 tcg_gen_mov_i64(dest
, result
);
782 tcg_temp_free_i64(result
);
783 tcg_temp_free_i64(flag
);
785 /* 32 bit arithmetic */
786 TCGv_i32 t0_32
= tcg_temp_new_i32();
787 TCGv_i32 t1_32
= tcg_temp_new_i32();
788 TCGv_i32 tmp
= tcg_temp_new_i32();
790 tcg_gen_movi_i32(tmp
, 0);
791 tcg_gen_extrl_i64_i32(t0_32
, t0
);
792 tcg_gen_extrl_i64_i32(t1_32
, t1
);
793 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
794 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
795 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
796 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
797 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
798 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
800 tcg_temp_free_i32(tmp
);
801 tcg_temp_free_i32(t0_32
);
802 tcg_temp_free_i32(t1_32
);
806 /* dest = T0 - T1; compute C, N, V and Z flags */
807 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
810 /* 64 bit arithmetic */
811 TCGv_i64 result
, flag
, tmp
;
813 result
= tcg_temp_new_i64();
814 flag
= tcg_temp_new_i64();
815 tcg_gen_sub_i64(result
, t0
, t1
);
817 gen_set_NZ64(result
);
819 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
820 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
822 tcg_gen_xor_i64(flag
, result
, t0
);
823 tmp
= tcg_temp_new_i64();
824 tcg_gen_xor_i64(tmp
, t0
, t1
);
825 tcg_gen_and_i64(flag
, flag
, tmp
);
826 tcg_temp_free_i64(tmp
);
827 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
828 tcg_gen_mov_i64(dest
, result
);
829 tcg_temp_free_i64(flag
);
830 tcg_temp_free_i64(result
);
832 /* 32 bit arithmetic */
833 TCGv_i32 t0_32
= tcg_temp_new_i32();
834 TCGv_i32 t1_32
= tcg_temp_new_i32();
837 tcg_gen_extrl_i64_i32(t0_32
, t0
);
838 tcg_gen_extrl_i64_i32(t1_32
, t1
);
839 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
840 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
841 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
842 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
843 tmp
= tcg_temp_new_i32();
844 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
845 tcg_temp_free_i32(t0_32
);
846 tcg_temp_free_i32(t1_32
);
847 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
848 tcg_temp_free_i32(tmp
);
849 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
853 /* dest = T0 + T1 + CF; do not compute flags. */
854 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
856 TCGv_i64 flag
= tcg_temp_new_i64();
857 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
858 tcg_gen_add_i64(dest
, t0
, t1
);
859 tcg_gen_add_i64(dest
, dest
, flag
);
860 tcg_temp_free_i64(flag
);
863 tcg_gen_ext32u_i64(dest
, dest
);
867 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
868 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
871 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
872 result
= tcg_temp_new_i64();
873 cf_64
= tcg_temp_new_i64();
874 vf_64
= tcg_temp_new_i64();
875 tmp
= tcg_const_i64(0);
877 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
878 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
879 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
880 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
881 gen_set_NZ64(result
);
883 tcg_gen_xor_i64(vf_64
, result
, t0
);
884 tcg_gen_xor_i64(tmp
, t0
, t1
);
885 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
886 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
888 tcg_gen_mov_i64(dest
, result
);
890 tcg_temp_free_i64(tmp
);
891 tcg_temp_free_i64(vf_64
);
892 tcg_temp_free_i64(cf_64
);
893 tcg_temp_free_i64(result
);
895 TCGv_i32 t0_32
, t1_32
, tmp
;
896 t0_32
= tcg_temp_new_i32();
897 t1_32
= tcg_temp_new_i32();
898 tmp
= tcg_const_i32(0);
900 tcg_gen_extrl_i64_i32(t0_32
, t0
);
901 tcg_gen_extrl_i64_i32(t1_32
, t1
);
902 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
903 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
905 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
906 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
907 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
908 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
909 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
911 tcg_temp_free_i32(tmp
);
912 tcg_temp_free_i32(t1_32
);
913 tcg_temp_free_i32(t0_32
);
918 * Load/Store generators
922 * Store from GPR register to memory.
924 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
925 TCGv_i64 tcg_addr
, int size
, int memidx
,
927 unsigned int iss_srt
,
928 bool iss_sf
, bool iss_ar
)
931 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
936 syn
= syn_data_abort_with_iss(0,
942 0, 0, 0, 0, 0, false);
943 disas_set_insn_syndrome(s
, syn
);
947 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
948 TCGv_i64 tcg_addr
, int size
,
950 unsigned int iss_srt
,
951 bool iss_sf
, bool iss_ar
)
953 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
954 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
958 * Load from memory to GPR register
960 static void do_gpr_ld_memidx(DisasContext
*s
,
961 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
962 int size
, bool is_signed
,
963 bool extend
, int memidx
,
964 bool iss_valid
, unsigned int iss_srt
,
965 bool iss_sf
, bool iss_ar
)
967 TCGMemOp memop
= s
->be_data
+ size
;
975 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
977 if (extend
&& is_signed
) {
979 tcg_gen_ext32u_i64(dest
, dest
);
985 syn
= syn_data_abort_with_iss(0,
991 0, 0, 0, 0, 0, false);
992 disas_set_insn_syndrome(s
, syn
);
996 static void do_gpr_ld(DisasContext
*s
,
997 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
998 int size
, bool is_signed
, bool extend
,
999 bool iss_valid
, unsigned int iss_srt
,
1000 bool iss_sf
, bool iss_ar
)
1002 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1004 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1008 * Store from FP register to memory
1010 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1012 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1013 TCGv_i64 tmp
= tcg_temp_new_i64();
1014 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1016 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1019 bool be
= s
->be_data
== MO_BE
;
1020 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1022 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1023 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1025 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1026 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1028 tcg_temp_free_i64(tcg_hiaddr
);
1031 tcg_temp_free_i64(tmp
);
1035 * Load from memory to FP register
1037 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1039 /* This always zero-extends and writes to a full 128 bit wide vector */
1040 TCGv_i64 tmplo
= tcg_temp_new_i64();
1044 TCGMemOp memop
= s
->be_data
+ size
;
1045 tmphi
= tcg_const_i64(0);
1046 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1048 bool be
= s
->be_data
== MO_BE
;
1049 TCGv_i64 tcg_hiaddr
;
1051 tmphi
= tcg_temp_new_i64();
1052 tcg_hiaddr
= tcg_temp_new_i64();
1054 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1055 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1057 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1059 tcg_temp_free_i64(tcg_hiaddr
);
1062 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1063 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1065 tcg_temp_free_i64(tmplo
);
1066 tcg_temp_free_i64(tmphi
);
1068 clear_vec_high(s
, true, destidx
);
1072 * Vector load/store helpers.
1074 * The principal difference between this and a FP load is that we don't
1075 * zero extend as we are filling a partial chunk of the vector register.
1076 * These functions don't support 128 bit loads/stores, which would be
1077 * normal load/store operations.
1079 * The _i32 versions are useful when operating on 32 bit quantities
1080 * (eg for floating point single or using Neon helper functions).
1083 /* Get value of an element within a vector register */
1084 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1085 int element
, TCGMemOp memop
)
1087 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1090 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1093 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1096 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1099 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1102 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1105 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1109 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1112 g_assert_not_reached();
1116 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1117 int element
, TCGMemOp memop
)
1119 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1122 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1125 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1128 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1131 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1135 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1138 g_assert_not_reached();
1142 /* Set value of an element within a vector register */
1143 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1144 int element
, TCGMemOp memop
)
1146 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1149 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1152 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1155 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1158 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1161 g_assert_not_reached();
1165 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1166 int destidx
, int element
, TCGMemOp memop
)
1168 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1171 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1174 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1177 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1180 g_assert_not_reached();
1184 /* Store from vector register to memory */
1185 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1186 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1188 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1190 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1191 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1193 tcg_temp_free_i64(tcg_tmp
);
1196 /* Load from memory to vector register */
1197 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1198 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1200 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1202 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1203 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1205 tcg_temp_free_i64(tcg_tmp
);
1208 /* Check that FP/Neon access is enabled. If it is, return
1209 * true. If not, emit code to generate an appropriate exception,
1210 * and return false; the caller should not emit any code for
1211 * the instruction. Note that this check must happen after all
1212 * unallocated-encoding checks (otherwise the syndrome information
1213 * for the resulting exception will be incorrect).
1215 static inline bool fp_access_check(DisasContext
*s
)
1217 assert(!s
->fp_access_checked
);
1218 s
->fp_access_checked
= true;
1220 if (!s
->fp_excp_el
) {
1224 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1229 /* Check that SVE access is enabled. If it is, return true.
1230 * If not, emit code to generate an appropriate exception and return false.
1232 bool sve_access_check(DisasContext
*s
)
1234 if (s
->sve_excp_el
) {
1235 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1239 return fp_access_check(s
);
1243 * This utility function is for doing register extension with an
1244 * optional shift. You will likely want to pass a temporary for the
1245 * destination register. See DecodeRegExtend() in the ARM ARM.
1247 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1248 int option
, unsigned int shift
)
1250 int extsize
= extract32(option
, 0, 2);
1251 bool is_signed
= extract32(option
, 2, 1);
1256 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1259 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1262 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1265 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1271 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1274 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1277 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1280 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1286 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1290 static inline void gen_check_sp_alignment(DisasContext
*s
)
1292 /* The AArch64 architecture mandates that (if enabled via PSTATE
1293 * or SCTLR bits) there is a check that SP is 16-aligned on every
1294 * SP-relative load or store (with an exception generated if it is not).
1295 * In line with general QEMU practice regarding misaligned accesses,
1296 * we omit these checks for the sake of guest program performance.
1297 * This function is provided as a hook so we can more easily add these
1298 * checks in future (possibly as a "favour catching guest program bugs
1299 * over speed" user selectable option).
1304 * This provides a simple table based table lookup decoder. It is
1305 * intended to be used when the relevant bits for decode are too
1306 * awkwardly placed and switch/if based logic would be confusing and
1307 * deeply nested. Since it's a linear search through the table, tables
1308 * should be kept small.
1310 * It returns the first handler where insn & mask == pattern, or
1311 * NULL if there is no match.
1312 * The table is terminated by an empty mask (i.e. 0)
1314 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1317 const AArch64DecodeTable
*tptr
= table
;
1319 while (tptr
->mask
) {
1320 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1321 return tptr
->disas_fn
;
1329 * The instruction disassembly implemented here matches
1330 * the instruction encoding classifications in chapter C4
1331 * of the ARM Architecture Reference Manual (DDI0487B_a);
1332 * classification names and decode diagrams here should generally
1333 * match up with those in the manual.
1336 /* Unconditional branch (immediate)
1338 * +----+-----------+-------------------------------------+
1339 * | op | 0 0 1 0 1 | imm26 |
1340 * +----+-----------+-------------------------------------+
1342 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1344 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1346 if (insn
& (1U << 31)) {
1347 /* BL Branch with link */
1348 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1351 /* B Branch / BL Branch with link */
1352 gen_goto_tb(s
, 0, addr
);
1355 /* Compare and branch (immediate)
1356 * 31 30 25 24 23 5 4 0
1357 * +----+-------------+----+---------------------+--------+
1358 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1359 * +----+-------------+----+---------------------+--------+
1361 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1363 unsigned int sf
, op
, rt
;
1365 TCGLabel
*label_match
;
1368 sf
= extract32(insn
, 31, 1);
1369 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1370 rt
= extract32(insn
, 0, 5);
1371 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1373 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1374 label_match
= gen_new_label();
1376 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1377 tcg_cmp
, 0, label_match
);
1379 gen_goto_tb(s
, 0, s
->pc
);
1380 gen_set_label(label_match
);
1381 gen_goto_tb(s
, 1, addr
);
1384 /* Test and branch (immediate)
1385 * 31 30 25 24 23 19 18 5 4 0
1386 * +----+-------------+----+-------+-------------+------+
1387 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1388 * +----+-------------+----+-------+-------------+------+
1390 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1392 unsigned int bit_pos
, op
, rt
;
1394 TCGLabel
*label_match
;
1397 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1398 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1399 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1400 rt
= extract32(insn
, 0, 5);
1402 tcg_cmp
= tcg_temp_new_i64();
1403 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1404 label_match
= gen_new_label();
1405 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1406 tcg_cmp
, 0, label_match
);
1407 tcg_temp_free_i64(tcg_cmp
);
1408 gen_goto_tb(s
, 0, s
->pc
);
1409 gen_set_label(label_match
);
1410 gen_goto_tb(s
, 1, addr
);
1413 /* Conditional branch (immediate)
1414 * 31 25 24 23 5 4 3 0
1415 * +---------------+----+---------------------+----+------+
1416 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1417 * +---------------+----+---------------------+----+------+
1419 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1424 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1425 unallocated_encoding(s
);
1428 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1429 cond
= extract32(insn
, 0, 4);
1432 /* genuinely conditional branches */
1433 TCGLabel
*label_match
= gen_new_label();
1434 arm_gen_test_cc(cond
, label_match
);
1435 gen_goto_tb(s
, 0, s
->pc
);
1436 gen_set_label(label_match
);
1437 gen_goto_tb(s
, 1, addr
);
1439 /* 0xe and 0xf are both "always" conditions */
1440 gen_goto_tb(s
, 0, addr
);
1444 /* HINT instruction group, including various allocated HINTs */
1445 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1446 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1448 unsigned int selector
= crm
<< 3 | op2
;
1451 unallocated_encoding(s
);
1456 case 0b00000: /* NOP */
1458 case 0b00011: /* WFI */
1459 s
->base
.is_jmp
= DISAS_WFI
;
1461 case 0b00001: /* YIELD */
1462 /* When running in MTTCG we don't generate jumps to the yield and
1463 * WFE helpers as it won't affect the scheduling of other vCPUs.
1464 * If we wanted to more completely model WFE/SEV so we don't busy
1465 * spin unnecessarily we would need to do something more involved.
1467 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1468 s
->base
.is_jmp
= DISAS_YIELD
;
1471 case 0b00010: /* WFE */
1472 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1473 s
->base
.is_jmp
= DISAS_WFE
;
1476 case 0b00100: /* SEV */
1477 case 0b00101: /* SEVL */
1478 /* we treat all as NOP at least for now */
1480 case 0b00111: /* XPACLRI */
1481 if (s
->pauth_active
) {
1482 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1485 case 0b01000: /* PACIA1716 */
1486 if (s
->pauth_active
) {
1487 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1490 case 0b01010: /* PACIB1716 */
1491 if (s
->pauth_active
) {
1492 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1495 case 0b01100: /* AUTIA1716 */
1496 if (s
->pauth_active
) {
1497 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1500 case 0b01110: /* AUTIB1716 */
1501 if (s
->pauth_active
) {
1502 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1505 case 0b11000: /* PACIAZ */
1506 if (s
->pauth_active
) {
1507 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1508 new_tmp_a64_zero(s
));
1511 case 0b11001: /* PACIASP */
1512 if (s
->pauth_active
) {
1513 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1516 case 0b11010: /* PACIBZ */
1517 if (s
->pauth_active
) {
1518 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1519 new_tmp_a64_zero(s
));
1522 case 0b11011: /* PACIBSP */
1523 if (s
->pauth_active
) {
1524 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1527 case 0b11100: /* AUTIAZ */
1528 if (s
->pauth_active
) {
1529 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1530 new_tmp_a64_zero(s
));
1533 case 0b11101: /* AUTIASP */
1534 if (s
->pauth_active
) {
1535 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1538 case 0b11110: /* AUTIBZ */
1539 if (s
->pauth_active
) {
1540 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1541 new_tmp_a64_zero(s
));
1544 case 0b11111: /* AUTIBSP */
1545 if (s
->pauth_active
) {
1546 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1550 /* default specified as NOP equivalent */
1555 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1557 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1560 /* CLREX, DSB, DMB, ISB */
1561 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1562 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1567 unallocated_encoding(s
);
1578 case 1: /* MBReqTypes_Reads */
1579 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1581 case 2: /* MBReqTypes_Writes */
1582 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1584 default: /* MBReqTypes_All */
1585 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1591 /* We need to break the TB after this insn to execute
1592 * a self-modified code correctly and also to take
1593 * any pending interrupts immediately.
1595 gen_goto_tb(s
, 0, s
->pc
);
1598 unallocated_encoding(s
);
1603 /* MSR (immediate) - move immediate to processor state field */
1604 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1605 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1607 int op
= op1
<< 3 | op2
;
1609 case 0x05: /* SPSel */
1610 if (s
->current_el
== 0) {
1611 unallocated_encoding(s
);
1615 case 0x1e: /* DAIFSet */
1616 case 0x1f: /* DAIFClear */
1618 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1619 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1620 gen_a64_set_pc_im(s
->pc
- 4);
1621 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1622 tcg_temp_free_i32(tcg_imm
);
1623 tcg_temp_free_i32(tcg_op
);
1624 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1625 gen_a64_set_pc_im(s
->pc
);
1626 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1630 unallocated_encoding(s
);
1635 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1637 TCGv_i32 tmp
= tcg_temp_new_i32();
1638 TCGv_i32 nzcv
= tcg_temp_new_i32();
1640 /* build bit 31, N */
1641 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1642 /* build bit 30, Z */
1643 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1644 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1645 /* build bit 29, C */
1646 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1647 /* build bit 28, V */
1648 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1649 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1650 /* generate result */
1651 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1653 tcg_temp_free_i32(nzcv
);
1654 tcg_temp_free_i32(tmp
);
1657 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1660 TCGv_i32 nzcv
= tcg_temp_new_i32();
1662 /* take NZCV from R[t] */
1663 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1666 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1668 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1669 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1671 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1672 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1674 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1675 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1676 tcg_temp_free_i32(nzcv
);
1679 /* MRS - move from system register
1680 * MSR (register) - move to system register
1683 * These are all essentially the same insn in 'read' and 'write'
1684 * versions, with varying op0 fields.
1686 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1687 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1688 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1690 const ARMCPRegInfo
*ri
;
1693 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1694 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1695 crn
, crm
, op0
, op1
, op2
));
1698 /* Unknown register; this might be a guest error or a QEMU
1699 * unimplemented feature.
1701 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1702 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1703 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1704 unallocated_encoding(s
);
1708 /* Check access permissions */
1709 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1710 unallocated_encoding(s
);
1715 /* Emit code to perform further access permissions checks at
1716 * runtime; this may result in an exception.
1719 TCGv_i32 tcg_syn
, tcg_isread
;
1722 gen_a64_set_pc_im(s
->pc
- 4);
1723 tmpptr
= tcg_const_ptr(ri
);
1724 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1725 tcg_syn
= tcg_const_i32(syndrome
);
1726 tcg_isread
= tcg_const_i32(isread
);
1727 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1728 tcg_temp_free_ptr(tmpptr
);
1729 tcg_temp_free_i32(tcg_syn
);
1730 tcg_temp_free_i32(tcg_isread
);
1733 /* Handle special cases first */
1734 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1738 tcg_rt
= cpu_reg(s
, rt
);
1740 gen_get_nzcv(tcg_rt
);
1742 gen_set_nzcv(tcg_rt
);
1745 case ARM_CP_CURRENTEL
:
1746 /* Reads as current EL value from pstate, which is
1747 * guaranteed to be constant by the tb flags.
1749 tcg_rt
= cpu_reg(s
, rt
);
1750 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1753 /* Writes clear the aligned block of memory which rt points into. */
1754 tcg_rt
= cpu_reg(s
, rt
);
1755 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1760 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1762 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1766 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1770 tcg_rt
= cpu_reg(s
, rt
);
1773 if (ri
->type
& ARM_CP_CONST
) {
1774 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1775 } else if (ri
->readfn
) {
1777 tmpptr
= tcg_const_ptr(ri
);
1778 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1779 tcg_temp_free_ptr(tmpptr
);
1781 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1784 if (ri
->type
& ARM_CP_CONST
) {
1785 /* If not forbidden by access permissions, treat as WI */
1787 } else if (ri
->writefn
) {
1789 tmpptr
= tcg_const_ptr(ri
);
1790 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1791 tcg_temp_free_ptr(tmpptr
);
1793 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1797 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1798 /* I/O operations must end the TB here (whether read or write) */
1800 s
->base
.is_jmp
= DISAS_UPDATE
;
1801 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1802 /* We default to ending the TB on a coprocessor register write,
1803 * but allow this to be suppressed by the register definition
1804 * (usually only necessary to work around guest bugs).
1806 s
->base
.is_jmp
= DISAS_UPDATE
;
1811 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1812 * +---------------------+---+-----+-----+-------+-------+-----+------+
1813 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1814 * +---------------------+---+-----+-----+-------+-------+-----+------+
1816 static void disas_system(DisasContext
*s
, uint32_t insn
)
1818 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1819 l
= extract32(insn
, 21, 1);
1820 op0
= extract32(insn
, 19, 2);
1821 op1
= extract32(insn
, 16, 3);
1822 crn
= extract32(insn
, 12, 4);
1823 crm
= extract32(insn
, 8, 4);
1824 op2
= extract32(insn
, 5, 3);
1825 rt
= extract32(insn
, 0, 5);
1828 if (l
|| rt
!= 31) {
1829 unallocated_encoding(s
);
1833 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1834 handle_hint(s
, insn
, op1
, op2
, crm
);
1836 case 3: /* CLREX, DSB, DMB, ISB */
1837 handle_sync(s
, insn
, op1
, op2
, crm
);
1839 case 4: /* MSR (immediate) */
1840 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1843 unallocated_encoding(s
);
1848 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1851 /* Exception generation
1853 * 31 24 23 21 20 5 4 2 1 0
1854 * +-----------------+-----+------------------------+-----+----+
1855 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1856 * +-----------------------+------------------------+----------+
1858 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1860 int opc
= extract32(insn
, 21, 3);
1861 int op2_ll
= extract32(insn
, 0, 5);
1862 int imm16
= extract32(insn
, 5, 16);
1867 /* For SVC, HVC and SMC we advance the single-step state
1868 * machine before taking the exception. This is architecturally
1869 * mandated, to ensure that single-stepping a system call
1870 * instruction works properly.
1875 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1876 default_exception_el(s
));
1879 if (s
->current_el
== 0) {
1880 unallocated_encoding(s
);
1883 /* The pre HVC helper handles cases when HVC gets trapped
1884 * as an undefined insn by runtime configuration.
1886 gen_a64_set_pc_im(s
->pc
- 4);
1887 gen_helper_pre_hvc(cpu_env
);
1889 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1892 if (s
->current_el
== 0) {
1893 unallocated_encoding(s
);
1896 gen_a64_set_pc_im(s
->pc
- 4);
1897 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1898 gen_helper_pre_smc(cpu_env
, tmp
);
1899 tcg_temp_free_i32(tmp
);
1901 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1904 unallocated_encoding(s
);
1910 unallocated_encoding(s
);
1914 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1918 unallocated_encoding(s
);
1921 /* HLT. This has two purposes.
1922 * Architecturally, it is an external halting debug instruction.
1923 * Since QEMU doesn't implement external debug, we treat this as
1924 * it is required for halting debug disabled: it will UNDEF.
1925 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1927 if (semihosting_enabled() && imm16
== 0xf000) {
1928 #ifndef CONFIG_USER_ONLY
1929 /* In system mode, don't allow userspace access to semihosting,
1930 * to provide some semblance of security (and for consistency
1931 * with our 32-bit semihosting).
1933 if (s
->current_el
== 0) {
1934 unsupported_encoding(s
, insn
);
1938 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1940 unsupported_encoding(s
, insn
);
1944 if (op2_ll
< 1 || op2_ll
> 3) {
1945 unallocated_encoding(s
);
1948 /* DCPS1, DCPS2, DCPS3 */
1949 unsupported_encoding(s
, insn
);
1952 unallocated_encoding(s
);
1957 /* Unconditional branch (register)
1958 * 31 25 24 21 20 16 15 10 9 5 4 0
1959 * +---------------+-------+-------+-------+------+-------+
1960 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1961 * +---------------+-------+-------+-------+------+-------+
1963 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1965 unsigned int opc
, op2
, op3
, rn
, op4
;
1969 opc
= extract32(insn
, 21, 4);
1970 op2
= extract32(insn
, 16, 5);
1971 op3
= extract32(insn
, 10, 6);
1972 rn
= extract32(insn
, 5, 5);
1973 op4
= extract32(insn
, 0, 5);
1976 goto do_unallocated
;
1987 goto do_unallocated
;
1989 dst
= cpu_reg(s
, rn
);
1994 if (!dc_isar_feature(aa64_pauth
, s
)) {
1995 goto do_unallocated
;
1999 if (rn
!= 0x1f || op4
!= 0x1f) {
2000 goto do_unallocated
;
2003 modifier
= cpu_X
[31];
2005 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2007 goto do_unallocated
;
2009 modifier
= new_tmp_a64_zero(s
);
2011 if (s
->pauth_active
) {
2012 dst
= new_tmp_a64(s
);
2014 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2016 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2019 dst
= cpu_reg(s
, rn
);
2024 goto do_unallocated
;
2027 gen_a64_set_pc(s
, dst
);
2028 /* BLR also needs to load return address */
2030 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2036 if (!dc_isar_feature(aa64_pauth
, s
)) {
2037 goto do_unallocated
;
2039 if (op3
!= 2 || op3
!= 3) {
2040 goto do_unallocated
;
2042 if (s
->pauth_active
) {
2043 dst
= new_tmp_a64(s
);
2044 modifier
= cpu_reg_sp(s
, op4
);
2046 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2048 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2051 dst
= cpu_reg(s
, rn
);
2053 gen_a64_set_pc(s
, dst
);
2054 /* BLRAA also needs to load return address */
2056 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2061 if (s
->current_el
== 0) {
2062 goto do_unallocated
;
2067 goto do_unallocated
;
2069 dst
= tcg_temp_new_i64();
2070 tcg_gen_ld_i64(dst
, cpu_env
,
2071 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2074 case 2: /* ERETAA */
2075 case 3: /* ERETAB */
2076 if (!dc_isar_feature(aa64_pauth
, s
)) {
2077 goto do_unallocated
;
2079 if (rn
!= 0x1f || op4
!= 0x1f) {
2080 goto do_unallocated
;
2082 dst
= tcg_temp_new_i64();
2083 tcg_gen_ld_i64(dst
, cpu_env
,
2084 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2085 if (s
->pauth_active
) {
2086 modifier
= cpu_X
[31];
2088 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2090 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2096 goto do_unallocated
;
2098 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2102 gen_helper_exception_return(cpu_env
, dst
);
2103 tcg_temp_free_i64(dst
);
2104 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2107 /* Must exit loop to check un-masked IRQs */
2108 s
->base
.is_jmp
= DISAS_EXIT
;
2112 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2113 goto do_unallocated
;
2115 unsupported_encoding(s
, insn
);
2121 unallocated_encoding(s
);
2125 s
->base
.is_jmp
= DISAS_JUMP
;
2128 /* Branches, exception generating and system instructions */
2129 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2131 switch (extract32(insn
, 25, 7)) {
2132 case 0x0a: case 0x0b:
2133 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2134 disas_uncond_b_imm(s
, insn
);
2136 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2137 disas_comp_b_imm(s
, insn
);
2139 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2140 disas_test_b_imm(s
, insn
);
2142 case 0x2a: /* Conditional branch (immediate) */
2143 disas_cond_b_imm(s
, insn
);
2145 case 0x6a: /* Exception generation / System */
2146 if (insn
& (1 << 24)) {
2147 disas_system(s
, insn
);
2152 case 0x6b: /* Unconditional branch (register) */
2153 disas_uncond_b_reg(s
, insn
);
2156 unallocated_encoding(s
);
2162 * Load/Store exclusive instructions are implemented by remembering
2163 * the value/address loaded, and seeing if these are the same
2164 * when the store is performed. This is not actually the architecturally
2165 * mandated semantics, but it works for typical guest code sequences
2166 * and avoids having to monitor regular stores.
2168 * The store exclusive uses the atomic cmpxchg primitives to avoid
2169 * races in multi-threaded linux-user and when MTTCG softmmu is
2172 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2173 TCGv_i64 addr
, int size
, bool is_pair
)
2175 int idx
= get_mem_index(s
);
2176 TCGMemOp memop
= s
->be_data
;
2178 g_assert(size
<= 3);
2180 g_assert(size
>= 2);
2182 /* The pair must be single-copy atomic for the doubleword. */
2183 memop
|= MO_64
| MO_ALIGN
;
2184 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2185 if (s
->be_data
== MO_LE
) {
2186 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2187 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2189 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2190 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2193 /* The pair must be single-copy atomic for *each* doubleword, not
2194 the entire quadword, however it must be quadword aligned. */
2196 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2197 memop
| MO_ALIGN_16
);
2199 TCGv_i64 addr2
= tcg_temp_new_i64();
2200 tcg_gen_addi_i64(addr2
, addr
, 8);
2201 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2202 tcg_temp_free_i64(addr2
);
2204 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2205 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2208 memop
|= size
| MO_ALIGN
;
2209 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2210 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2212 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2215 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2216 TCGv_i64 addr
, int size
, int is_pair
)
2218 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2219 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2222 * [addr + datasize] = {Rt2};
2228 * env->exclusive_addr = -1;
2230 TCGLabel
*fail_label
= gen_new_label();
2231 TCGLabel
*done_label
= gen_new_label();
2234 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2236 tmp
= tcg_temp_new_i64();
2239 if (s
->be_data
== MO_LE
) {
2240 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2242 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2244 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2245 cpu_exclusive_val
, tmp
,
2247 MO_64
| MO_ALIGN
| s
->be_data
);
2248 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2249 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2250 if (!HAVE_CMPXCHG128
) {
2251 gen_helper_exit_atomic(cpu_env
);
2252 s
->base
.is_jmp
= DISAS_NORETURN
;
2253 } else if (s
->be_data
== MO_LE
) {
2254 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2259 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2264 } else if (s
->be_data
== MO_LE
) {
2265 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2266 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2268 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2269 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2272 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2273 cpu_reg(s
, rt
), get_mem_index(s
),
2274 size
| MO_ALIGN
| s
->be_data
);
2275 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2277 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2278 tcg_temp_free_i64(tmp
);
2279 tcg_gen_br(done_label
);
2281 gen_set_label(fail_label
);
2282 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2283 gen_set_label(done_label
);
2284 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2287 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2290 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2291 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2292 int memidx
= get_mem_index(s
);
2293 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2296 gen_check_sp_alignment(s
);
2298 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, addr
, tcg_rs
, tcg_rt
, memidx
,
2299 size
| MO_ALIGN
| s
->be_data
);
2302 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2305 TCGv_i64 s1
= cpu_reg(s
, rs
);
2306 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2307 TCGv_i64 t1
= cpu_reg(s
, rt
);
2308 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2309 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2310 int memidx
= get_mem_index(s
);
2313 gen_check_sp_alignment(s
);
2317 TCGv_i64 cmp
= tcg_temp_new_i64();
2318 TCGv_i64 val
= tcg_temp_new_i64();
2320 if (s
->be_data
== MO_LE
) {
2321 tcg_gen_concat32_i64(val
, t1
, t2
);
2322 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2324 tcg_gen_concat32_i64(val
, t2
, t1
);
2325 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2328 tcg_gen_atomic_cmpxchg_i64(cmp
, addr
, cmp
, val
, memidx
,
2329 MO_64
| MO_ALIGN
| s
->be_data
);
2330 tcg_temp_free_i64(val
);
2332 if (s
->be_data
== MO_LE
) {
2333 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2335 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2337 tcg_temp_free_i64(cmp
);
2338 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2339 if (HAVE_CMPXCHG128
) {
2340 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2341 if (s
->be_data
== MO_LE
) {
2342 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2344 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2346 tcg_temp_free_i32(tcg_rs
);
2348 gen_helper_exit_atomic(cpu_env
);
2349 s
->base
.is_jmp
= DISAS_NORETURN
;
2352 TCGv_i64 d1
= tcg_temp_new_i64();
2353 TCGv_i64 d2
= tcg_temp_new_i64();
2354 TCGv_i64 a2
= tcg_temp_new_i64();
2355 TCGv_i64 c1
= tcg_temp_new_i64();
2356 TCGv_i64 c2
= tcg_temp_new_i64();
2357 TCGv_i64 zero
= tcg_const_i64(0);
2359 /* Load the two words, in memory order. */
2360 tcg_gen_qemu_ld_i64(d1
, addr
, memidx
,
2361 MO_64
| MO_ALIGN_16
| s
->be_data
);
2362 tcg_gen_addi_i64(a2
, addr
, 8);
2363 tcg_gen_qemu_ld_i64(d2
, addr
, memidx
, MO_64
| s
->be_data
);
2365 /* Compare the two words, also in memory order. */
2366 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2367 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2368 tcg_gen_and_i64(c2
, c2
, c1
);
2370 /* If compare equal, write back new data, else write back old data. */
2371 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2372 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2373 tcg_gen_qemu_st_i64(c1
, addr
, memidx
, MO_64
| s
->be_data
);
2374 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2375 tcg_temp_free_i64(a2
);
2376 tcg_temp_free_i64(c1
);
2377 tcg_temp_free_i64(c2
);
2378 tcg_temp_free_i64(zero
);
2380 /* Write back the data from memory to Rs. */
2381 tcg_gen_mov_i64(s1
, d1
);
2382 tcg_gen_mov_i64(s2
, d2
);
2383 tcg_temp_free_i64(d1
);
2384 tcg_temp_free_i64(d2
);
2388 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2389 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2391 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2393 int opc0
= extract32(opc
, 0, 1);
2397 regsize
= opc0
? 32 : 64;
2399 regsize
= size
== 3 ? 64 : 32;
2401 return regsize
== 64;
2404 /* Load/store exclusive
2406 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2407 * +-----+-------------+----+---+----+------+----+-------+------+------+
2408 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2409 * +-----+-------------+----+---+----+------+----+-------+------+------+
2411 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2412 * L: 0 -> store, 1 -> load
2413 * o2: 0 -> exclusive, 1 -> not
2414 * o1: 0 -> single register, 1 -> register pair
2415 * o0: 1 -> load-acquire/store-release, 0 -> not
2417 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2419 int rt
= extract32(insn
, 0, 5);
2420 int rn
= extract32(insn
, 5, 5);
2421 int rt2
= extract32(insn
, 10, 5);
2422 int rs
= extract32(insn
, 16, 5);
2423 int is_lasr
= extract32(insn
, 15, 1);
2424 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2425 int size
= extract32(insn
, 30, 2);
2428 switch (o2_L_o1_o0
) {
2429 case 0x0: /* STXR */
2430 case 0x1: /* STLXR */
2432 gen_check_sp_alignment(s
);
2435 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2437 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2438 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, false);
2441 case 0x4: /* LDXR */
2442 case 0x5: /* LDAXR */
2444 gen_check_sp_alignment(s
);
2446 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2448 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, false);
2450 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2454 case 0x8: /* STLLR */
2455 if (!dc_isar_feature(aa64_lor
, s
)) {
2458 /* StoreLORelease is the same as Store-Release for QEMU. */
2460 case 0x9: /* STLR */
2461 /* Generate ISS for non-exclusive accesses including LASR. */
2463 gen_check_sp_alignment(s
);
2465 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2466 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2467 do_gpr_st(s
, cpu_reg(s
, rt
), tcg_addr
, size
, true, rt
,
2468 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2471 case 0xc: /* LDLAR */
2472 if (!dc_isar_feature(aa64_lor
, s
)) {
2475 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2477 case 0xd: /* LDAR */
2478 /* Generate ISS for non-exclusive accesses including LASR. */
2480 gen_check_sp_alignment(s
);
2482 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2483 do_gpr_ld(s
, cpu_reg(s
, rt
), tcg_addr
, size
, false, false, true, rt
,
2484 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2485 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2488 case 0x2: case 0x3: /* CASP / STXP */
2489 if (size
& 2) { /* STXP / STLXP */
2491 gen_check_sp_alignment(s
);
2494 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2496 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2497 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, true);
2501 && ((rt
| rs
) & 1) == 0
2502 && dc_isar_feature(aa64_atomics
, s
)) {
2504 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2509 case 0x6: case 0x7: /* CASPA / LDXP */
2510 if (size
& 2) { /* LDXP / LDAXP */
2512 gen_check_sp_alignment(s
);
2514 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2516 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, true);
2518 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2523 && ((rt
| rs
) & 1) == 0
2524 && dc_isar_feature(aa64_atomics
, s
)) {
2525 /* CASPA / CASPAL */
2526 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2532 case 0xb: /* CASL */
2533 case 0xe: /* CASA */
2534 case 0xf: /* CASAL */
2535 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2536 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2541 unallocated_encoding(s
);
2545 * Load register (literal)
2547 * 31 30 29 27 26 25 24 23 5 4 0
2548 * +-----+-------+---+-----+-------------------+-------+
2549 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2550 * +-----+-------+---+-----+-------------------+-------+
2552 * V: 1 -> vector (simd/fp)
2553 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2554 * 10-> 32 bit signed, 11 -> prefetch
2555 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2557 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2559 int rt
= extract32(insn
, 0, 5);
2560 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2561 bool is_vector
= extract32(insn
, 26, 1);
2562 int opc
= extract32(insn
, 30, 2);
2563 bool is_signed
= false;
2565 TCGv_i64 tcg_rt
, tcg_addr
;
2569 unallocated_encoding(s
);
2573 if (!fp_access_check(s
)) {
2578 /* PRFM (literal) : prefetch */
2581 size
= 2 + extract32(opc
, 0, 1);
2582 is_signed
= extract32(opc
, 1, 1);
2585 tcg_rt
= cpu_reg(s
, rt
);
2587 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2589 do_fp_ld(s
, rt
, tcg_addr
, size
);
2591 /* Only unsigned 32bit loads target 32bit registers. */
2592 bool iss_sf
= opc
!= 0;
2594 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2595 true, rt
, iss_sf
, false);
2597 tcg_temp_free_i64(tcg_addr
);
2601 * LDNP (Load Pair - non-temporal hint)
2602 * LDP (Load Pair - non vector)
2603 * LDPSW (Load Pair Signed Word - non vector)
2604 * STNP (Store Pair - non-temporal hint)
2605 * STP (Store Pair - non vector)
2606 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2607 * LDP (Load Pair of SIMD&FP)
2608 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2609 * STP (Store Pair of SIMD&FP)
2611 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2612 * +-----+-------+---+---+-------+---+-----------------------------+
2613 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2614 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2616 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2618 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2619 * V: 0 -> GPR, 1 -> Vector
2620 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2621 * 10 -> signed offset, 11 -> pre-index
2622 * L: 0 -> Store 1 -> Load
2624 * Rt, Rt2 = GPR or SIMD registers to be stored
2625 * Rn = general purpose register containing address
2626 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2628 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2630 int rt
= extract32(insn
, 0, 5);
2631 int rn
= extract32(insn
, 5, 5);
2632 int rt2
= extract32(insn
, 10, 5);
2633 uint64_t offset
= sextract64(insn
, 15, 7);
2634 int index
= extract32(insn
, 23, 2);
2635 bool is_vector
= extract32(insn
, 26, 1);
2636 bool is_load
= extract32(insn
, 22, 1);
2637 int opc
= extract32(insn
, 30, 2);
2639 bool is_signed
= false;
2640 bool postindex
= false;
2643 TCGv_i64 tcg_addr
; /* calculated address */
2647 unallocated_encoding(s
);
2654 size
= 2 + extract32(opc
, 1, 1);
2655 is_signed
= extract32(opc
, 0, 1);
2656 if (!is_load
&& is_signed
) {
2657 unallocated_encoding(s
);
2663 case 1: /* post-index */
2668 /* signed offset with "non-temporal" hint. Since we don't emulate
2669 * caches we don't care about hints to the cache system about
2670 * data access patterns, and handle this identically to plain
2674 /* There is no non-temporal-hint version of LDPSW */
2675 unallocated_encoding(s
);
2680 case 2: /* signed offset, rn not updated */
2683 case 3: /* pre-index */
2689 if (is_vector
&& !fp_access_check(s
)) {
2696 gen_check_sp_alignment(s
);
2699 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2702 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2707 do_fp_ld(s
, rt
, tcg_addr
, size
);
2709 do_fp_st(s
, rt
, tcg_addr
, size
);
2711 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2713 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2715 do_fp_st(s
, rt2
, tcg_addr
, size
);
2718 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2719 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2722 TCGv_i64 tmp
= tcg_temp_new_i64();
2724 /* Do not modify tcg_rt before recognizing any exception
2725 * from the second load.
2727 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2728 false, 0, false, false);
2729 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2730 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2731 false, 0, false, false);
2733 tcg_gen_mov_i64(tcg_rt
, tmp
);
2734 tcg_temp_free_i64(tmp
);
2736 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2737 false, 0, false, false);
2738 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2739 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2740 false, 0, false, false);
2746 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2748 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2750 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2755 * Load/store (immediate post-indexed)
2756 * Load/store (immediate pre-indexed)
2757 * Load/store (unscaled immediate)
2759 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2760 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2761 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2762 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2764 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2766 * V = 0 -> non-vector
2767 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2768 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2770 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2776 int rn
= extract32(insn
, 5, 5);
2777 int imm9
= sextract32(insn
, 12, 9);
2778 int idx
= extract32(insn
, 10, 2);
2779 bool is_signed
= false;
2780 bool is_store
= false;
2781 bool is_extended
= false;
2782 bool is_unpriv
= (idx
== 2);
2783 bool iss_valid
= !is_vector
;
2790 size
|= (opc
& 2) << 1;
2791 if (size
> 4 || is_unpriv
) {
2792 unallocated_encoding(s
);
2795 is_store
= ((opc
& 1) == 0);
2796 if (!fp_access_check(s
)) {
2800 if (size
== 3 && opc
== 2) {
2801 /* PRFM - prefetch */
2803 unallocated_encoding(s
);
2808 if (opc
== 3 && size
> 1) {
2809 unallocated_encoding(s
);
2812 is_store
= (opc
== 0);
2813 is_signed
= extract32(opc
, 1, 1);
2814 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2832 g_assert_not_reached();
2836 gen_check_sp_alignment(s
);
2838 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2841 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2846 do_fp_st(s
, rt
, tcg_addr
, size
);
2848 do_fp_ld(s
, rt
, tcg_addr
, size
);
2851 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2852 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2853 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2856 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2857 iss_valid
, rt
, iss_sf
, false);
2859 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2860 is_signed
, is_extended
, memidx
,
2861 iss_valid
, rt
, iss_sf
, false);
2866 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2868 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2870 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2875 * Load/store (register offset)
2877 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2878 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2879 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2880 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2883 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2884 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2886 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2887 * opc<0>: 0 -> store, 1 -> load
2888 * V: 1 -> vector/simd
2889 * opt: extend encoding (see DecodeRegExtend)
2890 * S: if S=1 then scale (essentially index by sizeof(size))
2891 * Rt: register to transfer into/out of
2892 * Rn: address register or SP for base
2893 * Rm: offset register or ZR for offset
2895 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2901 int rn
= extract32(insn
, 5, 5);
2902 int shift
= extract32(insn
, 12, 1);
2903 int rm
= extract32(insn
, 16, 5);
2904 int opt
= extract32(insn
, 13, 3);
2905 bool is_signed
= false;
2906 bool is_store
= false;
2907 bool is_extended
= false;
2912 if (extract32(opt
, 1, 1) == 0) {
2913 unallocated_encoding(s
);
2918 size
|= (opc
& 2) << 1;
2920 unallocated_encoding(s
);
2923 is_store
= !extract32(opc
, 0, 1);
2924 if (!fp_access_check(s
)) {
2928 if (size
== 3 && opc
== 2) {
2929 /* PRFM - prefetch */
2932 if (opc
== 3 && size
> 1) {
2933 unallocated_encoding(s
);
2936 is_store
= (opc
== 0);
2937 is_signed
= extract32(opc
, 1, 1);
2938 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2942 gen_check_sp_alignment(s
);
2944 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2946 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2947 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2949 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2953 do_fp_st(s
, rt
, tcg_addr
, size
);
2955 do_fp_ld(s
, rt
, tcg_addr
, size
);
2958 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2959 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2961 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2962 true, rt
, iss_sf
, false);
2964 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2965 is_signed
, is_extended
,
2966 true, rt
, iss_sf
, false);
2972 * Load/store (unsigned immediate)
2974 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2975 * +----+-------+---+-----+-----+------------+-------+------+
2976 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2977 * +----+-------+---+-----+-----+------------+-------+------+
2980 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2981 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2983 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2984 * opc<0>: 0 -> store, 1 -> load
2985 * Rn: base address register (inc SP)
2986 * Rt: target register
2988 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2994 int rn
= extract32(insn
, 5, 5);
2995 unsigned int imm12
= extract32(insn
, 10, 12);
2996 unsigned int offset
;
3001 bool is_signed
= false;
3002 bool is_extended
= false;
3005 size
|= (opc
& 2) << 1;
3007 unallocated_encoding(s
);
3010 is_store
= !extract32(opc
, 0, 1);
3011 if (!fp_access_check(s
)) {
3015 if (size
== 3 && opc
== 2) {
3016 /* PRFM - prefetch */
3019 if (opc
== 3 && size
> 1) {
3020 unallocated_encoding(s
);
3023 is_store
= (opc
== 0);
3024 is_signed
= extract32(opc
, 1, 1);
3025 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3029 gen_check_sp_alignment(s
);
3031 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
3032 offset
= imm12
<< size
;
3033 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
3037 do_fp_st(s
, rt
, tcg_addr
, size
);
3039 do_fp_ld(s
, rt
, tcg_addr
, size
);
3042 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3043 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3045 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
3046 true, rt
, iss_sf
, false);
3048 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
3049 true, rt
, iss_sf
, false);
3054 /* Atomic memory operations
3056 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3057 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3058 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3059 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3061 * Rt: the result register
3062 * Rn: base address or SP
3063 * Rs: the source register for the operation
3064 * V: vector flag (always 0 as of v8.3)
3068 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3069 int size
, int rt
, bool is_vector
)
3071 int rs
= extract32(insn
, 16, 5);
3072 int rn
= extract32(insn
, 5, 5);
3073 int o3_opc
= extract32(insn
, 12, 4);
3074 TCGv_i64 tcg_rn
, tcg_rs
;
3075 AtomicThreeOpFn
*fn
;
3077 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3078 unallocated_encoding(s
);
3082 case 000: /* LDADD */
3083 fn
= tcg_gen_atomic_fetch_add_i64
;
3085 case 001: /* LDCLR */
3086 fn
= tcg_gen_atomic_fetch_and_i64
;
3088 case 002: /* LDEOR */
3089 fn
= tcg_gen_atomic_fetch_xor_i64
;
3091 case 003: /* LDSET */
3092 fn
= tcg_gen_atomic_fetch_or_i64
;
3094 case 004: /* LDSMAX */
3095 fn
= tcg_gen_atomic_fetch_smax_i64
;
3097 case 005: /* LDSMIN */
3098 fn
= tcg_gen_atomic_fetch_smin_i64
;
3100 case 006: /* LDUMAX */
3101 fn
= tcg_gen_atomic_fetch_umax_i64
;
3103 case 007: /* LDUMIN */
3104 fn
= tcg_gen_atomic_fetch_umin_i64
;
3107 fn
= tcg_gen_atomic_xchg_i64
;
3110 unallocated_encoding(s
);
3115 gen_check_sp_alignment(s
);
3117 tcg_rn
= cpu_reg_sp(s
, rn
);
3118 tcg_rs
= read_cpu_reg(s
, rs
, true);
3120 if (o3_opc
== 1) { /* LDCLR */
3121 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3124 /* The tcg atomic primitives are all full barriers. Therefore we
3125 * can ignore the Acquire and Release bits of this instruction.
3127 fn(cpu_reg(s
, rt
), tcg_rn
, tcg_rs
, get_mem_index(s
),
3128 s
->be_data
| size
| MO_ALIGN
);
3132 * PAC memory operations
3134 * 31 30 27 26 24 22 21 12 11 10 5 0
3135 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3136 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3137 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3139 * Rt: the result register
3140 * Rn: base address or SP
3141 * V: vector flag (always 0 as of v8.3)
3142 * M: clear for key DA, set for key DB
3143 * W: pre-indexing flag
3146 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3147 int size
, int rt
, bool is_vector
)
3149 int rn
= extract32(insn
, 5, 5);
3150 bool is_wback
= extract32(insn
, 11, 1);
3151 bool use_key_a
= !extract32(insn
, 23, 1);
3153 TCGv_i64 tcg_addr
, tcg_rt
;
3155 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3156 unallocated_encoding(s
);
3161 gen_check_sp_alignment(s
);
3163 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
3165 if (s
->pauth_active
) {
3167 gen_helper_autda(tcg_addr
, cpu_env
, tcg_addr
, cpu_X
[31]);
3169 gen_helper_autdb(tcg_addr
, cpu_env
, tcg_addr
, cpu_X
[31]);
3173 /* Form the 10-bit signed, scaled offset. */
3174 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3175 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3176 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
3178 tcg_rt
= cpu_reg(s
, rt
);
3180 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, /* is_signed */ false,
3181 /* extend */ false, /* iss_valid */ !is_wback
,
3182 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3185 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
3189 /* Load/store register (all forms) */
3190 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3192 int rt
= extract32(insn
, 0, 5);
3193 int opc
= extract32(insn
, 22, 2);
3194 bool is_vector
= extract32(insn
, 26, 1);
3195 int size
= extract32(insn
, 30, 2);
3197 switch (extract32(insn
, 24, 2)) {
3199 if (extract32(insn
, 21, 1) == 0) {
3200 /* Load/store register (unscaled immediate)
3201 * Load/store immediate pre/post-indexed
3202 * Load/store register unprivileged
3204 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3207 switch (extract32(insn
, 10, 2)) {
3209 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3212 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3215 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3220 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3223 unallocated_encoding(s
);
3226 /* AdvSIMD load/store multiple structures
3228 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3229 * +---+---+---------------+---+-------------+--------+------+------+------+
3230 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3231 * +---+---+---------------+---+-------------+--------+------+------+------+
3233 * AdvSIMD load/store multiple structures (post-indexed)
3235 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3236 * +---+---+---------------+---+---+---------+--------+------+------+------+
3237 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3238 * +---+---+---------------+---+---+---------+--------+------+------+------+
3240 * Rt: first (or only) SIMD&FP register to be transferred
3241 * Rn: base address or SP
3242 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3244 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3246 int rt
= extract32(insn
, 0, 5);
3247 int rn
= extract32(insn
, 5, 5);
3248 int size
= extract32(insn
, 10, 2);
3249 int opcode
= extract32(insn
, 12, 4);
3250 bool is_store
= !extract32(insn
, 22, 1);
3251 bool is_postidx
= extract32(insn
, 23, 1);
3252 bool is_q
= extract32(insn
, 30, 1);
3253 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3254 TCGMemOp endian
= s
->be_data
;
3256 int ebytes
; /* bytes per element */
3257 int elements
; /* elements per vector */
3258 int rpt
; /* num iterations */
3259 int selem
; /* structure elements */
3262 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3263 unallocated_encoding(s
);
3267 /* From the shared decode logic */
3298 unallocated_encoding(s
);
3302 if (size
== 3 && !is_q
&& selem
!= 1) {
3304 unallocated_encoding(s
);
3308 if (!fp_access_check(s
)) {
3313 gen_check_sp_alignment(s
);
3316 /* For our purposes, bytes are always little-endian. */
3321 /* Consecutive little-endian elements from a single register
3322 * can be promoted to a larger little-endian operation.
3324 if (selem
== 1 && endian
== MO_LE
) {
3328 elements
= (is_q
? 16 : 8) / ebytes
;
3330 tcg_rn
= cpu_reg_sp(s
, rn
);
3331 tcg_addr
= tcg_temp_new_i64();
3332 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3333 tcg_ebytes
= tcg_const_i64(ebytes
);
3335 for (r
= 0; r
< rpt
; r
++) {
3337 for (e
= 0; e
< elements
; e
++) {
3339 for (xs
= 0; xs
< selem
; xs
++) {
3340 int tt
= (rt
+ r
+ xs
) % 32;
3342 do_vec_st(s
, tt
, e
, tcg_addr
, size
, endian
);
3344 do_vec_ld(s
, tt
, e
, tcg_addr
, size
, endian
);
3346 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3352 /* For non-quad operations, setting a slice of the low
3353 * 64 bits of the register clears the high 64 bits (in
3354 * the ARM ARM pseudocode this is implicit in the fact
3355 * that 'rval' is a 64 bit wide variable).
3356 * For quad operations, we might still need to zero the
3359 for (r
= 0; r
< rpt
* selem
; r
++) {
3360 int tt
= (rt
+ r
) % 32;
3361 clear_vec_high(s
, is_q
, tt
);
3366 int rm
= extract32(insn
, 16, 5);
3368 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3370 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3373 tcg_temp_free_i64(tcg_ebytes
);
3374 tcg_temp_free_i64(tcg_addr
);
3377 /* AdvSIMD load/store single structure
3379 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3380 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3381 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3382 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3384 * AdvSIMD load/store single structure (post-indexed)
3386 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3387 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3388 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3389 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3391 * Rt: first (or only) SIMD&FP register to be transferred
3392 * Rn: base address or SP
3393 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3394 * index = encoded in Q:S:size dependent on size
3396 * lane_size = encoded in R, opc
3397 * transfer width = encoded in opc, S, size
3399 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3401 int rt
= extract32(insn
, 0, 5);
3402 int rn
= extract32(insn
, 5, 5);
3403 int size
= extract32(insn
, 10, 2);
3404 int S
= extract32(insn
, 12, 1);
3405 int opc
= extract32(insn
, 13, 3);
3406 int R
= extract32(insn
, 21, 1);
3407 int is_load
= extract32(insn
, 22, 1);
3408 int is_postidx
= extract32(insn
, 23, 1);
3409 int is_q
= extract32(insn
, 30, 1);
3411 int scale
= extract32(opc
, 1, 2);
3412 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3413 bool replicate
= false;
3414 int index
= is_q
<< 3 | S
<< 2 | size
;
3416 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3420 if (!is_load
|| S
) {
3421 unallocated_encoding(s
);
3430 if (extract32(size
, 0, 1)) {
3431 unallocated_encoding(s
);
3437 if (extract32(size
, 1, 1)) {
3438 unallocated_encoding(s
);
3441 if (!extract32(size
, 0, 1)) {
3445 unallocated_encoding(s
);
3453 g_assert_not_reached();
3456 if (!fp_access_check(s
)) {
3460 ebytes
= 1 << scale
;
3463 gen_check_sp_alignment(s
);
3466 tcg_rn
= cpu_reg_sp(s
, rn
);
3467 tcg_addr
= tcg_temp_new_i64();
3468 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3469 tcg_ebytes
= tcg_const_i64(ebytes
);
3471 for (xs
= 0; xs
< selem
; xs
++) {
3473 /* Load and replicate to all elements */
3474 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3476 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
3477 get_mem_index(s
), s
->be_data
+ scale
);
3478 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3479 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3481 tcg_temp_free_i64(tcg_tmp
);
3483 /* Load/store one element per register */
3485 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3487 do_vec_st(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3490 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3495 int rm
= extract32(insn
, 16, 5);
3497 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3499 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3502 tcg_temp_free_i64(tcg_ebytes
);
3503 tcg_temp_free_i64(tcg_addr
);
3506 /* Loads and stores */
3507 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3509 switch (extract32(insn
, 24, 6)) {
3510 case 0x08: /* Load/store exclusive */
3511 disas_ldst_excl(s
, insn
);
3513 case 0x18: case 0x1c: /* Load register (literal) */
3514 disas_ld_lit(s
, insn
);
3516 case 0x28: case 0x29:
3517 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3518 disas_ldst_pair(s
, insn
);
3520 case 0x38: case 0x39:
3521 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3522 disas_ldst_reg(s
, insn
);
3524 case 0x0c: /* AdvSIMD load/store multiple structures */
3525 disas_ldst_multiple_struct(s
, insn
);
3527 case 0x0d: /* AdvSIMD load/store single structure */
3528 disas_ldst_single_struct(s
, insn
);
3531 unallocated_encoding(s
);
3536 /* PC-rel. addressing
3537 * 31 30 29 28 24 23 5 4 0
3538 * +----+-------+-----------+-------------------+------+
3539 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3540 * +----+-------+-----------+-------------------+------+
3542 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3544 unsigned int page
, rd
;
3548 page
= extract32(insn
, 31, 1);
3549 /* SignExtend(immhi:immlo) -> offset */
3550 offset
= sextract64(insn
, 5, 19);
3551 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3552 rd
= extract32(insn
, 0, 5);
3556 /* ADRP (page based) */
3561 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3565 * Add/subtract (immediate)
3567 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3568 * +--+--+--+-----------+-----+-------------+-----+-----+
3569 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3570 * +--+--+--+-----------+-----+-------------+-----+-----+
3572 * sf: 0 -> 32bit, 1 -> 64bit
3573 * op: 0 -> add , 1 -> sub
3575 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3577 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3579 int rd
= extract32(insn
, 0, 5);
3580 int rn
= extract32(insn
, 5, 5);
3581 uint64_t imm
= extract32(insn
, 10, 12);
3582 int shift
= extract32(insn
, 22, 2);
3583 bool setflags
= extract32(insn
, 29, 1);
3584 bool sub_op
= extract32(insn
, 30, 1);
3585 bool is_64bit
= extract32(insn
, 31, 1);
3587 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3588 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3589 TCGv_i64 tcg_result
;
3598 unallocated_encoding(s
);
3602 tcg_result
= tcg_temp_new_i64();
3605 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3607 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3610 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3612 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3614 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3616 tcg_temp_free_i64(tcg_imm
);
3620 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3622 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3625 tcg_temp_free_i64(tcg_result
);
3628 /* The input should be a value in the bottom e bits (with higher
3629 * bits zero); returns that value replicated into every element
3630 * of size e in a 64 bit integer.
3632 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3642 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3643 static inline uint64_t bitmask64(unsigned int length
)
3645 assert(length
> 0 && length
<= 64);
3646 return ~0ULL >> (64 - length
);
3649 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3650 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3651 * value (ie should cause a guest UNDEF exception), and true if they are
3652 * valid, in which case the decoded bit pattern is written to result.
3654 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3655 unsigned int imms
, unsigned int immr
)
3658 unsigned e
, levels
, s
, r
;
3661 assert(immn
< 2 && imms
< 64 && immr
< 64);
3663 /* The bit patterns we create here are 64 bit patterns which
3664 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3665 * 64 bits each. Each element contains the same value: a run
3666 * of between 1 and e-1 non-zero bits, rotated within the
3667 * element by between 0 and e-1 bits.
3669 * The element size and run length are encoded into immn (1 bit)
3670 * and imms (6 bits) as follows:
3671 * 64 bit elements: immn = 1, imms = <length of run - 1>
3672 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3673 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3674 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3675 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3676 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3677 * Notice that immn = 0, imms = 11111x is the only combination
3678 * not covered by one of the above options; this is reserved.
3679 * Further, <length of run - 1> all-ones is a reserved pattern.
3681 * In all cases the rotation is by immr % e (and immr is 6 bits).
3684 /* First determine the element size */
3685 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3687 /* This is the immn == 0, imms == 0x11111x case */
3697 /* <length of run - 1> mustn't be all-ones. */
3701 /* Create the value of one element: s+1 set bits rotated
3702 * by r within the element (which is e bits wide)...
3704 mask
= bitmask64(s
+ 1);
3706 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3707 mask
&= bitmask64(e
);
3709 /* ...then replicate the element over the whole 64 bit value */
3710 mask
= bitfield_replicate(mask
, e
);
3715 /* Logical (immediate)
3716 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3717 * +----+-----+-------------+---+------+------+------+------+
3718 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3719 * +----+-----+-------------+---+------+------+------+------+
3721 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3723 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3724 TCGv_i64 tcg_rd
, tcg_rn
;
3726 bool is_and
= false;
3728 sf
= extract32(insn
, 31, 1);
3729 opc
= extract32(insn
, 29, 2);
3730 is_n
= extract32(insn
, 22, 1);
3731 immr
= extract32(insn
, 16, 6);
3732 imms
= extract32(insn
, 10, 6);
3733 rn
= extract32(insn
, 5, 5);
3734 rd
= extract32(insn
, 0, 5);
3737 unallocated_encoding(s
);
3741 if (opc
== 0x3) { /* ANDS */
3742 tcg_rd
= cpu_reg(s
, rd
);
3744 tcg_rd
= cpu_reg_sp(s
, rd
);
3746 tcg_rn
= cpu_reg(s
, rn
);
3748 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3749 /* some immediate field values are reserved */
3750 unallocated_encoding(s
);
3755 wmask
&= 0xffffffff;
3759 case 0x3: /* ANDS */
3761 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3765 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3768 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3771 assert(FALSE
); /* must handle all above */
3775 if (!sf
&& !is_and
) {
3776 /* zero extend final result; we know we can skip this for AND
3777 * since the immediate had the high 32 bits clear.
3779 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3782 if (opc
== 3) { /* ANDS */
3783 gen_logic_CC(sf
, tcg_rd
);
3788 * Move wide (immediate)
3790 * 31 30 29 28 23 22 21 20 5 4 0
3791 * +--+-----+-------------+-----+----------------+------+
3792 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3793 * +--+-----+-------------+-----+----------------+------+
3795 * sf: 0 -> 32 bit, 1 -> 64 bit
3796 * opc: 00 -> N, 10 -> Z, 11 -> K
3797 * hw: shift/16 (0,16, and sf only 32, 48)
3799 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3801 int rd
= extract32(insn
, 0, 5);
3802 uint64_t imm
= extract32(insn
, 5, 16);
3803 int sf
= extract32(insn
, 31, 1);
3804 int opc
= extract32(insn
, 29, 2);
3805 int pos
= extract32(insn
, 21, 2) << 4;
3806 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3809 if (!sf
&& (pos
>= 32)) {
3810 unallocated_encoding(s
);
3824 tcg_gen_movi_i64(tcg_rd
, imm
);
3827 tcg_imm
= tcg_const_i64(imm
);
3828 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3829 tcg_temp_free_i64(tcg_imm
);
3831 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3835 unallocated_encoding(s
);
3841 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3842 * +----+-----+-------------+---+------+------+------+------+
3843 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3844 * +----+-----+-------------+---+------+------+------+------+
3846 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3848 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3849 TCGv_i64 tcg_rd
, tcg_tmp
;
3851 sf
= extract32(insn
, 31, 1);
3852 opc
= extract32(insn
, 29, 2);
3853 n
= extract32(insn
, 22, 1);
3854 ri
= extract32(insn
, 16, 6);
3855 si
= extract32(insn
, 10, 6);
3856 rn
= extract32(insn
, 5, 5);
3857 rd
= extract32(insn
, 0, 5);
3858 bitsize
= sf
? 64 : 32;
3860 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3861 unallocated_encoding(s
);
3865 tcg_rd
= cpu_reg(s
, rd
);
3867 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3868 to be smaller than bitsize, we'll never reference data outside the
3869 low 32-bits anyway. */
3870 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3872 /* Recognize simple(r) extractions. */
3874 /* Wd<s-r:0> = Wn<s:r> */
3875 len
= (si
- ri
) + 1;
3876 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3877 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3879 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3880 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3883 /* opc == 1, BXFIL fall through to deposit */
3884 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3887 /* Handle the ri > si case with a deposit
3888 * Wd<32+s-r,32-r> = Wn<s:0>
3891 pos
= (bitsize
- ri
) & (bitsize
- 1);
3894 if (opc
== 0 && len
< ri
) {
3895 /* SBFM: sign extend the destination field from len to fill
3896 the balance of the word. Let the deposit below insert all
3897 of those sign bits. */
3898 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3902 if (opc
== 1) { /* BFM, BXFIL */
3903 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3905 /* SBFM or UBFM: We start with zero, and we haven't modified
3906 any bits outside bitsize, therefore the zero-extension
3907 below is unneeded. */
3908 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3913 if (!sf
) { /* zero extend final result */
3914 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3919 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3920 * +----+------+-------------+---+----+------+--------+------+------+
3921 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3922 * +----+------+-------------+---+----+------+--------+------+------+
3924 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3926 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3928 sf
= extract32(insn
, 31, 1);
3929 n
= extract32(insn
, 22, 1);
3930 rm
= extract32(insn
, 16, 5);
3931 imm
= extract32(insn
, 10, 6);
3932 rn
= extract32(insn
, 5, 5);
3933 rd
= extract32(insn
, 0, 5);
3934 op21
= extract32(insn
, 29, 2);
3935 op0
= extract32(insn
, 21, 1);
3936 bitsize
= sf
? 64 : 32;
3938 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3939 unallocated_encoding(s
);
3941 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3943 tcg_rd
= cpu_reg(s
, rd
);
3945 if (unlikely(imm
== 0)) {
3946 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3947 * so an extract from bit 0 is a special case.
3950 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3952 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3954 } else if (rm
== rn
) { /* ROR */
3955 tcg_rm
= cpu_reg(s
, rm
);
3957 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3959 TCGv_i32 tmp
= tcg_temp_new_i32();
3960 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3961 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3962 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3963 tcg_temp_free_i32(tmp
);
3966 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3967 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3968 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3969 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3970 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3972 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3978 /* Data processing - immediate */
3979 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3981 switch (extract32(insn
, 23, 6)) {
3982 case 0x20: case 0x21: /* PC-rel. addressing */
3983 disas_pc_rel_adr(s
, insn
);
3985 case 0x22: case 0x23: /* Add/subtract (immediate) */
3986 disas_add_sub_imm(s
, insn
);
3988 case 0x24: /* Logical (immediate) */
3989 disas_logic_imm(s
, insn
);
3991 case 0x25: /* Move wide (immediate) */
3992 disas_movw_imm(s
, insn
);
3994 case 0x26: /* Bitfield */
3995 disas_bitfield(s
, insn
);
3997 case 0x27: /* Extract */
3998 disas_extract(s
, insn
);
4001 unallocated_encoding(s
);
4006 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4007 * Note that it is the caller's responsibility to ensure that the
4008 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4009 * mandated semantics for out of range shifts.
4011 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4012 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4014 switch (shift_type
) {
4015 case A64_SHIFT_TYPE_LSL
:
4016 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4018 case A64_SHIFT_TYPE_LSR
:
4019 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4021 case A64_SHIFT_TYPE_ASR
:
4023 tcg_gen_ext32s_i64(dst
, src
);
4025 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4027 case A64_SHIFT_TYPE_ROR
:
4029 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4032 t0
= tcg_temp_new_i32();
4033 t1
= tcg_temp_new_i32();
4034 tcg_gen_extrl_i64_i32(t0
, src
);
4035 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4036 tcg_gen_rotr_i32(t0
, t0
, t1
);
4037 tcg_gen_extu_i32_i64(dst
, t0
);
4038 tcg_temp_free_i32(t0
);
4039 tcg_temp_free_i32(t1
);
4043 assert(FALSE
); /* all shift types should be handled */
4047 if (!sf
) { /* zero extend final result */
4048 tcg_gen_ext32u_i64(dst
, dst
);
4052 /* Shift a TCGv src by immediate, put result in dst.
4053 * The shift amount must be in range (this should always be true as the
4054 * relevant instructions will UNDEF on bad shift immediates).
4056 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4057 enum a64_shift_type shift_type
, unsigned int shift_i
)
4059 assert(shift_i
< (sf
? 64 : 32));
4062 tcg_gen_mov_i64(dst
, src
);
4064 TCGv_i64 shift_const
;
4066 shift_const
= tcg_const_i64(shift_i
);
4067 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4068 tcg_temp_free_i64(shift_const
);
4072 /* Logical (shifted register)
4073 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4074 * +----+-----+-----------+-------+---+------+--------+------+------+
4075 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4076 * +----+-----+-----------+-------+---+------+--------+------+------+
4078 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4080 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4081 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4083 sf
= extract32(insn
, 31, 1);
4084 opc
= extract32(insn
, 29, 2);
4085 shift_type
= extract32(insn
, 22, 2);
4086 invert
= extract32(insn
, 21, 1);
4087 rm
= extract32(insn
, 16, 5);
4088 shift_amount
= extract32(insn
, 10, 6);
4089 rn
= extract32(insn
, 5, 5);
4090 rd
= extract32(insn
, 0, 5);
4092 if (!sf
&& (shift_amount
& (1 << 5))) {
4093 unallocated_encoding(s
);
4097 tcg_rd
= cpu_reg(s
, rd
);
4099 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4100 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4101 * register-register MOV and MVN, so it is worth special casing.
4103 tcg_rm
= cpu_reg(s
, rm
);
4105 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4107 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4111 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4113 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4119 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4122 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4125 tcg_rn
= cpu_reg(s
, rn
);
4127 switch (opc
| (invert
<< 2)) {
4130 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4133 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4136 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4140 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4143 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4146 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4154 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4158 gen_logic_CC(sf
, tcg_rd
);
4163 * Add/subtract (extended register)
4165 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4166 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4167 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4168 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4170 * sf: 0 -> 32bit, 1 -> 64bit
4171 * op: 0 -> add , 1 -> sub
4174 * option: extension type (see DecodeRegExtend)
4175 * imm3: optional shift to Rm
4177 * Rd = Rn + LSL(extend(Rm), amount)
4179 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4181 int rd
= extract32(insn
, 0, 5);
4182 int rn
= extract32(insn
, 5, 5);
4183 int imm3
= extract32(insn
, 10, 3);
4184 int option
= extract32(insn
, 13, 3);
4185 int rm
= extract32(insn
, 16, 5);
4186 bool setflags
= extract32(insn
, 29, 1);
4187 bool sub_op
= extract32(insn
, 30, 1);
4188 bool sf
= extract32(insn
, 31, 1);
4190 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4192 TCGv_i64 tcg_result
;
4195 unallocated_encoding(s
);
4199 /* non-flag setting ops may use SP */
4201 tcg_rd
= cpu_reg_sp(s
, rd
);
4203 tcg_rd
= cpu_reg(s
, rd
);
4205 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4207 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4208 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4210 tcg_result
= tcg_temp_new_i64();
4214 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4216 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4220 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4222 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4227 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4229 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4232 tcg_temp_free_i64(tcg_result
);
4236 * Add/subtract (shifted register)
4238 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4239 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4240 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4241 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4243 * sf: 0 -> 32bit, 1 -> 64bit
4244 * op: 0 -> add , 1 -> sub
4246 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4247 * imm6: Shift amount to apply to Rm before the add/sub
4249 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4251 int rd
= extract32(insn
, 0, 5);
4252 int rn
= extract32(insn
, 5, 5);
4253 int imm6
= extract32(insn
, 10, 6);
4254 int rm
= extract32(insn
, 16, 5);
4255 int shift_type
= extract32(insn
, 22, 2);
4256 bool setflags
= extract32(insn
, 29, 1);
4257 bool sub_op
= extract32(insn
, 30, 1);
4258 bool sf
= extract32(insn
, 31, 1);
4260 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4261 TCGv_i64 tcg_rn
, tcg_rm
;
4262 TCGv_i64 tcg_result
;
4264 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4265 unallocated_encoding(s
);
4269 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4270 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4272 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4274 tcg_result
= tcg_temp_new_i64();
4278 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4280 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4284 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4286 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4291 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4293 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4296 tcg_temp_free_i64(tcg_result
);
4299 /* Data-processing (3 source)
4301 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4302 * +--+------+-----------+------+------+----+------+------+------+
4303 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4304 * +--+------+-----------+------+------+----+------+------+------+
4306 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4308 int rd
= extract32(insn
, 0, 5);
4309 int rn
= extract32(insn
, 5, 5);
4310 int ra
= extract32(insn
, 10, 5);
4311 int rm
= extract32(insn
, 16, 5);
4312 int op_id
= (extract32(insn
, 29, 3) << 4) |
4313 (extract32(insn
, 21, 3) << 1) |
4314 extract32(insn
, 15, 1);
4315 bool sf
= extract32(insn
, 31, 1);
4316 bool is_sub
= extract32(op_id
, 0, 1);
4317 bool is_high
= extract32(op_id
, 2, 1);
4318 bool is_signed
= false;
4323 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4325 case 0x42: /* SMADDL */
4326 case 0x43: /* SMSUBL */
4327 case 0x44: /* SMULH */
4330 case 0x0: /* MADD (32bit) */
4331 case 0x1: /* MSUB (32bit) */
4332 case 0x40: /* MADD (64bit) */
4333 case 0x41: /* MSUB (64bit) */
4334 case 0x4a: /* UMADDL */
4335 case 0x4b: /* UMSUBL */
4336 case 0x4c: /* UMULH */
4339 unallocated_encoding(s
);
4344 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4345 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4346 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4347 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4350 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4352 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4355 tcg_temp_free_i64(low_bits
);
4359 tcg_op1
= tcg_temp_new_i64();
4360 tcg_op2
= tcg_temp_new_i64();
4361 tcg_tmp
= tcg_temp_new_i64();
4364 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4365 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4368 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4369 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4371 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4372 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4376 if (ra
== 31 && !is_sub
) {
4377 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4378 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4380 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4382 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4384 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4389 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4392 tcg_temp_free_i64(tcg_op1
);
4393 tcg_temp_free_i64(tcg_op2
);
4394 tcg_temp_free_i64(tcg_tmp
);
4397 /* Add/subtract (with carry)
4398 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4399 * +--+--+--+------------------------+------+---------+------+-----+
4400 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4401 * +--+--+--+------------------------+------+---------+------+-----+
4405 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4407 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4408 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4410 if (extract32(insn
, 10, 6) != 0) {
4411 unallocated_encoding(s
);
4415 sf
= extract32(insn
, 31, 1);
4416 op
= extract32(insn
, 30, 1);
4417 setflags
= extract32(insn
, 29, 1);
4418 rm
= extract32(insn
, 16, 5);
4419 rn
= extract32(insn
, 5, 5);
4420 rd
= extract32(insn
, 0, 5);
4422 tcg_rd
= cpu_reg(s
, rd
);
4423 tcg_rn
= cpu_reg(s
, rn
);
4426 tcg_y
= new_tmp_a64(s
);
4427 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4429 tcg_y
= cpu_reg(s
, rm
);
4433 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4435 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4439 /* Conditional compare (immediate / register)
4440 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4441 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4442 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4443 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4446 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4448 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4449 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4450 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4453 if (!extract32(insn
, 29, 1)) {
4454 unallocated_encoding(s
);
4457 if (insn
& (1 << 10 | 1 << 4)) {
4458 unallocated_encoding(s
);
4461 sf
= extract32(insn
, 31, 1);
4462 op
= extract32(insn
, 30, 1);
4463 is_imm
= extract32(insn
, 11, 1);
4464 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4465 cond
= extract32(insn
, 12, 4);
4466 rn
= extract32(insn
, 5, 5);
4467 nzcv
= extract32(insn
, 0, 4);
4469 /* Set T0 = !COND. */
4470 tcg_t0
= tcg_temp_new_i32();
4471 arm_test_cc(&c
, cond
);
4472 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4475 /* Load the arguments for the new comparison. */
4477 tcg_y
= new_tmp_a64(s
);
4478 tcg_gen_movi_i64(tcg_y
, y
);
4480 tcg_y
= cpu_reg(s
, y
);
4482 tcg_rn
= cpu_reg(s
, rn
);
4484 /* Set the flags for the new comparison. */
4485 tcg_tmp
= tcg_temp_new_i64();
4487 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4489 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4491 tcg_temp_free_i64(tcg_tmp
);
4493 /* If COND was false, force the flags to #nzcv. Compute two masks
4494 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4495 * For tcg hosts that support ANDC, we can make do with just T1.
4496 * In either case, allow the tcg optimizer to delete any unused mask.
4498 tcg_t1
= tcg_temp_new_i32();
4499 tcg_t2
= tcg_temp_new_i32();
4500 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4501 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4503 if (nzcv
& 8) { /* N */
4504 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4506 if (TCG_TARGET_HAS_andc_i32
) {
4507 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4509 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4512 if (nzcv
& 4) { /* Z */
4513 if (TCG_TARGET_HAS_andc_i32
) {
4514 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4516 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4519 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4521 if (nzcv
& 2) { /* C */
4522 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4524 if (TCG_TARGET_HAS_andc_i32
) {
4525 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4527 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4530 if (nzcv
& 1) { /* V */
4531 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4533 if (TCG_TARGET_HAS_andc_i32
) {
4534 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4536 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4539 tcg_temp_free_i32(tcg_t0
);
4540 tcg_temp_free_i32(tcg_t1
);
4541 tcg_temp_free_i32(tcg_t2
);
4544 /* Conditional select
4545 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4546 * +----+----+---+-----------------+------+------+-----+------+------+
4547 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4548 * +----+----+---+-----------------+------+------+-----+------+------+
4550 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4552 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4553 TCGv_i64 tcg_rd
, zero
;
4556 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4557 /* S == 1 or op2<1> == 1 */
4558 unallocated_encoding(s
);
4561 sf
= extract32(insn
, 31, 1);
4562 else_inv
= extract32(insn
, 30, 1);
4563 rm
= extract32(insn
, 16, 5);
4564 cond
= extract32(insn
, 12, 4);
4565 else_inc
= extract32(insn
, 10, 1);
4566 rn
= extract32(insn
, 5, 5);
4567 rd
= extract32(insn
, 0, 5);
4569 tcg_rd
= cpu_reg(s
, rd
);
4571 a64_test_cc(&c
, cond
);
4572 zero
= tcg_const_i64(0);
4574 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4576 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4578 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4581 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4582 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4583 if (else_inv
&& else_inc
) {
4584 tcg_gen_neg_i64(t_false
, t_false
);
4585 } else if (else_inv
) {
4586 tcg_gen_not_i64(t_false
, t_false
);
4587 } else if (else_inc
) {
4588 tcg_gen_addi_i64(t_false
, t_false
, 1);
4590 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4593 tcg_temp_free_i64(zero
);
4597 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4601 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4602 unsigned int rn
, unsigned int rd
)
4604 TCGv_i64 tcg_rd
, tcg_rn
;
4605 tcg_rd
= cpu_reg(s
, rd
);
4606 tcg_rn
= cpu_reg(s
, rn
);
4609 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4611 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4612 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4613 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4614 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4615 tcg_temp_free_i32(tcg_tmp32
);
4619 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4620 unsigned int rn
, unsigned int rd
)
4622 TCGv_i64 tcg_rd
, tcg_rn
;
4623 tcg_rd
= cpu_reg(s
, rd
);
4624 tcg_rn
= cpu_reg(s
, rn
);
4627 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4629 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4630 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4631 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4632 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4633 tcg_temp_free_i32(tcg_tmp32
);
4637 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4638 unsigned int rn
, unsigned int rd
)
4640 TCGv_i64 tcg_rd
, tcg_rn
;
4641 tcg_rd
= cpu_reg(s
, rd
);
4642 tcg_rn
= cpu_reg(s
, rn
);
4645 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4647 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4648 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4649 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4650 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4651 tcg_temp_free_i32(tcg_tmp32
);
4655 /* REV with sf==1, opcode==3 ("REV64") */
4656 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4657 unsigned int rn
, unsigned int rd
)
4660 unallocated_encoding(s
);
4663 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4666 /* REV with sf==0, opcode==2
4667 * REV32 (sf==1, opcode==2)
4669 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4670 unsigned int rn
, unsigned int rd
)
4672 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4675 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4676 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4678 /* bswap32_i64 requires zero high word */
4679 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4680 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4681 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4682 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4683 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4685 tcg_temp_free_i64(tcg_tmp
);
4687 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4688 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4692 /* REV16 (opcode==1) */
4693 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4694 unsigned int rn
, unsigned int rd
)
4696 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4697 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4698 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4699 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4701 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4702 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4703 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4704 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4705 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4707 tcg_temp_free_i64(mask
);
4708 tcg_temp_free_i64(tcg_tmp
);
4711 /* Data-processing (1 source)
4712 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4713 * +----+---+---+-----------------+---------+--------+------+------+
4714 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4715 * +----+---+---+-----------------+---------+--------+------+------+
4717 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4719 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4722 if (extract32(insn
, 29, 1)) {
4723 unallocated_encoding(s
);
4727 sf
= extract32(insn
, 31, 1);
4728 opcode
= extract32(insn
, 10, 6);
4729 opcode2
= extract32(insn
, 16, 5);
4730 rn
= extract32(insn
, 5, 5);
4731 rd
= extract32(insn
, 0, 5);
4733 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4735 switch (MAP(sf
, opcode2
, opcode
)) {
4736 case MAP(0, 0x00, 0x00): /* RBIT */
4737 case MAP(1, 0x00, 0x00):
4738 handle_rbit(s
, sf
, rn
, rd
);
4740 case MAP(0, 0x00, 0x01): /* REV16 */
4741 case MAP(1, 0x00, 0x01):
4742 handle_rev16(s
, sf
, rn
, rd
);
4744 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4745 case MAP(1, 0x00, 0x02):
4746 handle_rev32(s
, sf
, rn
, rd
);
4748 case MAP(1, 0x00, 0x03): /* REV64 */
4749 handle_rev64(s
, sf
, rn
, rd
);
4751 case MAP(0, 0x00, 0x04): /* CLZ */
4752 case MAP(1, 0x00, 0x04):
4753 handle_clz(s
, sf
, rn
, rd
);
4755 case MAP(0, 0x00, 0x05): /* CLS */
4756 case MAP(1, 0x00, 0x05):
4757 handle_cls(s
, sf
, rn
, rd
);
4759 case MAP(1, 0x01, 0x00): /* PACIA */
4760 if (s
->pauth_active
) {
4761 tcg_rd
= cpu_reg(s
, rd
);
4762 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4763 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4764 goto do_unallocated
;
4767 case MAP(1, 0x01, 0x01): /* PACIB */
4768 if (s
->pauth_active
) {
4769 tcg_rd
= cpu_reg(s
, rd
);
4770 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4771 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4772 goto do_unallocated
;
4775 case MAP(1, 0x01, 0x02): /* PACDA */
4776 if (s
->pauth_active
) {
4777 tcg_rd
= cpu_reg(s
, rd
);
4778 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4779 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4780 goto do_unallocated
;
4783 case MAP(1, 0x01, 0x03): /* PACDB */
4784 if (s
->pauth_active
) {
4785 tcg_rd
= cpu_reg(s
, rd
);
4786 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4787 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4788 goto do_unallocated
;
4791 case MAP(1, 0x01, 0x04): /* AUTIA */
4792 if (s
->pauth_active
) {
4793 tcg_rd
= cpu_reg(s
, rd
);
4794 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4795 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4796 goto do_unallocated
;
4799 case MAP(1, 0x01, 0x05): /* AUTIB */
4800 if (s
->pauth_active
) {
4801 tcg_rd
= cpu_reg(s
, rd
);
4802 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4803 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4804 goto do_unallocated
;
4807 case MAP(1, 0x01, 0x06): /* AUTDA */
4808 if (s
->pauth_active
) {
4809 tcg_rd
= cpu_reg(s
, rd
);
4810 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4811 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4812 goto do_unallocated
;
4815 case MAP(1, 0x01, 0x07): /* AUTDB */
4816 if (s
->pauth_active
) {
4817 tcg_rd
= cpu_reg(s
, rd
);
4818 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4819 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4820 goto do_unallocated
;
4823 case MAP(1, 0x01, 0x08): /* PACIZA */
4824 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4825 goto do_unallocated
;
4826 } else if (s
->pauth_active
) {
4827 tcg_rd
= cpu_reg(s
, rd
);
4828 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4831 case MAP(1, 0x01, 0x09): /* PACIZB */
4832 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4833 goto do_unallocated
;
4834 } else if (s
->pauth_active
) {
4835 tcg_rd
= cpu_reg(s
, rd
);
4836 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4839 case MAP(1, 0x01, 0x0a): /* PACDZA */
4840 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4841 goto do_unallocated
;
4842 } else if (s
->pauth_active
) {
4843 tcg_rd
= cpu_reg(s
, rd
);
4844 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4847 case MAP(1, 0x01, 0x0b): /* PACDZB */
4848 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4849 goto do_unallocated
;
4850 } else if (s
->pauth_active
) {
4851 tcg_rd
= cpu_reg(s
, rd
);
4852 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4855 case MAP(1, 0x01, 0x0c): /* AUTIZA */
4856 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4857 goto do_unallocated
;
4858 } else if (s
->pauth_active
) {
4859 tcg_rd
= cpu_reg(s
, rd
);
4860 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4863 case MAP(1, 0x01, 0x0d): /* AUTIZB */
4864 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4865 goto do_unallocated
;
4866 } else if (s
->pauth_active
) {
4867 tcg_rd
= cpu_reg(s
, rd
);
4868 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4871 case MAP(1, 0x01, 0x0e): /* AUTDZA */
4872 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4873 goto do_unallocated
;
4874 } else if (s
->pauth_active
) {
4875 tcg_rd
= cpu_reg(s
, rd
);
4876 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4879 case MAP(1, 0x01, 0x0f): /* AUTDZB */
4880 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4881 goto do_unallocated
;
4882 } else if (s
->pauth_active
) {
4883 tcg_rd
= cpu_reg(s
, rd
);
4884 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4887 case MAP(1, 0x01, 0x10): /* XPACI */
4888 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4889 goto do_unallocated
;
4890 } else if (s
->pauth_active
) {
4891 tcg_rd
= cpu_reg(s
, rd
);
4892 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
4895 case MAP(1, 0x01, 0x11): /* XPACD */
4896 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4897 goto do_unallocated
;
4898 } else if (s
->pauth_active
) {
4899 tcg_rd
= cpu_reg(s
, rd
);
4900 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
4905 unallocated_encoding(s
);
4912 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4913 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4915 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4916 tcg_rd
= cpu_reg(s
, rd
);
4918 if (!sf
&& is_signed
) {
4919 tcg_n
= new_tmp_a64(s
);
4920 tcg_m
= new_tmp_a64(s
);
4921 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4922 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4924 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4925 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4929 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4931 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4934 if (!sf
) { /* zero extend final result */
4935 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4939 /* LSLV, LSRV, ASRV, RORV */
4940 static void handle_shift_reg(DisasContext
*s
,
4941 enum a64_shift_type shift_type
, unsigned int sf
,
4942 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4944 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4945 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4946 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4948 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4949 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4950 tcg_temp_free_i64(tcg_shift
);
4953 /* CRC32[BHWX], CRC32C[BHWX] */
4954 static void handle_crc32(DisasContext
*s
,
4955 unsigned int sf
, unsigned int sz
, bool crc32c
,
4956 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4958 TCGv_i64 tcg_acc
, tcg_val
;
4961 if (!dc_isar_feature(aa64_crc32
, s
)
4962 || (sf
== 1 && sz
!= 3)
4963 || (sf
== 0 && sz
== 3)) {
4964 unallocated_encoding(s
);
4969 tcg_val
= cpu_reg(s
, rm
);
4983 g_assert_not_reached();
4985 tcg_val
= new_tmp_a64(s
);
4986 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4989 tcg_acc
= cpu_reg(s
, rn
);
4990 tcg_bytes
= tcg_const_i32(1 << sz
);
4993 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4995 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4998 tcg_temp_free_i32(tcg_bytes
);
5001 /* Data-processing (2 source)
5002 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5003 * +----+---+---+-----------------+------+--------+------+------+
5004 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5005 * +----+---+---+-----------------+------+--------+------+------+
5007 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5009 unsigned int sf
, rm
, opcode
, rn
, rd
;
5010 sf
= extract32(insn
, 31, 1);
5011 rm
= extract32(insn
, 16, 5);
5012 opcode
= extract32(insn
, 10, 6);
5013 rn
= extract32(insn
, 5, 5);
5014 rd
= extract32(insn
, 0, 5);
5016 if (extract32(insn
, 29, 1)) {
5017 unallocated_encoding(s
);
5023 handle_div(s
, false, sf
, rm
, rn
, rd
);
5026 handle_div(s
, true, sf
, rm
, rn
, rd
);
5029 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5032 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5035 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5038 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5040 case 12: /* PACGA */
5041 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5042 goto do_unallocated
;
5044 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5045 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5054 case 23: /* CRC32 */
5056 int sz
= extract32(opcode
, 0, 2);
5057 bool crc32c
= extract32(opcode
, 2, 1);
5058 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5063 unallocated_encoding(s
);
5068 /* Data processing - register */
5069 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5071 switch (extract32(insn
, 24, 5)) {
5072 case 0x0a: /* Logical (shifted register) */
5073 disas_logic_reg(s
, insn
);
5075 case 0x0b: /* Add/subtract */
5076 if (insn
& (1 << 21)) { /* (extended register) */
5077 disas_add_sub_ext_reg(s
, insn
);
5079 disas_add_sub_reg(s
, insn
);
5082 case 0x1b: /* Data-processing (3 source) */
5083 disas_data_proc_3src(s
, insn
);
5086 switch (extract32(insn
, 21, 3)) {
5087 case 0x0: /* Add/subtract (with carry) */
5088 disas_adc_sbc(s
, insn
);
5090 case 0x2: /* Conditional compare */
5091 disas_cc(s
, insn
); /* both imm and reg forms */
5093 case 0x4: /* Conditional select */
5094 disas_cond_select(s
, insn
);
5096 case 0x6: /* Data-processing */
5097 if (insn
& (1 << 30)) { /* (1 source) */
5098 disas_data_proc_1src(s
, insn
);
5099 } else { /* (2 source) */
5100 disas_data_proc_2src(s
, insn
);
5104 unallocated_encoding(s
);
5109 unallocated_encoding(s
);
5114 static void handle_fp_compare(DisasContext
*s
, int size
,
5115 unsigned int rn
, unsigned int rm
,
5116 bool cmp_with_zero
, bool signal_all_nans
)
5118 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5119 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5121 if (size
== MO_64
) {
5122 TCGv_i64 tcg_vn
, tcg_vm
;
5124 tcg_vn
= read_fp_dreg(s
, rn
);
5125 if (cmp_with_zero
) {
5126 tcg_vm
= tcg_const_i64(0);
5128 tcg_vm
= read_fp_dreg(s
, rm
);
5130 if (signal_all_nans
) {
5131 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5133 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5135 tcg_temp_free_i64(tcg_vn
);
5136 tcg_temp_free_i64(tcg_vm
);
5138 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5139 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5141 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5142 if (cmp_with_zero
) {
5143 tcg_gen_movi_i32(tcg_vm
, 0);
5145 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5150 if (signal_all_nans
) {
5151 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5153 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5157 if (signal_all_nans
) {
5158 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5160 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5164 g_assert_not_reached();
5167 tcg_temp_free_i32(tcg_vn
);
5168 tcg_temp_free_i32(tcg_vm
);
5171 tcg_temp_free_ptr(fpst
);
5173 gen_set_nzcv(tcg_flags
);
5175 tcg_temp_free_i64(tcg_flags
);
5178 /* Floating point compare
5179 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5180 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5181 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5182 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5184 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5186 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5189 mos
= extract32(insn
, 29, 3);
5190 type
= extract32(insn
, 22, 2);
5191 rm
= extract32(insn
, 16, 5);
5192 op
= extract32(insn
, 14, 2);
5193 rn
= extract32(insn
, 5, 5);
5194 opc
= extract32(insn
, 3, 2);
5195 op2r
= extract32(insn
, 0, 3);
5197 if (mos
|| op
|| op2r
) {
5198 unallocated_encoding(s
);
5211 if (dc_isar_feature(aa64_fp16
, s
)) {
5216 unallocated_encoding(s
);
5220 if (!fp_access_check(s
)) {
5224 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5227 /* Floating point conditional compare
5228 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5229 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5230 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5231 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5233 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5235 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5237 TCGLabel
*label_continue
= NULL
;
5240 mos
= extract32(insn
, 29, 3);
5241 type
= extract32(insn
, 22, 2);
5242 rm
= extract32(insn
, 16, 5);
5243 cond
= extract32(insn
, 12, 4);
5244 rn
= extract32(insn
, 5, 5);
5245 op
= extract32(insn
, 4, 1);
5246 nzcv
= extract32(insn
, 0, 4);
5249 unallocated_encoding(s
);
5262 if (dc_isar_feature(aa64_fp16
, s
)) {
5267 unallocated_encoding(s
);
5271 if (!fp_access_check(s
)) {
5275 if (cond
< 0x0e) { /* not always */
5276 TCGLabel
*label_match
= gen_new_label();
5277 label_continue
= gen_new_label();
5278 arm_gen_test_cc(cond
, label_match
);
5280 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5281 gen_set_nzcv(tcg_flags
);
5282 tcg_temp_free_i64(tcg_flags
);
5283 tcg_gen_br(label_continue
);
5284 gen_set_label(label_match
);
5287 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5290 gen_set_label(label_continue
);
5294 /* Floating point conditional select
5295 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5296 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5297 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5298 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5300 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5302 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5303 TCGv_i64 t_true
, t_false
, t_zero
;
5307 mos
= extract32(insn
, 29, 3);
5308 type
= extract32(insn
, 22, 2);
5309 rm
= extract32(insn
, 16, 5);
5310 cond
= extract32(insn
, 12, 4);
5311 rn
= extract32(insn
, 5, 5);
5312 rd
= extract32(insn
, 0, 5);
5315 unallocated_encoding(s
);
5328 if (dc_isar_feature(aa64_fp16
, s
)) {
5333 unallocated_encoding(s
);
5337 if (!fp_access_check(s
)) {
5341 /* Zero extend sreg & hreg inputs to 64 bits now. */
5342 t_true
= tcg_temp_new_i64();
5343 t_false
= tcg_temp_new_i64();
5344 read_vec_element(s
, t_true
, rn
, 0, sz
);
5345 read_vec_element(s
, t_false
, rm
, 0, sz
);
5347 a64_test_cc(&c
, cond
);
5348 t_zero
= tcg_const_i64(0);
5349 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5350 tcg_temp_free_i64(t_zero
);
5351 tcg_temp_free_i64(t_false
);
5354 /* Note that sregs & hregs write back zeros to the high bits,
5355 and we've already done the zero-extension. */
5356 write_fp_dreg(s
, rd
, t_true
);
5357 tcg_temp_free_i64(t_true
);
5360 /* Floating-point data-processing (1 source) - half precision */
5361 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5363 TCGv_ptr fpst
= NULL
;
5364 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5365 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5368 case 0x0: /* FMOV */
5369 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5371 case 0x1: /* FABS */
5372 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5374 case 0x2: /* FNEG */
5375 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5377 case 0x3: /* FSQRT */
5378 fpst
= get_fpstatus_ptr(true);
5379 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5381 case 0x8: /* FRINTN */
5382 case 0x9: /* FRINTP */
5383 case 0xa: /* FRINTM */
5384 case 0xb: /* FRINTZ */
5385 case 0xc: /* FRINTA */
5387 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5388 fpst
= get_fpstatus_ptr(true);
5390 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5391 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5393 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5394 tcg_temp_free_i32(tcg_rmode
);
5397 case 0xe: /* FRINTX */
5398 fpst
= get_fpstatus_ptr(true);
5399 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5401 case 0xf: /* FRINTI */
5402 fpst
= get_fpstatus_ptr(true);
5403 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5409 write_fp_sreg(s
, rd
, tcg_res
);
5412 tcg_temp_free_ptr(fpst
);
5414 tcg_temp_free_i32(tcg_op
);
5415 tcg_temp_free_i32(tcg_res
);
5418 /* Floating-point data-processing (1 source) - single precision */
5419 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5425 fpst
= get_fpstatus_ptr(false);
5426 tcg_op
= read_fp_sreg(s
, rn
);
5427 tcg_res
= tcg_temp_new_i32();
5430 case 0x0: /* FMOV */
5431 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5433 case 0x1: /* FABS */
5434 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5436 case 0x2: /* FNEG */
5437 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5439 case 0x3: /* FSQRT */
5440 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5442 case 0x8: /* FRINTN */
5443 case 0x9: /* FRINTP */
5444 case 0xa: /* FRINTM */
5445 case 0xb: /* FRINTZ */
5446 case 0xc: /* FRINTA */
5448 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5450 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5451 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5453 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5454 tcg_temp_free_i32(tcg_rmode
);
5457 case 0xe: /* FRINTX */
5458 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5460 case 0xf: /* FRINTI */
5461 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5467 write_fp_sreg(s
, rd
, tcg_res
);
5469 tcg_temp_free_ptr(fpst
);
5470 tcg_temp_free_i32(tcg_op
);
5471 tcg_temp_free_i32(tcg_res
);
5474 /* Floating-point data-processing (1 source) - double precision */
5475 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5482 case 0x0: /* FMOV */
5483 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5487 fpst
= get_fpstatus_ptr(false);
5488 tcg_op
= read_fp_dreg(s
, rn
);
5489 tcg_res
= tcg_temp_new_i64();
5492 case 0x1: /* FABS */
5493 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5495 case 0x2: /* FNEG */
5496 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5498 case 0x3: /* FSQRT */
5499 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5501 case 0x8: /* FRINTN */
5502 case 0x9: /* FRINTP */
5503 case 0xa: /* FRINTM */
5504 case 0xb: /* FRINTZ */
5505 case 0xc: /* FRINTA */
5507 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5509 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5510 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5512 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5513 tcg_temp_free_i32(tcg_rmode
);
5516 case 0xe: /* FRINTX */
5517 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5519 case 0xf: /* FRINTI */
5520 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5526 write_fp_dreg(s
, rd
, tcg_res
);
5528 tcg_temp_free_ptr(fpst
);
5529 tcg_temp_free_i64(tcg_op
);
5530 tcg_temp_free_i64(tcg_res
);
5533 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5534 int rd
, int rn
, int dtype
, int ntype
)
5539 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5541 /* Single to double */
5542 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5543 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5544 write_fp_dreg(s
, rd
, tcg_rd
);
5545 tcg_temp_free_i64(tcg_rd
);
5547 /* Single to half */
5548 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5549 TCGv_i32 ahp
= get_ahp_flag();
5550 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5552 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5553 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5554 write_fp_sreg(s
, rd
, tcg_rd
);
5555 tcg_temp_free_i32(tcg_rd
);
5556 tcg_temp_free_i32(ahp
);
5557 tcg_temp_free_ptr(fpst
);
5559 tcg_temp_free_i32(tcg_rn
);
5564 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5565 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5567 /* Double to single */
5568 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5570 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5571 TCGv_i32 ahp
= get_ahp_flag();
5572 /* Double to half */
5573 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5574 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5575 tcg_temp_free_ptr(fpst
);
5576 tcg_temp_free_i32(ahp
);
5578 write_fp_sreg(s
, rd
, tcg_rd
);
5579 tcg_temp_free_i32(tcg_rd
);
5580 tcg_temp_free_i64(tcg_rn
);
5585 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5586 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5587 TCGv_i32 tcg_ahp
= get_ahp_flag();
5588 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5590 /* Half to single */
5591 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5592 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5593 write_fp_sreg(s
, rd
, tcg_rd
);
5594 tcg_temp_free_ptr(tcg_fpst
);
5595 tcg_temp_free_i32(tcg_ahp
);
5596 tcg_temp_free_i32(tcg_rd
);
5598 /* Half to double */
5599 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5600 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5601 write_fp_dreg(s
, rd
, tcg_rd
);
5602 tcg_temp_free_i64(tcg_rd
);
5604 tcg_temp_free_i32(tcg_rn
);
5612 /* Floating point data-processing (1 source)
5613 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5614 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5615 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5616 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5618 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5620 int type
= extract32(insn
, 22, 2);
5621 int opcode
= extract32(insn
, 15, 6);
5622 int rn
= extract32(insn
, 5, 5);
5623 int rd
= extract32(insn
, 0, 5);
5626 case 0x4: case 0x5: case 0x7:
5628 /* FCVT between half, single and double precision */
5629 int dtype
= extract32(opcode
, 0, 2);
5630 if (type
== 2 || dtype
== type
) {
5631 unallocated_encoding(s
);
5634 if (!fp_access_check(s
)) {
5638 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5644 /* 32-to-32 and 64-to-64 ops */
5647 if (!fp_access_check(s
)) {
5651 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5654 if (!fp_access_check(s
)) {
5658 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5661 if (!dc_isar_feature(aa64_fp16
, s
)) {
5662 unallocated_encoding(s
);
5666 if (!fp_access_check(s
)) {
5670 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5673 unallocated_encoding(s
);
5677 unallocated_encoding(s
);
5682 /* Floating-point data-processing (2 source) - single precision */
5683 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5684 int rd
, int rn
, int rm
)
5691 tcg_res
= tcg_temp_new_i32();
5692 fpst
= get_fpstatus_ptr(false);
5693 tcg_op1
= read_fp_sreg(s
, rn
);
5694 tcg_op2
= read_fp_sreg(s
, rm
);
5697 case 0x0: /* FMUL */
5698 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5700 case 0x1: /* FDIV */
5701 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5703 case 0x2: /* FADD */
5704 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5706 case 0x3: /* FSUB */
5707 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5709 case 0x4: /* FMAX */
5710 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5712 case 0x5: /* FMIN */
5713 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5715 case 0x6: /* FMAXNM */
5716 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5718 case 0x7: /* FMINNM */
5719 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5721 case 0x8: /* FNMUL */
5722 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5723 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5727 write_fp_sreg(s
, rd
, tcg_res
);
5729 tcg_temp_free_ptr(fpst
);
5730 tcg_temp_free_i32(tcg_op1
);
5731 tcg_temp_free_i32(tcg_op2
);
5732 tcg_temp_free_i32(tcg_res
);
5735 /* Floating-point data-processing (2 source) - double precision */
5736 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5737 int rd
, int rn
, int rm
)
5744 tcg_res
= tcg_temp_new_i64();
5745 fpst
= get_fpstatus_ptr(false);
5746 tcg_op1
= read_fp_dreg(s
, rn
);
5747 tcg_op2
= read_fp_dreg(s
, rm
);
5750 case 0x0: /* FMUL */
5751 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5753 case 0x1: /* FDIV */
5754 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5756 case 0x2: /* FADD */
5757 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5759 case 0x3: /* FSUB */
5760 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5762 case 0x4: /* FMAX */
5763 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5765 case 0x5: /* FMIN */
5766 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5768 case 0x6: /* FMAXNM */
5769 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5771 case 0x7: /* FMINNM */
5772 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5774 case 0x8: /* FNMUL */
5775 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5776 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5780 write_fp_dreg(s
, rd
, tcg_res
);
5782 tcg_temp_free_ptr(fpst
);
5783 tcg_temp_free_i64(tcg_op1
);
5784 tcg_temp_free_i64(tcg_op2
);
5785 tcg_temp_free_i64(tcg_res
);
5788 /* Floating-point data-processing (2 source) - half precision */
5789 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5790 int rd
, int rn
, int rm
)
5797 tcg_res
= tcg_temp_new_i32();
5798 fpst
= get_fpstatus_ptr(true);
5799 tcg_op1
= read_fp_hreg(s
, rn
);
5800 tcg_op2
= read_fp_hreg(s
, rm
);
5803 case 0x0: /* FMUL */
5804 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5806 case 0x1: /* FDIV */
5807 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5809 case 0x2: /* FADD */
5810 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5812 case 0x3: /* FSUB */
5813 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5815 case 0x4: /* FMAX */
5816 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5818 case 0x5: /* FMIN */
5819 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5821 case 0x6: /* FMAXNM */
5822 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5824 case 0x7: /* FMINNM */
5825 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5827 case 0x8: /* FNMUL */
5828 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5829 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5832 g_assert_not_reached();
5835 write_fp_sreg(s
, rd
, tcg_res
);
5837 tcg_temp_free_ptr(fpst
);
5838 tcg_temp_free_i32(tcg_op1
);
5839 tcg_temp_free_i32(tcg_op2
);
5840 tcg_temp_free_i32(tcg_res
);
5843 /* Floating point data-processing (2 source)
5844 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5845 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5846 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5847 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5849 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5851 int type
= extract32(insn
, 22, 2);
5852 int rd
= extract32(insn
, 0, 5);
5853 int rn
= extract32(insn
, 5, 5);
5854 int rm
= extract32(insn
, 16, 5);
5855 int opcode
= extract32(insn
, 12, 4);
5858 unallocated_encoding(s
);
5864 if (!fp_access_check(s
)) {
5867 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5870 if (!fp_access_check(s
)) {
5873 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5876 if (!dc_isar_feature(aa64_fp16
, s
)) {
5877 unallocated_encoding(s
);
5880 if (!fp_access_check(s
)) {
5883 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5886 unallocated_encoding(s
);
5890 /* Floating-point data-processing (3 source) - single precision */
5891 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5892 int rd
, int rn
, int rm
, int ra
)
5894 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5895 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5896 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5898 tcg_op1
= read_fp_sreg(s
, rn
);
5899 tcg_op2
= read_fp_sreg(s
, rm
);
5900 tcg_op3
= read_fp_sreg(s
, ra
);
5902 /* These are fused multiply-add, and must be done as one
5903 * floating point operation with no rounding between the
5904 * multiplication and addition steps.
5905 * NB that doing the negations here as separate steps is
5906 * correct : an input NaN should come out with its sign bit
5907 * flipped if it is a negated-input.
5910 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
5914 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
5917 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5919 write_fp_sreg(s
, rd
, tcg_res
);
5921 tcg_temp_free_ptr(fpst
);
5922 tcg_temp_free_i32(tcg_op1
);
5923 tcg_temp_free_i32(tcg_op2
);
5924 tcg_temp_free_i32(tcg_op3
);
5925 tcg_temp_free_i32(tcg_res
);
5928 /* Floating-point data-processing (3 source) - double precision */
5929 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
5930 int rd
, int rn
, int rm
, int ra
)
5932 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
5933 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5934 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5936 tcg_op1
= read_fp_dreg(s
, rn
);
5937 tcg_op2
= read_fp_dreg(s
, rm
);
5938 tcg_op3
= read_fp_dreg(s
, ra
);
5940 /* These are fused multiply-add, and must be done as one
5941 * floating point operation with no rounding between the
5942 * multiplication and addition steps.
5943 * NB that doing the negations here as separate steps is
5944 * correct : an input NaN should come out with its sign bit
5945 * flipped if it is a negated-input.
5948 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
5952 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
5955 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5957 write_fp_dreg(s
, rd
, tcg_res
);
5959 tcg_temp_free_ptr(fpst
);
5960 tcg_temp_free_i64(tcg_op1
);
5961 tcg_temp_free_i64(tcg_op2
);
5962 tcg_temp_free_i64(tcg_op3
);
5963 tcg_temp_free_i64(tcg_res
);
5966 /* Floating-point data-processing (3 source) - half precision */
5967 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
5968 int rd
, int rn
, int rm
, int ra
)
5970 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5971 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5972 TCGv_ptr fpst
= get_fpstatus_ptr(true);
5974 tcg_op1
= read_fp_hreg(s
, rn
);
5975 tcg_op2
= read_fp_hreg(s
, rm
);
5976 tcg_op3
= read_fp_hreg(s
, ra
);
5978 /* These are fused multiply-add, and must be done as one
5979 * floating point operation with no rounding between the
5980 * multiplication and addition steps.
5981 * NB that doing the negations here as separate steps is
5982 * correct : an input NaN should come out with its sign bit
5983 * flipped if it is a negated-input.
5986 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
5990 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
5993 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5995 write_fp_sreg(s
, rd
, tcg_res
);
5997 tcg_temp_free_ptr(fpst
);
5998 tcg_temp_free_i32(tcg_op1
);
5999 tcg_temp_free_i32(tcg_op2
);
6000 tcg_temp_free_i32(tcg_op3
);
6001 tcg_temp_free_i32(tcg_res
);
6004 /* Floating point data-processing (3 source)
6005 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6006 * +---+---+---+-----------+------+----+------+----+------+------+------+
6007 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6008 * +---+---+---+-----------+------+----+------+----+------+------+------+
6010 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6012 int type
= extract32(insn
, 22, 2);
6013 int rd
= extract32(insn
, 0, 5);
6014 int rn
= extract32(insn
, 5, 5);
6015 int ra
= extract32(insn
, 10, 5);
6016 int rm
= extract32(insn
, 16, 5);
6017 bool o0
= extract32(insn
, 15, 1);
6018 bool o1
= extract32(insn
, 21, 1);
6022 if (!fp_access_check(s
)) {
6025 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6028 if (!fp_access_check(s
)) {
6031 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6034 if (!dc_isar_feature(aa64_fp16
, s
)) {
6035 unallocated_encoding(s
);
6038 if (!fp_access_check(s
)) {
6041 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6044 unallocated_encoding(s
);
6048 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
6049 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
6050 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
6052 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
6058 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6059 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
6060 extract32(imm8
, 0, 6);
6064 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6065 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
6066 (extract32(imm8
, 0, 6) << 3);
6070 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6071 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
6072 (extract32(imm8
, 0, 6) << 6);
6075 g_assert_not_reached();
6080 /* Floating point immediate
6081 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6082 * +---+---+---+-----------+------+---+------------+-------+------+------+
6083 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6084 * +---+---+---+-----------+------+---+------------+-------+------+------+
6086 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6088 int rd
= extract32(insn
, 0, 5);
6089 int imm8
= extract32(insn
, 13, 8);
6090 int type
= extract32(insn
, 22, 2);
6104 if (dc_isar_feature(aa64_fp16
, s
)) {
6109 unallocated_encoding(s
);
6113 if (!fp_access_check(s
)) {
6117 imm
= vfp_expand_imm(sz
, imm8
);
6119 tcg_res
= tcg_const_i64(imm
);
6120 write_fp_dreg(s
, rd
, tcg_res
);
6121 tcg_temp_free_i64(tcg_res
);
6124 /* Handle floating point <=> fixed point conversions. Note that we can
6125 * also deal with fp <=> integer conversions as a special case (scale == 64)
6126 * OPTME: consider handling that special case specially or at least skipping
6127 * the call to scalbn in the helpers for zero shifts.
6129 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6130 bool itof
, int rmode
, int scale
, int sf
, int type
)
6132 bool is_signed
= !(opcode
& 1);
6133 TCGv_ptr tcg_fpstatus
;
6134 TCGv_i32 tcg_shift
, tcg_single
;
6135 TCGv_i64 tcg_double
;
6137 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6139 tcg_shift
= tcg_const_i32(64 - scale
);
6142 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6144 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6147 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6149 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6152 tcg_int
= tcg_extend
;
6156 case 1: /* float64 */
6157 tcg_double
= tcg_temp_new_i64();
6159 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6160 tcg_shift
, tcg_fpstatus
);
6162 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6163 tcg_shift
, tcg_fpstatus
);
6165 write_fp_dreg(s
, rd
, tcg_double
);
6166 tcg_temp_free_i64(tcg_double
);
6169 case 0: /* float32 */
6170 tcg_single
= tcg_temp_new_i32();
6172 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6173 tcg_shift
, tcg_fpstatus
);
6175 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6176 tcg_shift
, tcg_fpstatus
);
6178 write_fp_sreg(s
, rd
, tcg_single
);
6179 tcg_temp_free_i32(tcg_single
);
6182 case 3: /* float16 */
6183 tcg_single
= tcg_temp_new_i32();
6185 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6186 tcg_shift
, tcg_fpstatus
);
6188 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6189 tcg_shift
, tcg_fpstatus
);
6191 write_fp_sreg(s
, rd
, tcg_single
);
6192 tcg_temp_free_i32(tcg_single
);
6196 g_assert_not_reached();
6199 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6202 if (extract32(opcode
, 2, 1)) {
6203 /* There are too many rounding modes to all fit into rmode,
6204 * so FCVTA[US] is a special case.
6206 rmode
= FPROUNDING_TIEAWAY
;
6209 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6211 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6214 case 1: /* float64 */
6215 tcg_double
= read_fp_dreg(s
, rn
);
6218 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6219 tcg_shift
, tcg_fpstatus
);
6221 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6222 tcg_shift
, tcg_fpstatus
);
6226 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6227 tcg_shift
, tcg_fpstatus
);
6229 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6230 tcg_shift
, tcg_fpstatus
);
6234 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6236 tcg_temp_free_i64(tcg_double
);
6239 case 0: /* float32 */
6240 tcg_single
= read_fp_sreg(s
, rn
);
6243 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6244 tcg_shift
, tcg_fpstatus
);
6246 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6247 tcg_shift
, tcg_fpstatus
);
6250 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6252 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6253 tcg_shift
, tcg_fpstatus
);
6255 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6256 tcg_shift
, tcg_fpstatus
);
6258 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6259 tcg_temp_free_i32(tcg_dest
);
6261 tcg_temp_free_i32(tcg_single
);
6264 case 3: /* float16 */
6265 tcg_single
= read_fp_sreg(s
, rn
);
6268 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6269 tcg_shift
, tcg_fpstatus
);
6271 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6272 tcg_shift
, tcg_fpstatus
);
6275 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6277 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6278 tcg_shift
, tcg_fpstatus
);
6280 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6281 tcg_shift
, tcg_fpstatus
);
6283 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6284 tcg_temp_free_i32(tcg_dest
);
6286 tcg_temp_free_i32(tcg_single
);
6290 g_assert_not_reached();
6293 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6294 tcg_temp_free_i32(tcg_rmode
);
6297 tcg_temp_free_ptr(tcg_fpstatus
);
6298 tcg_temp_free_i32(tcg_shift
);
6301 /* Floating point <-> fixed point conversions
6302 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6303 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6304 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6305 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6307 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6309 int rd
= extract32(insn
, 0, 5);
6310 int rn
= extract32(insn
, 5, 5);
6311 int scale
= extract32(insn
, 10, 6);
6312 int opcode
= extract32(insn
, 16, 3);
6313 int rmode
= extract32(insn
, 19, 2);
6314 int type
= extract32(insn
, 22, 2);
6315 bool sbit
= extract32(insn
, 29, 1);
6316 bool sf
= extract32(insn
, 31, 1);
6319 if (sbit
|| (!sf
&& scale
< 32)) {
6320 unallocated_encoding(s
);
6325 case 0: /* float32 */
6326 case 1: /* float64 */
6328 case 3: /* float16 */
6329 if (dc_isar_feature(aa64_fp16
, s
)) {
6334 unallocated_encoding(s
);
6338 switch ((rmode
<< 3) | opcode
) {
6339 case 0x2: /* SCVTF */
6340 case 0x3: /* UCVTF */
6343 case 0x18: /* FCVTZS */
6344 case 0x19: /* FCVTZU */
6348 unallocated_encoding(s
);
6352 if (!fp_access_check(s
)) {
6356 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6359 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6361 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6362 * without conversion.
6366 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6372 tmp
= tcg_temp_new_i64();
6373 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6374 write_fp_dreg(s
, rd
, tmp
);
6375 tcg_temp_free_i64(tmp
);
6379 write_fp_dreg(s
, rd
, tcg_rn
);
6382 /* 64 bit to top half. */
6383 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6384 clear_vec_high(s
, true, rd
);
6388 tmp
= tcg_temp_new_i64();
6389 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6390 write_fp_dreg(s
, rd
, tmp
);
6391 tcg_temp_free_i64(tmp
);
6394 g_assert_not_reached();
6397 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6402 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6406 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6409 /* 64 bits from top half */
6410 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6414 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6417 g_assert_not_reached();
6422 /* Floating point <-> integer conversions
6423 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6424 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6425 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6426 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6428 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6430 int rd
= extract32(insn
, 0, 5);
6431 int rn
= extract32(insn
, 5, 5);
6432 int opcode
= extract32(insn
, 16, 3);
6433 int rmode
= extract32(insn
, 19, 2);
6434 int type
= extract32(insn
, 22, 2);
6435 bool sbit
= extract32(insn
, 29, 1);
6436 bool sf
= extract32(insn
, 31, 1);
6439 unallocated_encoding(s
);
6445 bool itof
= opcode
& 1;
6448 unallocated_encoding(s
);
6452 switch (sf
<< 3 | type
<< 1 | rmode
) {
6453 case 0x0: /* 32 bit */
6454 case 0xa: /* 64 bit */
6455 case 0xd: /* 64 bit to top half of quad */
6457 case 0x6: /* 16-bit float, 32-bit int */
6458 case 0xe: /* 16-bit float, 64-bit int */
6459 if (dc_isar_feature(aa64_fp16
, s
)) {
6464 /* all other sf/type/rmode combinations are invalid */
6465 unallocated_encoding(s
);
6469 if (!fp_access_check(s
)) {
6472 handle_fmov(s
, rd
, rn
, type
, itof
);
6474 /* actual FP conversions */
6475 bool itof
= extract32(opcode
, 1, 1);
6477 if (rmode
!= 0 && opcode
> 1) {
6478 unallocated_encoding(s
);
6482 case 0: /* float32 */
6483 case 1: /* float64 */
6485 case 3: /* float16 */
6486 if (dc_isar_feature(aa64_fp16
, s
)) {
6491 unallocated_encoding(s
);
6495 if (!fp_access_check(s
)) {
6498 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6502 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6503 * 31 30 29 28 25 24 0
6504 * +---+---+---+---------+-----------------------------+
6505 * | | 0 | | 1 1 1 1 | |
6506 * +---+---+---+---------+-----------------------------+
6508 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6510 if (extract32(insn
, 24, 1)) {
6511 /* Floating point data-processing (3 source) */
6512 disas_fp_3src(s
, insn
);
6513 } else if (extract32(insn
, 21, 1) == 0) {
6514 /* Floating point to fixed point conversions */
6515 disas_fp_fixed_conv(s
, insn
);
6517 switch (extract32(insn
, 10, 2)) {
6519 /* Floating point conditional compare */
6520 disas_fp_ccomp(s
, insn
);
6523 /* Floating point data-processing (2 source) */
6524 disas_fp_2src(s
, insn
);
6527 /* Floating point conditional select */
6528 disas_fp_csel(s
, insn
);
6531 switch (ctz32(extract32(insn
, 12, 4))) {
6532 case 0: /* [15:12] == xxx1 */
6533 /* Floating point immediate */
6534 disas_fp_imm(s
, insn
);
6536 case 1: /* [15:12] == xx10 */
6537 /* Floating point compare */
6538 disas_fp_compare(s
, insn
);
6540 case 2: /* [15:12] == x100 */
6541 /* Floating point data-processing (1 source) */
6542 disas_fp_1src(s
, insn
);
6544 case 3: /* [15:12] == 1000 */
6545 unallocated_encoding(s
);
6547 default: /* [15:12] == 0000 */
6548 /* Floating point <-> integer conversions */
6549 disas_fp_int_conv(s
, insn
);
6557 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6560 /* Extract 64 bits from the middle of two concatenated 64 bit
6561 * vector register slices left:right. The extracted bits start
6562 * at 'pos' bits into the right (least significant) side.
6563 * We return the result in tcg_right, and guarantee not to
6566 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6567 assert(pos
> 0 && pos
< 64);
6569 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6570 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6571 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6573 tcg_temp_free_i64(tcg_tmp
);
6577 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6578 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6579 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6580 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6582 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6584 int is_q
= extract32(insn
, 30, 1);
6585 int op2
= extract32(insn
, 22, 2);
6586 int imm4
= extract32(insn
, 11, 4);
6587 int rm
= extract32(insn
, 16, 5);
6588 int rn
= extract32(insn
, 5, 5);
6589 int rd
= extract32(insn
, 0, 5);
6590 int pos
= imm4
<< 3;
6591 TCGv_i64 tcg_resl
, tcg_resh
;
6593 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6594 unallocated_encoding(s
);
6598 if (!fp_access_check(s
)) {
6602 tcg_resh
= tcg_temp_new_i64();
6603 tcg_resl
= tcg_temp_new_i64();
6605 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6606 * either extracting 128 bits from a 128:128 concatenation, or
6607 * extracting 64 bits from a 64:64 concatenation.
6610 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6612 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6613 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6615 tcg_gen_movi_i64(tcg_resh
, 0);
6622 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6623 EltPosns
*elt
= eltposns
;
6630 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6632 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6635 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6636 tcg_hh
= tcg_temp_new_i64();
6637 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6638 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6639 tcg_temp_free_i64(tcg_hh
);
6643 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6644 tcg_temp_free_i64(tcg_resl
);
6645 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6646 tcg_temp_free_i64(tcg_resh
);
6650 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6651 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6652 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6653 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6655 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6657 int op2
= extract32(insn
, 22, 2);
6658 int is_q
= extract32(insn
, 30, 1);
6659 int rm
= extract32(insn
, 16, 5);
6660 int rn
= extract32(insn
, 5, 5);
6661 int rd
= extract32(insn
, 0, 5);
6662 int is_tblx
= extract32(insn
, 12, 1);
6663 int len
= extract32(insn
, 13, 2);
6664 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6665 TCGv_i32 tcg_regno
, tcg_numregs
;
6668 unallocated_encoding(s
);
6672 if (!fp_access_check(s
)) {
6676 /* This does a table lookup: for every byte element in the input
6677 * we index into a table formed from up to four vector registers,
6678 * and then the output is the result of the lookups. Our helper
6679 * function does the lookup operation for a single 64 bit part of
6682 tcg_resl
= tcg_temp_new_i64();
6683 tcg_resh
= tcg_temp_new_i64();
6686 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6688 tcg_gen_movi_i64(tcg_resl
, 0);
6690 if (is_tblx
&& is_q
) {
6691 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6693 tcg_gen_movi_i64(tcg_resh
, 0);
6696 tcg_idx
= tcg_temp_new_i64();
6697 tcg_regno
= tcg_const_i32(rn
);
6698 tcg_numregs
= tcg_const_i32(len
+ 1);
6699 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6700 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6701 tcg_regno
, tcg_numregs
);
6703 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6704 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6705 tcg_regno
, tcg_numregs
);
6707 tcg_temp_free_i64(tcg_idx
);
6708 tcg_temp_free_i32(tcg_regno
);
6709 tcg_temp_free_i32(tcg_numregs
);
6711 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6712 tcg_temp_free_i64(tcg_resl
);
6713 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6714 tcg_temp_free_i64(tcg_resh
);
6718 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6719 * +---+---+-------------+------+---+------+---+------------------+------+
6720 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6721 * +---+---+-------------+------+---+------+---+------------------+------+
6723 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6725 int rd
= extract32(insn
, 0, 5);
6726 int rn
= extract32(insn
, 5, 5);
6727 int rm
= extract32(insn
, 16, 5);
6728 int size
= extract32(insn
, 22, 2);
6729 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6730 * bit 2 indicates 1 vs 2 variant of the insn.
6732 int opcode
= extract32(insn
, 12, 2);
6733 bool part
= extract32(insn
, 14, 1);
6734 bool is_q
= extract32(insn
, 30, 1);
6735 int esize
= 8 << size
;
6737 int datasize
= is_q
? 128 : 64;
6738 int elements
= datasize
/ esize
;
6739 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6741 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6742 unallocated_encoding(s
);
6746 if (!fp_access_check(s
)) {
6750 tcg_resl
= tcg_const_i64(0);
6751 tcg_resh
= tcg_const_i64(0);
6752 tcg_res
= tcg_temp_new_i64();
6754 for (i
= 0; i
< elements
; i
++) {
6756 case 1: /* UZP1/2 */
6758 int midpoint
= elements
/ 2;
6760 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6762 read_vec_element(s
, tcg_res
, rm
,
6763 2 * (i
- midpoint
) + part
, size
);
6767 case 2: /* TRN1/2 */
6769 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6771 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6774 case 3: /* ZIP1/2 */
6776 int base
= part
* elements
/ 2;
6778 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6780 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6785 g_assert_not_reached();
6790 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6791 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6793 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6794 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6798 tcg_temp_free_i64(tcg_res
);
6800 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6801 tcg_temp_free_i64(tcg_resl
);
6802 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6803 tcg_temp_free_i64(tcg_resh
);
6807 * do_reduction_op helper
6809 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6810 * important for correct NaN propagation that we do these
6811 * operations in exactly the order specified by the pseudocode.
6813 * This is a recursive function, TCG temps should be freed by the
6814 * calling function once it is done with the values.
6816 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6817 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6819 if (esize
== size
) {
6821 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6824 /* We should have one register left here */
6825 assert(ctpop8(vmap
) == 1);
6826 element
= ctz32(vmap
);
6827 assert(element
< 8);
6829 tcg_elem
= tcg_temp_new_i32();
6830 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6833 int bits
= size
/ 2;
6834 int shift
= ctpop8(vmap
) / 2;
6835 int vmap_lo
= (vmap
>> shift
) & vmap
;
6836 int vmap_hi
= (vmap
& ~vmap_lo
);
6837 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6839 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6840 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6841 tcg_res
= tcg_temp_new_i32();
6844 case 0x0c: /* fmaxnmv half-precision */
6845 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6847 case 0x0f: /* fmaxv half-precision */
6848 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6850 case 0x1c: /* fminnmv half-precision */
6851 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6853 case 0x1f: /* fminv half-precision */
6854 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6856 case 0x2c: /* fmaxnmv */
6857 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6859 case 0x2f: /* fmaxv */
6860 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6862 case 0x3c: /* fminnmv */
6863 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6865 case 0x3f: /* fminv */
6866 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6869 g_assert_not_reached();
6872 tcg_temp_free_i32(tcg_hi
);
6873 tcg_temp_free_i32(tcg_lo
);
6878 /* AdvSIMD across lanes
6879 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6880 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6881 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6882 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6884 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6886 int rd
= extract32(insn
, 0, 5);
6887 int rn
= extract32(insn
, 5, 5);
6888 int size
= extract32(insn
, 22, 2);
6889 int opcode
= extract32(insn
, 12, 5);
6890 bool is_q
= extract32(insn
, 30, 1);
6891 bool is_u
= extract32(insn
, 29, 1);
6893 bool is_min
= false;
6897 TCGv_i64 tcg_res
, tcg_elt
;
6900 case 0x1b: /* ADDV */
6902 unallocated_encoding(s
);
6906 case 0x3: /* SADDLV, UADDLV */
6907 case 0xa: /* SMAXV, UMAXV */
6908 case 0x1a: /* SMINV, UMINV */
6909 if (size
== 3 || (size
== 2 && !is_q
)) {
6910 unallocated_encoding(s
);
6914 case 0xc: /* FMAXNMV, FMINNMV */
6915 case 0xf: /* FMAXV, FMINV */
6916 /* Bit 1 of size field encodes min vs max and the actual size
6917 * depends on the encoding of the U bit. If not set (and FP16
6918 * enabled) then we do half-precision float instead of single
6921 is_min
= extract32(size
, 1, 1);
6923 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
6925 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
6926 unallocated_encoding(s
);
6933 unallocated_encoding(s
);
6937 if (!fp_access_check(s
)) {
6942 elements
= (is_q
? 128 : 64) / esize
;
6944 tcg_res
= tcg_temp_new_i64();
6945 tcg_elt
= tcg_temp_new_i64();
6947 /* These instructions operate across all lanes of a vector
6948 * to produce a single result. We can guarantee that a 64
6949 * bit intermediate is sufficient:
6950 * + for [US]ADDLV the maximum element size is 32 bits, and
6951 * the result type is 64 bits
6952 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
6953 * same as the element size, which is 32 bits at most
6954 * For the integer operations we can choose to work at 64
6955 * or 32 bits and truncate at the end; for simplicity
6956 * we use 64 bits always. The floating point
6957 * ops do require 32 bit intermediates, though.
6960 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
6962 for (i
= 1; i
< elements
; i
++) {
6963 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
6966 case 0x03: /* SADDLV / UADDLV */
6967 case 0x1b: /* ADDV */
6968 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
6970 case 0x0a: /* SMAXV / UMAXV */
6972 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
6974 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
6977 case 0x1a: /* SMINV / UMINV */
6979 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
6981 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
6985 g_assert_not_reached();
6990 /* Floating point vector reduction ops which work across 32
6991 * bit (single) or 16 bit (half-precision) intermediates.
6992 * Note that correct NaN propagation requires that we do these
6993 * operations in exactly the order specified by the pseudocode.
6995 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
6996 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
6997 int vmap
= (1 << elements
) - 1;
6998 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
6999 (is_q
? 128 : 64), vmap
, fpst
);
7000 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7001 tcg_temp_free_i32(tcg_res32
);
7002 tcg_temp_free_ptr(fpst
);
7005 tcg_temp_free_i64(tcg_elt
);
7007 /* Now truncate the result to the width required for the final output */
7008 if (opcode
== 0x03) {
7009 /* SADDLV, UADDLV: result is 2*esize */
7015 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7018 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7021 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7026 g_assert_not_reached();
7029 write_fp_dreg(s
, rd
, tcg_res
);
7030 tcg_temp_free_i64(tcg_res
);
7033 /* DUP (Element, Vector)
7035 * 31 30 29 21 20 16 15 10 9 5 4 0
7036 * +---+---+-------------------+--------+-------------+------+------+
7037 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7038 * +---+---+-------------------+--------+-------------+------+------+
7040 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7042 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7045 int size
= ctz32(imm5
);
7046 int index
= imm5
>> (size
+ 1);
7048 if (size
> 3 || (size
== 3 && !is_q
)) {
7049 unallocated_encoding(s
);
7053 if (!fp_access_check(s
)) {
7057 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7058 vec_reg_offset(s
, rn
, index
, size
),
7059 is_q
? 16 : 8, vec_full_reg_size(s
));
7062 /* DUP (element, scalar)
7063 * 31 21 20 16 15 10 9 5 4 0
7064 * +-----------------------+--------+-------------+------+------+
7065 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7066 * +-----------------------+--------+-------------+------+------+
7068 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7071 int size
= ctz32(imm5
);
7076 unallocated_encoding(s
);
7080 if (!fp_access_check(s
)) {
7084 index
= imm5
>> (size
+ 1);
7086 /* This instruction just extracts the specified element and
7087 * zero-extends it into the bottom of the destination register.
7089 tmp
= tcg_temp_new_i64();
7090 read_vec_element(s
, tmp
, rn
, index
, size
);
7091 write_fp_dreg(s
, rd
, tmp
);
7092 tcg_temp_free_i64(tmp
);
7097 * 31 30 29 21 20 16 15 10 9 5 4 0
7098 * +---+---+-------------------+--------+-------------+------+------+
7099 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7100 * +---+---+-------------------+--------+-------------+------+------+
7102 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7104 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7107 int size
= ctz32(imm5
);
7108 uint32_t dofs
, oprsz
, maxsz
;
7110 if (size
> 3 || ((size
== 3) && !is_q
)) {
7111 unallocated_encoding(s
);
7115 if (!fp_access_check(s
)) {
7119 dofs
= vec_full_reg_offset(s
, rd
);
7120 oprsz
= is_q
? 16 : 8;
7121 maxsz
= vec_full_reg_size(s
);
7123 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7128 * 31 21 20 16 15 14 11 10 9 5 4 0
7129 * +-----------------------+--------+------------+---+------+------+
7130 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7131 * +-----------------------+--------+------------+---+------+------+
7133 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7134 * index: encoded in imm5<4:size+1>
7136 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7139 int size
= ctz32(imm5
);
7140 int src_index
, dst_index
;
7144 unallocated_encoding(s
);
7148 if (!fp_access_check(s
)) {
7152 dst_index
= extract32(imm5
, 1+size
, 5);
7153 src_index
= extract32(imm4
, size
, 4);
7155 tmp
= tcg_temp_new_i64();
7157 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7158 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7160 tcg_temp_free_i64(tmp
);
7166 * 31 21 20 16 15 10 9 5 4 0
7167 * +-----------------------+--------+-------------+------+------+
7168 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7169 * +-----------------------+--------+-------------+------+------+
7171 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7172 * index: encoded in imm5<4:size+1>
7174 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7176 int size
= ctz32(imm5
);
7180 unallocated_encoding(s
);
7184 if (!fp_access_check(s
)) {
7188 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7189 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7196 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7197 * +---+---+-------------------+--------+-------------+------+------+
7198 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7199 * +---+---+-------------------+--------+-------------+------+------+
7201 * U: unsigned when set
7202 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7204 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7205 int rn
, int rd
, int imm5
)
7207 int size
= ctz32(imm5
);
7211 /* Check for UnallocatedEncodings */
7213 if (size
> 2 || (size
== 2 && !is_q
)) {
7214 unallocated_encoding(s
);
7219 || (size
< 3 && is_q
)
7220 || (size
== 3 && !is_q
)) {
7221 unallocated_encoding(s
);
7226 if (!fp_access_check(s
)) {
7230 element
= extract32(imm5
, 1+size
, 4);
7232 tcg_rd
= cpu_reg(s
, rd
);
7233 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7234 if (is_signed
&& !is_q
) {
7235 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7240 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7241 * +---+---+----+-----------------+------+---+------+---+------+------+
7242 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7243 * +---+---+----+-----------------+------+---+------+---+------+------+
7245 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7247 int rd
= extract32(insn
, 0, 5);
7248 int rn
= extract32(insn
, 5, 5);
7249 int imm4
= extract32(insn
, 11, 4);
7250 int op
= extract32(insn
, 29, 1);
7251 int is_q
= extract32(insn
, 30, 1);
7252 int imm5
= extract32(insn
, 16, 5);
7257 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7259 unallocated_encoding(s
);
7264 /* DUP (element - vector) */
7265 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7269 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7274 handle_simd_insg(s
, rd
, rn
, imm5
);
7276 unallocated_encoding(s
);
7281 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7282 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7285 unallocated_encoding(s
);
7291 /* AdvSIMD modified immediate
7292 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7293 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7294 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7295 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7297 * There are a number of operations that can be carried out here:
7298 * MOVI - move (shifted) imm into register
7299 * MVNI - move inverted (shifted) imm into register
7300 * ORR - bitwise OR of (shifted) imm with register
7301 * BIC - bitwise clear of (shifted) imm with register
7302 * With ARMv8.2 we also have:
7303 * FMOV half-precision
7305 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7307 int rd
= extract32(insn
, 0, 5);
7308 int cmode
= extract32(insn
, 12, 4);
7309 int cmode_3_1
= extract32(cmode
, 1, 3);
7310 int cmode_0
= extract32(cmode
, 0, 1);
7311 int o2
= extract32(insn
, 11, 1);
7312 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7313 bool is_neg
= extract32(insn
, 29, 1);
7314 bool is_q
= extract32(insn
, 30, 1);
7317 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7318 /* Check for FMOV (vector, immediate) - half-precision */
7319 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7320 unallocated_encoding(s
);
7325 if (!fp_access_check(s
)) {
7329 /* See AdvSIMDExpandImm() in ARM ARM */
7330 switch (cmode_3_1
) {
7331 case 0: /* Replicate(Zeros(24):imm8, 2) */
7332 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7333 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7334 case 3: /* Replicate(imm8:Zeros(24), 2) */
7336 int shift
= cmode_3_1
* 8;
7337 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7340 case 4: /* Replicate(Zeros(8):imm8, 4) */
7341 case 5: /* Replicate(imm8:Zeros(8), 4) */
7343 int shift
= (cmode_3_1
& 0x1) * 8;
7344 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7349 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7350 imm
= (abcdefgh
<< 16) | 0xffff;
7352 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7353 imm
= (abcdefgh
<< 8) | 0xff;
7355 imm
= bitfield_replicate(imm
, 32);
7358 if (!cmode_0
&& !is_neg
) {
7359 imm
= bitfield_replicate(abcdefgh
, 8);
7360 } else if (!cmode_0
&& is_neg
) {
7363 for (i
= 0; i
< 8; i
++) {
7364 if ((abcdefgh
) & (1 << i
)) {
7365 imm
|= 0xffULL
<< (i
* 8);
7368 } else if (cmode_0
) {
7370 imm
= (abcdefgh
& 0x3f) << 48;
7371 if (abcdefgh
& 0x80) {
7372 imm
|= 0x8000000000000000ULL
;
7374 if (abcdefgh
& 0x40) {
7375 imm
|= 0x3fc0000000000000ULL
;
7377 imm
|= 0x4000000000000000ULL
;
7381 /* FMOV (vector, immediate) - half-precision */
7382 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7383 /* now duplicate across the lanes */
7384 imm
= bitfield_replicate(imm
, 16);
7386 imm
= (abcdefgh
& 0x3f) << 19;
7387 if (abcdefgh
& 0x80) {
7390 if (abcdefgh
& 0x40) {
7401 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7402 g_assert_not_reached();
7405 if (cmode_3_1
!= 7 && is_neg
) {
7409 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7410 /* MOVI or MVNI, with MVNI negation handled above. */
7411 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7412 vec_full_reg_size(s
), imm
);
7414 /* ORR or BIC, with BIC negation to AND handled above. */
7416 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7418 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7423 /* AdvSIMD scalar copy
7424 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7425 * +-----+----+-----------------+------+---+------+---+------+------+
7426 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7427 * +-----+----+-----------------+------+---+------+---+------+------+
7429 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7431 int rd
= extract32(insn
, 0, 5);
7432 int rn
= extract32(insn
, 5, 5);
7433 int imm4
= extract32(insn
, 11, 4);
7434 int imm5
= extract32(insn
, 16, 5);
7435 int op
= extract32(insn
, 29, 1);
7437 if (op
!= 0 || imm4
!= 0) {
7438 unallocated_encoding(s
);
7442 /* DUP (element, scalar) */
7443 handle_simd_dupes(s
, rd
, rn
, imm5
);
7446 /* AdvSIMD scalar pairwise
7447 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7448 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7449 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7450 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7452 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7454 int u
= extract32(insn
, 29, 1);
7455 int size
= extract32(insn
, 22, 2);
7456 int opcode
= extract32(insn
, 12, 5);
7457 int rn
= extract32(insn
, 5, 5);
7458 int rd
= extract32(insn
, 0, 5);
7461 /* For some ops (the FP ones), size[1] is part of the encoding.
7462 * For ADDP strictly it is not but size[1] is always 1 for valid
7465 opcode
|= (extract32(size
, 1, 1) << 5);
7468 case 0x3b: /* ADDP */
7469 if (u
|| size
!= 3) {
7470 unallocated_encoding(s
);
7473 if (!fp_access_check(s
)) {
7479 case 0xc: /* FMAXNMP */
7480 case 0xd: /* FADDP */
7481 case 0xf: /* FMAXP */
7482 case 0x2c: /* FMINNMP */
7483 case 0x2f: /* FMINP */
7484 /* FP op, size[0] is 32 or 64 bit*/
7486 if (!dc_isar_feature(aa64_fp16
, s
)) {
7487 unallocated_encoding(s
);
7493 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7496 if (!fp_access_check(s
)) {
7500 fpst
= get_fpstatus_ptr(size
== MO_16
);
7503 unallocated_encoding(s
);
7507 if (size
== MO_64
) {
7508 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7509 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7510 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7512 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7513 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7516 case 0x3b: /* ADDP */
7517 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7519 case 0xc: /* FMAXNMP */
7520 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7522 case 0xd: /* FADDP */
7523 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7525 case 0xf: /* FMAXP */
7526 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7528 case 0x2c: /* FMINNMP */
7529 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7531 case 0x2f: /* FMINP */
7532 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7535 g_assert_not_reached();
7538 write_fp_dreg(s
, rd
, tcg_res
);
7540 tcg_temp_free_i64(tcg_op1
);
7541 tcg_temp_free_i64(tcg_op2
);
7542 tcg_temp_free_i64(tcg_res
);
7544 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7545 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7546 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7548 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7549 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7551 if (size
== MO_16
) {
7553 case 0xc: /* FMAXNMP */
7554 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7556 case 0xd: /* FADDP */
7557 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7559 case 0xf: /* FMAXP */
7560 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7562 case 0x2c: /* FMINNMP */
7563 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7565 case 0x2f: /* FMINP */
7566 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7569 g_assert_not_reached();
7573 case 0xc: /* FMAXNMP */
7574 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7576 case 0xd: /* FADDP */
7577 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7579 case 0xf: /* FMAXP */
7580 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7582 case 0x2c: /* FMINNMP */
7583 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7585 case 0x2f: /* FMINP */
7586 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7589 g_assert_not_reached();
7593 write_fp_sreg(s
, rd
, tcg_res
);
7595 tcg_temp_free_i32(tcg_op1
);
7596 tcg_temp_free_i32(tcg_op2
);
7597 tcg_temp_free_i32(tcg_res
);
7601 tcg_temp_free_ptr(fpst
);
7606 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7608 * This code is handles the common shifting code and is used by both
7609 * the vector and scalar code.
7611 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7612 TCGv_i64 tcg_rnd
, bool accumulate
,
7613 bool is_u
, int size
, int shift
)
7615 bool extended_result
= false;
7616 bool round
= tcg_rnd
!= NULL
;
7618 TCGv_i64 tcg_src_hi
;
7620 if (round
&& size
== 3) {
7621 extended_result
= true;
7622 ext_lshift
= 64 - shift
;
7623 tcg_src_hi
= tcg_temp_new_i64();
7624 } else if (shift
== 64) {
7625 if (!accumulate
&& is_u
) {
7626 /* result is zero */
7627 tcg_gen_movi_i64(tcg_res
, 0);
7632 /* Deal with the rounding step */
7634 if (extended_result
) {
7635 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7637 /* take care of sign extending tcg_res */
7638 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7639 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7640 tcg_src
, tcg_src_hi
,
7643 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7647 tcg_temp_free_i64(tcg_zero
);
7649 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7653 /* Now do the shift right */
7654 if (round
&& extended_result
) {
7655 /* extended case, >64 bit precision required */
7656 if (ext_lshift
== 0) {
7657 /* special case, only high bits matter */
7658 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7660 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7661 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7662 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7667 /* essentially shifting in 64 zeros */
7668 tcg_gen_movi_i64(tcg_src
, 0);
7670 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7674 /* effectively extending the sign-bit */
7675 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7677 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7683 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7685 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7688 if (extended_result
) {
7689 tcg_temp_free_i64(tcg_src_hi
);
7693 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7694 static void handle_scalar_simd_shri(DisasContext
*s
,
7695 bool is_u
, int immh
, int immb
,
7696 int opcode
, int rn
, int rd
)
7699 int immhb
= immh
<< 3 | immb
;
7700 int shift
= 2 * (8 << size
) - immhb
;
7701 bool accumulate
= false;
7703 bool insert
= false;
7708 if (!extract32(immh
, 3, 1)) {
7709 unallocated_encoding(s
);
7713 if (!fp_access_check(s
)) {
7718 case 0x02: /* SSRA / USRA (accumulate) */
7721 case 0x04: /* SRSHR / URSHR (rounding) */
7724 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7725 accumulate
= round
= true;
7727 case 0x08: /* SRI */
7733 uint64_t round_const
= 1ULL << (shift
- 1);
7734 tcg_round
= tcg_const_i64(round_const
);
7739 tcg_rn
= read_fp_dreg(s
, rn
);
7740 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7743 /* shift count same as element size is valid but does nothing;
7744 * special case to avoid potential shift by 64.
7746 int esize
= 8 << size
;
7747 if (shift
!= esize
) {
7748 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7749 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7752 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7753 accumulate
, is_u
, size
, shift
);
7756 write_fp_dreg(s
, rd
, tcg_rd
);
7758 tcg_temp_free_i64(tcg_rn
);
7759 tcg_temp_free_i64(tcg_rd
);
7761 tcg_temp_free_i64(tcg_round
);
7765 /* SHL/SLI - Scalar shift left */
7766 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7767 int immh
, int immb
, int opcode
,
7770 int size
= 32 - clz32(immh
) - 1;
7771 int immhb
= immh
<< 3 | immb
;
7772 int shift
= immhb
- (8 << size
);
7773 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7774 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7776 if (!extract32(immh
, 3, 1)) {
7777 unallocated_encoding(s
);
7781 if (!fp_access_check(s
)) {
7785 tcg_rn
= read_fp_dreg(s
, rn
);
7786 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7789 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7791 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7794 write_fp_dreg(s
, rd
, tcg_rd
);
7796 tcg_temp_free_i64(tcg_rn
);
7797 tcg_temp_free_i64(tcg_rd
);
7800 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7801 * (signed/unsigned) narrowing */
7802 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7803 bool is_u_shift
, bool is_u_narrow
,
7804 int immh
, int immb
, int opcode
,
7807 int immhb
= immh
<< 3 | immb
;
7808 int size
= 32 - clz32(immh
) - 1;
7809 int esize
= 8 << size
;
7810 int shift
= (2 * esize
) - immhb
;
7811 int elements
= is_scalar
? 1 : (64 / esize
);
7812 bool round
= extract32(opcode
, 0, 1);
7813 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7814 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7815 TCGv_i32 tcg_rd_narrowed
;
7818 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7819 { gen_helper_neon_narrow_sat_s8
,
7820 gen_helper_neon_unarrow_sat8
},
7821 { gen_helper_neon_narrow_sat_s16
,
7822 gen_helper_neon_unarrow_sat16
},
7823 { gen_helper_neon_narrow_sat_s32
,
7824 gen_helper_neon_unarrow_sat32
},
7827 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7828 gen_helper_neon_narrow_sat_u8
,
7829 gen_helper_neon_narrow_sat_u16
,
7830 gen_helper_neon_narrow_sat_u32
,
7833 NeonGenNarrowEnvFn
*narrowfn
;
7839 if (extract32(immh
, 3, 1)) {
7840 unallocated_encoding(s
);
7844 if (!fp_access_check(s
)) {
7849 narrowfn
= unsigned_narrow_fns
[size
];
7851 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7854 tcg_rn
= tcg_temp_new_i64();
7855 tcg_rd
= tcg_temp_new_i64();
7856 tcg_rd_narrowed
= tcg_temp_new_i32();
7857 tcg_final
= tcg_const_i64(0);
7860 uint64_t round_const
= 1ULL << (shift
- 1);
7861 tcg_round
= tcg_const_i64(round_const
);
7866 for (i
= 0; i
< elements
; i
++) {
7867 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7868 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7869 false, is_u_shift
, size
+1, shift
);
7870 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7871 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7872 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7876 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7878 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7882 tcg_temp_free_i64(tcg_round
);
7884 tcg_temp_free_i64(tcg_rn
);
7885 tcg_temp_free_i64(tcg_rd
);
7886 tcg_temp_free_i32(tcg_rd_narrowed
);
7887 tcg_temp_free_i64(tcg_final
);
7889 clear_vec_high(s
, is_q
, rd
);
7892 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7893 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
7894 bool src_unsigned
, bool dst_unsigned
,
7895 int immh
, int immb
, int rn
, int rd
)
7897 int immhb
= immh
<< 3 | immb
;
7898 int size
= 32 - clz32(immh
) - 1;
7899 int shift
= immhb
- (8 << size
);
7903 assert(!(scalar
&& is_q
));
7906 if (!is_q
&& extract32(immh
, 3, 1)) {
7907 unallocated_encoding(s
);
7911 /* Since we use the variable-shift helpers we must
7912 * replicate the shift count into each element of
7913 * the tcg_shift value.
7917 shift
|= shift
<< 8;
7920 shift
|= shift
<< 16;
7926 g_assert_not_reached();
7930 if (!fp_access_check(s
)) {
7935 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
7936 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
7937 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
7938 { NULL
, gen_helper_neon_qshl_u64
},
7940 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
7941 int maxpass
= is_q
? 2 : 1;
7943 for (pass
= 0; pass
< maxpass
; pass
++) {
7944 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7946 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7947 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7948 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7950 tcg_temp_free_i64(tcg_op
);
7952 tcg_temp_free_i64(tcg_shift
);
7953 clear_vec_high(s
, is_q
, rd
);
7955 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
7956 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
7958 { gen_helper_neon_qshl_s8
,
7959 gen_helper_neon_qshl_s16
,
7960 gen_helper_neon_qshl_s32
},
7961 { gen_helper_neon_qshlu_s8
,
7962 gen_helper_neon_qshlu_s16
,
7963 gen_helper_neon_qshlu_s32
}
7965 { NULL
, NULL
, NULL
},
7966 { gen_helper_neon_qshl_u8
,
7967 gen_helper_neon_qshl_u16
,
7968 gen_helper_neon_qshl_u32
}
7971 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
7972 TCGMemOp memop
= scalar
? size
: MO_32
;
7973 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
7975 for (pass
= 0; pass
< maxpass
; pass
++) {
7976 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7978 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
7979 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7983 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
7986 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
7991 g_assert_not_reached();
7993 write_fp_sreg(s
, rd
, tcg_op
);
7995 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
7998 tcg_temp_free_i32(tcg_op
);
8000 tcg_temp_free_i32(tcg_shift
);
8003 clear_vec_high(s
, is_q
, rd
);
8008 /* Common vector code for handling integer to FP conversion */
8009 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8010 int elements
, int is_signed
,
8011 int fracbits
, int size
)
8013 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8014 TCGv_i32 tcg_shift
= NULL
;
8016 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8019 if (fracbits
|| size
== MO_64
) {
8020 tcg_shift
= tcg_const_i32(fracbits
);
8023 if (size
== MO_64
) {
8024 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8025 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8027 for (pass
= 0; pass
< elements
; pass
++) {
8028 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8031 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8032 tcg_shift
, tcg_fpst
);
8034 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8035 tcg_shift
, tcg_fpst
);
8037 if (elements
== 1) {
8038 write_fp_dreg(s
, rd
, tcg_double
);
8040 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8044 tcg_temp_free_i64(tcg_int64
);
8045 tcg_temp_free_i64(tcg_double
);
8048 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8049 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8051 for (pass
= 0; pass
< elements
; pass
++) {
8052 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8058 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8059 tcg_shift
, tcg_fpst
);
8061 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8062 tcg_shift
, tcg_fpst
);
8066 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8068 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8075 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8076 tcg_shift
, tcg_fpst
);
8078 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8079 tcg_shift
, tcg_fpst
);
8083 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8085 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8090 g_assert_not_reached();
8093 if (elements
== 1) {
8094 write_fp_sreg(s
, rd
, tcg_float
);
8096 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8100 tcg_temp_free_i32(tcg_int32
);
8101 tcg_temp_free_i32(tcg_float
);
8104 tcg_temp_free_ptr(tcg_fpst
);
8106 tcg_temp_free_i32(tcg_shift
);
8109 clear_vec_high(s
, elements
<< size
== 16, rd
);
8112 /* UCVTF/SCVTF - Integer to FP conversion */
8113 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8114 bool is_q
, bool is_u
,
8115 int immh
, int immb
, int opcode
,
8118 int size
, elements
, fracbits
;
8119 int immhb
= immh
<< 3 | immb
;
8123 if (!is_scalar
&& !is_q
) {
8124 unallocated_encoding(s
);
8127 } else if (immh
& 4) {
8129 } else if (immh
& 2) {
8131 if (!dc_isar_feature(aa64_fp16
, s
)) {
8132 unallocated_encoding(s
);
8136 /* immh == 0 would be a failure of the decode logic */
8137 g_assert(immh
== 1);
8138 unallocated_encoding(s
);
8145 elements
= (8 << is_q
) >> size
;
8147 fracbits
= (16 << size
) - immhb
;
8149 if (!fp_access_check(s
)) {
8153 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8156 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8157 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8158 bool is_q
, bool is_u
,
8159 int immh
, int immb
, int rn
, int rd
)
8161 int immhb
= immh
<< 3 | immb
;
8162 int pass
, size
, fracbits
;
8163 TCGv_ptr tcg_fpstatus
;
8164 TCGv_i32 tcg_rmode
, tcg_shift
;
8168 if (!is_scalar
&& !is_q
) {
8169 unallocated_encoding(s
);
8172 } else if (immh
& 0x4) {
8174 } else if (immh
& 0x2) {
8176 if (!dc_isar_feature(aa64_fp16
, s
)) {
8177 unallocated_encoding(s
);
8181 /* Should have split out AdvSIMD modified immediate earlier. */
8183 unallocated_encoding(s
);
8187 if (!fp_access_check(s
)) {
8191 assert(!(is_scalar
&& is_q
));
8193 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8194 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8195 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8196 fracbits
= (16 << size
) - immhb
;
8197 tcg_shift
= tcg_const_i32(fracbits
);
8199 if (size
== MO_64
) {
8200 int maxpass
= is_scalar
? 1 : 2;
8202 for (pass
= 0; pass
< maxpass
; pass
++) {
8203 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8205 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8207 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8209 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8211 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8212 tcg_temp_free_i64(tcg_op
);
8214 clear_vec_high(s
, is_q
, rd
);
8216 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8217 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8222 fn
= gen_helper_vfp_touhh
;
8224 fn
= gen_helper_vfp_toshh
;
8229 fn
= gen_helper_vfp_touls
;
8231 fn
= gen_helper_vfp_tosls
;
8235 g_assert_not_reached();
8238 for (pass
= 0; pass
< maxpass
; pass
++) {
8239 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8241 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8242 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8244 write_fp_sreg(s
, rd
, tcg_op
);
8246 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8248 tcg_temp_free_i32(tcg_op
);
8251 clear_vec_high(s
, is_q
, rd
);
8255 tcg_temp_free_ptr(tcg_fpstatus
);
8256 tcg_temp_free_i32(tcg_shift
);
8257 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8258 tcg_temp_free_i32(tcg_rmode
);
8261 /* AdvSIMD scalar shift by immediate
8262 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8263 * +-----+---+-------------+------+------+--------+---+------+------+
8264 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8265 * +-----+---+-------------+------+------+--------+---+------+------+
8267 * This is the scalar version so it works on a fixed sized registers
8269 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8271 int rd
= extract32(insn
, 0, 5);
8272 int rn
= extract32(insn
, 5, 5);
8273 int opcode
= extract32(insn
, 11, 5);
8274 int immb
= extract32(insn
, 16, 3);
8275 int immh
= extract32(insn
, 19, 4);
8276 bool is_u
= extract32(insn
, 29, 1);
8279 unallocated_encoding(s
);
8284 case 0x08: /* SRI */
8286 unallocated_encoding(s
);
8290 case 0x00: /* SSHR / USHR */
8291 case 0x02: /* SSRA / USRA */
8292 case 0x04: /* SRSHR / URSHR */
8293 case 0x06: /* SRSRA / URSRA */
8294 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8296 case 0x0a: /* SHL / SLI */
8297 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8299 case 0x1c: /* SCVTF, UCVTF */
8300 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8303 case 0x10: /* SQSHRUN, SQSHRUN2 */
8304 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8306 unallocated_encoding(s
);
8309 handle_vec_simd_sqshrn(s
, true, false, false, true,
8310 immh
, immb
, opcode
, rn
, rd
);
8312 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8313 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8314 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8315 immh
, immb
, opcode
, rn
, rd
);
8317 case 0xc: /* SQSHLU */
8319 unallocated_encoding(s
);
8322 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8324 case 0xe: /* SQSHL, UQSHL */
8325 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8327 case 0x1f: /* FCVTZS, FCVTZU */
8328 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8331 unallocated_encoding(s
);
8336 /* AdvSIMD scalar three different
8337 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8338 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8339 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8340 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8342 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8344 bool is_u
= extract32(insn
, 29, 1);
8345 int size
= extract32(insn
, 22, 2);
8346 int opcode
= extract32(insn
, 12, 4);
8347 int rm
= extract32(insn
, 16, 5);
8348 int rn
= extract32(insn
, 5, 5);
8349 int rd
= extract32(insn
, 0, 5);
8352 unallocated_encoding(s
);
8357 case 0x9: /* SQDMLAL, SQDMLAL2 */
8358 case 0xb: /* SQDMLSL, SQDMLSL2 */
8359 case 0xd: /* SQDMULL, SQDMULL2 */
8360 if (size
== 0 || size
== 3) {
8361 unallocated_encoding(s
);
8366 unallocated_encoding(s
);
8370 if (!fp_access_check(s
)) {
8375 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8376 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8377 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8379 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8380 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8382 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8383 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8386 case 0xd: /* SQDMULL, SQDMULL2 */
8388 case 0xb: /* SQDMLSL, SQDMLSL2 */
8389 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8391 case 0x9: /* SQDMLAL, SQDMLAL2 */
8392 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8393 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8397 g_assert_not_reached();
8400 write_fp_dreg(s
, rd
, tcg_res
);
8402 tcg_temp_free_i64(tcg_op1
);
8403 tcg_temp_free_i64(tcg_op2
);
8404 tcg_temp_free_i64(tcg_res
);
8406 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8407 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8408 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8410 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8411 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8414 case 0xd: /* SQDMULL, SQDMULL2 */
8416 case 0xb: /* SQDMLSL, SQDMLSL2 */
8417 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8419 case 0x9: /* SQDMLAL, SQDMLAL2 */
8421 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8422 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8423 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8425 tcg_temp_free_i64(tcg_op3
);
8429 g_assert_not_reached();
8432 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8433 write_fp_dreg(s
, rd
, tcg_res
);
8435 tcg_temp_free_i32(tcg_op1
);
8436 tcg_temp_free_i32(tcg_op2
);
8437 tcg_temp_free_i64(tcg_res
);
8441 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8442 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8444 /* Handle 64x64->64 opcodes which are shared between the scalar
8445 * and vector 3-same groups. We cover every opcode where size == 3
8446 * is valid in either the three-reg-same (integer, not pairwise)
8447 * or scalar-three-reg-same groups.
8452 case 0x1: /* SQADD */
8454 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8456 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8459 case 0x5: /* SQSUB */
8461 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8463 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8466 case 0x6: /* CMGT, CMHI */
8467 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8468 * We implement this using setcond (test) and then negating.
8470 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8472 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8473 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8475 case 0x7: /* CMGE, CMHS */
8476 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8478 case 0x11: /* CMTST, CMEQ */
8483 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8485 case 0x8: /* SSHL, USHL */
8487 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8489 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8492 case 0x9: /* SQSHL, UQSHL */
8494 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8496 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8499 case 0xa: /* SRSHL, URSHL */
8501 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8503 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8506 case 0xb: /* SQRSHL, UQRSHL */
8508 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8510 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8513 case 0x10: /* ADD, SUB */
8515 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8517 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8521 g_assert_not_reached();
8525 /* Handle the 3-same-operands float operations; shared by the scalar
8526 * and vector encodings. The caller must filter out any encodings
8527 * not allocated for the encoding it is dealing with.
8529 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8530 int fpopcode
, int rd
, int rn
, int rm
)
8533 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8535 for (pass
= 0; pass
< elements
; pass
++) {
8538 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8539 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8540 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8542 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8543 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8546 case 0x39: /* FMLS */
8547 /* As usual for ARM, separate negation for fused multiply-add */
8548 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8550 case 0x19: /* FMLA */
8551 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8552 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8555 case 0x18: /* FMAXNM */
8556 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8558 case 0x1a: /* FADD */
8559 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8561 case 0x1b: /* FMULX */
8562 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8564 case 0x1c: /* FCMEQ */
8565 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8567 case 0x1e: /* FMAX */
8568 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8570 case 0x1f: /* FRECPS */
8571 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8573 case 0x38: /* FMINNM */
8574 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8576 case 0x3a: /* FSUB */
8577 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8579 case 0x3e: /* FMIN */
8580 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8582 case 0x3f: /* FRSQRTS */
8583 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8585 case 0x5b: /* FMUL */
8586 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8588 case 0x5c: /* FCMGE */
8589 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8591 case 0x5d: /* FACGE */
8592 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8594 case 0x5f: /* FDIV */
8595 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8597 case 0x7a: /* FABD */
8598 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8599 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8601 case 0x7c: /* FCMGT */
8602 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8604 case 0x7d: /* FACGT */
8605 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8608 g_assert_not_reached();
8611 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8613 tcg_temp_free_i64(tcg_res
);
8614 tcg_temp_free_i64(tcg_op1
);
8615 tcg_temp_free_i64(tcg_op2
);
8618 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8619 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8620 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8622 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8623 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8626 case 0x39: /* FMLS */
8627 /* As usual for ARM, separate negation for fused multiply-add */
8628 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8630 case 0x19: /* FMLA */
8631 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8632 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8635 case 0x1a: /* FADD */
8636 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8638 case 0x1b: /* FMULX */
8639 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8641 case 0x1c: /* FCMEQ */
8642 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8644 case 0x1e: /* FMAX */
8645 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8647 case 0x1f: /* FRECPS */
8648 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8650 case 0x18: /* FMAXNM */
8651 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8653 case 0x38: /* FMINNM */
8654 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8656 case 0x3a: /* FSUB */
8657 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8659 case 0x3e: /* FMIN */
8660 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8662 case 0x3f: /* FRSQRTS */
8663 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8665 case 0x5b: /* FMUL */
8666 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8668 case 0x5c: /* FCMGE */
8669 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8671 case 0x5d: /* FACGE */
8672 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8674 case 0x5f: /* FDIV */
8675 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8677 case 0x7a: /* FABD */
8678 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8679 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8681 case 0x7c: /* FCMGT */
8682 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8684 case 0x7d: /* FACGT */
8685 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8688 g_assert_not_reached();
8691 if (elements
== 1) {
8692 /* scalar single so clear high part */
8693 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8695 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8696 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8697 tcg_temp_free_i64(tcg_tmp
);
8699 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8702 tcg_temp_free_i32(tcg_res
);
8703 tcg_temp_free_i32(tcg_op1
);
8704 tcg_temp_free_i32(tcg_op2
);
8708 tcg_temp_free_ptr(fpst
);
8710 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8713 /* AdvSIMD scalar three same
8714 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8715 * +-----+---+-----------+------+---+------+--------+---+------+------+
8716 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8717 * +-----+---+-----------+------+---+------+--------+---+------+------+
8719 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8721 int rd
= extract32(insn
, 0, 5);
8722 int rn
= extract32(insn
, 5, 5);
8723 int opcode
= extract32(insn
, 11, 5);
8724 int rm
= extract32(insn
, 16, 5);
8725 int size
= extract32(insn
, 22, 2);
8726 bool u
= extract32(insn
, 29, 1);
8729 if (opcode
>= 0x18) {
8730 /* Floating point: U, size[1] and opcode indicate operation */
8731 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8733 case 0x1b: /* FMULX */
8734 case 0x1f: /* FRECPS */
8735 case 0x3f: /* FRSQRTS */
8736 case 0x5d: /* FACGE */
8737 case 0x7d: /* FACGT */
8738 case 0x1c: /* FCMEQ */
8739 case 0x5c: /* FCMGE */
8740 case 0x7c: /* FCMGT */
8741 case 0x7a: /* FABD */
8744 unallocated_encoding(s
);
8748 if (!fp_access_check(s
)) {
8752 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8757 case 0x1: /* SQADD, UQADD */
8758 case 0x5: /* SQSUB, UQSUB */
8759 case 0x9: /* SQSHL, UQSHL */
8760 case 0xb: /* SQRSHL, UQRSHL */
8762 case 0x8: /* SSHL, USHL */
8763 case 0xa: /* SRSHL, URSHL */
8764 case 0x6: /* CMGT, CMHI */
8765 case 0x7: /* CMGE, CMHS */
8766 case 0x11: /* CMTST, CMEQ */
8767 case 0x10: /* ADD, SUB (vector) */
8769 unallocated_encoding(s
);
8773 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8774 if (size
!= 1 && size
!= 2) {
8775 unallocated_encoding(s
);
8780 unallocated_encoding(s
);
8784 if (!fp_access_check(s
)) {
8788 tcg_rd
= tcg_temp_new_i64();
8791 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8792 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8794 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8795 tcg_temp_free_i64(tcg_rn
);
8796 tcg_temp_free_i64(tcg_rm
);
8798 /* Do a single operation on the lowest element in the vector.
8799 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8800 * no side effects for all these operations.
8801 * OPTME: special-purpose helpers would avoid doing some
8802 * unnecessary work in the helper for the 8 and 16 bit cases.
8804 NeonGenTwoOpEnvFn
*genenvfn
;
8805 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8806 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8807 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8809 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8810 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8813 case 0x1: /* SQADD, UQADD */
8815 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8816 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8817 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8818 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8820 genenvfn
= fns
[size
][u
];
8823 case 0x5: /* SQSUB, UQSUB */
8825 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8826 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8827 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8828 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8830 genenvfn
= fns
[size
][u
];
8833 case 0x9: /* SQSHL, UQSHL */
8835 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8836 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8837 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8838 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8840 genenvfn
= fns
[size
][u
];
8843 case 0xb: /* SQRSHL, UQRSHL */
8845 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8846 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8847 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8848 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8850 genenvfn
= fns
[size
][u
];
8853 case 0x16: /* SQDMULH, SQRDMULH */
8855 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8856 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8857 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8859 assert(size
== 1 || size
== 2);
8860 genenvfn
= fns
[size
- 1][u
];
8864 g_assert_not_reached();
8867 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8868 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8869 tcg_temp_free_i32(tcg_rd32
);
8870 tcg_temp_free_i32(tcg_rn
);
8871 tcg_temp_free_i32(tcg_rm
);
8874 write_fp_dreg(s
, rd
, tcg_rd
);
8876 tcg_temp_free_i64(tcg_rd
);
8879 /* AdvSIMD scalar three same FP16
8880 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8881 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8882 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8883 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8884 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8885 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8887 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8890 int rd
= extract32(insn
, 0, 5);
8891 int rn
= extract32(insn
, 5, 5);
8892 int opcode
= extract32(insn
, 11, 3);
8893 int rm
= extract32(insn
, 16, 5);
8894 bool u
= extract32(insn
, 29, 1);
8895 bool a
= extract32(insn
, 23, 1);
8896 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
8903 case 0x03: /* FMULX */
8904 case 0x04: /* FCMEQ (reg) */
8905 case 0x07: /* FRECPS */
8906 case 0x0f: /* FRSQRTS */
8907 case 0x14: /* FCMGE (reg) */
8908 case 0x15: /* FACGE */
8909 case 0x1a: /* FABD */
8910 case 0x1c: /* FCMGT (reg) */
8911 case 0x1d: /* FACGT */
8914 unallocated_encoding(s
);
8918 if (!dc_isar_feature(aa64_fp16
, s
)) {
8919 unallocated_encoding(s
);
8922 if (!fp_access_check(s
)) {
8926 fpst
= get_fpstatus_ptr(true);
8928 tcg_op1
= read_fp_hreg(s
, rn
);
8929 tcg_op2
= read_fp_hreg(s
, rm
);
8930 tcg_res
= tcg_temp_new_i32();
8933 case 0x03: /* FMULX */
8934 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8936 case 0x04: /* FCMEQ (reg) */
8937 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8939 case 0x07: /* FRECPS */
8940 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8942 case 0x0f: /* FRSQRTS */
8943 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8945 case 0x14: /* FCMGE (reg) */
8946 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8948 case 0x15: /* FACGE */
8949 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8951 case 0x1a: /* FABD */
8952 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8953 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
8955 case 0x1c: /* FCMGT (reg) */
8956 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8958 case 0x1d: /* FACGT */
8959 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8962 g_assert_not_reached();
8965 write_fp_sreg(s
, rd
, tcg_res
);
8968 tcg_temp_free_i32(tcg_res
);
8969 tcg_temp_free_i32(tcg_op1
);
8970 tcg_temp_free_i32(tcg_op2
);
8971 tcg_temp_free_ptr(fpst
);
8974 /* AdvSIMD scalar three same extra
8975 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
8976 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8977 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
8978 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8980 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
8983 int rd
= extract32(insn
, 0, 5);
8984 int rn
= extract32(insn
, 5, 5);
8985 int opcode
= extract32(insn
, 11, 4);
8986 int rm
= extract32(insn
, 16, 5);
8987 int size
= extract32(insn
, 22, 2);
8988 bool u
= extract32(insn
, 29, 1);
8989 TCGv_i32 ele1
, ele2
, ele3
;
8993 switch (u
* 16 + opcode
) {
8994 case 0x10: /* SQRDMLAH (vector) */
8995 case 0x11: /* SQRDMLSH (vector) */
8996 if (size
!= 1 && size
!= 2) {
8997 unallocated_encoding(s
);
9000 feature
= dc_isar_feature(aa64_rdm
, s
);
9003 unallocated_encoding(s
);
9007 unallocated_encoding(s
);
9010 if (!fp_access_check(s
)) {
9014 /* Do a single operation on the lowest element in the vector.
9015 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9016 * with no side effects for all these operations.
9017 * OPTME: special-purpose helpers would avoid doing some
9018 * unnecessary work in the helper for the 16 bit cases.
9020 ele1
= tcg_temp_new_i32();
9021 ele2
= tcg_temp_new_i32();
9022 ele3
= tcg_temp_new_i32();
9024 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9025 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9026 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9029 case 0x0: /* SQRDMLAH */
9031 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9033 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9036 case 0x1: /* SQRDMLSH */
9038 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9040 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9044 g_assert_not_reached();
9046 tcg_temp_free_i32(ele1
);
9047 tcg_temp_free_i32(ele2
);
9049 res
= tcg_temp_new_i64();
9050 tcg_gen_extu_i32_i64(res
, ele3
);
9051 tcg_temp_free_i32(ele3
);
9053 write_fp_dreg(s
, rd
, res
);
9054 tcg_temp_free_i64(res
);
9057 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9058 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9059 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9061 /* Handle 64->64 opcodes which are shared between the scalar and
9062 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9063 * is valid in either group and also the double-precision fp ops.
9064 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9070 case 0x4: /* CLS, CLZ */
9072 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9074 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9078 /* This opcode is shared with CNT and RBIT but we have earlier
9079 * enforced that size == 3 if and only if this is the NOT insn.
9081 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9083 case 0x7: /* SQABS, SQNEG */
9085 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9087 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9090 case 0xa: /* CMLT */
9091 /* 64 bit integer comparison against zero, result is
9092 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9097 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9098 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9100 case 0x8: /* CMGT, CMGE */
9101 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9103 case 0x9: /* CMEQ, CMLE */
9104 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9106 case 0xb: /* ABS, NEG */
9108 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9110 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9111 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9112 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
9114 tcg_temp_free_i64(tcg_zero
);
9117 case 0x2f: /* FABS */
9118 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9120 case 0x6f: /* FNEG */
9121 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9123 case 0x7f: /* FSQRT */
9124 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9126 case 0x1a: /* FCVTNS */
9127 case 0x1b: /* FCVTMS */
9128 case 0x1c: /* FCVTAS */
9129 case 0x3a: /* FCVTPS */
9130 case 0x3b: /* FCVTZS */
9132 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9133 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9134 tcg_temp_free_i32(tcg_shift
);
9137 case 0x5a: /* FCVTNU */
9138 case 0x5b: /* FCVTMU */
9139 case 0x5c: /* FCVTAU */
9140 case 0x7a: /* FCVTPU */
9141 case 0x7b: /* FCVTZU */
9143 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9144 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9145 tcg_temp_free_i32(tcg_shift
);
9148 case 0x18: /* FRINTN */
9149 case 0x19: /* FRINTM */
9150 case 0x38: /* FRINTP */
9151 case 0x39: /* FRINTZ */
9152 case 0x58: /* FRINTA */
9153 case 0x79: /* FRINTI */
9154 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9156 case 0x59: /* FRINTX */
9157 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9160 g_assert_not_reached();
9164 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9165 bool is_scalar
, bool is_u
, bool is_q
,
9166 int size
, int rn
, int rd
)
9168 bool is_double
= (size
== MO_64
);
9171 if (!fp_access_check(s
)) {
9175 fpst
= get_fpstatus_ptr(size
== MO_16
);
9178 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9179 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9180 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9181 NeonGenTwoDoubleOPFn
*genfn
;
9186 case 0x2e: /* FCMLT (zero) */
9189 case 0x2c: /* FCMGT (zero) */
9190 genfn
= gen_helper_neon_cgt_f64
;
9192 case 0x2d: /* FCMEQ (zero) */
9193 genfn
= gen_helper_neon_ceq_f64
;
9195 case 0x6d: /* FCMLE (zero) */
9198 case 0x6c: /* FCMGE (zero) */
9199 genfn
= gen_helper_neon_cge_f64
;
9202 g_assert_not_reached();
9205 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9206 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9208 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9210 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9212 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9214 tcg_temp_free_i64(tcg_res
);
9215 tcg_temp_free_i64(tcg_zero
);
9216 tcg_temp_free_i64(tcg_op
);
9218 clear_vec_high(s
, !is_scalar
, rd
);
9220 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9221 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9222 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9223 NeonGenTwoSingleOPFn
*genfn
;
9225 int pass
, maxpasses
;
9227 if (size
== MO_16
) {
9229 case 0x2e: /* FCMLT (zero) */
9232 case 0x2c: /* FCMGT (zero) */
9233 genfn
= gen_helper_advsimd_cgt_f16
;
9235 case 0x2d: /* FCMEQ (zero) */
9236 genfn
= gen_helper_advsimd_ceq_f16
;
9238 case 0x6d: /* FCMLE (zero) */
9241 case 0x6c: /* FCMGE (zero) */
9242 genfn
= gen_helper_advsimd_cge_f16
;
9245 g_assert_not_reached();
9249 case 0x2e: /* FCMLT (zero) */
9252 case 0x2c: /* FCMGT (zero) */
9253 genfn
= gen_helper_neon_cgt_f32
;
9255 case 0x2d: /* FCMEQ (zero) */
9256 genfn
= gen_helper_neon_ceq_f32
;
9258 case 0x6d: /* FCMLE (zero) */
9261 case 0x6c: /* FCMGE (zero) */
9262 genfn
= gen_helper_neon_cge_f32
;
9265 g_assert_not_reached();
9272 int vector_size
= 8 << is_q
;
9273 maxpasses
= vector_size
>> size
;
9276 for (pass
= 0; pass
< maxpasses
; pass
++) {
9277 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9279 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9281 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9284 write_fp_sreg(s
, rd
, tcg_res
);
9286 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9289 tcg_temp_free_i32(tcg_res
);
9290 tcg_temp_free_i32(tcg_zero
);
9291 tcg_temp_free_i32(tcg_op
);
9293 clear_vec_high(s
, is_q
, rd
);
9297 tcg_temp_free_ptr(fpst
);
9300 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9301 bool is_scalar
, bool is_u
, bool is_q
,
9302 int size
, int rn
, int rd
)
9304 bool is_double
= (size
== 3);
9305 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9308 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9309 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9312 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9313 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9315 case 0x3d: /* FRECPE */
9316 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9318 case 0x3f: /* FRECPX */
9319 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9321 case 0x7d: /* FRSQRTE */
9322 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9325 g_assert_not_reached();
9327 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9329 tcg_temp_free_i64(tcg_res
);
9330 tcg_temp_free_i64(tcg_op
);
9331 clear_vec_high(s
, !is_scalar
, rd
);
9333 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9334 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9335 int pass
, maxpasses
;
9340 maxpasses
= is_q
? 4 : 2;
9343 for (pass
= 0; pass
< maxpasses
; pass
++) {
9344 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9347 case 0x3c: /* URECPE */
9348 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9350 case 0x3d: /* FRECPE */
9351 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9353 case 0x3f: /* FRECPX */
9354 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9356 case 0x7d: /* FRSQRTE */
9357 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9360 g_assert_not_reached();
9364 write_fp_sreg(s
, rd
, tcg_res
);
9366 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9369 tcg_temp_free_i32(tcg_res
);
9370 tcg_temp_free_i32(tcg_op
);
9372 clear_vec_high(s
, is_q
, rd
);
9375 tcg_temp_free_ptr(fpst
);
9378 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9379 int opcode
, bool u
, bool is_q
,
9380 int size
, int rn
, int rd
)
9382 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9383 * in the source becomes a size element in the destination).
9386 TCGv_i32 tcg_res
[2];
9387 int destelt
= is_q
? 2 : 0;
9388 int passes
= scalar
? 1 : 2;
9391 tcg_res
[1] = tcg_const_i32(0);
9394 for (pass
= 0; pass
< passes
; pass
++) {
9395 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9396 NeonGenNarrowFn
*genfn
= NULL
;
9397 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9400 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9402 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9404 tcg_res
[pass
] = tcg_temp_new_i32();
9407 case 0x12: /* XTN, SQXTUN */
9409 static NeonGenNarrowFn
* const xtnfns
[3] = {
9410 gen_helper_neon_narrow_u8
,
9411 gen_helper_neon_narrow_u16
,
9412 tcg_gen_extrl_i64_i32
,
9414 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9415 gen_helper_neon_unarrow_sat8
,
9416 gen_helper_neon_unarrow_sat16
,
9417 gen_helper_neon_unarrow_sat32
,
9420 genenvfn
= sqxtunfns
[size
];
9422 genfn
= xtnfns
[size
];
9426 case 0x14: /* SQXTN, UQXTN */
9428 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9429 { gen_helper_neon_narrow_sat_s8
,
9430 gen_helper_neon_narrow_sat_u8
},
9431 { gen_helper_neon_narrow_sat_s16
,
9432 gen_helper_neon_narrow_sat_u16
},
9433 { gen_helper_neon_narrow_sat_s32
,
9434 gen_helper_neon_narrow_sat_u32
},
9436 genenvfn
= fns
[size
][u
];
9439 case 0x16: /* FCVTN, FCVTN2 */
9440 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9442 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9444 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9445 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9446 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9447 TCGv_i32 ahp
= get_ahp_flag();
9449 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9450 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9451 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9452 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9453 tcg_temp_free_i32(tcg_lo
);
9454 tcg_temp_free_i32(tcg_hi
);
9455 tcg_temp_free_ptr(fpst
);
9456 tcg_temp_free_i32(ahp
);
9459 case 0x56: /* FCVTXN, FCVTXN2 */
9460 /* 64 bit to 32 bit float conversion
9461 * with von Neumann rounding (round to odd)
9464 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9467 g_assert_not_reached();
9471 genfn(tcg_res
[pass
], tcg_op
);
9472 } else if (genenvfn
) {
9473 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9476 tcg_temp_free_i64(tcg_op
);
9479 for (pass
= 0; pass
< 2; pass
++) {
9480 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9481 tcg_temp_free_i32(tcg_res
[pass
]);
9483 clear_vec_high(s
, is_q
, rd
);
9486 /* Remaining saturating accumulating ops */
9487 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9488 bool is_q
, int size
, int rn
, int rd
)
9490 bool is_double
= (size
== 3);
9493 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9494 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9497 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9498 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9499 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9501 if (is_u
) { /* USQADD */
9502 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9503 } else { /* SUQADD */
9504 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9506 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9508 tcg_temp_free_i64(tcg_rd
);
9509 tcg_temp_free_i64(tcg_rn
);
9510 clear_vec_high(s
, !is_scalar
, rd
);
9512 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9513 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9514 int pass
, maxpasses
;
9519 maxpasses
= is_q
? 4 : 2;
9522 for (pass
= 0; pass
< maxpasses
; pass
++) {
9524 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9525 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9527 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9528 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9531 if (is_u
) { /* USQADD */
9534 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9537 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9540 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9543 g_assert_not_reached();
9545 } else { /* SUQADD */
9548 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9551 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9554 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9557 g_assert_not_reached();
9562 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9563 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9564 tcg_temp_free_i64(tcg_zero
);
9566 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9568 tcg_temp_free_i32(tcg_rd
);
9569 tcg_temp_free_i32(tcg_rn
);
9570 clear_vec_high(s
, is_q
, rd
);
9574 /* AdvSIMD scalar two reg misc
9575 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9576 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9577 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9578 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9580 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9582 int rd
= extract32(insn
, 0, 5);
9583 int rn
= extract32(insn
, 5, 5);
9584 int opcode
= extract32(insn
, 12, 5);
9585 int size
= extract32(insn
, 22, 2);
9586 bool u
= extract32(insn
, 29, 1);
9587 bool is_fcvt
= false;
9590 TCGv_ptr tcg_fpstatus
;
9593 case 0x3: /* USQADD / SUQADD*/
9594 if (!fp_access_check(s
)) {
9597 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9599 case 0x7: /* SQABS / SQNEG */
9601 case 0xa: /* CMLT */
9603 unallocated_encoding(s
);
9607 case 0x8: /* CMGT, CMGE */
9608 case 0x9: /* CMEQ, CMLE */
9609 case 0xb: /* ABS, NEG */
9611 unallocated_encoding(s
);
9615 case 0x12: /* SQXTUN */
9617 unallocated_encoding(s
);
9621 case 0x14: /* SQXTN, UQXTN */
9623 unallocated_encoding(s
);
9626 if (!fp_access_check(s
)) {
9629 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9634 /* Floating point: U, size[1] and opcode indicate operation;
9635 * size[0] indicates single or double precision.
9637 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9638 size
= extract32(size
, 0, 1) ? 3 : 2;
9640 case 0x2c: /* FCMGT (zero) */
9641 case 0x2d: /* FCMEQ (zero) */
9642 case 0x2e: /* FCMLT (zero) */
9643 case 0x6c: /* FCMGE (zero) */
9644 case 0x6d: /* FCMLE (zero) */
9645 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9647 case 0x1d: /* SCVTF */
9648 case 0x5d: /* UCVTF */
9650 bool is_signed
= (opcode
== 0x1d);
9651 if (!fp_access_check(s
)) {
9654 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9657 case 0x3d: /* FRECPE */
9658 case 0x3f: /* FRECPX */
9659 case 0x7d: /* FRSQRTE */
9660 if (!fp_access_check(s
)) {
9663 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9665 case 0x1a: /* FCVTNS */
9666 case 0x1b: /* FCVTMS */
9667 case 0x3a: /* FCVTPS */
9668 case 0x3b: /* FCVTZS */
9669 case 0x5a: /* FCVTNU */
9670 case 0x5b: /* FCVTMU */
9671 case 0x7a: /* FCVTPU */
9672 case 0x7b: /* FCVTZU */
9674 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9676 case 0x1c: /* FCVTAS */
9677 case 0x5c: /* FCVTAU */
9678 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9680 rmode
= FPROUNDING_TIEAWAY
;
9682 case 0x56: /* FCVTXN, FCVTXN2 */
9684 unallocated_encoding(s
);
9687 if (!fp_access_check(s
)) {
9690 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9693 unallocated_encoding(s
);
9698 unallocated_encoding(s
);
9702 if (!fp_access_check(s
)) {
9707 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9708 tcg_fpstatus
= get_fpstatus_ptr(false);
9709 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9712 tcg_fpstatus
= NULL
;
9716 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9717 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9719 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9720 write_fp_dreg(s
, rd
, tcg_rd
);
9721 tcg_temp_free_i64(tcg_rd
);
9722 tcg_temp_free_i64(tcg_rn
);
9724 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9725 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9727 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9730 case 0x7: /* SQABS, SQNEG */
9732 NeonGenOneOpEnvFn
*genfn
;
9733 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9734 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9735 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9736 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9738 genfn
= fns
[size
][u
];
9739 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9742 case 0x1a: /* FCVTNS */
9743 case 0x1b: /* FCVTMS */
9744 case 0x1c: /* FCVTAS */
9745 case 0x3a: /* FCVTPS */
9746 case 0x3b: /* FCVTZS */
9748 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9749 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9750 tcg_temp_free_i32(tcg_shift
);
9753 case 0x5a: /* FCVTNU */
9754 case 0x5b: /* FCVTMU */
9755 case 0x5c: /* FCVTAU */
9756 case 0x7a: /* FCVTPU */
9757 case 0x7b: /* FCVTZU */
9759 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9760 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9761 tcg_temp_free_i32(tcg_shift
);
9765 g_assert_not_reached();
9768 write_fp_sreg(s
, rd
, tcg_rd
);
9769 tcg_temp_free_i32(tcg_rd
);
9770 tcg_temp_free_i32(tcg_rn
);
9774 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9775 tcg_temp_free_i32(tcg_rmode
);
9776 tcg_temp_free_ptr(tcg_fpstatus
);
9780 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9781 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9782 int immh
, int immb
, int opcode
, int rn
, int rd
)
9784 int size
= 32 - clz32(immh
) - 1;
9785 int immhb
= immh
<< 3 | immb
;
9786 int shift
= 2 * (8 << size
) - immhb
;
9787 bool accumulate
= false;
9788 int dsize
= is_q
? 128 : 64;
9789 int esize
= 8 << size
;
9790 int elements
= dsize
/esize
;
9791 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9792 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9793 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9795 uint64_t round_const
;
9798 if (extract32(immh
, 3, 1) && !is_q
) {
9799 unallocated_encoding(s
);
9802 tcg_debug_assert(size
<= 3);
9804 if (!fp_access_check(s
)) {
9809 case 0x02: /* SSRA / USRA (accumulate) */
9811 /* Shift count same as element size produces zero to add. */
9812 if (shift
== 8 << size
) {
9815 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9817 /* Shift count same as element size produces all sign to add. */
9818 if (shift
== 8 << size
) {
9821 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9824 case 0x08: /* SRI */
9825 /* Shift count same as element size is valid but does nothing. */
9826 if (shift
== 8 << size
) {
9829 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9832 case 0x00: /* SSHR / USHR */
9834 if (shift
== 8 << size
) {
9835 /* Shift count the same size as element size produces zero. */
9836 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9837 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9839 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9842 /* Shift count the same size as element size produces all sign. */
9843 if (shift
== 8 << size
) {
9846 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9850 case 0x04: /* SRSHR / URSHR (rounding) */
9852 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9856 g_assert_not_reached();
9859 round_const
= 1ULL << (shift
- 1);
9860 tcg_round
= tcg_const_i64(round_const
);
9862 for (i
= 0; i
< elements
; i
++) {
9863 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9865 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9868 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9869 accumulate
, is_u
, size
, shift
);
9871 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9873 tcg_temp_free_i64(tcg_round
);
9876 clear_vec_high(s
, is_q
, rd
);
9879 /* SHL/SLI - Vector shift left */
9880 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9881 int immh
, int immb
, int opcode
, int rn
, int rd
)
9883 int size
= 32 - clz32(immh
) - 1;
9884 int immhb
= immh
<< 3 | immb
;
9885 int shift
= immhb
- (8 << size
);
9887 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
9888 assert(size
>= 0 && size
<= 3);
9890 if (extract32(immh
, 3, 1) && !is_q
) {
9891 unallocated_encoding(s
);
9895 if (!fp_access_check(s
)) {
9900 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
9902 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
9906 /* USHLL/SHLL - Vector shift left with widening */
9907 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
9908 int immh
, int immb
, int opcode
, int rn
, int rd
)
9910 int size
= 32 - clz32(immh
) - 1;
9911 int immhb
= immh
<< 3 | immb
;
9912 int shift
= immhb
- (8 << size
);
9914 int esize
= 8 << size
;
9915 int elements
= dsize
/esize
;
9916 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9917 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9921 unallocated_encoding(s
);
9925 if (!fp_access_check(s
)) {
9929 /* For the LL variants the store is larger than the load,
9930 * so if rd == rn we would overwrite parts of our input.
9931 * So load everything right now and use shifts in the main loop.
9933 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
9935 for (i
= 0; i
< elements
; i
++) {
9936 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
9937 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
9938 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
9939 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
9943 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
9944 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
9945 int immh
, int immb
, int opcode
, int rn
, int rd
)
9947 int immhb
= immh
<< 3 | immb
;
9948 int size
= 32 - clz32(immh
) - 1;
9950 int esize
= 8 << size
;
9951 int elements
= dsize
/esize
;
9952 int shift
= (2 * esize
) - immhb
;
9953 bool round
= extract32(opcode
, 0, 1);
9954 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
9958 if (extract32(immh
, 3, 1)) {
9959 unallocated_encoding(s
);
9963 if (!fp_access_check(s
)) {
9967 tcg_rn
= tcg_temp_new_i64();
9968 tcg_rd
= tcg_temp_new_i64();
9969 tcg_final
= tcg_temp_new_i64();
9970 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
9973 uint64_t round_const
= 1ULL << (shift
- 1);
9974 tcg_round
= tcg_const_i64(round_const
);
9979 for (i
= 0; i
< elements
; i
++) {
9980 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
9981 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9982 false, true, size
+1, shift
);
9984 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
9988 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
9990 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
9993 tcg_temp_free_i64(tcg_round
);
9995 tcg_temp_free_i64(tcg_rn
);
9996 tcg_temp_free_i64(tcg_rd
);
9997 tcg_temp_free_i64(tcg_final
);
9999 clear_vec_high(s
, is_q
, rd
);
10003 /* AdvSIMD shift by immediate
10004 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10005 * +---+---+---+-------------+------+------+--------+---+------+------+
10006 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10007 * +---+---+---+-------------+------+------+--------+---+------+------+
10009 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10011 int rd
= extract32(insn
, 0, 5);
10012 int rn
= extract32(insn
, 5, 5);
10013 int opcode
= extract32(insn
, 11, 5);
10014 int immb
= extract32(insn
, 16, 3);
10015 int immh
= extract32(insn
, 19, 4);
10016 bool is_u
= extract32(insn
, 29, 1);
10017 bool is_q
= extract32(insn
, 30, 1);
10020 case 0x08: /* SRI */
10022 unallocated_encoding(s
);
10026 case 0x00: /* SSHR / USHR */
10027 case 0x02: /* SSRA / USRA (accumulate) */
10028 case 0x04: /* SRSHR / URSHR (rounding) */
10029 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10030 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10032 case 0x0a: /* SHL / SLI */
10033 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10035 case 0x10: /* SHRN */
10036 case 0x11: /* RSHRN / SQRSHRUN */
10038 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10041 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10044 case 0x12: /* SQSHRN / UQSHRN */
10045 case 0x13: /* SQRSHRN / UQRSHRN */
10046 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10049 case 0x14: /* SSHLL / USHLL */
10050 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10052 case 0x1c: /* SCVTF / UCVTF */
10053 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10056 case 0xc: /* SQSHLU */
10058 unallocated_encoding(s
);
10061 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10063 case 0xe: /* SQSHL, UQSHL */
10064 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10066 case 0x1f: /* FCVTZS/ FCVTZU */
10067 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10070 unallocated_encoding(s
);
10075 /* Generate code to do a "long" addition or subtraction, ie one done in
10076 * TCGv_i64 on vector lanes twice the width specified by size.
10078 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10079 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10081 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10082 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10083 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10084 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10086 NeonGenTwo64OpFn
*genfn
;
10089 genfn
= fns
[size
][is_sub
];
10090 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10093 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10094 int opcode
, int rd
, int rn
, int rm
)
10096 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10097 TCGv_i64 tcg_res
[2];
10100 tcg_res
[0] = tcg_temp_new_i64();
10101 tcg_res
[1] = tcg_temp_new_i64();
10103 /* Does this op do an adding accumulate, a subtracting accumulate,
10104 * or no accumulate at all?
10122 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10123 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10126 /* size == 2 means two 32x32->64 operations; this is worth special
10127 * casing because we can generally handle it inline.
10130 for (pass
= 0; pass
< 2; pass
++) {
10131 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10132 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10133 TCGv_i64 tcg_passres
;
10134 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10136 int elt
= pass
+ is_q
* 2;
10138 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10139 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10142 tcg_passres
= tcg_res
[pass
];
10144 tcg_passres
= tcg_temp_new_i64();
10148 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10149 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10151 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10152 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10154 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10155 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10157 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10158 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10160 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10161 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10162 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10164 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10165 tcg_temp_free_i64(tcg_tmp1
);
10166 tcg_temp_free_i64(tcg_tmp2
);
10169 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10170 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10171 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10172 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10174 case 9: /* SQDMLAL, SQDMLAL2 */
10175 case 11: /* SQDMLSL, SQDMLSL2 */
10176 case 13: /* SQDMULL, SQDMULL2 */
10177 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10178 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10179 tcg_passres
, tcg_passres
);
10182 g_assert_not_reached();
10185 if (opcode
== 9 || opcode
== 11) {
10186 /* saturating accumulate ops */
10188 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10190 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10191 tcg_res
[pass
], tcg_passres
);
10192 } else if (accop
> 0) {
10193 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10194 } else if (accop
< 0) {
10195 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10199 tcg_temp_free_i64(tcg_passres
);
10202 tcg_temp_free_i64(tcg_op1
);
10203 tcg_temp_free_i64(tcg_op2
);
10206 /* size 0 or 1, generally helper functions */
10207 for (pass
= 0; pass
< 2; pass
++) {
10208 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10209 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10210 TCGv_i64 tcg_passres
;
10211 int elt
= pass
+ is_q
* 2;
10213 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10214 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10217 tcg_passres
= tcg_res
[pass
];
10219 tcg_passres
= tcg_temp_new_i64();
10223 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10224 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10226 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10227 static NeonGenWidenFn
* const widenfns
[2][2] = {
10228 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10229 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10231 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10233 widenfn(tcg_op2_64
, tcg_op2
);
10234 widenfn(tcg_passres
, tcg_op1
);
10235 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10236 tcg_passres
, tcg_op2_64
);
10237 tcg_temp_free_i64(tcg_op2_64
);
10240 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10241 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10244 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10246 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10250 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10252 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10256 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10257 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10258 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10261 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10263 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10267 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10269 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10273 case 9: /* SQDMLAL, SQDMLAL2 */
10274 case 11: /* SQDMLSL, SQDMLSL2 */
10275 case 13: /* SQDMULL, SQDMULL2 */
10277 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10278 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10279 tcg_passres
, tcg_passres
);
10281 case 14: /* PMULL */
10283 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10286 g_assert_not_reached();
10288 tcg_temp_free_i32(tcg_op1
);
10289 tcg_temp_free_i32(tcg_op2
);
10292 if (opcode
== 9 || opcode
== 11) {
10293 /* saturating accumulate ops */
10295 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10297 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10301 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10302 tcg_res
[pass
], tcg_passres
);
10304 tcg_temp_free_i64(tcg_passres
);
10309 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10310 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10311 tcg_temp_free_i64(tcg_res
[0]);
10312 tcg_temp_free_i64(tcg_res
[1]);
10315 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10316 int opcode
, int rd
, int rn
, int rm
)
10318 TCGv_i64 tcg_res
[2];
10319 int part
= is_q
? 2 : 0;
10322 for (pass
= 0; pass
< 2; pass
++) {
10323 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10324 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10325 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10326 static NeonGenWidenFn
* const widenfns
[3][2] = {
10327 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10328 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10329 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10331 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10333 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10334 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10335 widenfn(tcg_op2_wide
, tcg_op2
);
10336 tcg_temp_free_i32(tcg_op2
);
10337 tcg_res
[pass
] = tcg_temp_new_i64();
10338 gen_neon_addl(size
, (opcode
== 3),
10339 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10340 tcg_temp_free_i64(tcg_op1
);
10341 tcg_temp_free_i64(tcg_op2_wide
);
10344 for (pass
= 0; pass
< 2; pass
++) {
10345 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10346 tcg_temp_free_i64(tcg_res
[pass
]);
10350 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10352 tcg_gen_addi_i64(in
, in
, 1U << 31);
10353 tcg_gen_extrh_i64_i32(res
, in
);
10356 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10357 int opcode
, int rd
, int rn
, int rm
)
10359 TCGv_i32 tcg_res
[2];
10360 int part
= is_q
? 2 : 0;
10363 for (pass
= 0; pass
< 2; pass
++) {
10364 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10365 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10366 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10367 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10368 { gen_helper_neon_narrow_high_u8
,
10369 gen_helper_neon_narrow_round_high_u8
},
10370 { gen_helper_neon_narrow_high_u16
,
10371 gen_helper_neon_narrow_round_high_u16
},
10372 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10374 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10376 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10377 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10379 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10381 tcg_temp_free_i64(tcg_op1
);
10382 tcg_temp_free_i64(tcg_op2
);
10384 tcg_res
[pass
] = tcg_temp_new_i32();
10385 gennarrow(tcg_res
[pass
], tcg_wideres
);
10386 tcg_temp_free_i64(tcg_wideres
);
10389 for (pass
= 0; pass
< 2; pass
++) {
10390 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10391 tcg_temp_free_i32(tcg_res
[pass
]);
10393 clear_vec_high(s
, is_q
, rd
);
10396 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10398 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10399 * is the only three-reg-diff instruction which produces a
10400 * 128-bit wide result from a single operation. However since
10401 * it's possible to calculate the two halves more or less
10402 * separately we just use two helper calls.
10404 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10405 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10406 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10408 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10409 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10410 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10411 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10412 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10413 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10415 tcg_temp_free_i64(tcg_op1
);
10416 tcg_temp_free_i64(tcg_op2
);
10417 tcg_temp_free_i64(tcg_res
);
10420 /* AdvSIMD three different
10421 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10422 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10423 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10424 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10426 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10428 /* Instructions in this group fall into three basic classes
10429 * (in each case with the operation working on each element in
10430 * the input vectors):
10431 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10433 * (2) wide 64 x 128 -> 128
10434 * (3) narrowing 128 x 128 -> 64
10435 * Here we do initial decode, catch unallocated cases and
10436 * dispatch to separate functions for each class.
10438 int is_q
= extract32(insn
, 30, 1);
10439 int is_u
= extract32(insn
, 29, 1);
10440 int size
= extract32(insn
, 22, 2);
10441 int opcode
= extract32(insn
, 12, 4);
10442 int rm
= extract32(insn
, 16, 5);
10443 int rn
= extract32(insn
, 5, 5);
10444 int rd
= extract32(insn
, 0, 5);
10447 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10448 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10449 /* 64 x 128 -> 128 */
10451 unallocated_encoding(s
);
10454 if (!fp_access_check(s
)) {
10457 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10459 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10460 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10461 /* 128 x 128 -> 64 */
10463 unallocated_encoding(s
);
10466 if (!fp_access_check(s
)) {
10469 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10471 case 14: /* PMULL, PMULL2 */
10472 if (is_u
|| size
== 1 || size
== 2) {
10473 unallocated_encoding(s
);
10477 if (!dc_isar_feature(aa64_pmull
, s
)) {
10478 unallocated_encoding(s
);
10481 if (!fp_access_check(s
)) {
10484 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10488 case 9: /* SQDMLAL, SQDMLAL2 */
10489 case 11: /* SQDMLSL, SQDMLSL2 */
10490 case 13: /* SQDMULL, SQDMULL2 */
10491 if (is_u
|| size
== 0) {
10492 unallocated_encoding(s
);
10496 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10497 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10498 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10499 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10500 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10501 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10502 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10503 /* 64 x 64 -> 128 */
10505 unallocated_encoding(s
);
10509 if (!fp_access_check(s
)) {
10513 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10516 /* opcode 15 not allocated */
10517 unallocated_encoding(s
);
10522 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10523 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10525 int rd
= extract32(insn
, 0, 5);
10526 int rn
= extract32(insn
, 5, 5);
10527 int rm
= extract32(insn
, 16, 5);
10528 int size
= extract32(insn
, 22, 2);
10529 bool is_u
= extract32(insn
, 29, 1);
10530 bool is_q
= extract32(insn
, 30, 1);
10532 if (!fp_access_check(s
)) {
10536 switch (size
+ 4 * is_u
) {
10538 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10541 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10544 if (rn
== rm
) { /* MOV */
10545 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_mov
, 0);
10547 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10551 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10554 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10557 case 5: /* BSL bitwise select */
10558 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10560 case 6: /* BIT, bitwise insert if true */
10561 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10563 case 7: /* BIF, bitwise insert if false */
10564 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10568 g_assert_not_reached();
10572 /* Pairwise op subgroup of C3.6.16.
10574 * This is called directly or via the handle_3same_float for float pairwise
10575 * operations where the opcode and size are calculated differently.
10577 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10578 int size
, int rn
, int rm
, int rd
)
10583 /* Floating point operations need fpst */
10584 if (opcode
>= 0x58) {
10585 fpst
= get_fpstatus_ptr(false);
10590 if (!fp_access_check(s
)) {
10594 /* These operations work on the concatenated rm:rn, with each pair of
10595 * adjacent elements being operated on to produce an element in the result.
10598 TCGv_i64 tcg_res
[2];
10600 for (pass
= 0; pass
< 2; pass
++) {
10601 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10602 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10603 int passreg
= (pass
== 0) ? rn
: rm
;
10605 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10606 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10607 tcg_res
[pass
] = tcg_temp_new_i64();
10610 case 0x17: /* ADDP */
10611 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10613 case 0x58: /* FMAXNMP */
10614 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10616 case 0x5a: /* FADDP */
10617 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10619 case 0x5e: /* FMAXP */
10620 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10622 case 0x78: /* FMINNMP */
10623 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10625 case 0x7e: /* FMINP */
10626 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10629 g_assert_not_reached();
10632 tcg_temp_free_i64(tcg_op1
);
10633 tcg_temp_free_i64(tcg_op2
);
10636 for (pass
= 0; pass
< 2; pass
++) {
10637 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10638 tcg_temp_free_i64(tcg_res
[pass
]);
10641 int maxpass
= is_q
? 4 : 2;
10642 TCGv_i32 tcg_res
[4];
10644 for (pass
= 0; pass
< maxpass
; pass
++) {
10645 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10646 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10647 NeonGenTwoOpFn
*genfn
= NULL
;
10648 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10649 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10651 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10652 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10653 tcg_res
[pass
] = tcg_temp_new_i32();
10656 case 0x17: /* ADDP */
10658 static NeonGenTwoOpFn
* const fns
[3] = {
10659 gen_helper_neon_padd_u8
,
10660 gen_helper_neon_padd_u16
,
10666 case 0x14: /* SMAXP, UMAXP */
10668 static NeonGenTwoOpFn
* const fns
[3][2] = {
10669 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10670 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10671 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10673 genfn
= fns
[size
][u
];
10676 case 0x15: /* SMINP, UMINP */
10678 static NeonGenTwoOpFn
* const fns
[3][2] = {
10679 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10680 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10681 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10683 genfn
= fns
[size
][u
];
10686 /* The FP operations are all on single floats (32 bit) */
10687 case 0x58: /* FMAXNMP */
10688 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10690 case 0x5a: /* FADDP */
10691 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10693 case 0x5e: /* FMAXP */
10694 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10696 case 0x78: /* FMINNMP */
10697 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10699 case 0x7e: /* FMINP */
10700 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10703 g_assert_not_reached();
10706 /* FP ops called directly, otherwise call now */
10708 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10711 tcg_temp_free_i32(tcg_op1
);
10712 tcg_temp_free_i32(tcg_op2
);
10715 for (pass
= 0; pass
< maxpass
; pass
++) {
10716 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10717 tcg_temp_free_i32(tcg_res
[pass
]);
10719 clear_vec_high(s
, is_q
, rd
);
10723 tcg_temp_free_ptr(fpst
);
10727 /* Floating point op subgroup of C3.6.16. */
10728 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10730 /* For floating point ops, the U, size[1] and opcode bits
10731 * together indicate the operation. size[0] indicates single
10734 int fpopcode
= extract32(insn
, 11, 5)
10735 | (extract32(insn
, 23, 1) << 5)
10736 | (extract32(insn
, 29, 1) << 6);
10737 int is_q
= extract32(insn
, 30, 1);
10738 int size
= extract32(insn
, 22, 1);
10739 int rm
= extract32(insn
, 16, 5);
10740 int rn
= extract32(insn
, 5, 5);
10741 int rd
= extract32(insn
, 0, 5);
10743 int datasize
= is_q
? 128 : 64;
10744 int esize
= 32 << size
;
10745 int elements
= datasize
/ esize
;
10747 if (size
== 1 && !is_q
) {
10748 unallocated_encoding(s
);
10752 switch (fpopcode
) {
10753 case 0x58: /* FMAXNMP */
10754 case 0x5a: /* FADDP */
10755 case 0x5e: /* FMAXP */
10756 case 0x78: /* FMINNMP */
10757 case 0x7e: /* FMINP */
10758 if (size
&& !is_q
) {
10759 unallocated_encoding(s
);
10762 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10765 case 0x1b: /* FMULX */
10766 case 0x1f: /* FRECPS */
10767 case 0x3f: /* FRSQRTS */
10768 case 0x5d: /* FACGE */
10769 case 0x7d: /* FACGT */
10770 case 0x19: /* FMLA */
10771 case 0x39: /* FMLS */
10772 case 0x18: /* FMAXNM */
10773 case 0x1a: /* FADD */
10774 case 0x1c: /* FCMEQ */
10775 case 0x1e: /* FMAX */
10776 case 0x38: /* FMINNM */
10777 case 0x3a: /* FSUB */
10778 case 0x3e: /* FMIN */
10779 case 0x5b: /* FMUL */
10780 case 0x5c: /* FCMGE */
10781 case 0x5f: /* FDIV */
10782 case 0x7a: /* FABD */
10783 case 0x7c: /* FCMGT */
10784 if (!fp_access_check(s
)) {
10788 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10791 unallocated_encoding(s
);
10796 /* Integer op subgroup of C3.6.16. */
10797 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10799 int is_q
= extract32(insn
, 30, 1);
10800 int u
= extract32(insn
, 29, 1);
10801 int size
= extract32(insn
, 22, 2);
10802 int opcode
= extract32(insn
, 11, 5);
10803 int rm
= extract32(insn
, 16, 5);
10804 int rn
= extract32(insn
, 5, 5);
10805 int rd
= extract32(insn
, 0, 5);
10810 case 0x13: /* MUL, PMUL */
10811 if (u
&& size
!= 0) {
10812 unallocated_encoding(s
);
10816 case 0x0: /* SHADD, UHADD */
10817 case 0x2: /* SRHADD, URHADD */
10818 case 0x4: /* SHSUB, UHSUB */
10819 case 0xc: /* SMAX, UMAX */
10820 case 0xd: /* SMIN, UMIN */
10821 case 0xe: /* SABD, UABD */
10822 case 0xf: /* SABA, UABA */
10823 case 0x12: /* MLA, MLS */
10825 unallocated_encoding(s
);
10829 case 0x16: /* SQDMULH, SQRDMULH */
10830 if (size
== 0 || size
== 3) {
10831 unallocated_encoding(s
);
10836 if (size
== 3 && !is_q
) {
10837 unallocated_encoding(s
);
10843 if (!fp_access_check(s
)) {
10848 case 0x10: /* ADD, SUB */
10850 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10852 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10855 case 0x13: /* MUL, PMUL */
10856 if (!u
) { /* MUL */
10857 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10861 case 0x12: /* MLA, MLS */
10863 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10865 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10869 if (!u
) { /* CMTST */
10870 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10874 cond
= TCG_COND_EQ
;
10876 case 0x06: /* CMGT, CMHI */
10877 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10879 case 0x07: /* CMGE, CMHS */
10880 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10882 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10883 vec_full_reg_offset(s
, rn
),
10884 vec_full_reg_offset(s
, rm
),
10885 is_q
? 16 : 8, vec_full_reg_size(s
));
10891 for (pass
= 0; pass
< 2; pass
++) {
10892 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10893 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10894 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10896 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10897 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10899 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
10901 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10903 tcg_temp_free_i64(tcg_res
);
10904 tcg_temp_free_i64(tcg_op1
);
10905 tcg_temp_free_i64(tcg_op2
);
10908 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10909 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10910 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10911 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10912 NeonGenTwoOpFn
*genfn
= NULL
;
10913 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
10915 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
10916 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
10919 case 0x0: /* SHADD, UHADD */
10921 static NeonGenTwoOpFn
* const fns
[3][2] = {
10922 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
10923 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
10924 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
10926 genfn
= fns
[size
][u
];
10929 case 0x1: /* SQADD, UQADD */
10931 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10932 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
10933 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
10934 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
10936 genenvfn
= fns
[size
][u
];
10939 case 0x2: /* SRHADD, URHADD */
10941 static NeonGenTwoOpFn
* const fns
[3][2] = {
10942 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
10943 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
10944 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
10946 genfn
= fns
[size
][u
];
10949 case 0x4: /* SHSUB, UHSUB */
10951 static NeonGenTwoOpFn
* const fns
[3][2] = {
10952 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
10953 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
10954 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
10956 genfn
= fns
[size
][u
];
10959 case 0x5: /* SQSUB, UQSUB */
10961 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10962 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
10963 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
10964 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
10966 genenvfn
= fns
[size
][u
];
10969 case 0x8: /* SSHL, USHL */
10971 static NeonGenTwoOpFn
* const fns
[3][2] = {
10972 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
10973 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
10974 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
10976 genfn
= fns
[size
][u
];
10979 case 0x9: /* SQSHL, UQSHL */
10981 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10982 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
10983 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
10984 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
10986 genenvfn
= fns
[size
][u
];
10989 case 0xa: /* SRSHL, URSHL */
10991 static NeonGenTwoOpFn
* const fns
[3][2] = {
10992 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
10993 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
10994 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
10996 genfn
= fns
[size
][u
];
10999 case 0xb: /* SQRSHL, UQRSHL */
11001 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11002 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11003 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11004 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11006 genenvfn
= fns
[size
][u
];
11009 case 0xc: /* SMAX, UMAX */
11011 static NeonGenTwoOpFn
* const fns
[3][2] = {
11012 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
11013 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
11014 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11016 genfn
= fns
[size
][u
];
11020 case 0xd: /* SMIN, UMIN */
11022 static NeonGenTwoOpFn
* const fns
[3][2] = {
11023 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
11024 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
11025 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11027 genfn
= fns
[size
][u
];
11030 case 0xe: /* SABD, UABD */
11031 case 0xf: /* SABA, UABA */
11033 static NeonGenTwoOpFn
* const fns
[3][2] = {
11034 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11035 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11036 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11038 genfn
= fns
[size
][u
];
11041 case 0x13: /* MUL, PMUL */
11042 assert(u
); /* PMUL */
11044 genfn
= gen_helper_neon_mul_p8
;
11046 case 0x16: /* SQDMULH, SQRDMULH */
11048 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11049 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11050 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11052 assert(size
== 1 || size
== 2);
11053 genenvfn
= fns
[size
- 1][u
];
11057 g_assert_not_reached();
11061 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11063 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11066 if (opcode
== 0xf) {
11067 /* SABA, UABA: accumulating ops */
11068 static NeonGenTwoOpFn
* const fns
[3] = {
11069 gen_helper_neon_add_u8
,
11070 gen_helper_neon_add_u16
,
11074 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11075 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11078 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11080 tcg_temp_free_i32(tcg_res
);
11081 tcg_temp_free_i32(tcg_op1
);
11082 tcg_temp_free_i32(tcg_op2
);
11085 clear_vec_high(s
, is_q
, rd
);
11088 /* AdvSIMD three same
11089 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11090 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11091 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11092 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11094 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11096 int opcode
= extract32(insn
, 11, 5);
11099 case 0x3: /* logic ops */
11100 disas_simd_3same_logic(s
, insn
);
11102 case 0x17: /* ADDP */
11103 case 0x14: /* SMAXP, UMAXP */
11104 case 0x15: /* SMINP, UMINP */
11106 /* Pairwise operations */
11107 int is_q
= extract32(insn
, 30, 1);
11108 int u
= extract32(insn
, 29, 1);
11109 int size
= extract32(insn
, 22, 2);
11110 int rm
= extract32(insn
, 16, 5);
11111 int rn
= extract32(insn
, 5, 5);
11112 int rd
= extract32(insn
, 0, 5);
11113 if (opcode
== 0x17) {
11114 if (u
|| (size
== 3 && !is_q
)) {
11115 unallocated_encoding(s
);
11120 unallocated_encoding(s
);
11124 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11127 case 0x18 ... 0x31:
11128 /* floating point ops, sz[1] and U are part of opcode */
11129 disas_simd_3same_float(s
, insn
);
11132 disas_simd_3same_int(s
, insn
);
11138 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11140 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11141 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11142 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11143 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11145 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11146 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11149 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11151 int opcode
, fpopcode
;
11152 int is_q
, u
, a
, rm
, rn
, rd
;
11153 int datasize
, elements
;
11156 bool pairwise
= false;
11158 if (!dc_isar_feature(aa64_fp16
, s
)) {
11159 unallocated_encoding(s
);
11163 if (!fp_access_check(s
)) {
11167 /* For these floating point ops, the U, a and opcode bits
11168 * together indicate the operation.
11170 opcode
= extract32(insn
, 11, 3);
11171 u
= extract32(insn
, 29, 1);
11172 a
= extract32(insn
, 23, 1);
11173 is_q
= extract32(insn
, 30, 1);
11174 rm
= extract32(insn
, 16, 5);
11175 rn
= extract32(insn
, 5, 5);
11176 rd
= extract32(insn
, 0, 5);
11178 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11179 datasize
= is_q
? 128 : 64;
11180 elements
= datasize
/ 16;
11182 switch (fpopcode
) {
11183 case 0x10: /* FMAXNMP */
11184 case 0x12: /* FADDP */
11185 case 0x16: /* FMAXP */
11186 case 0x18: /* FMINNMP */
11187 case 0x1e: /* FMINP */
11192 fpst
= get_fpstatus_ptr(true);
11195 int maxpass
= is_q
? 8 : 4;
11196 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11197 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11198 TCGv_i32 tcg_res
[8];
11200 for (pass
= 0; pass
< maxpass
; pass
++) {
11201 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11202 int passelt
= (pass
<< 1) & (maxpass
- 1);
11204 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11205 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11206 tcg_res
[pass
] = tcg_temp_new_i32();
11208 switch (fpopcode
) {
11209 case 0x10: /* FMAXNMP */
11210 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11213 case 0x12: /* FADDP */
11214 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11216 case 0x16: /* FMAXP */
11217 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11219 case 0x18: /* FMINNMP */
11220 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11223 case 0x1e: /* FMINP */
11224 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11227 g_assert_not_reached();
11231 for (pass
= 0; pass
< maxpass
; pass
++) {
11232 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11233 tcg_temp_free_i32(tcg_res
[pass
]);
11236 tcg_temp_free_i32(tcg_op1
);
11237 tcg_temp_free_i32(tcg_op2
);
11240 for (pass
= 0; pass
< elements
; pass
++) {
11241 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11242 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11243 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11245 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11246 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11248 switch (fpopcode
) {
11249 case 0x0: /* FMAXNM */
11250 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11252 case 0x1: /* FMLA */
11253 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11254 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11257 case 0x2: /* FADD */
11258 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11260 case 0x3: /* FMULX */
11261 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11263 case 0x4: /* FCMEQ */
11264 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11266 case 0x6: /* FMAX */
11267 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11269 case 0x7: /* FRECPS */
11270 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11272 case 0x8: /* FMINNM */
11273 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11275 case 0x9: /* FMLS */
11276 /* As usual for ARM, separate negation for fused multiply-add */
11277 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11278 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11279 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11282 case 0xa: /* FSUB */
11283 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11285 case 0xe: /* FMIN */
11286 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11288 case 0xf: /* FRSQRTS */
11289 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11291 case 0x13: /* FMUL */
11292 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11294 case 0x14: /* FCMGE */
11295 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11297 case 0x15: /* FACGE */
11298 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11300 case 0x17: /* FDIV */
11301 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11303 case 0x1a: /* FABD */
11304 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11305 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11307 case 0x1c: /* FCMGT */
11308 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11310 case 0x1d: /* FACGT */
11311 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11314 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11315 __func__
, insn
, fpopcode
, s
->pc
);
11316 g_assert_not_reached();
11319 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11320 tcg_temp_free_i32(tcg_res
);
11321 tcg_temp_free_i32(tcg_op1
);
11322 tcg_temp_free_i32(tcg_op2
);
11326 tcg_temp_free_ptr(fpst
);
11328 clear_vec_high(s
, is_q
, rd
);
11331 /* AdvSIMD three same extra
11332 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11333 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11334 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11335 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11337 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11339 int rd
= extract32(insn
, 0, 5);
11340 int rn
= extract32(insn
, 5, 5);
11341 int opcode
= extract32(insn
, 11, 4);
11342 int rm
= extract32(insn
, 16, 5);
11343 int size
= extract32(insn
, 22, 2);
11344 bool u
= extract32(insn
, 29, 1);
11345 bool is_q
= extract32(insn
, 30, 1);
11349 switch (u
* 16 + opcode
) {
11350 case 0x10: /* SQRDMLAH (vector) */
11351 case 0x11: /* SQRDMLSH (vector) */
11352 if (size
!= 1 && size
!= 2) {
11353 unallocated_encoding(s
);
11356 feature
= dc_isar_feature(aa64_rdm
, s
);
11358 case 0x02: /* SDOT (vector) */
11359 case 0x12: /* UDOT (vector) */
11360 if (size
!= MO_32
) {
11361 unallocated_encoding(s
);
11364 feature
= dc_isar_feature(aa64_dp
, s
);
11366 case 0x18: /* FCMLA, #0 */
11367 case 0x19: /* FCMLA, #90 */
11368 case 0x1a: /* FCMLA, #180 */
11369 case 0x1b: /* FCMLA, #270 */
11370 case 0x1c: /* FCADD, #90 */
11371 case 0x1e: /* FCADD, #270 */
11373 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11374 || (size
== 3 && !is_q
)) {
11375 unallocated_encoding(s
);
11378 feature
= dc_isar_feature(aa64_fcma
, s
);
11381 unallocated_encoding(s
);
11385 unallocated_encoding(s
);
11388 if (!fp_access_check(s
)) {
11393 case 0x0: /* SQRDMLAH (vector) */
11396 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11399 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11402 g_assert_not_reached();
11406 case 0x1: /* SQRDMLSH (vector) */
11409 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11412 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11415 g_assert_not_reached();
11419 case 0x2: /* SDOT / UDOT */
11420 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11421 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11424 case 0x8: /* FCMLA, #0 */
11425 case 0x9: /* FCMLA, #90 */
11426 case 0xa: /* FCMLA, #180 */
11427 case 0xb: /* FCMLA, #270 */
11428 rot
= extract32(opcode
, 0, 2);
11431 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11432 gen_helper_gvec_fcmlah
);
11435 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11436 gen_helper_gvec_fcmlas
);
11439 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11440 gen_helper_gvec_fcmlad
);
11443 g_assert_not_reached();
11447 case 0xc: /* FCADD, #90 */
11448 case 0xe: /* FCADD, #270 */
11449 rot
= extract32(opcode
, 1, 1);
11452 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11453 gen_helper_gvec_fcaddh
);
11456 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11457 gen_helper_gvec_fcadds
);
11460 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11461 gen_helper_gvec_fcaddd
);
11464 g_assert_not_reached();
11469 g_assert_not_reached();
11473 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11474 int size
, int rn
, int rd
)
11476 /* Handle 2-reg-misc ops which are widening (so each size element
11477 * in the source becomes a 2*size element in the destination.
11478 * The only instruction like this is FCVTL.
11483 /* 32 -> 64 bit fp conversion */
11484 TCGv_i64 tcg_res
[2];
11485 int srcelt
= is_q
? 2 : 0;
11487 for (pass
= 0; pass
< 2; pass
++) {
11488 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11489 tcg_res
[pass
] = tcg_temp_new_i64();
11491 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11492 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11493 tcg_temp_free_i32(tcg_op
);
11495 for (pass
= 0; pass
< 2; pass
++) {
11496 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11497 tcg_temp_free_i64(tcg_res
[pass
]);
11500 /* 16 -> 32 bit fp conversion */
11501 int srcelt
= is_q
? 4 : 0;
11502 TCGv_i32 tcg_res
[4];
11503 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11504 TCGv_i32 ahp
= get_ahp_flag();
11506 for (pass
= 0; pass
< 4; pass
++) {
11507 tcg_res
[pass
] = tcg_temp_new_i32();
11509 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11510 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11513 for (pass
= 0; pass
< 4; pass
++) {
11514 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11515 tcg_temp_free_i32(tcg_res
[pass
]);
11518 tcg_temp_free_ptr(fpst
);
11519 tcg_temp_free_i32(ahp
);
11523 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11524 bool is_q
, int size
, int rn
, int rd
)
11526 int op
= (opcode
<< 1) | u
;
11527 int opsz
= op
+ size
;
11528 int grp_size
= 3 - opsz
;
11529 int dsize
= is_q
? 128 : 64;
11533 unallocated_encoding(s
);
11537 if (!fp_access_check(s
)) {
11542 /* Special case bytes, use bswap op on each group of elements */
11543 int groups
= dsize
/ (8 << grp_size
);
11545 for (i
= 0; i
< groups
; i
++) {
11546 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11548 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11549 switch (grp_size
) {
11551 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11554 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11557 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11560 g_assert_not_reached();
11562 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11563 tcg_temp_free_i64(tcg_tmp
);
11565 clear_vec_high(s
, is_q
, rd
);
11567 int revmask
= (1 << grp_size
) - 1;
11568 int esize
= 8 << size
;
11569 int elements
= dsize
/ esize
;
11570 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11571 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11572 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11574 for (i
= 0; i
< elements
; i
++) {
11575 int e_rev
= (i
& 0xf) ^ revmask
;
11576 int off
= e_rev
* esize
;
11577 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11579 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11580 tcg_rn
, off
- 64, esize
);
11582 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11585 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11586 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11588 tcg_temp_free_i64(tcg_rd_hi
);
11589 tcg_temp_free_i64(tcg_rd
);
11590 tcg_temp_free_i64(tcg_rn
);
11594 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11595 bool is_q
, int size
, int rn
, int rd
)
11597 /* Implement the pairwise operations from 2-misc:
11598 * SADDLP, UADDLP, SADALP, UADALP.
11599 * These all add pairs of elements in the input to produce a
11600 * double-width result element in the output (possibly accumulating).
11602 bool accum
= (opcode
== 0x6);
11603 int maxpass
= is_q
? 2 : 1;
11605 TCGv_i64 tcg_res
[2];
11608 /* 32 + 32 -> 64 op */
11609 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11611 for (pass
= 0; pass
< maxpass
; pass
++) {
11612 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11613 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11615 tcg_res
[pass
] = tcg_temp_new_i64();
11617 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11618 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11619 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11621 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11622 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11625 tcg_temp_free_i64(tcg_op1
);
11626 tcg_temp_free_i64(tcg_op2
);
11629 for (pass
= 0; pass
< maxpass
; pass
++) {
11630 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11631 NeonGenOneOpFn
*genfn
;
11632 static NeonGenOneOpFn
* const fns
[2][2] = {
11633 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11634 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11637 genfn
= fns
[size
][u
];
11639 tcg_res
[pass
] = tcg_temp_new_i64();
11641 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11642 genfn(tcg_res
[pass
], tcg_op
);
11645 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11647 gen_helper_neon_addl_u16(tcg_res
[pass
],
11648 tcg_res
[pass
], tcg_op
);
11650 gen_helper_neon_addl_u32(tcg_res
[pass
],
11651 tcg_res
[pass
], tcg_op
);
11654 tcg_temp_free_i64(tcg_op
);
11658 tcg_res
[1] = tcg_const_i64(0);
11660 for (pass
= 0; pass
< 2; pass
++) {
11661 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11662 tcg_temp_free_i64(tcg_res
[pass
]);
11666 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11668 /* Implement SHLL and SHLL2 */
11670 int part
= is_q
? 2 : 0;
11671 TCGv_i64 tcg_res
[2];
11673 for (pass
= 0; pass
< 2; pass
++) {
11674 static NeonGenWidenFn
* const widenfns
[3] = {
11675 gen_helper_neon_widen_u8
,
11676 gen_helper_neon_widen_u16
,
11677 tcg_gen_extu_i32_i64
,
11679 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11680 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11682 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11683 tcg_res
[pass
] = tcg_temp_new_i64();
11684 widenfn(tcg_res
[pass
], tcg_op
);
11685 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11687 tcg_temp_free_i32(tcg_op
);
11690 for (pass
= 0; pass
< 2; pass
++) {
11691 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11692 tcg_temp_free_i64(tcg_res
[pass
]);
11696 /* AdvSIMD two reg misc
11697 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11698 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11699 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11700 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11702 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11704 int size
= extract32(insn
, 22, 2);
11705 int opcode
= extract32(insn
, 12, 5);
11706 bool u
= extract32(insn
, 29, 1);
11707 bool is_q
= extract32(insn
, 30, 1);
11708 int rn
= extract32(insn
, 5, 5);
11709 int rd
= extract32(insn
, 0, 5);
11710 bool need_fpstatus
= false;
11711 bool need_rmode
= false;
11713 TCGv_i32 tcg_rmode
;
11714 TCGv_ptr tcg_fpstatus
;
11717 case 0x0: /* REV64, REV32 */
11718 case 0x1: /* REV16 */
11719 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11721 case 0x5: /* CNT, NOT, RBIT */
11722 if (u
&& size
== 0) {
11725 } else if (u
&& size
== 1) {
11728 } else if (!u
&& size
== 0) {
11732 unallocated_encoding(s
);
11734 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11735 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11737 unallocated_encoding(s
);
11740 if (!fp_access_check(s
)) {
11744 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11746 case 0x4: /* CLS, CLZ */
11748 unallocated_encoding(s
);
11752 case 0x2: /* SADDLP, UADDLP */
11753 case 0x6: /* SADALP, UADALP */
11755 unallocated_encoding(s
);
11758 if (!fp_access_check(s
)) {
11761 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11763 case 0x13: /* SHLL, SHLL2 */
11764 if (u
== 0 || size
== 3) {
11765 unallocated_encoding(s
);
11768 if (!fp_access_check(s
)) {
11771 handle_shll(s
, is_q
, size
, rn
, rd
);
11773 case 0xa: /* CMLT */
11775 unallocated_encoding(s
);
11779 case 0x8: /* CMGT, CMGE */
11780 case 0x9: /* CMEQ, CMLE */
11781 case 0xb: /* ABS, NEG */
11782 if (size
== 3 && !is_q
) {
11783 unallocated_encoding(s
);
11787 case 0x3: /* SUQADD, USQADD */
11788 if (size
== 3 && !is_q
) {
11789 unallocated_encoding(s
);
11792 if (!fp_access_check(s
)) {
11795 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11797 case 0x7: /* SQABS, SQNEG */
11798 if (size
== 3 && !is_q
) {
11799 unallocated_encoding(s
);
11804 case 0x16 ... 0x1d:
11807 /* Floating point: U, size[1] and opcode indicate operation;
11808 * size[0] indicates single or double precision.
11810 int is_double
= extract32(size
, 0, 1);
11811 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11812 size
= is_double
? 3 : 2;
11814 case 0x2f: /* FABS */
11815 case 0x6f: /* FNEG */
11816 if (size
== 3 && !is_q
) {
11817 unallocated_encoding(s
);
11821 case 0x1d: /* SCVTF */
11822 case 0x5d: /* UCVTF */
11824 bool is_signed
= (opcode
== 0x1d) ? true : false;
11825 int elements
= is_double
? 2 : is_q
? 4 : 2;
11826 if (is_double
&& !is_q
) {
11827 unallocated_encoding(s
);
11830 if (!fp_access_check(s
)) {
11833 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11836 case 0x2c: /* FCMGT (zero) */
11837 case 0x2d: /* FCMEQ (zero) */
11838 case 0x2e: /* FCMLT (zero) */
11839 case 0x6c: /* FCMGE (zero) */
11840 case 0x6d: /* FCMLE (zero) */
11841 if (size
== 3 && !is_q
) {
11842 unallocated_encoding(s
);
11845 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11847 case 0x7f: /* FSQRT */
11848 if (size
== 3 && !is_q
) {
11849 unallocated_encoding(s
);
11853 case 0x1a: /* FCVTNS */
11854 case 0x1b: /* FCVTMS */
11855 case 0x3a: /* FCVTPS */
11856 case 0x3b: /* FCVTZS */
11857 case 0x5a: /* FCVTNU */
11858 case 0x5b: /* FCVTMU */
11859 case 0x7a: /* FCVTPU */
11860 case 0x7b: /* FCVTZU */
11861 need_fpstatus
= true;
11863 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11864 if (size
== 3 && !is_q
) {
11865 unallocated_encoding(s
);
11869 case 0x5c: /* FCVTAU */
11870 case 0x1c: /* FCVTAS */
11871 need_fpstatus
= true;
11873 rmode
= FPROUNDING_TIEAWAY
;
11874 if (size
== 3 && !is_q
) {
11875 unallocated_encoding(s
);
11879 case 0x3c: /* URECPE */
11881 unallocated_encoding(s
);
11885 case 0x3d: /* FRECPE */
11886 case 0x7d: /* FRSQRTE */
11887 if (size
== 3 && !is_q
) {
11888 unallocated_encoding(s
);
11891 if (!fp_access_check(s
)) {
11894 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11896 case 0x56: /* FCVTXN, FCVTXN2 */
11898 unallocated_encoding(s
);
11902 case 0x16: /* FCVTN, FCVTN2 */
11903 /* handle_2misc_narrow does a 2*size -> size operation, but these
11904 * instructions encode the source size rather than dest size.
11906 if (!fp_access_check(s
)) {
11909 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
11911 case 0x17: /* FCVTL, FCVTL2 */
11912 if (!fp_access_check(s
)) {
11915 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
11917 case 0x18: /* FRINTN */
11918 case 0x19: /* FRINTM */
11919 case 0x38: /* FRINTP */
11920 case 0x39: /* FRINTZ */
11922 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11924 case 0x59: /* FRINTX */
11925 case 0x79: /* FRINTI */
11926 need_fpstatus
= true;
11927 if (size
== 3 && !is_q
) {
11928 unallocated_encoding(s
);
11932 case 0x58: /* FRINTA */
11934 rmode
= FPROUNDING_TIEAWAY
;
11935 need_fpstatus
= true;
11936 if (size
== 3 && !is_q
) {
11937 unallocated_encoding(s
);
11941 case 0x7c: /* URSQRTE */
11943 unallocated_encoding(s
);
11946 need_fpstatus
= true;
11949 unallocated_encoding(s
);
11955 unallocated_encoding(s
);
11959 if (!fp_access_check(s
)) {
11963 if (need_fpstatus
|| need_rmode
) {
11964 tcg_fpstatus
= get_fpstatus_ptr(false);
11966 tcg_fpstatus
= NULL
;
11969 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
11970 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
11977 if (u
&& size
== 0) { /* NOT */
11978 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
11984 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
11991 /* All 64-bit element operations can be shared with scalar 2misc */
11994 /* Coverity claims (size == 3 && !is_q) has been eliminated
11995 * from all paths leading to here.
11997 tcg_debug_assert(is_q
);
11998 for (pass
= 0; pass
< 2; pass
++) {
11999 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12000 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12002 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12004 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12005 tcg_rmode
, tcg_fpstatus
);
12007 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12009 tcg_temp_free_i64(tcg_res
);
12010 tcg_temp_free_i64(tcg_op
);
12015 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12016 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12017 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12020 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12023 /* Special cases for 32 bit elements */
12025 case 0xa: /* CMLT */
12026 /* 32 bit integer comparison against zero, result is
12027 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12030 cond
= TCG_COND_LT
;
12032 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12033 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12035 case 0x8: /* CMGT, CMGE */
12036 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12038 case 0x9: /* CMEQ, CMLE */
12039 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12041 case 0x4: /* CLS */
12043 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12045 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12048 case 0x7: /* SQABS, SQNEG */
12050 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12052 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12055 case 0xb: /* ABS, NEG */
12057 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12059 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12060 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12061 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12062 tcg_zero
, tcg_op
, tcg_res
);
12063 tcg_temp_free_i32(tcg_zero
);
12066 case 0x2f: /* FABS */
12067 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12069 case 0x6f: /* FNEG */
12070 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12072 case 0x7f: /* FSQRT */
12073 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12075 case 0x1a: /* FCVTNS */
12076 case 0x1b: /* FCVTMS */
12077 case 0x1c: /* FCVTAS */
12078 case 0x3a: /* FCVTPS */
12079 case 0x3b: /* FCVTZS */
12081 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12082 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12083 tcg_shift
, tcg_fpstatus
);
12084 tcg_temp_free_i32(tcg_shift
);
12087 case 0x5a: /* FCVTNU */
12088 case 0x5b: /* FCVTMU */
12089 case 0x5c: /* FCVTAU */
12090 case 0x7a: /* FCVTPU */
12091 case 0x7b: /* FCVTZU */
12093 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12094 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12095 tcg_shift
, tcg_fpstatus
);
12096 tcg_temp_free_i32(tcg_shift
);
12099 case 0x18: /* FRINTN */
12100 case 0x19: /* FRINTM */
12101 case 0x38: /* FRINTP */
12102 case 0x39: /* FRINTZ */
12103 case 0x58: /* FRINTA */
12104 case 0x79: /* FRINTI */
12105 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12107 case 0x59: /* FRINTX */
12108 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12110 case 0x7c: /* URSQRTE */
12111 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12114 g_assert_not_reached();
12117 /* Use helpers for 8 and 16 bit elements */
12119 case 0x5: /* CNT, RBIT */
12120 /* For these two insns size is part of the opcode specifier
12121 * (handled earlier); they always operate on byte elements.
12124 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12126 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12129 case 0x7: /* SQABS, SQNEG */
12131 NeonGenOneOpEnvFn
*genfn
;
12132 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12133 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12134 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12136 genfn
= fns
[size
][u
];
12137 genfn(tcg_res
, cpu_env
, tcg_op
);
12140 case 0x8: /* CMGT, CMGE */
12141 case 0x9: /* CMEQ, CMLE */
12142 case 0xa: /* CMLT */
12144 static NeonGenTwoOpFn
* const fns
[3][2] = {
12145 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12146 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12147 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12149 NeonGenTwoOpFn
*genfn
;
12152 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12154 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12155 comp
= (opcode
- 0x8) * 2 + u
;
12156 /* ...but LE, LT are implemented as reverse GE, GT */
12157 reverse
= (comp
> 2);
12161 genfn
= fns
[comp
][size
];
12163 genfn(tcg_res
, tcg_zero
, tcg_op
);
12165 genfn(tcg_res
, tcg_op
, tcg_zero
);
12167 tcg_temp_free_i32(tcg_zero
);
12170 case 0xb: /* ABS, NEG */
12172 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12174 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12176 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12178 tcg_temp_free_i32(tcg_zero
);
12181 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12183 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12187 case 0x4: /* CLS, CLZ */
12190 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12192 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12196 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12198 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12203 g_assert_not_reached();
12207 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12209 tcg_temp_free_i32(tcg_res
);
12210 tcg_temp_free_i32(tcg_op
);
12213 clear_vec_high(s
, is_q
, rd
);
12216 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12217 tcg_temp_free_i32(tcg_rmode
);
12219 if (need_fpstatus
) {
12220 tcg_temp_free_ptr(tcg_fpstatus
);
12224 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12226 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12227 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12228 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12229 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12230 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12231 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12233 * This actually covers two groups where scalar access is governed by
12234 * bit 28. A bunch of the instructions (float to integral) only exist
12235 * in the vector form and are un-allocated for the scalar decode. Also
12236 * in the scalar decode Q is always 1.
12238 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12240 int fpop
, opcode
, a
, u
;
12244 bool only_in_vector
= false;
12247 TCGv_i32 tcg_rmode
= NULL
;
12248 TCGv_ptr tcg_fpstatus
= NULL
;
12249 bool need_rmode
= false;
12250 bool need_fpst
= true;
12253 if (!dc_isar_feature(aa64_fp16
, s
)) {
12254 unallocated_encoding(s
);
12258 rd
= extract32(insn
, 0, 5);
12259 rn
= extract32(insn
, 5, 5);
12261 a
= extract32(insn
, 23, 1);
12262 u
= extract32(insn
, 29, 1);
12263 is_scalar
= extract32(insn
, 28, 1);
12264 is_q
= extract32(insn
, 30, 1);
12266 opcode
= extract32(insn
, 12, 5);
12267 fpop
= deposit32(opcode
, 5, 1, a
);
12268 fpop
= deposit32(fpop
, 6, 1, u
);
12270 rd
= extract32(insn
, 0, 5);
12271 rn
= extract32(insn
, 5, 5);
12274 case 0x1d: /* SCVTF */
12275 case 0x5d: /* UCVTF */
12282 elements
= (is_q
? 8 : 4);
12285 if (!fp_access_check(s
)) {
12288 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12292 case 0x2c: /* FCMGT (zero) */
12293 case 0x2d: /* FCMEQ (zero) */
12294 case 0x2e: /* FCMLT (zero) */
12295 case 0x6c: /* FCMGE (zero) */
12296 case 0x6d: /* FCMLE (zero) */
12297 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12299 case 0x3d: /* FRECPE */
12300 case 0x3f: /* FRECPX */
12302 case 0x18: /* FRINTN */
12304 only_in_vector
= true;
12305 rmode
= FPROUNDING_TIEEVEN
;
12307 case 0x19: /* FRINTM */
12309 only_in_vector
= true;
12310 rmode
= FPROUNDING_NEGINF
;
12312 case 0x38: /* FRINTP */
12314 only_in_vector
= true;
12315 rmode
= FPROUNDING_POSINF
;
12317 case 0x39: /* FRINTZ */
12319 only_in_vector
= true;
12320 rmode
= FPROUNDING_ZERO
;
12322 case 0x58: /* FRINTA */
12324 only_in_vector
= true;
12325 rmode
= FPROUNDING_TIEAWAY
;
12327 case 0x59: /* FRINTX */
12328 case 0x79: /* FRINTI */
12329 only_in_vector
= true;
12330 /* current rounding mode */
12332 case 0x1a: /* FCVTNS */
12334 rmode
= FPROUNDING_TIEEVEN
;
12336 case 0x1b: /* FCVTMS */
12338 rmode
= FPROUNDING_NEGINF
;
12340 case 0x1c: /* FCVTAS */
12342 rmode
= FPROUNDING_TIEAWAY
;
12344 case 0x3a: /* FCVTPS */
12346 rmode
= FPROUNDING_POSINF
;
12348 case 0x3b: /* FCVTZS */
12350 rmode
= FPROUNDING_ZERO
;
12352 case 0x5a: /* FCVTNU */
12354 rmode
= FPROUNDING_TIEEVEN
;
12356 case 0x5b: /* FCVTMU */
12358 rmode
= FPROUNDING_NEGINF
;
12360 case 0x5c: /* FCVTAU */
12362 rmode
= FPROUNDING_TIEAWAY
;
12364 case 0x7a: /* FCVTPU */
12366 rmode
= FPROUNDING_POSINF
;
12368 case 0x7b: /* FCVTZU */
12370 rmode
= FPROUNDING_ZERO
;
12372 case 0x2f: /* FABS */
12373 case 0x6f: /* FNEG */
12376 case 0x7d: /* FRSQRTE */
12377 case 0x7f: /* FSQRT (vector) */
12380 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12381 g_assert_not_reached();
12385 /* Check additional constraints for the scalar encoding */
12388 unallocated_encoding(s
);
12391 /* FRINTxx is only in the vector form */
12392 if (only_in_vector
) {
12393 unallocated_encoding(s
);
12398 if (!fp_access_check(s
)) {
12402 if (need_rmode
|| need_fpst
) {
12403 tcg_fpstatus
= get_fpstatus_ptr(true);
12407 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12408 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12412 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12413 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12416 case 0x1a: /* FCVTNS */
12417 case 0x1b: /* FCVTMS */
12418 case 0x1c: /* FCVTAS */
12419 case 0x3a: /* FCVTPS */
12420 case 0x3b: /* FCVTZS */
12421 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12423 case 0x3d: /* FRECPE */
12424 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12426 case 0x3f: /* FRECPX */
12427 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12429 case 0x5a: /* FCVTNU */
12430 case 0x5b: /* FCVTMU */
12431 case 0x5c: /* FCVTAU */
12432 case 0x7a: /* FCVTPU */
12433 case 0x7b: /* FCVTZU */
12434 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12436 case 0x6f: /* FNEG */
12437 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12439 case 0x7d: /* FRSQRTE */
12440 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12443 g_assert_not_reached();
12446 /* limit any sign extension going on */
12447 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12448 write_fp_sreg(s
, rd
, tcg_res
);
12450 tcg_temp_free_i32(tcg_res
);
12451 tcg_temp_free_i32(tcg_op
);
12453 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12454 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12455 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12457 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12460 case 0x1a: /* FCVTNS */
12461 case 0x1b: /* FCVTMS */
12462 case 0x1c: /* FCVTAS */
12463 case 0x3a: /* FCVTPS */
12464 case 0x3b: /* FCVTZS */
12465 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12467 case 0x3d: /* FRECPE */
12468 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12470 case 0x5a: /* FCVTNU */
12471 case 0x5b: /* FCVTMU */
12472 case 0x5c: /* FCVTAU */
12473 case 0x7a: /* FCVTPU */
12474 case 0x7b: /* FCVTZU */
12475 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12477 case 0x18: /* FRINTN */
12478 case 0x19: /* FRINTM */
12479 case 0x38: /* FRINTP */
12480 case 0x39: /* FRINTZ */
12481 case 0x58: /* FRINTA */
12482 case 0x79: /* FRINTI */
12483 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12485 case 0x59: /* FRINTX */
12486 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12488 case 0x2f: /* FABS */
12489 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12491 case 0x6f: /* FNEG */
12492 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12494 case 0x7d: /* FRSQRTE */
12495 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12497 case 0x7f: /* FSQRT */
12498 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12501 g_assert_not_reached();
12504 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12506 tcg_temp_free_i32(tcg_res
);
12507 tcg_temp_free_i32(tcg_op
);
12510 clear_vec_high(s
, is_q
, rd
);
12514 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12515 tcg_temp_free_i32(tcg_rmode
);
12518 if (tcg_fpstatus
) {
12519 tcg_temp_free_ptr(tcg_fpstatus
);
12523 /* AdvSIMD scalar x indexed element
12524 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12525 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12526 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12527 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12528 * AdvSIMD vector x indexed element
12529 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12530 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12531 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12532 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12534 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12536 /* This encoding has two kinds of instruction:
12537 * normal, where we perform elt x idxelt => elt for each
12538 * element in the vector
12539 * long, where we perform elt x idxelt and generate a result of
12540 * double the width of the input element
12541 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12543 bool is_scalar
= extract32(insn
, 28, 1);
12544 bool is_q
= extract32(insn
, 30, 1);
12545 bool u
= extract32(insn
, 29, 1);
12546 int size
= extract32(insn
, 22, 2);
12547 int l
= extract32(insn
, 21, 1);
12548 int m
= extract32(insn
, 20, 1);
12549 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12550 int rm
= extract32(insn
, 16, 4);
12551 int opcode
= extract32(insn
, 12, 4);
12552 int h
= extract32(insn
, 11, 1);
12553 int rn
= extract32(insn
, 5, 5);
12554 int rd
= extract32(insn
, 0, 5);
12555 bool is_long
= false;
12557 bool is_fp16
= false;
12561 switch (16 * u
+ opcode
) {
12562 case 0x08: /* MUL */
12563 case 0x10: /* MLA */
12564 case 0x14: /* MLS */
12566 unallocated_encoding(s
);
12570 case 0x02: /* SMLAL, SMLAL2 */
12571 case 0x12: /* UMLAL, UMLAL2 */
12572 case 0x06: /* SMLSL, SMLSL2 */
12573 case 0x16: /* UMLSL, UMLSL2 */
12574 case 0x0a: /* SMULL, SMULL2 */
12575 case 0x1a: /* UMULL, UMULL2 */
12577 unallocated_encoding(s
);
12582 case 0x03: /* SQDMLAL, SQDMLAL2 */
12583 case 0x07: /* SQDMLSL, SQDMLSL2 */
12584 case 0x0b: /* SQDMULL, SQDMULL2 */
12587 case 0x0c: /* SQDMULH */
12588 case 0x0d: /* SQRDMULH */
12590 case 0x01: /* FMLA */
12591 case 0x05: /* FMLS */
12592 case 0x09: /* FMUL */
12593 case 0x19: /* FMULX */
12596 case 0x1d: /* SQRDMLAH */
12597 case 0x1f: /* SQRDMLSH */
12598 if (!dc_isar_feature(aa64_rdm
, s
)) {
12599 unallocated_encoding(s
);
12603 case 0x0e: /* SDOT */
12604 case 0x1e: /* UDOT */
12605 if (size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12606 unallocated_encoding(s
);
12610 case 0x11: /* FCMLA #0 */
12611 case 0x13: /* FCMLA #90 */
12612 case 0x15: /* FCMLA #180 */
12613 case 0x17: /* FCMLA #270 */
12614 if (!dc_isar_feature(aa64_fcma
, s
)) {
12615 unallocated_encoding(s
);
12621 unallocated_encoding(s
);
12626 case 1: /* normal fp */
12627 /* convert insn encoded size to TCGMemOp size */
12629 case 0: /* half-precision */
12633 case MO_32
: /* single precision */
12634 case MO_64
: /* double precision */
12637 unallocated_encoding(s
);
12642 case 2: /* complex fp */
12643 /* Each indexable element is a complex pair. */
12648 unallocated_encoding(s
);
12656 unallocated_encoding(s
);
12661 default: /* integer */
12665 unallocated_encoding(s
);
12670 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12671 unallocated_encoding(s
);
12675 /* Given TCGMemOp size, adjust register and indexing. */
12678 index
= h
<< 2 | l
<< 1 | m
;
12681 index
= h
<< 1 | l
;
12686 unallocated_encoding(s
);
12693 g_assert_not_reached();
12696 if (!fp_access_check(s
)) {
12701 fpst
= get_fpstatus_ptr(is_fp16
);
12706 switch (16 * u
+ opcode
) {
12707 case 0x0e: /* SDOT */
12708 case 0x1e: /* UDOT */
12709 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12710 u
? gen_helper_gvec_udot_idx_b
12711 : gen_helper_gvec_sdot_idx_b
);
12713 case 0x11: /* FCMLA #0 */
12714 case 0x13: /* FCMLA #90 */
12715 case 0x15: /* FCMLA #180 */
12716 case 0x17: /* FCMLA #270 */
12718 int rot
= extract32(insn
, 13, 2);
12719 int data
= (index
<< 2) | rot
;
12720 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12721 vec_full_reg_offset(s
, rn
),
12722 vec_full_reg_offset(s
, rm
), fpst
,
12723 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12725 ? gen_helper_gvec_fcmlas_idx
12726 : gen_helper_gvec_fcmlah_idx
);
12727 tcg_temp_free_ptr(fpst
);
12733 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12736 assert(is_fp
&& is_q
&& !is_long
);
12738 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12740 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12741 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12742 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12744 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12746 switch (16 * u
+ opcode
) {
12747 case 0x05: /* FMLS */
12748 /* As usual for ARM, separate negation for fused multiply-add */
12749 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12751 case 0x01: /* FMLA */
12752 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12753 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12755 case 0x09: /* FMUL */
12756 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12758 case 0x19: /* FMULX */
12759 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12762 g_assert_not_reached();
12765 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12766 tcg_temp_free_i64(tcg_op
);
12767 tcg_temp_free_i64(tcg_res
);
12770 tcg_temp_free_i64(tcg_idx
);
12771 clear_vec_high(s
, !is_scalar
, rd
);
12772 } else if (!is_long
) {
12773 /* 32 bit floating point, or 16 or 32 bit integer.
12774 * For the 16 bit scalar case we use the usual Neon helpers and
12775 * rely on the fact that 0 op 0 == 0 with no side effects.
12777 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12778 int pass
, maxpasses
;
12783 maxpasses
= is_q
? 4 : 2;
12786 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12788 if (size
== 1 && !is_scalar
) {
12789 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12790 * the index into both halves of the 32 bit tcg_idx and then use
12791 * the usual Neon helpers.
12793 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12796 for (pass
= 0; pass
< maxpasses
; pass
++) {
12797 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12798 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12800 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12802 switch (16 * u
+ opcode
) {
12803 case 0x08: /* MUL */
12804 case 0x10: /* MLA */
12805 case 0x14: /* MLS */
12807 static NeonGenTwoOpFn
* const fns
[2][2] = {
12808 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12809 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12811 NeonGenTwoOpFn
*genfn
;
12812 bool is_sub
= opcode
== 0x4;
12815 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12817 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12819 if (opcode
== 0x8) {
12822 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12823 genfn
= fns
[size
- 1][is_sub
];
12824 genfn(tcg_res
, tcg_op
, tcg_res
);
12827 case 0x05: /* FMLS */
12828 case 0x01: /* FMLA */
12829 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12830 is_scalar
? size
: MO_32
);
12833 if (opcode
== 0x5) {
12834 /* As usual for ARM, separate negation for fused
12836 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12839 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12842 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12847 if (opcode
== 0x5) {
12848 /* As usual for ARM, separate negation for
12849 * fused multiply-add */
12850 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12852 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12856 g_assert_not_reached();
12859 case 0x09: /* FMUL */
12863 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12866 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12871 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12874 g_assert_not_reached();
12877 case 0x19: /* FMULX */
12881 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12884 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12889 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12892 g_assert_not_reached();
12895 case 0x0c: /* SQDMULH */
12897 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
12900 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
12904 case 0x0d: /* SQRDMULH */
12906 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
12909 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
12913 case 0x1d: /* SQRDMLAH */
12914 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12915 is_scalar
? size
: MO_32
);
12917 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
12918 tcg_op
, tcg_idx
, tcg_res
);
12920 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
12921 tcg_op
, tcg_idx
, tcg_res
);
12924 case 0x1f: /* SQRDMLSH */
12925 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12926 is_scalar
? size
: MO_32
);
12928 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
12929 tcg_op
, tcg_idx
, tcg_res
);
12931 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
12932 tcg_op
, tcg_idx
, tcg_res
);
12936 g_assert_not_reached();
12940 write_fp_sreg(s
, rd
, tcg_res
);
12942 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12945 tcg_temp_free_i32(tcg_op
);
12946 tcg_temp_free_i32(tcg_res
);
12949 tcg_temp_free_i32(tcg_idx
);
12950 clear_vec_high(s
, is_q
, rd
);
12952 /* long ops: 16x16->32 or 32x32->64 */
12953 TCGv_i64 tcg_res
[2];
12955 bool satop
= extract32(opcode
, 0, 1);
12956 TCGMemOp memop
= MO_32
;
12963 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12965 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
12967 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12968 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12969 TCGv_i64 tcg_passres
;
12975 passelt
= pass
+ (is_q
* 2);
12978 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
12980 tcg_res
[pass
] = tcg_temp_new_i64();
12982 if (opcode
== 0xa || opcode
== 0xb) {
12983 /* Non-accumulating ops */
12984 tcg_passres
= tcg_res
[pass
];
12986 tcg_passres
= tcg_temp_new_i64();
12989 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
12990 tcg_temp_free_i64(tcg_op
);
12993 /* saturating, doubling */
12994 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
12995 tcg_passres
, tcg_passres
);
12998 if (opcode
== 0xa || opcode
== 0xb) {
13002 /* Accumulating op: handle accumulate step */
13003 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13006 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13007 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13009 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13010 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13012 case 0x7: /* SQDMLSL, SQDMLSL2 */
13013 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13015 case 0x3: /* SQDMLAL, SQDMLAL2 */
13016 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13021 g_assert_not_reached();
13023 tcg_temp_free_i64(tcg_passres
);
13025 tcg_temp_free_i64(tcg_idx
);
13027 clear_vec_high(s
, !is_scalar
, rd
);
13029 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13032 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13035 /* The simplest way to handle the 16x16 indexed ops is to
13036 * duplicate the index into both halves of the 32 bit tcg_idx
13037 * and then use the usual Neon helpers.
13039 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13042 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13043 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13044 TCGv_i64 tcg_passres
;
13047 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13049 read_vec_element_i32(s
, tcg_op
, rn
,
13050 pass
+ (is_q
* 2), MO_32
);
13053 tcg_res
[pass
] = tcg_temp_new_i64();
13055 if (opcode
== 0xa || opcode
== 0xb) {
13056 /* Non-accumulating ops */
13057 tcg_passres
= tcg_res
[pass
];
13059 tcg_passres
= tcg_temp_new_i64();
13062 if (memop
& MO_SIGN
) {
13063 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13065 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13068 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13069 tcg_passres
, tcg_passres
);
13071 tcg_temp_free_i32(tcg_op
);
13073 if (opcode
== 0xa || opcode
== 0xb) {
13077 /* Accumulating op: handle accumulate step */
13078 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13081 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13082 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13085 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13086 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13089 case 0x7: /* SQDMLSL, SQDMLSL2 */
13090 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13092 case 0x3: /* SQDMLAL, SQDMLAL2 */
13093 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13098 g_assert_not_reached();
13100 tcg_temp_free_i64(tcg_passres
);
13102 tcg_temp_free_i32(tcg_idx
);
13105 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13110 tcg_res
[1] = tcg_const_i64(0);
13113 for (pass
= 0; pass
< 2; pass
++) {
13114 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13115 tcg_temp_free_i64(tcg_res
[pass
]);
13120 tcg_temp_free_ptr(fpst
);
13125 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13126 * +-----------------+------+-----------+--------+-----+------+------+
13127 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13128 * +-----------------+------+-----------+--------+-----+------+------+
13130 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13132 int size
= extract32(insn
, 22, 2);
13133 int opcode
= extract32(insn
, 12, 5);
13134 int rn
= extract32(insn
, 5, 5);
13135 int rd
= extract32(insn
, 0, 5);
13137 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13138 TCGv_i32 tcg_decrypt
;
13139 CryptoThreeOpIntFn
*genfn
;
13141 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13142 unallocated_encoding(s
);
13147 case 0x4: /* AESE */
13149 genfn
= gen_helper_crypto_aese
;
13151 case 0x6: /* AESMC */
13153 genfn
= gen_helper_crypto_aesmc
;
13155 case 0x5: /* AESD */
13157 genfn
= gen_helper_crypto_aese
;
13159 case 0x7: /* AESIMC */
13161 genfn
= gen_helper_crypto_aesmc
;
13164 unallocated_encoding(s
);
13168 if (!fp_access_check(s
)) {
13172 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13173 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13174 tcg_decrypt
= tcg_const_i32(decrypt
);
13176 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13178 tcg_temp_free_ptr(tcg_rd_ptr
);
13179 tcg_temp_free_ptr(tcg_rn_ptr
);
13180 tcg_temp_free_i32(tcg_decrypt
);
13183 /* Crypto three-reg SHA
13184 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13185 * +-----------------+------+---+------+---+--------+-----+------+------+
13186 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13187 * +-----------------+------+---+------+---+--------+-----+------+------+
13189 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13191 int size
= extract32(insn
, 22, 2);
13192 int opcode
= extract32(insn
, 12, 3);
13193 int rm
= extract32(insn
, 16, 5);
13194 int rn
= extract32(insn
, 5, 5);
13195 int rd
= extract32(insn
, 0, 5);
13196 CryptoThreeOpFn
*genfn
;
13197 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13201 unallocated_encoding(s
);
13206 case 0: /* SHA1C */
13207 case 1: /* SHA1P */
13208 case 2: /* SHA1M */
13209 case 3: /* SHA1SU0 */
13211 feature
= dc_isar_feature(aa64_sha1
, s
);
13213 case 4: /* SHA256H */
13214 genfn
= gen_helper_crypto_sha256h
;
13215 feature
= dc_isar_feature(aa64_sha256
, s
);
13217 case 5: /* SHA256H2 */
13218 genfn
= gen_helper_crypto_sha256h2
;
13219 feature
= dc_isar_feature(aa64_sha256
, s
);
13221 case 6: /* SHA256SU1 */
13222 genfn
= gen_helper_crypto_sha256su1
;
13223 feature
= dc_isar_feature(aa64_sha256
, s
);
13226 unallocated_encoding(s
);
13231 unallocated_encoding(s
);
13235 if (!fp_access_check(s
)) {
13239 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13240 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13241 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13244 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13246 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13248 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13249 tcg_rm_ptr
, tcg_opcode
);
13250 tcg_temp_free_i32(tcg_opcode
);
13253 tcg_temp_free_ptr(tcg_rd_ptr
);
13254 tcg_temp_free_ptr(tcg_rn_ptr
);
13255 tcg_temp_free_ptr(tcg_rm_ptr
);
13258 /* Crypto two-reg SHA
13259 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13260 * +-----------------+------+-----------+--------+-----+------+------+
13261 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13262 * +-----------------+------+-----------+--------+-----+------+------+
13264 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13266 int size
= extract32(insn
, 22, 2);
13267 int opcode
= extract32(insn
, 12, 5);
13268 int rn
= extract32(insn
, 5, 5);
13269 int rd
= extract32(insn
, 0, 5);
13270 CryptoTwoOpFn
*genfn
;
13272 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13275 unallocated_encoding(s
);
13280 case 0: /* SHA1H */
13281 feature
= dc_isar_feature(aa64_sha1
, s
);
13282 genfn
= gen_helper_crypto_sha1h
;
13284 case 1: /* SHA1SU1 */
13285 feature
= dc_isar_feature(aa64_sha1
, s
);
13286 genfn
= gen_helper_crypto_sha1su1
;
13288 case 2: /* SHA256SU0 */
13289 feature
= dc_isar_feature(aa64_sha256
, s
);
13290 genfn
= gen_helper_crypto_sha256su0
;
13293 unallocated_encoding(s
);
13298 unallocated_encoding(s
);
13302 if (!fp_access_check(s
)) {
13306 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13307 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13309 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13311 tcg_temp_free_ptr(tcg_rd_ptr
);
13312 tcg_temp_free_ptr(tcg_rn_ptr
);
13315 /* Crypto three-reg SHA512
13316 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13317 * +-----------------------+------+---+---+-----+--------+------+------+
13318 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13319 * +-----------------------+------+---+---+-----+--------+------+------+
13321 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13323 int opcode
= extract32(insn
, 10, 2);
13324 int o
= extract32(insn
, 14, 1);
13325 int rm
= extract32(insn
, 16, 5);
13326 int rn
= extract32(insn
, 5, 5);
13327 int rd
= extract32(insn
, 0, 5);
13329 CryptoThreeOpFn
*genfn
;
13333 case 0: /* SHA512H */
13334 feature
= dc_isar_feature(aa64_sha512
, s
);
13335 genfn
= gen_helper_crypto_sha512h
;
13337 case 1: /* SHA512H2 */
13338 feature
= dc_isar_feature(aa64_sha512
, s
);
13339 genfn
= gen_helper_crypto_sha512h2
;
13341 case 2: /* SHA512SU1 */
13342 feature
= dc_isar_feature(aa64_sha512
, s
);
13343 genfn
= gen_helper_crypto_sha512su1
;
13346 feature
= dc_isar_feature(aa64_sha3
, s
);
13352 case 0: /* SM3PARTW1 */
13353 feature
= dc_isar_feature(aa64_sm3
, s
);
13354 genfn
= gen_helper_crypto_sm3partw1
;
13356 case 1: /* SM3PARTW2 */
13357 feature
= dc_isar_feature(aa64_sm3
, s
);
13358 genfn
= gen_helper_crypto_sm3partw2
;
13360 case 2: /* SM4EKEY */
13361 feature
= dc_isar_feature(aa64_sm4
, s
);
13362 genfn
= gen_helper_crypto_sm4ekey
;
13365 unallocated_encoding(s
);
13371 unallocated_encoding(s
);
13375 if (!fp_access_check(s
)) {
13380 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13382 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13383 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13384 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13386 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13388 tcg_temp_free_ptr(tcg_rd_ptr
);
13389 tcg_temp_free_ptr(tcg_rn_ptr
);
13390 tcg_temp_free_ptr(tcg_rm_ptr
);
13392 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13395 tcg_op1
= tcg_temp_new_i64();
13396 tcg_op2
= tcg_temp_new_i64();
13397 tcg_res
[0] = tcg_temp_new_i64();
13398 tcg_res
[1] = tcg_temp_new_i64();
13400 for (pass
= 0; pass
< 2; pass
++) {
13401 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13402 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13404 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13405 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13407 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13408 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13410 tcg_temp_free_i64(tcg_op1
);
13411 tcg_temp_free_i64(tcg_op2
);
13412 tcg_temp_free_i64(tcg_res
[0]);
13413 tcg_temp_free_i64(tcg_res
[1]);
13417 /* Crypto two-reg SHA512
13418 * 31 12 11 10 9 5 4 0
13419 * +-----------------------------------------+--------+------+------+
13420 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13421 * +-----------------------------------------+--------+------+------+
13423 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13425 int opcode
= extract32(insn
, 10, 2);
13426 int rn
= extract32(insn
, 5, 5);
13427 int rd
= extract32(insn
, 0, 5);
13428 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13430 CryptoTwoOpFn
*genfn
;
13433 case 0: /* SHA512SU0 */
13434 feature
= dc_isar_feature(aa64_sha512
, s
);
13435 genfn
= gen_helper_crypto_sha512su0
;
13438 feature
= dc_isar_feature(aa64_sm4
, s
);
13439 genfn
= gen_helper_crypto_sm4e
;
13442 unallocated_encoding(s
);
13447 unallocated_encoding(s
);
13451 if (!fp_access_check(s
)) {
13455 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13456 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13458 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13460 tcg_temp_free_ptr(tcg_rd_ptr
);
13461 tcg_temp_free_ptr(tcg_rn_ptr
);
13464 /* Crypto four-register
13465 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13466 * +-------------------+-----+------+---+------+------+------+
13467 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13468 * +-------------------+-----+------+---+------+------+------+
13470 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13472 int op0
= extract32(insn
, 21, 2);
13473 int rm
= extract32(insn
, 16, 5);
13474 int ra
= extract32(insn
, 10, 5);
13475 int rn
= extract32(insn
, 5, 5);
13476 int rd
= extract32(insn
, 0, 5);
13482 feature
= dc_isar_feature(aa64_sha3
, s
);
13484 case 2: /* SM3SS1 */
13485 feature
= dc_isar_feature(aa64_sm3
, s
);
13488 unallocated_encoding(s
);
13493 unallocated_encoding(s
);
13497 if (!fp_access_check(s
)) {
13502 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13505 tcg_op1
= tcg_temp_new_i64();
13506 tcg_op2
= tcg_temp_new_i64();
13507 tcg_op3
= tcg_temp_new_i64();
13508 tcg_res
[0] = tcg_temp_new_i64();
13509 tcg_res
[1] = tcg_temp_new_i64();
13511 for (pass
= 0; pass
< 2; pass
++) {
13512 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13513 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13514 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13518 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13521 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13523 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13525 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13526 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13528 tcg_temp_free_i64(tcg_op1
);
13529 tcg_temp_free_i64(tcg_op2
);
13530 tcg_temp_free_i64(tcg_op3
);
13531 tcg_temp_free_i64(tcg_res
[0]);
13532 tcg_temp_free_i64(tcg_res
[1]);
13534 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13536 tcg_op1
= tcg_temp_new_i32();
13537 tcg_op2
= tcg_temp_new_i32();
13538 tcg_op3
= tcg_temp_new_i32();
13539 tcg_res
= tcg_temp_new_i32();
13540 tcg_zero
= tcg_const_i32(0);
13542 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13543 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13544 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13546 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13547 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13548 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13549 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13551 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13552 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13553 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13554 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13556 tcg_temp_free_i32(tcg_op1
);
13557 tcg_temp_free_i32(tcg_op2
);
13558 tcg_temp_free_i32(tcg_op3
);
13559 tcg_temp_free_i32(tcg_res
);
13560 tcg_temp_free_i32(tcg_zero
);
13565 * 31 21 20 16 15 10 9 5 4 0
13566 * +-----------------------+------+--------+------+------+
13567 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13568 * +-----------------------+------+--------+------+------+
13570 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13572 int rm
= extract32(insn
, 16, 5);
13573 int imm6
= extract32(insn
, 10, 6);
13574 int rn
= extract32(insn
, 5, 5);
13575 int rd
= extract32(insn
, 0, 5);
13576 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13579 if (!dc_isar_feature(aa64_sha3
, s
)) {
13580 unallocated_encoding(s
);
13584 if (!fp_access_check(s
)) {
13588 tcg_op1
= tcg_temp_new_i64();
13589 tcg_op2
= tcg_temp_new_i64();
13590 tcg_res
[0] = tcg_temp_new_i64();
13591 tcg_res
[1] = tcg_temp_new_i64();
13593 for (pass
= 0; pass
< 2; pass
++) {
13594 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13595 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13597 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13598 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13600 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13601 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13603 tcg_temp_free_i64(tcg_op1
);
13604 tcg_temp_free_i64(tcg_op2
);
13605 tcg_temp_free_i64(tcg_res
[0]);
13606 tcg_temp_free_i64(tcg_res
[1]);
13609 /* Crypto three-reg imm2
13610 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13611 * +-----------------------+------+-----+------+--------+------+------+
13612 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13613 * +-----------------------+------+-----+------+--------+------+------+
13615 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13617 int opcode
= extract32(insn
, 10, 2);
13618 int imm2
= extract32(insn
, 12, 2);
13619 int rm
= extract32(insn
, 16, 5);
13620 int rn
= extract32(insn
, 5, 5);
13621 int rd
= extract32(insn
, 0, 5);
13622 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13623 TCGv_i32 tcg_imm2
, tcg_opcode
;
13625 if (!dc_isar_feature(aa64_sm3
, s
)) {
13626 unallocated_encoding(s
);
13630 if (!fp_access_check(s
)) {
13634 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13635 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13636 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13637 tcg_imm2
= tcg_const_i32(imm2
);
13638 tcg_opcode
= tcg_const_i32(opcode
);
13640 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13643 tcg_temp_free_ptr(tcg_rd_ptr
);
13644 tcg_temp_free_ptr(tcg_rn_ptr
);
13645 tcg_temp_free_ptr(tcg_rm_ptr
);
13646 tcg_temp_free_i32(tcg_imm2
);
13647 tcg_temp_free_i32(tcg_opcode
);
13650 /* C3.6 Data processing - SIMD, inc Crypto
13652 * As the decode gets a little complex we are using a table based
13653 * approach for this part of the decode.
13655 static const AArch64DecodeTable data_proc_simd
[] = {
13656 /* pattern , mask , fn */
13657 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13658 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13659 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13660 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13661 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13662 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13663 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13664 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13665 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13666 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13667 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13668 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13669 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13670 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13671 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13672 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13673 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13674 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13675 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13676 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13677 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13678 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13679 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13680 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13681 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13682 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13683 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13684 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13685 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13686 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13687 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13688 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13689 { 0x00000000, 0x00000000, NULL
}
13692 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13694 /* Note that this is called with all non-FP cases from
13695 * table C3-6 so it must UNDEF for entries not specifically
13696 * allocated to instructions in that table.
13698 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13702 unallocated_encoding(s
);
13706 /* C3.6 Data processing - SIMD and floating point */
13707 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13709 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13710 disas_data_proc_fp(s
, insn
);
13712 /* SIMD, including crypto */
13713 disas_data_proc_simd(s
, insn
);
13717 /* C3.1 A64 instruction index by encoding */
13718 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13722 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13726 s
->fp_access_checked
= false;
13728 switch (extract32(insn
, 25, 4)) {
13729 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
13730 unallocated_encoding(s
);
13733 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
13734 unallocated_encoding(s
);
13737 case 0x8: case 0x9: /* Data processing - immediate */
13738 disas_data_proc_imm(s
, insn
);
13740 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13741 disas_b_exc_sys(s
, insn
);
13746 case 0xe: /* Loads and stores */
13747 disas_ldst(s
, insn
);
13750 case 0xd: /* Data processing - register */
13751 disas_data_proc_reg(s
, insn
);
13754 case 0xf: /* Data processing - SIMD and floating point */
13755 disas_data_proc_simd_fp(s
, insn
);
13758 assert(FALSE
); /* all 15 cases should be handled above */
13762 /* if we allocated any temporaries, free them here */
13766 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
13769 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13770 CPUARMState
*env
= cpu
->env_ptr
;
13771 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
13772 uint32_t tb_flags
= dc
->base
.tb
->flags
;
13773 int bound
, core_mmu_idx
;
13775 dc
->isar
= &arm_cpu
->isar
;
13776 dc
->pc
= dc
->base
.pc_first
;
13780 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13781 * there is no secure EL1, so we route exceptions to EL3.
13783 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
13784 !arm_el_is_aa64(env
, 3);
13787 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
13788 dc
->condexec_mask
= 0;
13789 dc
->condexec_cond
= 0;
13790 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
13791 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
13792 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
13793 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
13794 #if !defined(CONFIG_USER_ONLY)
13795 dc
->user
= (dc
->current_el
== 0);
13797 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
13798 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
13799 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
13800 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
13802 dc
->vec_stride
= 0;
13803 dc
->cp_regs
= arm_cpu
->cp_regs
;
13804 dc
->features
= env
->features
;
13806 /* Single step state. The code-generation logic here is:
13808 * generate code with no special handling for single-stepping (except
13809 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13810 * this happens anyway because those changes are all system register or
13812 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13813 * emit code for one insn
13814 * emit code to clear PSTATE.SS
13815 * emit code to generate software step exception for completed step
13816 * end TB (as usual for having generated an exception)
13817 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13818 * emit code to generate a software step exception
13821 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
13822 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
13823 dc
->is_ldex
= false;
13824 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
13826 /* Bound the number of insns to execute to those left on the page. */
13827 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
13829 /* If architectural single step active, limit to 1. */
13830 if (dc
->ss_active
) {
13833 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
13835 init_tmp_a64_array(dc
);
13838 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
13842 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13844 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13846 tcg_gen_insn_start(dc
->pc
, 0, 0);
13847 dc
->insn_start
= tcg_last_op();
13850 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
13851 const CPUBreakpoint
*bp
)
13853 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13855 if (bp
->flags
& BP_CPU
) {
13856 gen_a64_set_pc_im(dc
->pc
);
13857 gen_helper_check_breakpoints(cpu_env
);
13858 /* End the TB early; it likely won't be executed */
13859 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13861 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
13862 /* The address covered by the breakpoint must be
13863 included in [tb->pc, tb->pc + tb->size) in order
13864 to for it to be properly cleared -- thus we
13865 increment the PC here so that the logic setting
13866 tb->size below does the right thing. */
13868 dc
->base
.is_jmp
= DISAS_NORETURN
;
13874 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13876 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13877 CPUARMState
*env
= cpu
->env_ptr
;
13879 if (dc
->ss_active
&& !dc
->pstate_ss
) {
13880 /* Singlestep state is Active-pending.
13881 * If we're in this state at the start of a TB then either
13882 * a) we just took an exception to an EL which is being debugged
13883 * and this is the first insn in the exception handler
13884 * b) debug exceptions were masked and we just unmasked them
13885 * without changing EL (eg by clearing PSTATE.D)
13886 * In either case we're going to take a swstep exception in the
13887 * "did not step an insn" case, and so the syndrome ISV and EX
13888 * bits should be zero.
13890 assert(dc
->base
.num_insns
== 1);
13891 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
13892 default_exception_el(dc
));
13893 dc
->base
.is_jmp
= DISAS_NORETURN
;
13895 disas_a64_insn(env
, dc
);
13898 dc
->base
.pc_next
= dc
->pc
;
13899 translator_loop_temp_check(&dc
->base
);
13902 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
13904 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13906 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
13907 /* Note that this means single stepping WFI doesn't halt the CPU.
13908 * For conditional branch insns this is harmless unreachable code as
13909 * gen_goto_tb() has already handled emitting the debug exception
13910 * (and thus a tb-jump is not possible when singlestepping).
13912 switch (dc
->base
.is_jmp
) {
13914 gen_a64_set_pc_im(dc
->pc
);
13918 if (dc
->base
.singlestep_enabled
) {
13919 gen_exception_internal(EXCP_DEBUG
);
13921 gen_step_complete_exception(dc
);
13924 case DISAS_NORETURN
:
13928 switch (dc
->base
.is_jmp
) {
13930 case DISAS_TOO_MANY
:
13931 gen_goto_tb(dc
, 1, dc
->pc
);
13935 gen_a64_set_pc_im(dc
->pc
);
13938 tcg_gen_exit_tb(NULL
, 0);
13941 tcg_gen_lookup_and_goto_ptr();
13943 case DISAS_NORETURN
:
13947 gen_a64_set_pc_im(dc
->pc
);
13948 gen_helper_wfe(cpu_env
);
13951 gen_a64_set_pc_im(dc
->pc
);
13952 gen_helper_yield(cpu_env
);
13956 /* This is a special case because we don't want to just halt the CPU
13957 * if trying to debug across a WFI.
13959 TCGv_i32 tmp
= tcg_const_i32(4);
13961 gen_a64_set_pc_im(dc
->pc
);
13962 gen_helper_wfi(cpu_env
, tmp
);
13963 tcg_temp_free_i32(tmp
);
13964 /* The helper doesn't necessarily throw an exception, but we
13965 * must go back to the main loop to check for interrupts anyway.
13967 tcg_gen_exit_tb(NULL
, 0);
13973 /* Functions above can change dc->pc, so re-align db->pc_next */
13974 dc
->base
.pc_next
= dc
->pc
;
13977 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
13980 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13982 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
13983 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
13986 const TranslatorOps aarch64_translator_ops
= {
13987 .init_disas_context
= aarch64_tr_init_disas_context
,
13988 .tb_start
= aarch64_tr_tb_start
,
13989 .insn_start
= aarch64_tr_insn_start
,
13990 .breakpoint_check
= aarch64_tr_breakpoint_check
,
13991 .translate_insn
= aarch64_tr_translate_insn
,
13992 .tb_stop
= aarch64_tr_tb_stop
,
13993 .disas_log
= aarch64_tr_disas_log
,