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i386/kvm: set tsc_khz before configuring Hyper-V CPUID
[qemu/ar7.git] / target / i386 / kvm.c
blob15d56ae3f8de2fa72fd758243573803497f40209
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39 #include "hw/i386/intel_iommu.h"
40 #include "hw/i386/x86-iommu.h"
41
42 #include "exec/ioport.h"
43 #include "standard-headers/asm-x86/hyperv.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_xss;
93
94 static bool has_msr_architectural_pmu;
95 static uint32_t num_architectural_pmu_counters;
96
97 static int has_xsave;
98 static int has_xcrs;
99 static int has_pit_state2;
100
101 static bool has_msr_mcg_ext_ctl;
102
103 static struct kvm_cpuid2 *cpuid_cache;
104
105 int kvm_has_pit_state2(void)
106 {
107 return has_pit_state2;
108 }
109
110 bool kvm_has_smm(void)
111 {
112 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
113 }
114
115 bool kvm_has_adjust_clock_stable(void)
116 {
117 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
118
119 return (ret == KVM_CLOCK_TSC_STABLE);
120 }
121
122 bool kvm_allows_irq0_override(void)
123 {
124 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
125 }
126
127 static bool kvm_x2apic_api_set_flags(uint64_t flags)
128 {
129 KVMState *s = KVM_STATE(current_machine->accelerator);
130
131 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
132 }
133
134 #define MEMORIZE(fn, _result) \
135 ({ \
136 static bool _memorized; \
137 \
138 if (_memorized) { \
139 return _result; \
140 } \
141 _memorized = true; \
142 _result = fn; \
143 })
144
145 static bool has_x2apic_api;
146
147 bool kvm_has_x2apic_api(void)
148 {
149 return has_x2apic_api;
150 }
151
152 bool kvm_enable_x2apic(void)
153 {
154 return MEMORIZE(
155 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
156 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
157 has_x2apic_api);
158 }
159
160 static int kvm_get_tsc(CPUState *cs)
161 {
162 X86CPU *cpu = X86_CPU(cs);
163 CPUX86State *env = &cpu->env;
164 struct {
165 struct kvm_msrs info;
166 struct kvm_msr_entry entries[1];
167 } msr_data;
168 int ret;
169
170 if (env->tsc_valid) {
171 return 0;
172 }
173
174 msr_data.info.nmsrs = 1;
175 msr_data.entries[0].index = MSR_IA32_TSC;
176 env->tsc_valid = !runstate_is_running();
177
178 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
179 if (ret < 0) {
180 return ret;
181 }
182
183 assert(ret == 1);
184 env->tsc = msr_data.entries[0].data;
185 return 0;
186 }
187
188 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
189 {
190 kvm_get_tsc(cpu);
191 }
192
193 void kvm_synchronize_all_tsc(void)
194 {
195 CPUState *cpu;
196
197 if (kvm_enabled()) {
198 CPU_FOREACH(cpu) {
199 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
200 }
201 }
202 }
203
204 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
205 {
206 struct kvm_cpuid2 *cpuid;
207 int r, size;
208
209 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
210 cpuid = g_malloc0(size);
211 cpuid->nent = max;
212 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
213 if (r == 0 && cpuid->nent >= max) {
214 r = -E2BIG;
215 }
216 if (r < 0) {
217 if (r == -E2BIG) {
218 g_free(cpuid);
219 return NULL;
220 } else {
221 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
222 strerror(-r));
223 exit(1);
224 }
225 }
226 return cpuid;
227 }
228
229 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
230 * for all entries.
231 */
232 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
233 {
234 struct kvm_cpuid2 *cpuid;
235 int max = 1;
236
237 if (cpuid_cache != NULL) {
238 return cpuid_cache;
239 }
240 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
241 max *= 2;
242 }
243 cpuid_cache = cpuid;
244 return cpuid;
245 }
246
247 static const struct kvm_para_features {
248 int cap;
249 int feature;
250 } para_features[] = {
251 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
252 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
253 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
254 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
255 };
256
257 static int get_para_features(KVMState *s)
258 {
259 int i, features = 0;
260
261 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
262 if (kvm_check_extension(s, para_features[i].cap)) {
263 features |= (1 << para_features[i].feature);
264 }
265 }
266
267 return features;
268 }
269
270 static bool host_tsx_blacklisted(void)
271 {
272 int family, model, stepping;\
273 char vendor[CPUID_VENDOR_SZ + 1];
274
275 host_vendor_fms(vendor, &family, &model, &stepping);
276
277 /* Check if we are running on a Haswell host known to have broken TSX */
278 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
279 (family == 6) &&
280 ((model == 63 && stepping < 4) ||
281 model == 60 || model == 69 || model == 70);
282 }
283
284 /* Returns the value for a specific register on the cpuid entry
285 */
286 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
287 {
288 uint32_t ret = 0;
289 switch (reg) {
290 case R_EAX:
291 ret = entry->eax;
292 break;
293 case R_EBX:
294 ret = entry->ebx;
295 break;
296 case R_ECX:
297 ret = entry->ecx;
298 break;
299 case R_EDX:
300 ret = entry->edx;
301 break;
302 }
303 return ret;
304 }
305
306 /* Find matching entry for function/index on kvm_cpuid2 struct
307 */
308 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
309 uint32_t function,
310 uint32_t index)
311 {
312 int i;
313 for (i = 0; i < cpuid->nent; ++i) {
314 if (cpuid->entries[i].function == function &&
315 cpuid->entries[i].index == index) {
316 return &cpuid->entries[i];
317 }
318 }
319 /* not found: */
320 return NULL;
321 }
322
323 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
324 uint32_t index, int reg)
325 {
326 struct kvm_cpuid2 *cpuid;
327 uint32_t ret = 0;
328 uint32_t cpuid_1_edx;
329 bool found = false;
330
331 cpuid = get_supported_cpuid(s);
332
333 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
334 if (entry) {
335 found = true;
336 ret = cpuid_entry_get_reg(entry, reg);
337 }
338
339 /* Fixups for the data returned by KVM, below */
340
341 if (function == 1 && reg == R_EDX) {
342 /* KVM before 2.6.30 misreports the following features */
343 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
344 } else if (function == 1 && reg == R_ECX) {
345 /* We can set the hypervisor flag, even if KVM does not return it on
346 * GET_SUPPORTED_CPUID
347 */
348 ret |= CPUID_EXT_HYPERVISOR;
349 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
350 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
351 * and the irqchip is in the kernel.
352 */
353 if (kvm_irqchip_in_kernel() &&
354 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
355 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
356 }
357
358 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
359 * without the in-kernel irqchip
360 */
361 if (!kvm_irqchip_in_kernel()) {
362 ret &= ~CPUID_EXT_X2APIC;
363 }
364 } else if (function == 6 && reg == R_EAX) {
365 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
366 } else if (function == 7 && index == 0 && reg == R_EBX) {
367 if (host_tsx_blacklisted()) {
368 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
369 }
370 } else if (function == 0x80000001 && reg == R_EDX) {
371 /* On Intel, kvm returns cpuid according to the Intel spec,
372 * so add missing bits according to the AMD spec:
373 */
374 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
375 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
376 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
377 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
378 * be enabled without the in-kernel irqchip
379 */
380 if (!kvm_irqchip_in_kernel()) {
381 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
382 }
383 }
384
385 /* fallback for older kernels */
386 if ((function == KVM_CPUID_FEATURES) && !found) {
387 ret = get_para_features(s);
388 }
389
390 return ret;
391 }
392
393 typedef struct HWPoisonPage {
394 ram_addr_t ram_addr;
395 QLIST_ENTRY(HWPoisonPage) list;
396 } HWPoisonPage;
397
398 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
399 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
400
401 static void kvm_unpoison_all(void *param)
402 {
403 HWPoisonPage *page, *next_page;
404
405 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
406 QLIST_REMOVE(page, list);
407 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
408 g_free(page);
409 }
410 }
411
412 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
413 {
414 HWPoisonPage *page;
415
416 QLIST_FOREACH(page, &hwpoison_page_list, list) {
417 if (page->ram_addr == ram_addr) {
418 return;
419 }
420 }
421 page = g_new(HWPoisonPage, 1);
422 page->ram_addr = ram_addr;
423 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
424 }
425
426 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
427 int *max_banks)
428 {
429 int r;
430
431 r = kvm_check_extension(s, KVM_CAP_MCE);
432 if (r > 0) {
433 *max_banks = r;
434 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
435 }
436 return -ENOSYS;
437 }
438
439 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
440 {
441 CPUState *cs = CPU(cpu);
442 CPUX86State *env = &cpu->env;
443 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
444 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
445 uint64_t mcg_status = MCG_STATUS_MCIP;
446 int flags = 0;
447
448 if (code == BUS_MCEERR_AR) {
449 status |= MCI_STATUS_AR | 0x134;
450 mcg_status |= MCG_STATUS_EIPV;
451 } else {
452 status |= 0xc0;
453 mcg_status |= MCG_STATUS_RIPV;
454 }
455
456 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
457 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
458 * guest kernel back into env->mcg_ext_ctl.
459 */
460 cpu_synchronize_state(cs);
461 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
462 mcg_status |= MCG_STATUS_LMCE;
463 flags = 0;
464 }
465
466 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
467 (MCM_ADDR_PHYS << 6) | 0xc, flags);
468 }
469
470 static void hardware_memory_error(void)
471 {
472 fprintf(stderr, "Hardware memory error!\n");
473 exit(1);
474 }
475
476 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
477 {
478 X86CPU *cpu = X86_CPU(c);
479 CPUX86State *env = &cpu->env;
480 ram_addr_t ram_addr;
481 hwaddr paddr;
482
483 /* If we get an action required MCE, it has been injected by KVM
484 * while the VM was running. An action optional MCE instead should
485 * be coming from the main thread, which qemu_init_sigbus identifies
486 * as the "early kill" thread.
487 */
488 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
489
490 if ((env->mcg_cap & MCG_SER_P) && addr) {
491 ram_addr = qemu_ram_addr_from_host(addr);
492 if (ram_addr != RAM_ADDR_INVALID &&
493 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
494 kvm_hwpoison_page_add(ram_addr);
495 kvm_mce_inject(cpu, paddr, code);
496 return;
497 }
498
499 fprintf(stderr, "Hardware memory error for memory used by "
500 "QEMU itself instead of guest system!\n");
501 }
502
503 if (code == BUS_MCEERR_AR) {
504 hardware_memory_error();
505 }
506
507 /* Hope we are lucky for AO MCE */
508 }
509
510 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
511 {
512 CPUX86State *env = &cpu->env;
513
514 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
515 unsigned int bank, bank_num = env->mcg_cap & 0xff;
516 struct kvm_x86_mce mce;
517
518 env->exception_injected = -1;
519
520 /*
521 * There must be at least one bank in use if an MCE is pending.
522 * Find it and use its values for the event injection.
523 */
524 for (bank = 0; bank < bank_num; bank++) {
525 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
526 break;
527 }
528 }
529 assert(bank < bank_num);
530
531 mce.bank = bank;
532 mce.status = env->mce_banks[bank * 4 + 1];
533 mce.mcg_status = env->mcg_status;
534 mce.addr = env->mce_banks[bank * 4 + 2];
535 mce.misc = env->mce_banks[bank * 4 + 3];
536
537 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
538 }
539 return 0;
540 }
541
542 static void cpu_update_state(void *opaque, int running, RunState state)
543 {
544 CPUX86State *env = opaque;
545
546 if (running) {
547 env->tsc_valid = false;
548 }
549 }
550
551 unsigned long kvm_arch_vcpu_id(CPUState *cs)
552 {
553 X86CPU *cpu = X86_CPU(cs);
554 return cpu->apic_id;
555 }
556
557 #ifndef KVM_CPUID_SIGNATURE_NEXT
558 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
559 #endif
560
561 static bool hyperv_hypercall_available(X86CPU *cpu)
562 {
563 return cpu->hyperv_vapic ||
564 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
565 }
566
567 static bool hyperv_enabled(X86CPU *cpu)
568 {
569 CPUState *cs = CPU(cpu);
570 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
571 (hyperv_hypercall_available(cpu) ||
572 cpu->hyperv_time ||
573 cpu->hyperv_relaxed_timing ||
574 cpu->hyperv_crash ||
575 cpu->hyperv_reset ||
576 cpu->hyperv_vpindex ||
577 cpu->hyperv_runtime ||
578 cpu->hyperv_synic ||
579 cpu->hyperv_stimer);
580 }
581
582 static int kvm_arch_set_tsc_khz(CPUState *cs)
583 {
584 X86CPU *cpu = X86_CPU(cs);
585 CPUX86State *env = &cpu->env;
586 int r;
587
588 if (!env->tsc_khz) {
589 return 0;
590 }
591
592 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
593 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
594 -ENOTSUP;
595 if (r < 0) {
596 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
597 * TSC frequency doesn't match the one we want.
598 */
599 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
600 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
601 -ENOTSUP;
602 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
603 warn_report("TSC frequency mismatch between "
604 "VM (%" PRId64 " kHz) and host (%d kHz), "
605 "and TSC scaling unavailable",
606 env->tsc_khz, cur_freq);
607 return r;
608 }
609 }
610
611 return 0;
612 }
613
614 static int hyperv_handle_properties(CPUState *cs)
615 {
616 X86CPU *cpu = X86_CPU(cs);
617 CPUX86State *env = &cpu->env;
618
619 if (cpu->hyperv_time &&
620 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
621 cpu->hyperv_time = false;
622 }
623
624 if (cpu->hyperv_relaxed_timing) {
625 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
626 }
627 if (cpu->hyperv_vapic) {
628 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
629 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
630 }
631 if (cpu->hyperv_time) {
632 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
633 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
634 env->features[FEAT_HYPERV_EAX] |= 0x200;
635 }
636 if (cpu->hyperv_crash && has_msr_hv_crash) {
637 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
638 }
639 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
640 if (cpu->hyperv_reset && has_msr_hv_reset) {
641 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
642 }
643 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
644 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
645 }
646 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
647 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
648 }
649 if (cpu->hyperv_synic) {
650 int sint;
651
652 if (!has_msr_hv_synic ||
653 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
654 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
655 return -ENOSYS;
656 }
657
658 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
659 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
660 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
661 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
662 }
663 }
664 if (cpu->hyperv_stimer) {
665 if (!has_msr_hv_stimer) {
666 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
667 return -ENOSYS;
668 }
669 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
670 }
671 return 0;
672 }
673
674 static Error *invtsc_mig_blocker;
675
676 #define KVM_MAX_CPUID_ENTRIES 100
677
678 int kvm_arch_init_vcpu(CPUState *cs)
679 {
680 struct {
681 struct kvm_cpuid2 cpuid;
682 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
683 } QEMU_PACKED cpuid_data;
684 X86CPU *cpu = X86_CPU(cs);
685 CPUX86State *env = &cpu->env;
686 uint32_t limit, i, j, cpuid_i;
687 uint32_t unused;
688 struct kvm_cpuid_entry2 *c;
689 uint32_t signature[3];
690 int kvm_base = KVM_CPUID_SIGNATURE;
691 int r;
692 Error *local_err = NULL;
693
694 memset(&cpuid_data, 0, sizeof(cpuid_data));
695
696 cpuid_i = 0;
697
698 r = kvm_arch_set_tsc_khz(cs);
699 if (r < 0) {
700 goto fail;
701 }
702
703 /* vcpu's TSC frequency is either specified by user, or following
704 * the value used by KVM if the former is not present. In the
705 * latter case, we query it from KVM and record in env->tsc_khz,
706 * so that vcpu's TSC frequency can be migrated later via this field.
707 */
708 if (!env->tsc_khz) {
709 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
710 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
711 -ENOTSUP;
712 if (r > 0) {
713 env->tsc_khz = r;
714 }
715 }
716
717 /* Paravirtualization CPUIDs */
718 if (hyperv_enabled(cpu)) {
719 c = &cpuid_data.entries[cpuid_i++];
720 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
721 if (!cpu->hyperv_vendor_id) {
722 memcpy(signature, "Microsoft Hv", 12);
723 } else {
724 size_t len = strlen(cpu->hyperv_vendor_id);
725
726 if (len > 12) {
727 error_report("hv-vendor-id truncated to 12 characters");
728 len = 12;
729 }
730 memset(signature, 0, 12);
731 memcpy(signature, cpu->hyperv_vendor_id, len);
732 }
733 c->eax = HYPERV_CPUID_MIN;
734 c->ebx = signature[0];
735 c->ecx = signature[1];
736 c->edx = signature[2];
737
738 c = &cpuid_data.entries[cpuid_i++];
739 c->function = HYPERV_CPUID_INTERFACE;
740 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
741 c->eax = signature[0];
742 c->ebx = 0;
743 c->ecx = 0;
744 c->edx = 0;
745
746 c = &cpuid_data.entries[cpuid_i++];
747 c->function = HYPERV_CPUID_VERSION;
748 c->eax = 0x00001bbc;
749 c->ebx = 0x00060001;
750
751 c = &cpuid_data.entries[cpuid_i++];
752 c->function = HYPERV_CPUID_FEATURES;
753 r = hyperv_handle_properties(cs);
754 if (r) {
755 return r;
756 }
757 c->eax = env->features[FEAT_HYPERV_EAX];
758 c->ebx = env->features[FEAT_HYPERV_EBX];
759 c->edx = env->features[FEAT_HYPERV_EDX];
760
761 c = &cpuid_data.entries[cpuid_i++];
762 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
763 if (cpu->hyperv_relaxed_timing) {
764 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
765 }
766 if (cpu->hyperv_vapic) {
767 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
768 }
769 c->ebx = cpu->hyperv_spinlock_attempts;
770
771 c = &cpuid_data.entries[cpuid_i++];
772 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
773 c->eax = 0x40;
774 c->ebx = 0x40;
775
776 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
777 has_msr_hv_hypercall = true;
778 }
779
780 if (cpu->expose_kvm) {
781 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
782 c = &cpuid_data.entries[cpuid_i++];
783 c->function = KVM_CPUID_SIGNATURE | kvm_base;
784 c->eax = KVM_CPUID_FEATURES | kvm_base;
785 c->ebx = signature[0];
786 c->ecx = signature[1];
787 c->edx = signature[2];
788
789 c = &cpuid_data.entries[cpuid_i++];
790 c->function = KVM_CPUID_FEATURES | kvm_base;
791 c->eax = env->features[FEAT_KVM];
792 }
793
794 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
795
796 for (i = 0; i <= limit; i++) {
797 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
798 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
799 abort();
800 }
801 c = &cpuid_data.entries[cpuid_i++];
802
803 switch (i) {
804 case 2: {
805 /* Keep reading function 2 till all the input is received */
806 int times;
807
808 c->function = i;
809 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
810 KVM_CPUID_FLAG_STATE_READ_NEXT;
811 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
812 times = c->eax & 0xff;
813
814 for (j = 1; j < times; ++j) {
815 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
816 fprintf(stderr, "cpuid_data is full, no space for "
817 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
818 abort();
819 }
820 c = &cpuid_data.entries[cpuid_i++];
821 c->function = i;
822 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
823 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
824 }
825 break;
826 }
827 case 4:
828 case 0xb:
829 case 0xd:
830 for (j = 0; ; j++) {
831 if (i == 0xd && j == 64) {
832 break;
833 }
834 c->function = i;
835 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
836 c->index = j;
837 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
838
839 if (i == 4 && c->eax == 0) {
840 break;
841 }
842 if (i == 0xb && !(c->ecx & 0xff00)) {
843 break;
844 }
845 if (i == 0xd && c->eax == 0) {
846 continue;
847 }
848 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
849 fprintf(stderr, "cpuid_data is full, no space for "
850 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
851 abort();
852 }
853 c = &cpuid_data.entries[cpuid_i++];
854 }
855 break;
856 default:
857 c->function = i;
858 c->flags = 0;
859 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
860 break;
861 }
862 }
863
864 if (limit >= 0x0a) {
865 uint32_t ver;
866
867 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
868 if ((ver & 0xff) > 0) {
869 has_msr_architectural_pmu = true;
870 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
871
872 /* Shouldn't be more than 32, since that's the number of bits
873 * available in EBX to tell us _which_ counters are available.
874 * Play it safe.
875 */
876 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
877 num_architectural_pmu_counters = MAX_GP_COUNTERS;
878 }
879 }
880 }
881
882 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
883
884 for (i = 0x80000000; i <= limit; i++) {
885 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
886 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
887 abort();
888 }
889 c = &cpuid_data.entries[cpuid_i++];
890
891 c->function = i;
892 c->flags = 0;
893 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
894 }
895
896 /* Call Centaur's CPUID instructions they are supported. */
897 if (env->cpuid_xlevel2 > 0) {
898 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
899
900 for (i = 0xC0000000; i <= limit; i++) {
901 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
902 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
903 abort();
904 }
905 c = &cpuid_data.entries[cpuid_i++];
906
907 c->function = i;
908 c->flags = 0;
909 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
910 }
911 }
912
913 cpuid_data.cpuid.nent = cpuid_i;
914
915 if (((env->cpuid_version >> 8)&0xF) >= 6
916 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
917 (CPUID_MCE | CPUID_MCA)
918 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
919 uint64_t mcg_cap, unsupported_caps;
920 int banks;
921 int ret;
922
923 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
924 if (ret < 0) {
925 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
926 return ret;
927 }
928
929 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
930 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
931 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
932 return -ENOTSUP;
933 }
934
935 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
936 if (unsupported_caps) {
937 if (unsupported_caps & MCG_LMCE_P) {
938 error_report("kvm: LMCE not supported");
939 return -ENOTSUP;
940 }
941 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
942 unsupported_caps);
943 }
944
945 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
946 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
947 if (ret < 0) {
948 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
949 return ret;
950 }
951 }
952
953 qemu_add_vm_change_state_handler(cpu_update_state, env);
954
955 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
956 if (c) {
957 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
958 !!(c->ecx & CPUID_EXT_SMX);
959 }
960
961 if (env->mcg_cap & MCG_LMCE_P) {
962 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
963 }
964
965 if (!env->user_tsc_khz) {
966 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
967 invtsc_mig_blocker == NULL) {
968 /* for migration */
969 error_setg(&invtsc_mig_blocker,
970 "State blocked by non-migratable CPU device"
971 " (invtsc flag)");
972 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
973 if (local_err) {
974 error_report_err(local_err);
975 error_free(invtsc_mig_blocker);
976 goto fail;
977 }
978 /* for savevm */
979 vmstate_x86_cpu.unmigratable = 1;
980 }
981 }
982
983 if (cpu->vmware_cpuid_freq
984 /* Guests depend on 0x40000000 to detect this feature, so only expose
985 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
986 && cpu->expose_kvm
987 && kvm_base == KVM_CPUID_SIGNATURE
988 /* TSC clock must be stable and known for this feature. */
989 && ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
990 || env->user_tsc_khz != 0)
991 && env->tsc_khz != 0) {
992
993 c = &cpuid_data.entries[cpuid_i++];
994 c->function = KVM_CPUID_SIGNATURE | 0x10;
995 c->eax = env->tsc_khz;
996 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
997 * APIC_BUS_CYCLE_NS */
998 c->ebx = 1000000;
999 c->ecx = c->edx = 0;
1000
1001 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1002 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1003 }
1004
1005 cpuid_data.cpuid.nent = cpuid_i;
1006
1007 cpuid_data.cpuid.padding = 0;
1008 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1009 if (r) {
1010 goto fail;
1011 }
1012
1013 if (has_xsave) {
1014 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1015 }
1016 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1017
1018 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1019 has_msr_tsc_aux = false;
1020 }
1021
1022 return 0;
1023
1024 fail:
1025 migrate_del_blocker(invtsc_mig_blocker);
1026 return r;
1027 }
1028
1029 void kvm_arch_reset_vcpu(X86CPU *cpu)
1030 {
1031 CPUX86State *env = &cpu->env;
1032
1033 env->exception_injected = -1;
1034 env->interrupt_injected = -1;
1035 env->xcr0 = 1;
1036 if (kvm_irqchip_in_kernel()) {
1037 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1038 KVM_MP_STATE_UNINITIALIZED;
1039 } else {
1040 env->mp_state = KVM_MP_STATE_RUNNABLE;
1041 }
1042 }
1043
1044 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1045 {
1046 CPUX86State *env = &cpu->env;
1047
1048 /* APs get directly into wait-for-SIPI state. */
1049 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1050 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1051 }
1052 }
1053
1054 static int kvm_get_supported_msrs(KVMState *s)
1055 {
1056 static int kvm_supported_msrs;
1057 int ret = 0;
1058
1059 /* first time */
1060 if (kvm_supported_msrs == 0) {
1061 struct kvm_msr_list msr_list, *kvm_msr_list;
1062
1063 kvm_supported_msrs = -1;
1064
1065 /* Obtain MSR list from KVM. These are the MSRs that we must
1066 * save/restore */
1067 msr_list.nmsrs = 0;
1068 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1069 if (ret < 0 && ret != -E2BIG) {
1070 return ret;
1071 }
1072 /* Old kernel modules had a bug and could write beyond the provided
1073 memory. Allocate at least a safe amount of 1K. */
1074 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1075 msr_list.nmsrs *
1076 sizeof(msr_list.indices[0])));
1077
1078 kvm_msr_list->nmsrs = msr_list.nmsrs;
1079 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1080 if (ret >= 0) {
1081 int i;
1082
1083 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1084 switch (kvm_msr_list->indices[i]) {
1085 case MSR_STAR:
1086 has_msr_star = true;
1087 break;
1088 case MSR_VM_HSAVE_PA:
1089 has_msr_hsave_pa = true;
1090 break;
1091 case MSR_TSC_AUX:
1092 has_msr_tsc_aux = true;
1093 break;
1094 case MSR_TSC_ADJUST:
1095 has_msr_tsc_adjust = true;
1096 break;
1097 case MSR_IA32_TSCDEADLINE:
1098 has_msr_tsc_deadline = true;
1099 break;
1100 case MSR_IA32_SMBASE:
1101 has_msr_smbase = true;
1102 break;
1103 case MSR_IA32_MISC_ENABLE:
1104 has_msr_misc_enable = true;
1105 break;
1106 case MSR_IA32_BNDCFGS:
1107 has_msr_bndcfgs = true;
1108 break;
1109 case MSR_IA32_XSS:
1110 has_msr_xss = true;
1111 break;;
1112 case HV_X64_MSR_CRASH_CTL:
1113 has_msr_hv_crash = true;
1114 break;
1115 case HV_X64_MSR_RESET:
1116 has_msr_hv_reset = true;
1117 break;
1118 case HV_X64_MSR_VP_INDEX:
1119 has_msr_hv_vpindex = true;
1120 break;
1121 case HV_X64_MSR_VP_RUNTIME:
1122 has_msr_hv_runtime = true;
1123 break;
1124 case HV_X64_MSR_SCONTROL:
1125 has_msr_hv_synic = true;
1126 break;
1127 case HV_X64_MSR_STIMER0_CONFIG:
1128 has_msr_hv_stimer = true;
1129 break;
1130 }
1131 }
1132 }
1133
1134 g_free(kvm_msr_list);
1135 }
1136
1137 return ret;
1138 }
1139
1140 static Notifier smram_machine_done;
1141 static KVMMemoryListener smram_listener;
1142 static AddressSpace smram_address_space;
1143 static MemoryRegion smram_as_root;
1144 static MemoryRegion smram_as_mem;
1145
1146 static void register_smram_listener(Notifier *n, void *unused)
1147 {
1148 MemoryRegion *smram =
1149 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1150
1151 /* Outer container... */
1152 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1153 memory_region_set_enabled(&smram_as_root, true);
1154
1155 /* ... with two regions inside: normal system memory with low
1156 * priority, and...
1157 */
1158 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1159 get_system_memory(), 0, ~0ull);
1160 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1161 memory_region_set_enabled(&smram_as_mem, true);
1162
1163 if (smram) {
1164 /* ... SMRAM with higher priority */
1165 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1166 memory_region_set_enabled(smram, true);
1167 }
1168
1169 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1170 kvm_memory_listener_register(kvm_state, &smram_listener,
1171 &smram_address_space, 1);
1172 }
1173
1174 int kvm_arch_init(MachineState *ms, KVMState *s)
1175 {
1176 uint64_t identity_base = 0xfffbc000;
1177 uint64_t shadow_mem;
1178 int ret;
1179 struct utsname utsname;
1180
1181 #ifdef KVM_CAP_XSAVE
1182 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1183 #endif
1184
1185 #ifdef KVM_CAP_XCRS
1186 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1187 #endif
1188
1189 #ifdef KVM_CAP_PIT_STATE2
1190 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1191 #endif
1192
1193 ret = kvm_get_supported_msrs(s);
1194 if (ret < 0) {
1195 return ret;
1196 }
1197
1198 uname(&utsname);
1199 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1200
1201 /*
1202 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1203 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1204 * Since these must be part of guest physical memory, we need to allocate
1205 * them, both by setting their start addresses in the kernel and by
1206 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1207 *
1208 * Older KVM versions may not support setting the identity map base. In
1209 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1210 * size.
1211 */
1212 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1213 /* Allows up to 16M BIOSes. */
1214 identity_base = 0xfeffc000;
1215
1216 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1217 if (ret < 0) {
1218 return ret;
1219 }
1220 }
1221
1222 /* Set TSS base one page after EPT identity map. */
1223 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1224 if (ret < 0) {
1225 return ret;
1226 }
1227
1228 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1229 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1230 if (ret < 0) {
1231 fprintf(stderr, "e820_add_entry() table is full\n");
1232 return ret;
1233 }
1234 qemu_register_reset(kvm_unpoison_all, NULL);
1235
1236 shadow_mem = machine_kvm_shadow_mem(ms);
1237 if (shadow_mem != -1) {
1238 shadow_mem /= 4096;
1239 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1240 if (ret < 0) {
1241 return ret;
1242 }
1243 }
1244
1245 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1246 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1247 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1248 smram_machine_done.notify = register_smram_listener;
1249 qemu_add_machine_init_done_notifier(&smram_machine_done);
1250 }
1251 return 0;
1252 }
1253
1254 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1255 {
1256 lhs->selector = rhs->selector;
1257 lhs->base = rhs->base;
1258 lhs->limit = rhs->limit;
1259 lhs->type = 3;
1260 lhs->present = 1;
1261 lhs->dpl = 3;
1262 lhs->db = 0;
1263 lhs->s = 1;
1264 lhs->l = 0;
1265 lhs->g = 0;
1266 lhs->avl = 0;
1267 lhs->unusable = 0;
1268 }
1269
1270 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1271 {
1272 unsigned flags = rhs->flags;
1273 lhs->selector = rhs->selector;
1274 lhs->base = rhs->base;
1275 lhs->limit = rhs->limit;
1276 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1277 lhs->present = (flags & DESC_P_MASK) != 0;
1278 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1279 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1280 lhs->s = (flags & DESC_S_MASK) != 0;
1281 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1282 lhs->g = (flags & DESC_G_MASK) != 0;
1283 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1284 lhs->unusable = !lhs->present;
1285 lhs->padding = 0;
1286 }
1287
1288 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1289 {
1290 lhs->selector = rhs->selector;
1291 lhs->base = rhs->base;
1292 lhs->limit = rhs->limit;
1293 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1294 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1295 (rhs->dpl << DESC_DPL_SHIFT) |
1296 (rhs->db << DESC_B_SHIFT) |
1297 (rhs->s * DESC_S_MASK) |
1298 (rhs->l << DESC_L_SHIFT) |
1299 (rhs->g * DESC_G_MASK) |
1300 (rhs->avl * DESC_AVL_MASK);
1301 }
1302
1303 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1304 {
1305 if (set) {
1306 *kvm_reg = *qemu_reg;
1307 } else {
1308 *qemu_reg = *kvm_reg;
1309 }
1310 }
1311
1312 static int kvm_getput_regs(X86CPU *cpu, int set)
1313 {
1314 CPUX86State *env = &cpu->env;
1315 struct kvm_regs regs;
1316 int ret = 0;
1317
1318 if (!set) {
1319 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1320 if (ret < 0) {
1321 return ret;
1322 }
1323 }
1324
1325 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1326 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1327 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1328 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1329 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1330 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1331 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1332 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1333 #ifdef TARGET_X86_64
1334 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1335 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1336 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1337 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1338 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1339 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1340 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1341 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1342 #endif
1343
1344 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1345 kvm_getput_reg(&regs.rip, &env->eip, set);
1346
1347 if (set) {
1348 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1349 }
1350
1351 return ret;
1352 }
1353
1354 static int kvm_put_fpu(X86CPU *cpu)
1355 {
1356 CPUX86State *env = &cpu->env;
1357 struct kvm_fpu fpu;
1358 int i;
1359
1360 memset(&fpu, 0, sizeof fpu);
1361 fpu.fsw = env->fpus & ~(7 << 11);
1362 fpu.fsw |= (env->fpstt & 7) << 11;
1363 fpu.fcw = env->fpuc;
1364 fpu.last_opcode = env->fpop;
1365 fpu.last_ip = env->fpip;
1366 fpu.last_dp = env->fpdp;
1367 for (i = 0; i < 8; ++i) {
1368 fpu.ftwx |= (!env->fptags[i]) << i;
1369 }
1370 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1371 for (i = 0; i < CPU_NB_REGS; i++) {
1372 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1373 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1374 }
1375 fpu.mxcsr = env->mxcsr;
1376
1377 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1378 }
1379
1380 #define XSAVE_FCW_FSW 0
1381 #define XSAVE_FTW_FOP 1
1382 #define XSAVE_CWD_RIP 2
1383 #define XSAVE_CWD_RDP 4
1384 #define XSAVE_MXCSR 6
1385 #define XSAVE_ST_SPACE 8
1386 #define XSAVE_XMM_SPACE 40
1387 #define XSAVE_XSTATE_BV 128
1388 #define XSAVE_YMMH_SPACE 144
1389 #define XSAVE_BNDREGS 240
1390 #define XSAVE_BNDCSR 256
1391 #define XSAVE_OPMASK 272
1392 #define XSAVE_ZMM_Hi256 288
1393 #define XSAVE_Hi16_ZMM 416
1394 #define XSAVE_PKRU 672
1395
1396 #define XSAVE_BYTE_OFFSET(word_offset) \
1397 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1398
1399 #define ASSERT_OFFSET(word_offset, field) \
1400 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1401 offsetof(X86XSaveArea, field))
1402
1403 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1404 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1405 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1406 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1407 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1408 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1409 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1410 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1411 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1412 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1413 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1414 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1415 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1416 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1417 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1418
1419 static int kvm_put_xsave(X86CPU *cpu)
1420 {
1421 CPUX86State *env = &cpu->env;
1422 X86XSaveArea *xsave = env->kvm_xsave_buf;
1423
1424 if (!has_xsave) {
1425 return kvm_put_fpu(cpu);
1426 }
1427 x86_cpu_xsave_all_areas(cpu, xsave);
1428
1429 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1430 }
1431
1432 static int kvm_put_xcrs(X86CPU *cpu)
1433 {
1434 CPUX86State *env = &cpu->env;
1435 struct kvm_xcrs xcrs = {};
1436
1437 if (!has_xcrs) {
1438 return 0;
1439 }
1440
1441 xcrs.nr_xcrs = 1;
1442 xcrs.flags = 0;
1443 xcrs.xcrs[0].xcr = 0;
1444 xcrs.xcrs[0].value = env->xcr0;
1445 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1446 }
1447
1448 static int kvm_put_sregs(X86CPU *cpu)
1449 {
1450 CPUX86State *env = &cpu->env;
1451 struct kvm_sregs sregs;
1452
1453 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1454 if (env->interrupt_injected >= 0) {
1455 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1456 (uint64_t)1 << (env->interrupt_injected % 64);
1457 }
1458
1459 if ((env->eflags & VM_MASK)) {
1460 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1461 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1462 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1463 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1464 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1465 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1466 } else {
1467 set_seg(&sregs.cs, &env->segs[R_CS]);
1468 set_seg(&sregs.ds, &env->segs[R_DS]);
1469 set_seg(&sregs.es, &env->segs[R_ES]);
1470 set_seg(&sregs.fs, &env->segs[R_FS]);
1471 set_seg(&sregs.gs, &env->segs[R_GS]);
1472 set_seg(&sregs.ss, &env->segs[R_SS]);
1473 }
1474
1475 set_seg(&sregs.tr, &env->tr);
1476 set_seg(&sregs.ldt, &env->ldt);
1477
1478 sregs.idt.limit = env->idt.limit;
1479 sregs.idt.base = env->idt.base;
1480 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1481 sregs.gdt.limit = env->gdt.limit;
1482 sregs.gdt.base = env->gdt.base;
1483 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1484
1485 sregs.cr0 = env->cr[0];
1486 sregs.cr2 = env->cr[2];
1487 sregs.cr3 = env->cr[3];
1488 sregs.cr4 = env->cr[4];
1489
1490 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1491 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1492
1493 sregs.efer = env->efer;
1494
1495 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1496 }
1497
1498 static void kvm_msr_buf_reset(X86CPU *cpu)
1499 {
1500 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1501 }
1502
1503 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1504 {
1505 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1506 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1507 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1508
1509 assert((void *)(entry + 1) <= limit);
1510
1511 entry->index = index;
1512 entry->reserved = 0;
1513 entry->data = value;
1514 msrs->nmsrs++;
1515 }
1516
1517 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1518 {
1519 kvm_msr_buf_reset(cpu);
1520 kvm_msr_entry_add(cpu, index, value);
1521
1522 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1523 }
1524
1525 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1526 {
1527 int ret;
1528
1529 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1530 assert(ret == 1);
1531 }
1532
1533 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1534 {
1535 CPUX86State *env = &cpu->env;
1536 int ret;
1537
1538 if (!has_msr_tsc_deadline) {
1539 return 0;
1540 }
1541
1542 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1543 if (ret < 0) {
1544 return ret;
1545 }
1546
1547 assert(ret == 1);
1548 return 0;
1549 }
1550
1551 /*
1552 * Provide a separate write service for the feature control MSR in order to
1553 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1554 * before writing any other state because forcibly leaving nested mode
1555 * invalidates the VCPU state.
1556 */
1557 static int kvm_put_msr_feature_control(X86CPU *cpu)
1558 {
1559 int ret;
1560
1561 if (!has_msr_feature_control) {
1562 return 0;
1563 }
1564
1565 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1566 cpu->env.msr_ia32_feature_control);
1567 if (ret < 0) {
1568 return ret;
1569 }
1570
1571 assert(ret == 1);
1572 return 0;
1573 }
1574
1575 static int kvm_put_msrs(X86CPU *cpu, int level)
1576 {
1577 CPUX86State *env = &cpu->env;
1578 int i;
1579 int ret;
1580
1581 kvm_msr_buf_reset(cpu);
1582
1583 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1584 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1585 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1586 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1587 if (has_msr_star) {
1588 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1589 }
1590 if (has_msr_hsave_pa) {
1591 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1592 }
1593 if (has_msr_tsc_aux) {
1594 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1595 }
1596 if (has_msr_tsc_adjust) {
1597 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1598 }
1599 if (has_msr_misc_enable) {
1600 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1601 env->msr_ia32_misc_enable);
1602 }
1603 if (has_msr_smbase) {
1604 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1605 }
1606 if (has_msr_bndcfgs) {
1607 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1608 }
1609 if (has_msr_xss) {
1610 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1611 }
1612 #ifdef TARGET_X86_64
1613 if (lm_capable_kernel) {
1614 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1615 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1616 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1617 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1618 }
1619 #endif
1620 /*
1621 * The following MSRs have side effects on the guest or are too heavy
1622 * for normal writeback. Limit them to reset or full state updates.
1623 */
1624 if (level >= KVM_PUT_RESET_STATE) {
1625 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1626 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1627 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1628 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1629 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1630 }
1631 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1632 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1633 }
1634 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1635 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1636 }
1637 if (has_msr_architectural_pmu) {
1638 /* Stop the counter. */
1639 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1640 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1641
1642 /* Set the counter values. */
1643 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1644 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1645 env->msr_fixed_counters[i]);
1646 }
1647 for (i = 0; i < num_architectural_pmu_counters; i++) {
1648 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1649 env->msr_gp_counters[i]);
1650 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1651 env->msr_gp_evtsel[i]);
1652 }
1653 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1654 env->msr_global_status);
1655 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1656 env->msr_global_ovf_ctrl);
1657
1658 /* Now start the PMU. */
1659 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1660 env->msr_fixed_ctr_ctrl);
1661 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1662 env->msr_global_ctrl);
1663 }
1664 if (has_msr_hv_hypercall) {
1665 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1666 env->msr_hv_guest_os_id);
1667 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1668 env->msr_hv_hypercall);
1669 }
1670 if (cpu->hyperv_vapic) {
1671 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1672 env->msr_hv_vapic);
1673 }
1674 if (cpu->hyperv_time) {
1675 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1676 }
1677 if (has_msr_hv_crash) {
1678 int j;
1679
1680 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1681 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1682 env->msr_hv_crash_params[j]);
1683
1684 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1685 HV_X64_MSR_CRASH_CTL_NOTIFY);
1686 }
1687 if (has_msr_hv_runtime) {
1688 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1689 }
1690 if (cpu->hyperv_synic) {
1691 int j;
1692
1693 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1694 env->msr_hv_synic_control);
1695 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1696 env->msr_hv_synic_version);
1697 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1698 env->msr_hv_synic_evt_page);
1699 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1700 env->msr_hv_synic_msg_page);
1701
1702 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1703 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1704 env->msr_hv_synic_sint[j]);
1705 }
1706 }
1707 if (has_msr_hv_stimer) {
1708 int j;
1709
1710 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1712 env->msr_hv_stimer_config[j]);
1713 }
1714
1715 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1716 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1717 env->msr_hv_stimer_count[j]);
1718 }
1719 }
1720 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1721 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1722
1723 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1724 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1725 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1726 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1727 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1728 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1729 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1730 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1731 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1732 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1733 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1734 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1735 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1736 /* The CPU GPs if we write to a bit above the physical limit of
1737 * the host CPU (and KVM emulates that)
1738 */
1739 uint64_t mask = env->mtrr_var[i].mask;
1740 mask &= phys_mask;
1741
1742 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1743 env->mtrr_var[i].base);
1744 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1745 }
1746 }
1747
1748 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1749 * kvm_put_msr_feature_control. */
1750 }
1751 if (env->mcg_cap) {
1752 int i;
1753
1754 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1755 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1756 if (has_msr_mcg_ext_ctl) {
1757 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1758 }
1759 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1760 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1761 }
1762 }
1763
1764 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1765 if (ret < 0) {
1766 return ret;
1767 }
1768
1769 if (ret < cpu->kvm_msr_buf->nmsrs) {
1770 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1771 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1772 (uint32_t)e->index, (uint64_t)e->data);
1773 }
1774
1775 assert(ret == cpu->kvm_msr_buf->nmsrs);
1776 return 0;
1777 }
1778
1779
1780 static int kvm_get_fpu(X86CPU *cpu)
1781 {
1782 CPUX86State *env = &cpu->env;
1783 struct kvm_fpu fpu;
1784 int i, ret;
1785
1786 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1787 if (ret < 0) {
1788 return ret;
1789 }
1790
1791 env->fpstt = (fpu.fsw >> 11) & 7;
1792 env->fpus = fpu.fsw;
1793 env->fpuc = fpu.fcw;
1794 env->fpop = fpu.last_opcode;
1795 env->fpip = fpu.last_ip;
1796 env->fpdp = fpu.last_dp;
1797 for (i = 0; i < 8; ++i) {
1798 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1799 }
1800 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1801 for (i = 0; i < CPU_NB_REGS; i++) {
1802 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1803 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1804 }
1805 env->mxcsr = fpu.mxcsr;
1806
1807 return 0;
1808 }
1809
1810 static int kvm_get_xsave(X86CPU *cpu)
1811 {
1812 CPUX86State *env = &cpu->env;
1813 X86XSaveArea *xsave = env->kvm_xsave_buf;
1814 int ret;
1815
1816 if (!has_xsave) {
1817 return kvm_get_fpu(cpu);
1818 }
1819
1820 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1821 if (ret < 0) {
1822 return ret;
1823 }
1824 x86_cpu_xrstor_all_areas(cpu, xsave);
1825
1826 return 0;
1827 }
1828
1829 static int kvm_get_xcrs(X86CPU *cpu)
1830 {
1831 CPUX86State *env = &cpu->env;
1832 int i, ret;
1833 struct kvm_xcrs xcrs;
1834
1835 if (!has_xcrs) {
1836 return 0;
1837 }
1838
1839 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1840 if (ret < 0) {
1841 return ret;
1842 }
1843
1844 for (i = 0; i < xcrs.nr_xcrs; i++) {
1845 /* Only support xcr0 now */
1846 if (xcrs.xcrs[i].xcr == 0) {
1847 env->xcr0 = xcrs.xcrs[i].value;
1848 break;
1849 }
1850 }
1851 return 0;
1852 }
1853
1854 static int kvm_get_sregs(X86CPU *cpu)
1855 {
1856 CPUX86State *env = &cpu->env;
1857 struct kvm_sregs sregs;
1858 uint32_t hflags;
1859 int bit, i, ret;
1860
1861 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1862 if (ret < 0) {
1863 return ret;
1864 }
1865
1866 /* There can only be one pending IRQ set in the bitmap at a time, so try
1867 to find it and save its number instead (-1 for none). */
1868 env->interrupt_injected = -1;
1869 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1870 if (sregs.interrupt_bitmap[i]) {
1871 bit = ctz64(sregs.interrupt_bitmap[i]);
1872 env->interrupt_injected = i * 64 + bit;
1873 break;
1874 }
1875 }
1876
1877 get_seg(&env->segs[R_CS], &sregs.cs);
1878 get_seg(&env->segs[R_DS], &sregs.ds);
1879 get_seg(&env->segs[R_ES], &sregs.es);
1880 get_seg(&env->segs[R_FS], &sregs.fs);
1881 get_seg(&env->segs[R_GS], &sregs.gs);
1882 get_seg(&env->segs[R_SS], &sregs.ss);
1883
1884 get_seg(&env->tr, &sregs.tr);
1885 get_seg(&env->ldt, &sregs.ldt);
1886
1887 env->idt.limit = sregs.idt.limit;
1888 env->idt.base = sregs.idt.base;
1889 env->gdt.limit = sregs.gdt.limit;
1890 env->gdt.base = sregs.gdt.base;
1891
1892 env->cr[0] = sregs.cr0;
1893 env->cr[2] = sregs.cr2;
1894 env->cr[3] = sregs.cr3;
1895 env->cr[4] = sregs.cr4;
1896
1897 env->efer = sregs.efer;
1898
1899 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1900
1901 #define HFLAG_COPY_MASK \
1902 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1903 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1904 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1905 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1906
1907 hflags = env->hflags & HFLAG_COPY_MASK;
1908 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1909 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1910 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1911 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1912 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1913
1914 if (env->cr[4] & CR4_OSFXSR_MASK) {
1915 hflags |= HF_OSFXSR_MASK;
1916 }
1917
1918 if (env->efer & MSR_EFER_LMA) {
1919 hflags |= HF_LMA_MASK;
1920 }
1921
1922 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1923 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1924 } else {
1925 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1926 (DESC_B_SHIFT - HF_CS32_SHIFT);
1927 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1928 (DESC_B_SHIFT - HF_SS32_SHIFT);
1929 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1930 !(hflags & HF_CS32_MASK)) {
1931 hflags |= HF_ADDSEG_MASK;
1932 } else {
1933 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1934 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1935 }
1936 }
1937 env->hflags = hflags;
1938
1939 return 0;
1940 }
1941
1942 static int kvm_get_msrs(X86CPU *cpu)
1943 {
1944 CPUX86State *env = &cpu->env;
1945 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1946 int ret, i;
1947 uint64_t mtrr_top_bits;
1948
1949 kvm_msr_buf_reset(cpu);
1950
1951 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1952 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1953 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1954 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1955 if (has_msr_star) {
1956 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1957 }
1958 if (has_msr_hsave_pa) {
1959 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1960 }
1961 if (has_msr_tsc_aux) {
1962 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1963 }
1964 if (has_msr_tsc_adjust) {
1965 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1966 }
1967 if (has_msr_tsc_deadline) {
1968 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1969 }
1970 if (has_msr_misc_enable) {
1971 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1972 }
1973 if (has_msr_smbase) {
1974 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
1975 }
1976 if (has_msr_feature_control) {
1977 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
1978 }
1979 if (has_msr_bndcfgs) {
1980 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
1981 }
1982 if (has_msr_xss) {
1983 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
1984 }
1985
1986
1987 if (!env->tsc_valid) {
1988 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1989 env->tsc_valid = !runstate_is_running();
1990 }
1991
1992 #ifdef TARGET_X86_64
1993 if (lm_capable_kernel) {
1994 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
1995 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
1996 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
1997 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
1998 }
1999 #endif
2000 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2001 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2002 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2003 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2004 }
2005 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2006 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2007 }
2008 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2009 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2010 }
2011 if (has_msr_architectural_pmu) {
2012 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2013 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2014 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2015 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2016 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2017 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2018 }
2019 for (i = 0; i < num_architectural_pmu_counters; i++) {
2020 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2021 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2022 }
2023 }
2024
2025 if (env->mcg_cap) {
2026 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2027 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2028 if (has_msr_mcg_ext_ctl) {
2029 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2030 }
2031 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2032 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2033 }
2034 }
2035
2036 if (has_msr_hv_hypercall) {
2037 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2038 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2039 }
2040 if (cpu->hyperv_vapic) {
2041 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2042 }
2043 if (cpu->hyperv_time) {
2044 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2045 }
2046 if (has_msr_hv_crash) {
2047 int j;
2048
2049 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2050 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2051 }
2052 }
2053 if (has_msr_hv_runtime) {
2054 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2055 }
2056 if (cpu->hyperv_synic) {
2057 uint32_t msr;
2058
2059 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2060 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2061 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2062 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2063 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2064 kvm_msr_entry_add(cpu, msr, 0);
2065 }
2066 }
2067 if (has_msr_hv_stimer) {
2068 uint32_t msr;
2069
2070 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2071 msr++) {
2072 kvm_msr_entry_add(cpu, msr, 0);
2073 }
2074 }
2075 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2076 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2077 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2078 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2079 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2080 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2081 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2082 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2083 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2084 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2085 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2086 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2087 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2088 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2089 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2090 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2091 }
2092 }
2093
2094 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2095 if (ret < 0) {
2096 return ret;
2097 }
2098
2099 if (ret < cpu->kvm_msr_buf->nmsrs) {
2100 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2101 error_report("error: failed to get MSR 0x%" PRIx32,
2102 (uint32_t)e->index);
2103 }
2104
2105 assert(ret == cpu->kvm_msr_buf->nmsrs);
2106 /*
2107 * MTRR masks: Each mask consists of 5 parts
2108 * a 10..0: must be zero
2109 * b 11 : valid bit
2110 * c n-1.12: actual mask bits
2111 * d 51..n: reserved must be zero
2112 * e 63.52: reserved must be zero
2113 *
2114 * 'n' is the number of physical bits supported by the CPU and is
2115 * apparently always <= 52. We know our 'n' but don't know what
2116 * the destinations 'n' is; it might be smaller, in which case
2117 * it masks (c) on loading. It might be larger, in which case
2118 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2119 * we're migrating to.
2120 */
2121
2122 if (cpu->fill_mtrr_mask) {
2123 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2124 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2125 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2126 } else {
2127 mtrr_top_bits = 0;
2128 }
2129
2130 for (i = 0; i < ret; i++) {
2131 uint32_t index = msrs[i].index;
2132 switch (index) {
2133 case MSR_IA32_SYSENTER_CS:
2134 env->sysenter_cs = msrs[i].data;
2135 break;
2136 case MSR_IA32_SYSENTER_ESP:
2137 env->sysenter_esp = msrs[i].data;
2138 break;
2139 case MSR_IA32_SYSENTER_EIP:
2140 env->sysenter_eip = msrs[i].data;
2141 break;
2142 case MSR_PAT:
2143 env->pat = msrs[i].data;
2144 break;
2145 case MSR_STAR:
2146 env->star = msrs[i].data;
2147 break;
2148 #ifdef TARGET_X86_64
2149 case MSR_CSTAR:
2150 env->cstar = msrs[i].data;
2151 break;
2152 case MSR_KERNELGSBASE:
2153 env->kernelgsbase = msrs[i].data;
2154 break;
2155 case MSR_FMASK:
2156 env->fmask = msrs[i].data;
2157 break;
2158 case MSR_LSTAR:
2159 env->lstar = msrs[i].data;
2160 break;
2161 #endif
2162 case MSR_IA32_TSC:
2163 env->tsc = msrs[i].data;
2164 break;
2165 case MSR_TSC_AUX:
2166 env->tsc_aux = msrs[i].data;
2167 break;
2168 case MSR_TSC_ADJUST:
2169 env->tsc_adjust = msrs[i].data;
2170 break;
2171 case MSR_IA32_TSCDEADLINE:
2172 env->tsc_deadline = msrs[i].data;
2173 break;
2174 case MSR_VM_HSAVE_PA:
2175 env->vm_hsave = msrs[i].data;
2176 break;
2177 case MSR_KVM_SYSTEM_TIME:
2178 env->system_time_msr = msrs[i].data;
2179 break;
2180 case MSR_KVM_WALL_CLOCK:
2181 env->wall_clock_msr = msrs[i].data;
2182 break;
2183 case MSR_MCG_STATUS:
2184 env->mcg_status = msrs[i].data;
2185 break;
2186 case MSR_MCG_CTL:
2187 env->mcg_ctl = msrs[i].data;
2188 break;
2189 case MSR_MCG_EXT_CTL:
2190 env->mcg_ext_ctl = msrs[i].data;
2191 break;
2192 case MSR_IA32_MISC_ENABLE:
2193 env->msr_ia32_misc_enable = msrs[i].data;
2194 break;
2195 case MSR_IA32_SMBASE:
2196 env->smbase = msrs[i].data;
2197 break;
2198 case MSR_IA32_FEATURE_CONTROL:
2199 env->msr_ia32_feature_control = msrs[i].data;
2200 break;
2201 case MSR_IA32_BNDCFGS:
2202 env->msr_bndcfgs = msrs[i].data;
2203 break;
2204 case MSR_IA32_XSS:
2205 env->xss = msrs[i].data;
2206 break;
2207 default:
2208 if (msrs[i].index >= MSR_MC0_CTL &&
2209 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2210 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2211 }
2212 break;
2213 case MSR_KVM_ASYNC_PF_EN:
2214 env->async_pf_en_msr = msrs[i].data;
2215 break;
2216 case MSR_KVM_PV_EOI_EN:
2217 env->pv_eoi_en_msr = msrs[i].data;
2218 break;
2219 case MSR_KVM_STEAL_TIME:
2220 env->steal_time_msr = msrs[i].data;
2221 break;
2222 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2223 env->msr_fixed_ctr_ctrl = msrs[i].data;
2224 break;
2225 case MSR_CORE_PERF_GLOBAL_CTRL:
2226 env->msr_global_ctrl = msrs[i].data;
2227 break;
2228 case MSR_CORE_PERF_GLOBAL_STATUS:
2229 env->msr_global_status = msrs[i].data;
2230 break;
2231 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2232 env->msr_global_ovf_ctrl = msrs[i].data;
2233 break;
2234 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2235 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2236 break;
2237 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2238 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2239 break;
2240 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2241 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2242 break;
2243 case HV_X64_MSR_HYPERCALL:
2244 env->msr_hv_hypercall = msrs[i].data;
2245 break;
2246 case HV_X64_MSR_GUEST_OS_ID:
2247 env->msr_hv_guest_os_id = msrs[i].data;
2248 break;
2249 case HV_X64_MSR_APIC_ASSIST_PAGE:
2250 env->msr_hv_vapic = msrs[i].data;
2251 break;
2252 case HV_X64_MSR_REFERENCE_TSC:
2253 env->msr_hv_tsc = msrs[i].data;
2254 break;
2255 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2256 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2257 break;
2258 case HV_X64_MSR_VP_RUNTIME:
2259 env->msr_hv_runtime = msrs[i].data;
2260 break;
2261 case HV_X64_MSR_SCONTROL:
2262 env->msr_hv_synic_control = msrs[i].data;
2263 break;
2264 case HV_X64_MSR_SVERSION:
2265 env->msr_hv_synic_version = msrs[i].data;
2266 break;
2267 case HV_X64_MSR_SIEFP:
2268 env->msr_hv_synic_evt_page = msrs[i].data;
2269 break;
2270 case HV_X64_MSR_SIMP:
2271 env->msr_hv_synic_msg_page = msrs[i].data;
2272 break;
2273 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2274 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2275 break;
2276 case HV_X64_MSR_STIMER0_CONFIG:
2277 case HV_X64_MSR_STIMER1_CONFIG:
2278 case HV_X64_MSR_STIMER2_CONFIG:
2279 case HV_X64_MSR_STIMER3_CONFIG:
2280 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2281 msrs[i].data;
2282 break;
2283 case HV_X64_MSR_STIMER0_COUNT:
2284 case HV_X64_MSR_STIMER1_COUNT:
2285 case HV_X64_MSR_STIMER2_COUNT:
2286 case HV_X64_MSR_STIMER3_COUNT:
2287 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2288 msrs[i].data;
2289 break;
2290 case MSR_MTRRdefType:
2291 env->mtrr_deftype = msrs[i].data;
2292 break;
2293 case MSR_MTRRfix64K_00000:
2294 env->mtrr_fixed[0] = msrs[i].data;
2295 break;
2296 case MSR_MTRRfix16K_80000:
2297 env->mtrr_fixed[1] = msrs[i].data;
2298 break;
2299 case MSR_MTRRfix16K_A0000:
2300 env->mtrr_fixed[2] = msrs[i].data;
2301 break;
2302 case MSR_MTRRfix4K_C0000:
2303 env->mtrr_fixed[3] = msrs[i].data;
2304 break;
2305 case MSR_MTRRfix4K_C8000:
2306 env->mtrr_fixed[4] = msrs[i].data;
2307 break;
2308 case MSR_MTRRfix4K_D0000:
2309 env->mtrr_fixed[5] = msrs[i].data;
2310 break;
2311 case MSR_MTRRfix4K_D8000:
2312 env->mtrr_fixed[6] = msrs[i].data;
2313 break;
2314 case MSR_MTRRfix4K_E0000:
2315 env->mtrr_fixed[7] = msrs[i].data;
2316 break;
2317 case MSR_MTRRfix4K_E8000:
2318 env->mtrr_fixed[8] = msrs[i].data;
2319 break;
2320 case MSR_MTRRfix4K_F0000:
2321 env->mtrr_fixed[9] = msrs[i].data;
2322 break;
2323 case MSR_MTRRfix4K_F8000:
2324 env->mtrr_fixed[10] = msrs[i].data;
2325 break;
2326 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2327 if (index & 1) {
2328 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2329 mtrr_top_bits;
2330 } else {
2331 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2332 }
2333 break;
2334 }
2335 }
2336
2337 return 0;
2338 }
2339
2340 static int kvm_put_mp_state(X86CPU *cpu)
2341 {
2342 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2343
2344 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2345 }
2346
2347 static int kvm_get_mp_state(X86CPU *cpu)
2348 {
2349 CPUState *cs = CPU(cpu);
2350 CPUX86State *env = &cpu->env;
2351 struct kvm_mp_state mp_state;
2352 int ret;
2353
2354 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2355 if (ret < 0) {
2356 return ret;
2357 }
2358 env->mp_state = mp_state.mp_state;
2359 if (kvm_irqchip_in_kernel()) {
2360 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2361 }
2362 return 0;
2363 }
2364
2365 static int kvm_get_apic(X86CPU *cpu)
2366 {
2367 DeviceState *apic = cpu->apic_state;
2368 struct kvm_lapic_state kapic;
2369 int ret;
2370
2371 if (apic && kvm_irqchip_in_kernel()) {
2372 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2373 if (ret < 0) {
2374 return ret;
2375 }
2376
2377 kvm_get_apic_state(apic, &kapic);
2378 }
2379 return 0;
2380 }
2381
2382 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2383 {
2384 CPUState *cs = CPU(cpu);
2385 CPUX86State *env = &cpu->env;
2386 struct kvm_vcpu_events events = {};
2387
2388 if (!kvm_has_vcpu_events()) {
2389 return 0;
2390 }
2391
2392 events.exception.injected = (env->exception_injected >= 0);
2393 events.exception.nr = env->exception_injected;
2394 events.exception.has_error_code = env->has_error_code;
2395 events.exception.error_code = env->error_code;
2396 events.exception.pad = 0;
2397
2398 events.interrupt.injected = (env->interrupt_injected >= 0);
2399 events.interrupt.nr = env->interrupt_injected;
2400 events.interrupt.soft = env->soft_interrupt;
2401
2402 events.nmi.injected = env->nmi_injected;
2403 events.nmi.pending = env->nmi_pending;
2404 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2405 events.nmi.pad = 0;
2406
2407 events.sipi_vector = env->sipi_vector;
2408 events.flags = 0;
2409
2410 if (has_msr_smbase) {
2411 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2412 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2413 if (kvm_irqchip_in_kernel()) {
2414 /* As soon as these are moved to the kernel, remove them
2415 * from cs->interrupt_request.
2416 */
2417 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2418 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2419 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2420 } else {
2421 /* Keep these in cs->interrupt_request. */
2422 events.smi.pending = 0;
2423 events.smi.latched_init = 0;
2424 }
2425 /* Stop SMI delivery on old machine types to avoid a reboot
2426 * on an inward migration of an old VM.
2427 */
2428 if (!cpu->kvm_no_smi_migration) {
2429 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2430 }
2431 }
2432
2433 if (level >= KVM_PUT_RESET_STATE) {
2434 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2435 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2436 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2437 }
2438 }
2439
2440 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2441 }
2442
2443 static int kvm_get_vcpu_events(X86CPU *cpu)
2444 {
2445 CPUX86State *env = &cpu->env;
2446 struct kvm_vcpu_events events;
2447 int ret;
2448
2449 if (!kvm_has_vcpu_events()) {
2450 return 0;
2451 }
2452
2453 memset(&events, 0, sizeof(events));
2454 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2455 if (ret < 0) {
2456 return ret;
2457 }
2458 env->exception_injected =
2459 events.exception.injected ? events.exception.nr : -1;
2460 env->has_error_code = events.exception.has_error_code;
2461 env->error_code = events.exception.error_code;
2462
2463 env->interrupt_injected =
2464 events.interrupt.injected ? events.interrupt.nr : -1;
2465 env->soft_interrupt = events.interrupt.soft;
2466
2467 env->nmi_injected = events.nmi.injected;
2468 env->nmi_pending = events.nmi.pending;
2469 if (events.nmi.masked) {
2470 env->hflags2 |= HF2_NMI_MASK;
2471 } else {
2472 env->hflags2 &= ~HF2_NMI_MASK;
2473 }
2474
2475 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2476 if (events.smi.smm) {
2477 env->hflags |= HF_SMM_MASK;
2478 } else {
2479 env->hflags &= ~HF_SMM_MASK;
2480 }
2481 if (events.smi.pending) {
2482 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2483 } else {
2484 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2485 }
2486 if (events.smi.smm_inside_nmi) {
2487 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2488 } else {
2489 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2490 }
2491 if (events.smi.latched_init) {
2492 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2493 } else {
2494 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2495 }
2496 }
2497
2498 env->sipi_vector = events.sipi_vector;
2499
2500 return 0;
2501 }
2502
2503 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2504 {
2505 CPUState *cs = CPU(cpu);
2506 CPUX86State *env = &cpu->env;
2507 int ret = 0;
2508 unsigned long reinject_trap = 0;
2509
2510 if (!kvm_has_vcpu_events()) {
2511 if (env->exception_injected == 1) {
2512 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2513 } else if (env->exception_injected == 3) {
2514 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2515 }
2516 env->exception_injected = -1;
2517 }
2518
2519 /*
2520 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2521 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2522 * by updating the debug state once again if single-stepping is on.
2523 * Another reason to call kvm_update_guest_debug here is a pending debug
2524 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2525 * reinject them via SET_GUEST_DEBUG.
2526 */
2527 if (reinject_trap ||
2528 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2529 ret = kvm_update_guest_debug(cs, reinject_trap);
2530 }
2531 return ret;
2532 }
2533
2534 static int kvm_put_debugregs(X86CPU *cpu)
2535 {
2536 CPUX86State *env = &cpu->env;
2537 struct kvm_debugregs dbgregs;
2538 int i;
2539
2540 if (!kvm_has_debugregs()) {
2541 return 0;
2542 }
2543
2544 for (i = 0; i < 4; i++) {
2545 dbgregs.db[i] = env->dr[i];
2546 }
2547 dbgregs.dr6 = env->dr[6];
2548 dbgregs.dr7 = env->dr[7];
2549 dbgregs.flags = 0;
2550
2551 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2552 }
2553
2554 static int kvm_get_debugregs(X86CPU *cpu)
2555 {
2556 CPUX86State *env = &cpu->env;
2557 struct kvm_debugregs dbgregs;
2558 int i, ret;
2559
2560 if (!kvm_has_debugregs()) {
2561 return 0;
2562 }
2563
2564 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2565 if (ret < 0) {
2566 return ret;
2567 }
2568 for (i = 0; i < 4; i++) {
2569 env->dr[i] = dbgregs.db[i];
2570 }
2571 env->dr[4] = env->dr[6] = dbgregs.dr6;
2572 env->dr[5] = env->dr[7] = dbgregs.dr7;
2573
2574 return 0;
2575 }
2576
2577 int kvm_arch_put_registers(CPUState *cpu, int level)
2578 {
2579 X86CPU *x86_cpu = X86_CPU(cpu);
2580 int ret;
2581
2582 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2583
2584 if (level >= KVM_PUT_RESET_STATE) {
2585 ret = kvm_put_msr_feature_control(x86_cpu);
2586 if (ret < 0) {
2587 return ret;
2588 }
2589 }
2590
2591 if (level == KVM_PUT_FULL_STATE) {
2592 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2593 * because TSC frequency mismatch shouldn't abort migration,
2594 * unless the user explicitly asked for a more strict TSC
2595 * setting (e.g. using an explicit "tsc-freq" option).
2596 */
2597 kvm_arch_set_tsc_khz(cpu);
2598 }
2599
2600 ret = kvm_getput_regs(x86_cpu, 1);
2601 if (ret < 0) {
2602 return ret;
2603 }
2604 ret = kvm_put_xsave(x86_cpu);
2605 if (ret < 0) {
2606 return ret;
2607 }
2608 ret = kvm_put_xcrs(x86_cpu);
2609 if (ret < 0) {
2610 return ret;
2611 }
2612 ret = kvm_put_sregs(x86_cpu);
2613 if (ret < 0) {
2614 return ret;
2615 }
2616 /* must be before kvm_put_msrs */
2617 ret = kvm_inject_mce_oldstyle(x86_cpu);
2618 if (ret < 0) {
2619 return ret;
2620 }
2621 ret = kvm_put_msrs(x86_cpu, level);
2622 if (ret < 0) {
2623 return ret;
2624 }
2625 ret = kvm_put_vcpu_events(x86_cpu, level);
2626 if (ret < 0) {
2627 return ret;
2628 }
2629 if (level >= KVM_PUT_RESET_STATE) {
2630 ret = kvm_put_mp_state(x86_cpu);
2631 if (ret < 0) {
2632 return ret;
2633 }
2634 }
2635
2636 ret = kvm_put_tscdeadline_msr(x86_cpu);
2637 if (ret < 0) {
2638 return ret;
2639 }
2640 ret = kvm_put_debugregs(x86_cpu);
2641 if (ret < 0) {
2642 return ret;
2643 }
2644 /* must be last */
2645 ret = kvm_guest_debug_workarounds(x86_cpu);
2646 if (ret < 0) {
2647 return ret;
2648 }
2649 return 0;
2650 }
2651
2652 int kvm_arch_get_registers(CPUState *cs)
2653 {
2654 X86CPU *cpu = X86_CPU(cs);
2655 int ret;
2656
2657 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2658
2659 ret = kvm_get_vcpu_events(cpu);
2660 if (ret < 0) {
2661 goto out;
2662 }
2663 /*
2664 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2665 * KVM_GET_REGS and KVM_GET_SREGS.
2666 */
2667 ret = kvm_get_mp_state(cpu);
2668 if (ret < 0) {
2669 goto out;
2670 }
2671 ret = kvm_getput_regs(cpu, 0);
2672 if (ret < 0) {
2673 goto out;
2674 }
2675 ret = kvm_get_xsave(cpu);
2676 if (ret < 0) {
2677 goto out;
2678 }
2679 ret = kvm_get_xcrs(cpu);
2680 if (ret < 0) {
2681 goto out;
2682 }
2683 ret = kvm_get_sregs(cpu);
2684 if (ret < 0) {
2685 goto out;
2686 }
2687 ret = kvm_get_msrs(cpu);
2688 if (ret < 0) {
2689 goto out;
2690 }
2691 ret = kvm_get_apic(cpu);
2692 if (ret < 0) {
2693 goto out;
2694 }
2695 ret = kvm_get_debugregs(cpu);
2696 if (ret < 0) {
2697 goto out;
2698 }
2699 ret = 0;
2700 out:
2701 cpu_sync_bndcs_hflags(&cpu->env);
2702 return ret;
2703 }
2704
2705 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2706 {
2707 X86CPU *x86_cpu = X86_CPU(cpu);
2708 CPUX86State *env = &x86_cpu->env;
2709 int ret;
2710
2711 /* Inject NMI */
2712 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2713 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2714 qemu_mutex_lock_iothread();
2715 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2716 qemu_mutex_unlock_iothread();
2717 DPRINTF("injected NMI\n");
2718 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2719 if (ret < 0) {
2720 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2721 strerror(-ret));
2722 }
2723 }
2724 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2725 qemu_mutex_lock_iothread();
2726 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2727 qemu_mutex_unlock_iothread();
2728 DPRINTF("injected SMI\n");
2729 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2730 if (ret < 0) {
2731 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2732 strerror(-ret));
2733 }
2734 }
2735 }
2736
2737 if (!kvm_pic_in_kernel()) {
2738 qemu_mutex_lock_iothread();
2739 }
2740
2741 /* Force the VCPU out of its inner loop to process any INIT requests
2742 * or (for userspace APIC, but it is cheap to combine the checks here)
2743 * pending TPR access reports.
2744 */
2745 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2746 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2747 !(env->hflags & HF_SMM_MASK)) {
2748 cpu->exit_request = 1;
2749 }
2750 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2751 cpu->exit_request = 1;
2752 }
2753 }
2754
2755 if (!kvm_pic_in_kernel()) {
2756 /* Try to inject an interrupt if the guest can accept it */
2757 if (run->ready_for_interrupt_injection &&
2758 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2759 (env->eflags & IF_MASK)) {
2760 int irq;
2761
2762 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2763 irq = cpu_get_pic_interrupt(env);
2764 if (irq >= 0) {
2765 struct kvm_interrupt intr;
2766
2767 intr.irq = irq;
2768 DPRINTF("injected interrupt %d\n", irq);
2769 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2770 if (ret < 0) {
2771 fprintf(stderr,
2772 "KVM: injection failed, interrupt lost (%s)\n",
2773 strerror(-ret));
2774 }
2775 }
2776 }
2777
2778 /* If we have an interrupt but the guest is not ready to receive an
2779 * interrupt, request an interrupt window exit. This will
2780 * cause a return to userspace as soon as the guest is ready to
2781 * receive interrupts. */
2782 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2783 run->request_interrupt_window = 1;
2784 } else {
2785 run->request_interrupt_window = 0;
2786 }
2787
2788 DPRINTF("setting tpr\n");
2789 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2790
2791 qemu_mutex_unlock_iothread();
2792 }
2793 }
2794
2795 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2796 {
2797 X86CPU *x86_cpu = X86_CPU(cpu);
2798 CPUX86State *env = &x86_cpu->env;
2799
2800 if (run->flags & KVM_RUN_X86_SMM) {
2801 env->hflags |= HF_SMM_MASK;
2802 } else {
2803 env->hflags &= ~HF_SMM_MASK;
2804 }
2805 if (run->if_flag) {
2806 env->eflags |= IF_MASK;
2807 } else {
2808 env->eflags &= ~IF_MASK;
2809 }
2810
2811 /* We need to protect the apic state against concurrent accesses from
2812 * different threads in case the userspace irqchip is used. */
2813 if (!kvm_irqchip_in_kernel()) {
2814 qemu_mutex_lock_iothread();
2815 }
2816 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2817 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2818 if (!kvm_irqchip_in_kernel()) {
2819 qemu_mutex_unlock_iothread();
2820 }
2821 return cpu_get_mem_attrs(env);
2822 }
2823
2824 int kvm_arch_process_async_events(CPUState *cs)
2825 {
2826 X86CPU *cpu = X86_CPU(cs);
2827 CPUX86State *env = &cpu->env;
2828
2829 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2830 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2831 assert(env->mcg_cap);
2832
2833 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2834
2835 kvm_cpu_synchronize_state(cs);
2836
2837 if (env->exception_injected == EXCP08_DBLE) {
2838 /* this means triple fault */
2839 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2840 cs->exit_request = 1;
2841 return 0;
2842 }
2843 env->exception_injected = EXCP12_MCHK;
2844 env->has_error_code = 0;
2845
2846 cs->halted = 0;
2847 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2848 env->mp_state = KVM_MP_STATE_RUNNABLE;
2849 }
2850 }
2851
2852 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2853 !(env->hflags & HF_SMM_MASK)) {
2854 kvm_cpu_synchronize_state(cs);
2855 do_cpu_init(cpu);
2856 }
2857
2858 if (kvm_irqchip_in_kernel()) {
2859 return 0;
2860 }
2861
2862 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2863 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2864 apic_poll_irq(cpu->apic_state);
2865 }
2866 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2867 (env->eflags & IF_MASK)) ||
2868 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2869 cs->halted = 0;
2870 }
2871 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2872 kvm_cpu_synchronize_state(cs);
2873 do_cpu_sipi(cpu);
2874 }
2875 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2876 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2877 kvm_cpu_synchronize_state(cs);
2878 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2879 env->tpr_access_type);
2880 }
2881
2882 return cs->halted;
2883 }
2884
2885 static int kvm_handle_halt(X86CPU *cpu)
2886 {
2887 CPUState *cs = CPU(cpu);
2888 CPUX86State *env = &cpu->env;
2889
2890 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2891 (env->eflags & IF_MASK)) &&
2892 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2893 cs->halted = 1;
2894 return EXCP_HLT;
2895 }
2896
2897 return 0;
2898 }
2899
2900 static int kvm_handle_tpr_access(X86CPU *cpu)
2901 {
2902 CPUState *cs = CPU(cpu);
2903 struct kvm_run *run = cs->kvm_run;
2904
2905 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2906 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2907 : TPR_ACCESS_READ);
2908 return 1;
2909 }
2910
2911 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2912 {
2913 static const uint8_t int3 = 0xcc;
2914
2915 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2916 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2917 return -EINVAL;
2918 }
2919 return 0;
2920 }
2921
2922 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2923 {
2924 uint8_t int3;
2925
2926 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2927 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2928 return -EINVAL;
2929 }
2930 return 0;
2931 }
2932
2933 static struct {
2934 target_ulong addr;
2935 int len;
2936 int type;
2937 } hw_breakpoint[4];
2938
2939 static int nb_hw_breakpoint;
2940
2941 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2942 {
2943 int n;
2944
2945 for (n = 0; n < nb_hw_breakpoint; n++) {
2946 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2947 (hw_breakpoint[n].len == len || len == -1)) {
2948 return n;
2949 }
2950 }
2951 return -1;
2952 }
2953
2954 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2955 target_ulong len, int type)
2956 {
2957 switch (type) {
2958 case GDB_BREAKPOINT_HW:
2959 len = 1;
2960 break;
2961 case GDB_WATCHPOINT_WRITE:
2962 case GDB_WATCHPOINT_ACCESS:
2963 switch (len) {
2964 case 1:
2965 break;
2966 case 2:
2967 case 4:
2968 case 8:
2969 if (addr & (len - 1)) {
2970 return -EINVAL;
2971 }
2972 break;
2973 default:
2974 return -EINVAL;
2975 }
2976 break;
2977 default:
2978 return -ENOSYS;
2979 }
2980
2981 if (nb_hw_breakpoint == 4) {
2982 return -ENOBUFS;
2983 }
2984 if (find_hw_breakpoint(addr, len, type) >= 0) {
2985 return -EEXIST;
2986 }
2987 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2988 hw_breakpoint[nb_hw_breakpoint].len = len;
2989 hw_breakpoint[nb_hw_breakpoint].type = type;
2990 nb_hw_breakpoint++;
2991
2992 return 0;
2993 }
2994
2995 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2996 target_ulong len, int type)
2997 {
2998 int n;
2999
3000 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3001 if (n < 0) {
3002 return -ENOENT;
3003 }
3004 nb_hw_breakpoint--;
3005 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3006
3007 return 0;
3008 }
3009
3010 void kvm_arch_remove_all_hw_breakpoints(void)
3011 {
3012 nb_hw_breakpoint = 0;
3013 }
3014
3015 static CPUWatchpoint hw_watchpoint;
3016
3017 static int kvm_handle_debug(X86CPU *cpu,
3018 struct kvm_debug_exit_arch *arch_info)
3019 {
3020 CPUState *cs = CPU(cpu);
3021 CPUX86State *env = &cpu->env;
3022 int ret = 0;
3023 int n;
3024
3025 if (arch_info->exception == 1) {
3026 if (arch_info->dr6 & (1 << 14)) {
3027 if (cs->singlestep_enabled) {
3028 ret = EXCP_DEBUG;
3029 }
3030 } else {
3031 for (n = 0; n < 4; n++) {
3032 if (arch_info->dr6 & (1 << n)) {
3033 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3034 case 0x0:
3035 ret = EXCP_DEBUG;
3036 break;
3037 case 0x1:
3038 ret = EXCP_DEBUG;
3039 cs->watchpoint_hit = &hw_watchpoint;
3040 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3041 hw_watchpoint.flags = BP_MEM_WRITE;
3042 break;
3043 case 0x3:
3044 ret = EXCP_DEBUG;
3045 cs->watchpoint_hit = &hw_watchpoint;
3046 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3047 hw_watchpoint.flags = BP_MEM_ACCESS;
3048 break;
3049 }
3050 }
3051 }
3052 }
3053 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3054 ret = EXCP_DEBUG;
3055 }
3056 if (ret == 0) {
3057 cpu_synchronize_state(cs);
3058 assert(env->exception_injected == -1);
3059
3060 /* pass to guest */
3061 env->exception_injected = arch_info->exception;
3062 env->has_error_code = 0;
3063 }
3064
3065 return ret;
3066 }
3067
3068 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3069 {
3070 const uint8_t type_code[] = {
3071 [GDB_BREAKPOINT_HW] = 0x0,
3072 [GDB_WATCHPOINT_WRITE] = 0x1,
3073 [GDB_WATCHPOINT_ACCESS] = 0x3
3074 };
3075 const uint8_t len_code[] = {
3076 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3077 };
3078 int n;
3079
3080 if (kvm_sw_breakpoints_active(cpu)) {
3081 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3082 }
3083 if (nb_hw_breakpoint > 0) {
3084 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3085 dbg->arch.debugreg[7] = 0x0600;
3086 for (n = 0; n < nb_hw_breakpoint; n++) {
3087 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3088 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3089 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3090 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3091 }
3092 }
3093 }
3094
3095 static bool host_supports_vmx(void)
3096 {
3097 uint32_t ecx, unused;
3098
3099 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3100 return ecx & CPUID_EXT_VMX;
3101 }
3102
3103 #define VMX_INVALID_GUEST_STATE 0x80000021
3104
3105 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3106 {
3107 X86CPU *cpu = X86_CPU(cs);
3108 uint64_t code;
3109 int ret;
3110
3111 switch (run->exit_reason) {
3112 case KVM_EXIT_HLT:
3113 DPRINTF("handle_hlt\n");
3114 qemu_mutex_lock_iothread();
3115 ret = kvm_handle_halt(cpu);
3116 qemu_mutex_unlock_iothread();
3117 break;
3118 case KVM_EXIT_SET_TPR:
3119 ret = 0;
3120 break;
3121 case KVM_EXIT_TPR_ACCESS:
3122 qemu_mutex_lock_iothread();
3123 ret = kvm_handle_tpr_access(cpu);
3124 qemu_mutex_unlock_iothread();
3125 break;
3126 case KVM_EXIT_FAIL_ENTRY:
3127 code = run->fail_entry.hardware_entry_failure_reason;
3128 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3129 code);
3130 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3131 fprintf(stderr,
3132 "\nIf you're running a guest on an Intel machine without "
3133 "unrestricted mode\n"
3134 "support, the failure can be most likely due to the guest "
3135 "entering an invalid\n"
3136 "state for Intel VT. For example, the guest maybe running "
3137 "in big real mode\n"
3138 "which is not supported on less recent Intel processors."
3139 "\n\n");
3140 }
3141 ret = -1;
3142 break;
3143 case KVM_EXIT_EXCEPTION:
3144 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3145 run->ex.exception, run->ex.error_code);
3146 ret = -1;
3147 break;
3148 case KVM_EXIT_DEBUG:
3149 DPRINTF("kvm_exit_debug\n");
3150 qemu_mutex_lock_iothread();
3151 ret = kvm_handle_debug(cpu, &run->debug.arch);
3152 qemu_mutex_unlock_iothread();
3153 break;
3154 case KVM_EXIT_HYPERV:
3155 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3156 break;
3157 case KVM_EXIT_IOAPIC_EOI:
3158 ioapic_eoi_broadcast(run->eoi.vector);
3159 ret = 0;
3160 break;
3161 default:
3162 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3163 ret = -1;
3164 break;
3165 }
3166
3167 return ret;
3168 }
3169
3170 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3171 {
3172 X86CPU *cpu = X86_CPU(cs);
3173 CPUX86State *env = &cpu->env;
3174
3175 kvm_cpu_synchronize_state(cs);
3176 return !(env->cr[0] & CR0_PE_MASK) ||
3177 ((env->segs[R_CS].selector & 3) != 3);
3178 }
3179
3180 void kvm_arch_init_irq_routing(KVMState *s)
3181 {
3182 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3183 /* If kernel can't do irq routing, interrupt source
3184 * override 0->2 cannot be set up as required by HPET.
3185 * So we have to disable it.
3186 */
3187 no_hpet = 1;
3188 }
3189 /* We know at this point that we're using the in-kernel
3190 * irqchip, so we can use irqfds, and on x86 we know
3191 * we can use msi via irqfd and GSI routing.
3192 */
3193 kvm_msi_via_irqfd_allowed = true;
3194 kvm_gsi_routing_allowed = true;
3195
3196 if (kvm_irqchip_is_split()) {
3197 int i;
3198
3199 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3200 MSI routes for signaling interrupts to the local apics. */
3201 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3202 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3203 error_report("Could not enable split IRQ mode.");
3204 exit(1);
3205 }
3206 }
3207 }
3208 }
3209
3210 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3211 {
3212 int ret;
3213 if (machine_kernel_irqchip_split(ms)) {
3214 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3215 if (ret) {
3216 error_report("Could not enable split irqchip mode: %s",
3217 strerror(-ret));
3218 exit(1);
3219 } else {
3220 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3221 kvm_split_irqchip = true;
3222 return 1;
3223 }
3224 } else {
3225 return 0;
3226 }
3227 }
3228
3229 /* Classic KVM device assignment interface. Will remain x86 only. */
3230 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3231 uint32_t flags, uint32_t *dev_id)
3232 {
3233 struct kvm_assigned_pci_dev dev_data = {
3234 .segnr = dev_addr->domain,
3235 .busnr = dev_addr->bus,
3236 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3237 .flags = flags,
3238 };
3239 int ret;
3240
3241 dev_data.assigned_dev_id =
3242 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3243
3244 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3245 if (ret < 0) {
3246 return ret;
3247 }
3248
3249 *dev_id = dev_data.assigned_dev_id;
3250
3251 return 0;
3252 }
3253
3254 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3255 {
3256 struct kvm_assigned_pci_dev dev_data = {
3257 .assigned_dev_id = dev_id,
3258 };
3259
3260 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3261 }
3262
3263 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3264 uint32_t irq_type, uint32_t guest_irq)
3265 {
3266 struct kvm_assigned_irq assigned_irq = {
3267 .assigned_dev_id = dev_id,
3268 .guest_irq = guest_irq,
3269 .flags = irq_type,
3270 };
3271
3272 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3273 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3274 } else {
3275 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3276 }
3277 }
3278
3279 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3280 uint32_t guest_irq)
3281 {
3282 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3283 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3284
3285 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3286 }
3287
3288 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3289 {
3290 struct kvm_assigned_pci_dev dev_data = {
3291 .assigned_dev_id = dev_id,
3292 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3293 };
3294
3295 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3296 }
3297
3298 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3299 uint32_t type)
3300 {
3301 struct kvm_assigned_irq assigned_irq = {
3302 .assigned_dev_id = dev_id,
3303 .flags = type,
3304 };
3305
3306 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3307 }
3308
3309 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3310 {
3311 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3312 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3313 }
3314
3315 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3316 {
3317 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3318 KVM_DEV_IRQ_GUEST_MSI, virq);
3319 }
3320
3321 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3322 {
3323 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3324 KVM_DEV_IRQ_HOST_MSI);
3325 }
3326
3327 bool kvm_device_msix_supported(KVMState *s)
3328 {
3329 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3330 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3331 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3332 }
3333
3334 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3335 uint32_t nr_vectors)
3336 {
3337 struct kvm_assigned_msix_nr msix_nr = {
3338 .assigned_dev_id = dev_id,
3339 .entry_nr = nr_vectors,
3340 };
3341
3342 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3343 }
3344
3345 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3346 int virq)
3347 {
3348 struct kvm_assigned_msix_entry msix_entry = {
3349 .assigned_dev_id = dev_id,
3350 .gsi = virq,
3351 .entry = vector,
3352 };
3353
3354 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3355 }
3356
3357 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3358 {
3359 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3360 KVM_DEV_IRQ_GUEST_MSIX, 0);
3361 }
3362
3363 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3364 {
3365 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3366 KVM_DEV_IRQ_HOST_MSIX);
3367 }
3368
3369 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3370 uint64_t address, uint32_t data, PCIDevice *dev)
3371 {
3372 X86IOMMUState *iommu = x86_iommu_get_default();
3373
3374 if (iommu) {
3375 int ret;
3376 MSIMessage src, dst;
3377 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3378
3379 src.address = route->u.msi.address_hi;
3380 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3381 src.address |= route->u.msi.address_lo;
3382 src.data = route->u.msi.data;
3383
3384 ret = class->int_remap(iommu, &src, &dst, dev ? \
3385 pci_requester_id(dev) : \
3386 X86_IOMMU_SID_INVALID);
3387 if (ret) {
3388 trace_kvm_x86_fixup_msi_error(route->gsi);
3389 return 1;
3390 }
3391
3392 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3393 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3394 route->u.msi.data = dst.data;
3395 }
3396
3397 return 0;
3398 }
3399
3400 typedef struct MSIRouteEntry MSIRouteEntry;
3401
3402 struct MSIRouteEntry {
3403 PCIDevice *dev; /* Device pointer */
3404 int vector; /* MSI/MSIX vector index */
3405 int virq; /* Virtual IRQ index */
3406 QLIST_ENTRY(MSIRouteEntry) list;
3407 };
3408
3409 /* List of used GSI routes */
3410 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3411 QLIST_HEAD_INITIALIZER(msi_route_list);
3412
3413 static void kvm_update_msi_routes_all(void *private, bool global,
3414 uint32_t index, uint32_t mask)
3415 {
3416 int cnt = 0;
3417 MSIRouteEntry *entry;
3418 MSIMessage msg;
3419 PCIDevice *dev;
3420
3421 /* TODO: explicit route update */
3422 QLIST_FOREACH(entry, &msi_route_list, list) {
3423 cnt++;
3424 dev = entry->dev;
3425 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3426 continue;
3427 }
3428 msg = pci_get_msi_message(dev, entry->vector);
3429 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3430 }
3431 kvm_irqchip_commit_routes(kvm_state);
3432 trace_kvm_x86_update_msi_routes(cnt);
3433 }
3434
3435 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3436 int vector, PCIDevice *dev)
3437 {
3438 static bool notify_list_inited = false;
3439 MSIRouteEntry *entry;
3440
3441 if (!dev) {
3442 /* These are (possibly) IOAPIC routes only used for split
3443 * kernel irqchip mode, while what we are housekeeping are
3444 * PCI devices only. */
3445 return 0;
3446 }
3447
3448 entry = g_new0(MSIRouteEntry, 1);
3449 entry->dev = dev;
3450 entry->vector = vector;
3451 entry->virq = route->gsi;
3452 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3453
3454 trace_kvm_x86_add_msi_route(route->gsi);
3455
3456 if (!notify_list_inited) {
3457 /* For the first time we do add route, add ourselves into
3458 * IOMMU's IEC notify list if needed. */
3459 X86IOMMUState *iommu = x86_iommu_get_default();
3460 if (iommu) {
3461 x86_iommu_iec_register_notifier(iommu,
3462 kvm_update_msi_routes_all,
3463 NULL);
3464 }
3465 notify_list_inited = true;
3466 }
3467 return 0;
3468 }
3469
3470 int kvm_arch_release_virq_post(int virq)
3471 {
3472 MSIRouteEntry *entry, *next;
3473 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3474 if (entry->virq == virq) {
3475 trace_kvm_x86_remove_msi_route(virq);
3476 QLIST_REMOVE(entry, list);
3477 break;
3478 }
3479 }
3480 return 0;
3481 }
3482
3483 int kvm_arch_msi_data_to_gsi(uint32_t data)
3484 {
3485 abort();
3486 }
AR7 emulation for QEMU