2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include "qemu/osdep.h"
13 #include <sys/ioctl.h>
15 #include <linux/kvm.h>
17 #include "qemu-common.h"
20 #include "qemu/error-report.h"
21 #include "qemu/main-loop.h"
22 #include "qemu/timer.h"
23 #include "sysemu/kvm.h"
24 #include "sysemu/kvm_int.h"
25 #include "sysemu/runstate.h"
26 #include "sysemu/cpus.h"
28 #include "exec/memattrs.h"
29 #include "hw/boards.h"
33 #define DPRINTF(fmt, ...) \
34 do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
36 static int kvm_mips_fpu_cap
;
37 static int kvm_mips_msa_cap
;
39 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
43 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
);
45 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
50 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
52 /* MIPS has 128 signals */
53 kvm_set_sigmask_len(s
, 16);
55 kvm_mips_fpu_cap
= kvm_check_extension(s
, KVM_CAP_MIPS_FPU
);
56 kvm_mips_msa_cap
= kvm_check_extension(s
, KVM_CAP_MIPS_MSA
);
58 DPRINTF("%s\n", __func__
);
62 int kvm_arch_irqchip_create(KVMState
*s
)
67 int kvm_arch_init_vcpu(CPUState
*cs
)
69 MIPSCPU
*cpu
= MIPS_CPU(cs
);
70 CPUMIPSState
*env
= &cpu
->env
;
73 qemu_add_vm_change_state_handler(kvm_mips_update_state
, cs
);
75 if (kvm_mips_fpu_cap
&& env
->CP0_Config1
& (1 << CP0C1_FP
)) {
76 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_MIPS_FPU
, 0, 0);
78 /* mark unsupported so it gets disabled on reset */
84 if (kvm_mips_msa_cap
&& env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
85 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_MIPS_MSA
, 0, 0);
87 /* mark unsupported so it gets disabled on reset */
93 DPRINTF("%s\n", __func__
);
97 int kvm_arch_destroy_vcpu(CPUState
*cs
)
102 void kvm_mips_reset_vcpu(MIPSCPU
*cpu
)
104 CPUMIPSState
*env
= &cpu
->env
;
106 if (!kvm_mips_fpu_cap
&& env
->CP0_Config1
& (1 << CP0C1_FP
)) {
107 warn_report("KVM does not support FPU, disabling");
108 env
->CP0_Config1
&= ~(1 << CP0C1_FP
);
110 if (!kvm_mips_msa_cap
&& env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
111 warn_report("KVM does not support MSA, disabling");
112 env
->CP0_Config3
&= ~(1 << CP0C3_MSAP
);
115 DPRINTF("%s\n", __func__
);
118 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
120 DPRINTF("%s\n", __func__
);
124 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
126 DPRINTF("%s\n", __func__
);
130 static inline int cpu_mips_io_interrupts_pending(MIPSCPU
*cpu
)
132 CPUMIPSState
*env
= &cpu
->env
;
134 return env
->CP0_Cause
& (0x1 << (2 + CP0Ca_IP
));
138 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
140 MIPSCPU
*cpu
= MIPS_CPU(cs
);
142 struct kvm_mips_interrupt intr
;
144 qemu_mutex_lock_iothread();
146 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
147 cpu_mips_io_interrupts_pending(cpu
)) {
150 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
152 error_report("%s: cpu %d: failed to inject IRQ %x",
153 __func__
, cs
->cpu_index
, intr
.irq
);
157 qemu_mutex_unlock_iothread();
160 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
162 return MEMTXATTRS_UNSPECIFIED
;
165 int kvm_arch_process_async_events(CPUState
*cs
)
170 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
174 DPRINTF("%s\n", __func__
);
175 switch (run
->exit_reason
) {
177 error_report("%s: unknown exit reason %d",
178 __func__
, run
->exit_reason
);
186 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
188 DPRINTF("%s\n", __func__
);
192 void kvm_arch_init_irq_routing(KVMState
*s
)
196 int kvm_mips_set_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
198 CPUState
*cs
= CPU(cpu
);
199 struct kvm_mips_interrupt intr
;
201 if (!kvm_enabled()) {
213 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
218 int kvm_mips_set_ipi_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
220 CPUState
*cs
= current_cpu
;
221 CPUState
*dest_cs
= CPU(cpu
);
222 struct kvm_mips_interrupt intr
;
224 if (!kvm_enabled()) {
228 intr
.cpu
= dest_cs
->cpu_index
;
236 DPRINTF("%s: CPU %d, IRQ: %d\n", __func__
, intr
.cpu
, intr
.irq
);
238 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
243 #define MIPS_CP0_32(_R, _S) \
244 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
246 #define MIPS_CP0_64(_R, _S) \
247 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
249 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
250 #define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0)
251 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
252 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
253 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
254 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
255 #define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5)
256 #define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6)
257 #define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7)
258 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
259 #define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6)
260 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
261 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
262 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
263 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
264 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
265 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
266 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
267 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
268 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
269 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
270 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
271 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
272 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
273 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
274 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
275 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
276 #define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6)
277 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
278 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
279 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
280 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
281 #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4)
282 #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5)
283 #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6)
284 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
286 static inline int kvm_mips_put_one_reg(CPUState
*cs
, uint64_t reg_id
,
289 struct kvm_one_reg cp0reg
= {
291 .addr
= (uintptr_t)addr
294 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
297 static inline int kvm_mips_put_one_ureg(CPUState
*cs
, uint64_t reg_id
,
300 struct kvm_one_reg cp0reg
= {
302 .addr
= (uintptr_t)addr
305 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
308 static inline int kvm_mips_put_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
311 uint64_t val64
= *addr
;
312 struct kvm_one_reg cp0reg
= {
314 .addr
= (uintptr_t)&val64
317 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
320 static inline int kvm_mips_put_one_reg64(CPUState
*cs
, uint64_t reg_id
,
323 struct kvm_one_reg cp0reg
= {
325 .addr
= (uintptr_t)addr
328 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
331 static inline int kvm_mips_put_one_ureg64(CPUState
*cs
, uint64_t reg_id
,
334 struct kvm_one_reg cp0reg
= {
336 .addr
= (uintptr_t)addr
339 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
342 static inline int kvm_mips_get_one_reg(CPUState
*cs
, uint64_t reg_id
,
345 struct kvm_one_reg cp0reg
= {
347 .addr
= (uintptr_t)addr
350 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
353 static inline int kvm_mips_get_one_ureg(CPUState
*cs
, uint64_t reg_id
,
356 struct kvm_one_reg cp0reg
= {
358 .addr
= (uintptr_t)addr
361 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
364 static inline int kvm_mips_get_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
369 struct kvm_one_reg cp0reg
= {
371 .addr
= (uintptr_t)&val64
374 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
381 static inline int kvm_mips_get_one_reg64(CPUState
*cs
, uint64_t reg_id
,
384 struct kvm_one_reg cp0reg
= {
386 .addr
= (uintptr_t)addr
389 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
392 static inline int kvm_mips_get_one_ureg64(CPUState
*cs
, uint64_t reg_id
,
395 struct kvm_one_reg cp0reg
= {
397 .addr
= (uintptr_t)addr
400 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
403 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
404 #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \
406 #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M)
407 #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \
409 #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M)
410 #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \
411 (1U << CP0C5_UFE) | \
412 (1U << CP0C5_FRE) | \
414 #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \
415 (0x3fU << CP0C6_KPOS) | \
417 (1U << CP0C6_VTLBONLY) | \
418 (1U << CP0C6_LASX) | \
419 (1U << CP0C6_SSEN) | \
420 (1U << CP0C6_DISDRTIME) | \
421 (1U << CP0C6_PIXNUEN) | \
422 (1U << CP0C6_SCRAND) | \
423 (1U << CP0C6_LLEXCEN) | \
424 (1U << CP0C6_DISVC) | \
425 (1U << CP0C6_VCLRU) | \
426 (1U << CP0C6_DCLRU) | \
427 (1U << CP0C6_PIXUEN) | \
428 (1U << CP0C6_DISBLKLYEN) | \
429 (1U << CP0C6_UMEMUALEN) | \
430 (1U << CP0C6_SFBEN) | \
431 (1U << CP0C6_FLTINT) | \
432 (1U << CP0C6_VLTINT) | \
433 (1U << CP0C6_DISBTB) | \
434 (3U << CP0C6_STPREFCTL) | \
435 (1U << CP0C6_INSTPREF) | \
436 (1U << CP0C6_DATAPREF))
438 static inline int kvm_mips_change_one_reg(CPUState
*cs
, uint64_t reg_id
,
439 int32_t *addr
, int32_t mask
)
444 err
= kvm_mips_get_one_reg(cs
, reg_id
, &tmp
);
449 /* only change bits in mask */
450 change
= (*addr
^ tmp
) & mask
;
456 return kvm_mips_put_one_reg(cs
, reg_id
, &tmp
);
460 * We freeze the KVM timer when either the VM clock is stopped or the state is
461 * saved (the state is dirty).
465 * Save the state of the KVM timer when VM clock is stopped or state is synced
468 static int kvm_mips_save_count(CPUState
*cs
)
470 MIPSCPU
*cpu
= MIPS_CPU(cs
);
471 CPUMIPSState
*env
= &cpu
->env
;
475 /* freeze KVM timer */
476 err
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
478 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err
);
480 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
481 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
482 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
484 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
490 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
492 DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__
, err
);
497 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
499 DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__
, err
);
507 * Restore the state of the KVM timer when VM clock is restarted or state is
510 static int kvm_mips_restore_count(CPUState
*cs
)
512 MIPSCPU
*cpu
= MIPS_CPU(cs
);
513 CPUMIPSState
*env
= &cpu
->env
;
515 int err_dc
, err
, ret
= 0;
517 /* check the timer is frozen */
518 err_dc
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
520 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err_dc
);
522 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
523 /* freeze timer (sets COUNT_RESUME for us) */
524 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
525 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
527 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
533 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
535 DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__
, err
);
540 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
542 DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__
, err
);
546 /* resume KVM timer */
548 count_ctl
&= ~KVM_REG_MIPS_COUNT_CTL_DC
;
549 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
551 DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__
, err
);
560 * Handle the VM clock being started or stopped
562 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
)
564 CPUState
*cs
= opaque
;
566 uint64_t count_resume
;
569 * If state is already dirty (synced to QEMU) then the KVM timer state is
570 * already saved and can be restored when it is synced back to KVM.
573 if (!cs
->vcpu_dirty
) {
574 ret
= kvm_mips_save_count(cs
);
576 warn_report("Failed saving count");
580 /* Set clock restore time to now */
581 count_resume
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
582 ret
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_RESUME
,
585 warn_report("Failed setting COUNT_RESUME");
589 if (!cs
->vcpu_dirty
) {
590 ret
= kvm_mips_restore_count(cs
);
592 warn_report("Failed restoring count");
598 static int kvm_mips_put_fpu_registers(CPUState
*cs
, int level
)
600 MIPSCPU
*cpu
= MIPS_CPU(cs
);
601 CPUMIPSState
*env
= &cpu
->env
;
605 /* Only put FPU state if we're emulating a CPU with an FPU */
606 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
607 /* FPU Control Registers */
608 if (level
== KVM_PUT_FULL_STATE
) {
609 err
= kvm_mips_put_one_ureg(cs
, KVM_REG_MIPS_FCR_IR
,
610 &env
->active_fpu
.fcr0
);
612 DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__
, err
);
616 err
= kvm_mips_put_one_ureg(cs
, KVM_REG_MIPS_FCR_CSR
,
617 &env
->active_fpu
.fcr31
);
619 DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__
, err
);
624 * FPU register state is a subset of MSA vector state, so don't put FPU
625 * registers if we're emulating a CPU with MSA.
627 if (!(env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
628 /* Floating point registers */
629 for (i
= 0; i
< 32; ++i
) {
630 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
631 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_FPR_64(i
),
632 &env
->active_fpu
.fpr
[i
].d
);
634 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FPR_32(i
),
635 &env
->active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]);
638 DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__
, i
, err
);
645 /* Only put MSA state if we're emulating a CPU with MSA */
646 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
647 /* MSA Control Registers */
648 if (level
== KVM_PUT_FULL_STATE
) {
649 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_MSA_IR
,
652 DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__
, err
);
656 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_MSA_CSR
,
657 &env
->active_tc
.msacsr
);
659 DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__
, err
);
663 /* Vector registers (includes FP registers) */
664 for (i
= 0; i
< 32; ++i
) {
665 /* Big endian MSA not supported by QEMU yet anyway */
666 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_VEC_128(i
),
667 env
->active_fpu
.fpr
[i
].wr
.d
);
669 DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__
, i
, err
);
678 static int kvm_mips_get_fpu_registers(CPUState
*cs
)
680 MIPSCPU
*cpu
= MIPS_CPU(cs
);
681 CPUMIPSState
*env
= &cpu
->env
;
685 /* Only get FPU state if we're emulating a CPU with an FPU */
686 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
687 /* FPU Control Registers */
688 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FCR_IR
,
689 &env
->active_fpu
.fcr0
);
691 DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__
, err
);
694 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FCR_CSR
,
695 &env
->active_fpu
.fcr31
);
697 DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__
, err
);
700 restore_fp_status(env
);
704 * FPU register state is a subset of MSA vector state, so don't save FPU
705 * registers if we're emulating a CPU with MSA.
707 if (!(env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
708 /* Floating point registers */
709 for (i
= 0; i
< 32; ++i
) {
710 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
711 err
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_FPR_64(i
),
712 &env
->active_fpu
.fpr
[i
].d
);
714 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FPR_32(i
),
715 &env
->active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]);
718 DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__
, i
, err
);
725 /* Only get MSA state if we're emulating a CPU with MSA */
726 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
727 /* MSA Control Registers */
728 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_MSA_IR
,
731 DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__
, err
);
734 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_MSA_CSR
,
735 &env
->active_tc
.msacsr
);
737 DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__
, err
);
740 restore_msa_fp_status(env
);
743 /* Vector registers (includes FP registers) */
744 for (i
= 0; i
< 32; ++i
) {
745 /* Big endian MSA not supported by QEMU yet anyway */
746 err
= kvm_mips_get_one_reg64(cs
, KVM_REG_MIPS_VEC_128(i
),
747 env
->active_fpu
.fpr
[i
].wr
.d
);
749 DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__
, i
, err
);
759 static int kvm_mips_put_cp0_registers(CPUState
*cs
, int level
)
761 MIPSCPU
*cpu
= MIPS_CPU(cs
);
762 CPUMIPSState
*env
= &cpu
->env
;
767 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
769 DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__
, err
);
772 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_RANDOM
, &env
->CP0_Random
);
774 DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__
, err
);
777 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
780 DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__
, err
);
783 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
784 &env
->active_tc
.CP0_UserLocal
);
786 DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__
, err
);
789 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
792 DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__
, err
);
795 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEGRAIN
,
796 &env
->CP0_PageGrain
);
798 DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__
, err
);
801 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_PWBASE
,
804 DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__
, err
);
807 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_PWFIELD
,
810 DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__
, err
);
813 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_PWSIZE
,
816 DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__
, err
);
819 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
821 DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__
, err
);
824 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PWCTL
, &env
->CP0_PWCtl
);
826 DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__
, err
);
829 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
831 DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__
, err
);
834 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
837 DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__
, err
);
841 /* If VM clock stopped then state will be restored when it is restarted */
842 if (runstate_is_running()) {
843 err
= kvm_mips_restore_count(cs
);
849 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
852 DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__
, err
);
855 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
858 DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__
, err
);
861 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
863 DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__
, err
);
866 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
868 DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__
, err
);
871 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PRID
, &env
->CP0_PRid
);
873 DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__
, err
);
876 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_EBASE
, &env
->CP0_EBase
);
878 DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__
, err
);
881 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG
,
883 KVM_REG_MIPS_CP0_CONFIG_MASK
);
885 DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__
, err
);
888 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG1
,
890 KVM_REG_MIPS_CP0_CONFIG1_MASK
);
892 DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__
, err
);
895 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG2
,
897 KVM_REG_MIPS_CP0_CONFIG2_MASK
);
899 DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__
, err
);
902 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG3
,
904 KVM_REG_MIPS_CP0_CONFIG3_MASK
);
906 DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__
, err
);
909 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG4
,
911 KVM_REG_MIPS_CP0_CONFIG4_MASK
);
913 DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__
, err
);
916 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG5
,
918 KVM_REG_MIPS_CP0_CONFIG5_MASK
);
920 DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__
, err
);
923 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG6
,
925 KVM_REG_MIPS_CP0_CONFIG6_MASK
);
927 DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__
, err
);
930 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_XCONTEXT
,
933 DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__
, err
);
936 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
939 DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__
, err
);
942 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH1
,
943 &env
->CP0_KScratch
[0]);
945 DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__
, err
);
948 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH2
,
949 &env
->CP0_KScratch
[1]);
951 DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__
, err
);
954 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH3
,
955 &env
->CP0_KScratch
[2]);
957 DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__
, err
);
960 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH4
,
961 &env
->CP0_KScratch
[3]);
963 DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__
, err
);
966 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH5
,
967 &env
->CP0_KScratch
[4]);
969 DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__
, err
);
972 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH6
,
973 &env
->CP0_KScratch
[5]);
975 DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__
, err
);
982 static int kvm_mips_get_cp0_registers(CPUState
*cs
)
984 MIPSCPU
*cpu
= MIPS_CPU(cs
);
985 CPUMIPSState
*env
= &cpu
->env
;
988 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
990 DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__
, err
);
993 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_RANDOM
, &env
->CP0_Random
);
995 DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__
, err
);
998 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
1001 DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__
, err
);
1004 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
1005 &env
->active_tc
.CP0_UserLocal
);
1007 DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__
, err
);
1010 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
1011 &env
->CP0_PageMask
);
1013 DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__
, err
);
1016 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEGRAIN
,
1017 &env
->CP0_PageGrain
);
1019 DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__
, err
);
1022 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_PWBASE
,
1025 DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__
, err
);
1028 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_PWFIELD
,
1031 DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__
, err
);
1034 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_PWSIZE
,
1037 DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__
, err
);
1040 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
1042 DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__
, err
);
1045 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PWCTL
, &env
->CP0_PWCtl
);
1047 DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__
, err
);
1050 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
1052 DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__
, err
);
1055 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
1056 &env
->CP0_BadVAddr
);
1058 DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__
, err
);
1061 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
1064 DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__
, err
);
1067 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
1070 DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__
, err
);
1073 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
1075 DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__
, err
);
1079 /* If VM clock stopped then state was already saved when it was stopped */
1080 if (runstate_is_running()) {
1081 err
= kvm_mips_save_count(cs
);
1087 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
1089 DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__
, err
);
1092 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PRID
, &env
->CP0_PRid
);
1094 DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__
, err
);
1097 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_EBASE
, &env
->CP0_EBase
);
1099 DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__
, err
);
1102 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG
, &env
->CP0_Config0
);
1104 DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__
, err
);
1107 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG1
, &env
->CP0_Config1
);
1109 DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__
, err
);
1112 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG2
, &env
->CP0_Config2
);
1114 DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__
, err
);
1117 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG3
, &env
->CP0_Config3
);
1119 DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__
, err
);
1122 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG4
, &env
->CP0_Config4
);
1124 DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__
, err
);
1127 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG5
, &env
->CP0_Config5
);
1129 DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__
, err
);
1132 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG6
, &env
->CP0_Config6
);
1134 DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__
, err
);
1137 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_XCONTEXT
,
1138 &env
->CP0_XContext
);
1140 DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__
, err
);
1143 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
1144 &env
->CP0_ErrorEPC
);
1146 DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__
, err
);
1149 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH1
,
1150 &env
->CP0_KScratch
[0]);
1152 DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__
, err
);
1155 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH2
,
1156 &env
->CP0_KScratch
[1]);
1158 DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__
, err
);
1161 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH3
,
1162 &env
->CP0_KScratch
[2]);
1164 DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__
, err
);
1167 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH4
,
1168 &env
->CP0_KScratch
[3]);
1170 DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__
, err
);
1173 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH5
,
1174 &env
->CP0_KScratch
[4]);
1176 DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__
, err
);
1179 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_KSCRATCH6
,
1180 &env
->CP0_KScratch
[5]);
1182 DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__
, err
);
1189 int kvm_arch_put_registers(CPUState
*cs
, int level
)
1191 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1192 CPUMIPSState
*env
= &cpu
->env
;
1193 struct kvm_regs regs
;
1197 /* Set the registers based on QEMU's view of things */
1198 for (i
= 0; i
< 32; i
++) {
1199 regs
.gpr
[i
] = (int64_t)(target_long
)env
->active_tc
.gpr
[i
];
1202 regs
.hi
= (int64_t)(target_long
)env
->active_tc
.HI
[0];
1203 regs
.lo
= (int64_t)(target_long
)env
->active_tc
.LO
[0];
1204 regs
.pc
= (int64_t)(target_long
)env
->active_tc
.PC
;
1206 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
1212 ret
= kvm_mips_put_cp0_registers(cs
, level
);
1217 ret
= kvm_mips_put_fpu_registers(cs
, level
);
1225 int kvm_arch_get_registers(CPUState
*cs
)
1227 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1228 CPUMIPSState
*env
= &cpu
->env
;
1230 struct kvm_regs regs
;
1233 /* Get the current register set as KVM seems it */
1234 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
1240 for (i
= 0; i
< 32; i
++) {
1241 env
->active_tc
.gpr
[i
] = regs
.gpr
[i
];
1244 env
->active_tc
.HI
[0] = regs
.hi
;
1245 env
->active_tc
.LO
[0] = regs
.lo
;
1246 env
->active_tc
.PC
= regs
.pc
;
1248 kvm_mips_get_cp0_registers(cs
);
1249 kvm_mips_get_fpu_registers(cs
);
1254 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
1255 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
1260 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
1261 int vector
, PCIDevice
*dev
)
1266 int kvm_arch_release_virq_post(int virq
)
1271 int kvm_arch_msi_data_to_gsi(uint32_t data
)
1276 int mips_kvm_type(MachineState
*machine
, const char *vm_type
)
1278 #if defined(KVM_CAP_MIPS_VZ) || defined(KVM_CAP_MIPS_TE)
1280 KVMState
*s
= KVM_STATE(machine
->accelerator
);
1283 #if defined(KVM_CAP_MIPS_VZ)
1284 r
= kvm_check_extension(s
, KVM_CAP_MIPS_VZ
);
1286 return KVM_VM_MIPS_VZ
;
1290 #if defined(KVM_CAP_MIPS_TE)
1291 r
= kvm_check_extension(s
, KVM_CAP_MIPS_TE
);
1293 return KVM_VM_MIPS_TE
;