4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include <hw/pci/msi.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/sysbus.h>
30 #include "qemu/error-report.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/dma.h"
34 #include <hw/ide/pci.h>
35 #include <hw/ide/ahci.h>
39 #define DPRINTF(port, fmt, ...) \
42 fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \
43 fprintf(stderr, fmt, ## __VA_ARGS__); \
47 static void check_cmd(AHCIState
*s
, int port
);
48 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
);
49 static void ahci_reset_port(AHCIState
*s
, int port
);
50 static void ahci_write_fis_d2h(AHCIDevice
*ad
, uint8_t *cmd_fis
);
51 static void ahci_init_d2h(AHCIDevice
*ad
);
52 static int ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
);
53 static void ahci_commit_buf(IDEDMA
*dma
, uint32_t tx_bytes
);
54 static bool ahci_map_clb_address(AHCIDevice
*ad
);
55 static bool ahci_map_fis_address(AHCIDevice
*ad
);
56 static void ahci_unmap_clb_address(AHCIDevice
*ad
);
57 static void ahci_unmap_fis_address(AHCIDevice
*ad
);
60 static uint32_t ahci_port_read(AHCIState
*s
, int port
, int offset
)
64 pr
= &s
->dev
[port
].port_regs
;
70 case PORT_LST_ADDR_HI
:
71 val
= pr
->lst_addr_hi
;
76 case PORT_FIS_ADDR_HI
:
77 val
= pr
->fis_addr_hi
;
95 if (s
->dev
[port
].port
.ifs
[0].blk
) {
96 val
= SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP
|
97 SATA_SCR_SSTATUS_SPD_GEN1
| SATA_SCR_SSTATUS_IPM_ACTIVE
;
99 val
= SATA_SCR_SSTATUS_DET_NODEV
;
109 pr
->scr_act
&= ~s
->dev
[port
].finished
;
110 s
->dev
[port
].finished
= 0;
120 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
125 static void ahci_irq_raise(AHCIState
*s
, AHCIDevice
*dev
)
127 AHCIPCIState
*d
= container_of(s
, AHCIPCIState
, ahci
);
129 (PCIDevice
*)object_dynamic_cast(OBJECT(d
), TYPE_PCI_DEVICE
);
131 DPRINTF(0, "raise irq\n");
133 if (pci_dev
&& msi_enabled(pci_dev
)) {
134 msi_notify(pci_dev
, 0);
136 qemu_irq_raise(s
->irq
);
140 static void ahci_irq_lower(AHCIState
*s
, AHCIDevice
*dev
)
142 AHCIPCIState
*d
= container_of(s
, AHCIPCIState
, ahci
);
144 (PCIDevice
*)object_dynamic_cast(OBJECT(d
), TYPE_PCI_DEVICE
);
146 DPRINTF(0, "lower irq\n");
148 if (!pci_dev
|| !msi_enabled(pci_dev
)) {
149 qemu_irq_lower(s
->irq
);
153 static void ahci_check_irq(AHCIState
*s
)
157 DPRINTF(-1, "check irq %#x\n", s
->control_regs
.irqstatus
);
159 s
->control_regs
.irqstatus
= 0;
160 for (i
= 0; i
< s
->ports
; i
++) {
161 AHCIPortRegs
*pr
= &s
->dev
[i
].port_regs
;
162 if (pr
->irq_stat
& pr
->irq_mask
) {
163 s
->control_regs
.irqstatus
|= (1 << i
);
167 if (s
->control_regs
.irqstatus
&&
168 (s
->control_regs
.ghc
& HOST_CTL_IRQ_EN
)) {
169 ahci_irq_raise(s
, NULL
);
171 ahci_irq_lower(s
, NULL
);
175 static void ahci_trigger_irq(AHCIState
*s
, AHCIDevice
*d
,
178 DPRINTF(d
->port_no
, "trigger irq %#x -> %x\n",
179 irq_type
, d
->port_regs
.irq_mask
& irq_type
);
181 d
->port_regs
.irq_stat
|= irq_type
;
185 static void map_page(AddressSpace
*as
, uint8_t **ptr
, uint64_t addr
,
191 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
194 *ptr
= dma_memory_map(as
, addr
, &len
, DMA_DIRECTION_FROM_DEVICE
);
196 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
202 * Check the cmd register to see if we should start or stop
203 * the DMA or FIS RX engines.
205 * @ad: Device to engage.
206 * @allow_stop: Allow device to transition from started to stopped?
207 * 'no' is useful for migration post_load, which does not expect a transition.
209 * @return 0 on success, -1 on error.
211 static int ahci_cond_start_engines(AHCIDevice
*ad
, bool allow_stop
)
213 AHCIPortRegs
*pr
= &ad
->port_regs
;
215 if (pr
->cmd
& PORT_CMD_START
) {
216 if (ahci_map_clb_address(ad
)) {
217 pr
->cmd
|= PORT_CMD_LIST_ON
;
219 error_report("AHCI: Failed to start DMA engine: "
220 "bad command list buffer address");
223 } else if (pr
->cmd
& PORT_CMD_LIST_ON
) {
225 ahci_unmap_clb_address(ad
);
226 pr
->cmd
= pr
->cmd
& ~(PORT_CMD_LIST_ON
);
228 error_report("AHCI: DMA engine should be off, "
229 "but appears to still be running");
234 if (pr
->cmd
& PORT_CMD_FIS_RX
) {
235 if (ahci_map_fis_address(ad
)) {
236 pr
->cmd
|= PORT_CMD_FIS_ON
;
238 error_report("AHCI: Failed to start FIS receive engine: "
239 "bad FIS receive buffer address");
242 } else if (pr
->cmd
& PORT_CMD_FIS_ON
) {
244 ahci_unmap_fis_address(ad
);
245 pr
->cmd
= pr
->cmd
& ~(PORT_CMD_FIS_ON
);
247 error_report("AHCI: FIS receive engine should be off, "
248 "but appears to still be running");
256 static void ahci_port_write(AHCIState
*s
, int port
, int offset
, uint32_t val
)
258 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
260 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
265 case PORT_LST_ADDR_HI
:
266 pr
->lst_addr_hi
= val
;
271 case PORT_FIS_ADDR_HI
:
272 pr
->fis_addr_hi
= val
;
275 pr
->irq_stat
&= ~val
;
279 pr
->irq_mask
= val
& 0xfdc000ff;
283 /* Block any Read-only fields from being set;
284 * including LIST_ON and FIS_ON. */
285 pr
->cmd
= (pr
->cmd
& PORT_CMD_RO_MASK
) | (val
& ~PORT_CMD_RO_MASK
);
287 /* Check FIS RX and CLB engines, allow transition to false: */
288 ahci_cond_start_engines(&s
->dev
[port
], true);
290 /* XXX usually the FIS would be pending on the bus here and
291 issuing deferred until the OS enables FIS receival.
292 Instead, we only submit it once - which works in most
293 cases, but is a hack. */
294 if ((pr
->cmd
& PORT_CMD_FIS_ON
) &&
295 !s
->dev
[port
].init_d2h_sent
) {
296 ahci_init_d2h(&s
->dev
[port
]);
297 s
->dev
[port
].init_d2h_sent
= true;
312 if (((pr
->scr_ctl
& AHCI_SCR_SCTL_DET
) == 1) &&
313 ((val
& AHCI_SCR_SCTL_DET
) == 0)) {
314 ahci_reset_port(s
, port
);
326 pr
->cmd_issue
|= val
;
334 static uint64_t ahci_mem_read_32(void *opaque
, hwaddr addr
)
336 AHCIState
*s
= opaque
;
339 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
342 val
= s
->control_regs
.cap
;
345 val
= s
->control_regs
.ghc
;
348 val
= s
->control_regs
.irqstatus
;
350 case HOST_PORTS_IMPL
:
351 val
= s
->control_regs
.impl
;
354 val
= s
->control_regs
.version
;
358 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr
, val
);
359 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
360 (addr
< (AHCI_PORT_REGS_START_ADDR
+
361 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
362 val
= ahci_port_read(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
363 addr
& AHCI_PORT_ADDR_OFFSET_MASK
);
371 * AHCI 1.3 section 3 ("HBA Memory Registers")
372 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
373 * Caller is responsible for masking unwanted higher order bytes.
375 static uint64_t ahci_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
377 hwaddr aligned
= addr
& ~0x3;
378 int ofst
= addr
- aligned
;
379 uint64_t lo
= ahci_mem_read_32(opaque
, aligned
);
382 /* if < 8 byte read does not cross 4 byte boundary */
383 if (ofst
+ size
<= 4) {
384 return lo
>> (ofst
* 8);
386 g_assert_cmpint(size
, >, 1);
388 /* If the 64bit read is unaligned, we will produce undefined
389 * results. AHCI does not support unaligned 64bit reads. */
390 hi
= ahci_mem_read_32(opaque
, aligned
+ 4);
391 return (hi
<< 32 | lo
) >> (ofst
* 8);
395 static void ahci_mem_write(void *opaque
, hwaddr addr
,
396 uint64_t val
, unsigned size
)
398 AHCIState
*s
= opaque
;
400 /* Only aligned reads are allowed on AHCI */
402 fprintf(stderr
, "ahci: Mis-aligned write to addr 0x"
403 TARGET_FMT_plx
"\n", addr
);
407 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
408 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64
"\n", (unsigned) addr
, val
);
411 case HOST_CAP
: /* R/WO, RO */
412 /* FIXME handle R/WO */
414 case HOST_CTL
: /* R/W */
415 if (val
& HOST_CTL_RESET
) {
416 DPRINTF(-1, "HBA Reset\n");
419 s
->control_regs
.ghc
= (val
& 0x3) | HOST_CTL_AHCI_EN
;
423 case HOST_IRQ_STAT
: /* R/WC, RO */
424 s
->control_regs
.irqstatus
&= ~val
;
427 case HOST_PORTS_IMPL
: /* R/WO, RO */
428 /* FIXME handle R/WO */
430 case HOST_VERSION
: /* RO */
431 /* FIXME report write? */
434 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr
);
436 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
437 (addr
< (AHCI_PORT_REGS_START_ADDR
+
438 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
439 ahci_port_write(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
440 addr
& AHCI_PORT_ADDR_OFFSET_MASK
, val
);
445 static const MemoryRegionOps ahci_mem_ops
= {
446 .read
= ahci_mem_read
,
447 .write
= ahci_mem_write
,
448 .endianness
= DEVICE_LITTLE_ENDIAN
,
451 static uint64_t ahci_idp_read(void *opaque
, hwaddr addr
,
454 AHCIState
*s
= opaque
;
456 if (addr
== s
->idp_offset
) {
459 } else if (addr
== s
->idp_offset
+ 4) {
460 /* data register - do memory read at location selected by index */
461 return ahci_mem_read(opaque
, s
->idp_index
, size
);
467 static void ahci_idp_write(void *opaque
, hwaddr addr
,
468 uint64_t val
, unsigned size
)
470 AHCIState
*s
= opaque
;
472 if (addr
== s
->idp_offset
) {
473 /* index register - mask off reserved bits */
474 s
->idp_index
= (uint32_t)val
& ((AHCI_MEM_BAR_SIZE
- 1) & ~3);
475 } else if (addr
== s
->idp_offset
+ 4) {
476 /* data register - do memory write at location selected by index */
477 ahci_mem_write(opaque
, s
->idp_index
, val
, size
);
481 static const MemoryRegionOps ahci_idp_ops
= {
482 .read
= ahci_idp_read
,
483 .write
= ahci_idp_write
,
484 .endianness
= DEVICE_LITTLE_ENDIAN
,
488 static void ahci_reg_init(AHCIState
*s
)
492 s
->control_regs
.cap
= (s
->ports
- 1) |
493 (AHCI_NUM_COMMAND_SLOTS
<< 8) |
494 (AHCI_SUPPORTED_SPEED_GEN1
<< AHCI_SUPPORTED_SPEED
) |
495 HOST_CAP_NCQ
| HOST_CAP_AHCI
;
497 s
->control_regs
.impl
= (1 << s
->ports
) - 1;
499 s
->control_regs
.version
= AHCI_VERSION_1_0
;
501 for (i
= 0; i
< s
->ports
; i
++) {
502 s
->dev
[i
].port_state
= STATE_RUN
;
506 static void check_cmd(AHCIState
*s
, int port
)
508 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
511 if ((pr
->cmd
& PORT_CMD_START
) && pr
->cmd_issue
) {
512 for (slot
= 0; (slot
< 32) && pr
->cmd_issue
; slot
++) {
513 if ((pr
->cmd_issue
& (1U << slot
)) &&
514 !handle_cmd(s
, port
, slot
)) {
515 pr
->cmd_issue
&= ~(1U << slot
);
521 static void ahci_check_cmd_bh(void *opaque
)
523 AHCIDevice
*ad
= opaque
;
525 qemu_bh_delete(ad
->check_bh
);
528 if ((ad
->busy_slot
!= -1) &&
529 !(ad
->port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
))) {
531 ad
->port_regs
.cmd_issue
&= ~(1 << ad
->busy_slot
);
535 check_cmd(ad
->hba
, ad
->port_no
);
538 static void ahci_init_d2h(AHCIDevice
*ad
)
540 uint8_t init_fis
[20];
541 IDEState
*ide_state
= &ad
->port
.ifs
[0];
543 memset(init_fis
, 0, sizeof(init_fis
));
548 if (ide_state
->drive_kind
== IDE_CD
) {
549 init_fis
[5] = ide_state
->lcyl
;
550 init_fis
[6] = ide_state
->hcyl
;
553 ahci_write_fis_d2h(ad
, init_fis
);
556 static void ahci_reset_port(AHCIState
*s
, int port
)
558 AHCIDevice
*d
= &s
->dev
[port
];
559 AHCIPortRegs
*pr
= &d
->port_regs
;
560 IDEState
*ide_state
= &d
->port
.ifs
[0];
563 DPRINTF(port
, "reset port\n");
565 ide_bus_reset(&d
->port
);
566 ide_state
->ncq_queues
= AHCI_MAX_CMDS
;
572 pr
->sig
= 0xFFFFFFFF;
574 d
->init_d2h_sent
= false;
576 ide_state
= &s
->dev
[port
].port
.ifs
[0];
577 if (!ide_state
->blk
) {
581 /* reset ncq queue */
582 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
583 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[i
];
584 ncq_tfs
->halt
= false;
585 if (!ncq_tfs
->used
) {
589 if (ncq_tfs
->aiocb
) {
590 blk_aio_cancel(ncq_tfs
->aiocb
);
591 ncq_tfs
->aiocb
= NULL
;
594 /* Maybe we just finished the request thanks to blk_aio_cancel() */
595 if (!ncq_tfs
->used
) {
599 qemu_sglist_destroy(&ncq_tfs
->sglist
);
603 s
->dev
[port
].port_state
= STATE_RUN
;
604 if (!ide_state
->blk
) {
606 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
607 } else if (ide_state
->drive_kind
== IDE_CD
) {
608 pr
->sig
= SATA_SIGNATURE_CDROM
;
609 ide_state
->lcyl
= 0x14;
610 ide_state
->hcyl
= 0xeb;
611 DPRINTF(port
, "set lcyl = %d\n", ide_state
->lcyl
);
612 ide_state
->status
= SEEK_STAT
| WRERR_STAT
| READY_STAT
;
614 pr
->sig
= SATA_SIGNATURE_DISK
;
615 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
618 ide_state
->error
= 1;
622 static void debug_print_fis(uint8_t *fis
, int cmd_len
)
627 fprintf(stderr
, "fis:");
628 for (i
= 0; i
< cmd_len
; i
++) {
629 if ((i
& 0xf) == 0) {
630 fprintf(stderr
, "\n%02x:",i
);
632 fprintf(stderr
, "%02x ",fis
[i
]);
634 fprintf(stderr
, "\n");
638 static bool ahci_map_fis_address(AHCIDevice
*ad
)
640 AHCIPortRegs
*pr
= &ad
->port_regs
;
641 map_page(ad
->hba
->as
, &ad
->res_fis
,
642 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
643 return ad
->res_fis
!= NULL
;
646 static void ahci_unmap_fis_address(AHCIDevice
*ad
)
648 dma_memory_unmap(ad
->hba
->as
, ad
->res_fis
, 256,
649 DMA_DIRECTION_FROM_DEVICE
, 256);
653 static bool ahci_map_clb_address(AHCIDevice
*ad
)
655 AHCIPortRegs
*pr
= &ad
->port_regs
;
657 map_page(ad
->hba
->as
, &ad
->lst
,
658 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
659 return ad
->lst
!= NULL
;
662 static void ahci_unmap_clb_address(AHCIDevice
*ad
)
664 dma_memory_unmap(ad
->hba
->as
, ad
->lst
, 1024,
665 DMA_DIRECTION_FROM_DEVICE
, 1024);
669 static void ahci_write_fis_sdb(AHCIState
*s
, int port
, uint32_t finished
)
671 AHCIDevice
*ad
= &s
->dev
[port
];
672 AHCIPortRegs
*pr
= &ad
->port_regs
;
676 if (!s
->dev
[port
].res_fis
||
677 !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
681 sdb_fis
= (SDBFIS
*)&ad
->res_fis
[RES_FIS_SDBFIS
];
682 ide_state
= &ad
->port
.ifs
[0];
684 sdb_fis
->type
= SATA_FIS_TYPE_SDB
;
685 /* Interrupt pending & Notification bit */
686 sdb_fis
->flags
= (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
687 sdb_fis
->status
= ide_state
->status
& 0x77;
688 sdb_fis
->error
= ide_state
->error
;
689 /* update SAct field in SDB_FIS */
690 s
->dev
[port
].finished
|= finished
;
691 sdb_fis
->payload
= cpu_to_le32(ad
->finished
);
693 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
694 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
695 (ad
->port
.ifs
[0].status
& 0x77) |
698 ahci_trigger_irq(s
, ad
, PORT_IRQ_SDB_FIS
);
701 static void ahci_write_fis_pio(AHCIDevice
*ad
, uint16_t len
)
703 AHCIPortRegs
*pr
= &ad
->port_regs
;
705 IDEState
*s
= &ad
->port
.ifs
[0];
707 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
711 pio_fis
= &ad
->res_fis
[RES_FIS_PSFIS
];
713 pio_fis
[0] = SATA_FIS_TYPE_PIO_SETUP
;
714 pio_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
715 pio_fis
[2] = s
->status
;
716 pio_fis
[3] = s
->error
;
718 pio_fis
[4] = s
->sector
;
719 pio_fis
[5] = s
->lcyl
;
720 pio_fis
[6] = s
->hcyl
;
721 pio_fis
[7] = s
->select
;
722 pio_fis
[8] = s
->hob_sector
;
723 pio_fis
[9] = s
->hob_lcyl
;
724 pio_fis
[10] = s
->hob_hcyl
;
726 pio_fis
[12] = s
->nsector
& 0xFF;
727 pio_fis
[13] = (s
->nsector
>> 8) & 0xFF;
729 pio_fis
[15] = s
->status
;
730 pio_fis
[16] = len
& 255;
731 pio_fis
[17] = len
>> 8;
735 /* Update shadow registers: */
736 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
737 ad
->port
.ifs
[0].status
;
739 if (pio_fis
[2] & ERR_STAT
) {
740 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_TF_ERR
);
743 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_PIOS_FIS
);
746 static void ahci_write_fis_d2h(AHCIDevice
*ad
, uint8_t *cmd_fis
)
748 AHCIPortRegs
*pr
= &ad
->port_regs
;
751 IDEState
*s
= &ad
->port
.ifs
[0];
753 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
757 d2h_fis
= &ad
->res_fis
[RES_FIS_RFIS
];
759 d2h_fis
[0] = SATA_FIS_TYPE_REGISTER_D2H
;
760 d2h_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
761 d2h_fis
[2] = s
->status
;
762 d2h_fis
[3] = s
->error
;
764 d2h_fis
[4] = s
->sector
;
765 d2h_fis
[5] = s
->lcyl
;
766 d2h_fis
[6] = s
->hcyl
;
767 d2h_fis
[7] = s
->select
;
768 d2h_fis
[8] = s
->hob_sector
;
769 d2h_fis
[9] = s
->hob_lcyl
;
770 d2h_fis
[10] = s
->hob_hcyl
;
772 d2h_fis
[12] = s
->nsector
& 0xFF;
773 d2h_fis
[13] = (s
->nsector
>> 8) & 0xFF;
774 for (i
= 14; i
< 20; i
++) {
778 /* Update shadow registers: */
779 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
780 ad
->port
.ifs
[0].status
;
782 if (d2h_fis
[2] & ERR_STAT
) {
783 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_TF_ERR
);
786 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_D2H_REG_FIS
);
789 static int prdt_tbl_entry_size(const AHCI_SG
*tbl
)
791 /* flags_size is zero-based */
792 return (le32_to_cpu(tbl
->flags_size
) & AHCI_PRDT_SIZE_MASK
) + 1;
795 static int ahci_populate_sglist(AHCIDevice
*ad
, QEMUSGList
*sglist
,
796 AHCICmdHdr
*cmd
, int64_t limit
, int32_t offset
)
798 uint16_t opts
= le16_to_cpu(cmd
->opts
);
799 uint16_t prdtl
= le16_to_cpu(cmd
->prdtl
);
800 uint64_t cfis_addr
= le64_to_cpu(cmd
->tbl_addr
);
801 uint64_t prdt_addr
= cfis_addr
+ 0x80;
802 dma_addr_t prdt_len
= (prdtl
* sizeof(AHCI_SG
));
803 dma_addr_t real_prdt_len
= prdt_len
;
809 int64_t off_pos
= -1;
811 IDEBus
*bus
= &ad
->port
;
812 BusState
*qbus
= BUS(bus
);
815 * Note: AHCI PRDT can describe up to 256GiB. SATA/ATA only support
816 * transactions of up to 32MiB as of ATA8-ACS3 rev 1b, assuming a
817 * 512 byte sector size. We limit the PRDT in this implementation to
818 * a reasonably large 2GiB, which can accommodate the maximum transfer
819 * request for sector sizes up to 32K.
823 DPRINTF(ad
->port_no
, "no sg list given by guest: 0x%08x\n", opts
);
828 if (!(prdt
= dma_memory_map(ad
->hba
->as
, prdt_addr
, &prdt_len
,
829 DMA_DIRECTION_TO_DEVICE
))){
830 DPRINTF(ad
->port_no
, "map failed\n");
834 if (prdt_len
< real_prdt_len
) {
835 DPRINTF(ad
->port_no
, "mapped less than expected\n");
840 /* Get entries in the PRDT, init a qemu sglist accordingly */
842 AHCI_SG
*tbl
= (AHCI_SG
*)prdt
;
844 for (i
= 0; i
< prdtl
; i
++) {
845 tbl_entry_size
= prdt_tbl_entry_size(&tbl
[i
]);
846 if (offset
< (sum
+ tbl_entry_size
)) {
848 off_pos
= offset
- sum
;
851 sum
+= tbl_entry_size
;
853 if ((off_idx
== -1) || (off_pos
< 0) || (off_pos
> tbl_entry_size
)) {
854 DPRINTF(ad
->port_no
, "%s: Incorrect offset! "
855 "off_idx: %d, off_pos: %"PRId64
"\n",
856 __func__
, off_idx
, off_pos
);
861 qemu_sglist_init(sglist
, qbus
->parent
, (prdtl
- off_idx
),
863 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[off_idx
].addr
) + off_pos
,
864 MIN(prdt_tbl_entry_size(&tbl
[off_idx
]) - off_pos
,
867 for (i
= off_idx
+ 1; i
< prdtl
&& sglist
->size
< limit
; i
++) {
868 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[i
].addr
),
869 MIN(prdt_tbl_entry_size(&tbl
[i
]),
870 limit
- sglist
->size
));
871 if (sglist
->size
> INT32_MAX
) {
872 error_report("AHCI Physical Region Descriptor Table describes "
873 "more than 2 GiB.\n");
874 qemu_sglist_destroy(sglist
);
882 dma_memory_unmap(ad
->hba
->as
, prdt
, prdt_len
,
883 DMA_DIRECTION_TO_DEVICE
, prdt_len
);
887 static void ncq_err(NCQTransferState
*ncq_tfs
)
889 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
891 ide_state
->error
= ABRT_ERR
;
892 ide_state
->status
= READY_STAT
| ERR_STAT
;
893 ncq_tfs
->drive
->port_regs
.scr_err
|= (1 << ncq_tfs
->tag
);
896 static void ncq_finish(NCQTransferState
*ncq_tfs
)
898 /* Clear bit for this tag in SActive */
899 ncq_tfs
->drive
->port_regs
.scr_act
&= ~(1 << ncq_tfs
->tag
);
901 ahci_write_fis_sdb(ncq_tfs
->drive
->hba
, ncq_tfs
->drive
->port_no
,
902 (1 << ncq_tfs
->tag
));
904 DPRINTF(ncq_tfs
->drive
->port_no
, "NCQ transfer tag %d finished\n",
907 block_acct_done(blk_get_stats(ncq_tfs
->drive
->port
.ifs
[0].blk
),
909 qemu_sglist_destroy(&ncq_tfs
->sglist
);
913 static void ncq_cb(void *opaque
, int ret
)
915 NCQTransferState
*ncq_tfs
= (NCQTransferState
*)opaque
;
916 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
918 if (ret
== -ECANCELED
) {
923 bool is_read
= ncq_tfs
->cmd
== READ_FPDMA_QUEUED
;
924 BlockErrorAction action
= blk_get_error_action(ide_state
->blk
,
926 if (action
== BLOCK_ERROR_ACTION_STOP
) {
927 ncq_tfs
->halt
= true;
928 ide_state
->bus
->error_status
= IDE_RETRY_HBA
;
929 } else if (action
== BLOCK_ERROR_ACTION_REPORT
) {
932 blk_error_action(ide_state
->blk
, action
, is_read
, -ret
);
934 ide_state
->status
= READY_STAT
| SEEK_STAT
;
937 if (!ncq_tfs
->halt
) {
942 static int is_ncq(uint8_t ata_cmd
)
944 /* Based on SATA 3.2 section 13.6.3.2 */
946 case READ_FPDMA_QUEUED
:
947 case WRITE_FPDMA_QUEUED
:
949 case RECEIVE_FPDMA_QUEUED
:
950 case SEND_FPDMA_QUEUED
:
957 static void execute_ncq_command(NCQTransferState
*ncq_tfs
)
959 AHCIDevice
*ad
= ncq_tfs
->drive
;
960 IDEState
*ide_state
= &ad
->port
.ifs
[0];
961 int port
= ad
->port_no
;
963 g_assert(is_ncq(ncq_tfs
->cmd
));
964 ncq_tfs
->halt
= false;
966 switch (ncq_tfs
->cmd
) {
967 case READ_FPDMA_QUEUED
:
968 DPRINTF(port
, "NCQ reading %d sectors from LBA %"PRId64
", tag %d\n",
969 ncq_tfs
->sector_count
, ncq_tfs
->lba
, ncq_tfs
->tag
);
971 DPRINTF(port
, "tag %d aio read %"PRId64
"\n",
972 ncq_tfs
->tag
, ncq_tfs
->lba
);
974 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
975 &ncq_tfs
->sglist
, BLOCK_ACCT_READ
);
976 ncq_tfs
->aiocb
= dma_blk_read(ide_state
->blk
, &ncq_tfs
->sglist
,
977 ncq_tfs
->lba
, ncq_cb
, ncq_tfs
);
979 case WRITE_FPDMA_QUEUED
:
980 DPRINTF(port
, "NCQ writing %d sectors to LBA %"PRId64
", tag %d\n",
981 ncq_tfs
->sector_count
, ncq_tfs
->lba
, ncq_tfs
->tag
);
983 DPRINTF(port
, "tag %d aio write %"PRId64
"\n",
984 ncq_tfs
->tag
, ncq_tfs
->lba
);
986 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
987 &ncq_tfs
->sglist
, BLOCK_ACCT_WRITE
);
988 ncq_tfs
->aiocb
= dma_blk_write(ide_state
->blk
, &ncq_tfs
->sglist
,
989 ncq_tfs
->lba
, ncq_cb
, ncq_tfs
);
992 DPRINTF(port
, "error: unsupported NCQ command (0x%02x) received\n",
994 qemu_sglist_destroy(&ncq_tfs
->sglist
);
1000 static void process_ncq_command(AHCIState
*s
, int port
, uint8_t *cmd_fis
,
1003 AHCIDevice
*ad
= &s
->dev
[port
];
1004 IDEState
*ide_state
= &ad
->port
.ifs
[0];
1005 NCQFrame
*ncq_fis
= (NCQFrame
*)cmd_fis
;
1006 uint8_t tag
= ncq_fis
->tag
>> 3;
1007 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[tag
];
1010 g_assert(is_ncq(ncq_fis
->command
));
1011 if (ncq_tfs
->used
) {
1012 /* error - already in use */
1013 fprintf(stderr
, "%s: tag %d already used\n", __FUNCTION__
, tag
);
1018 ncq_tfs
->drive
= ad
;
1019 ncq_tfs
->slot
= slot
;
1020 ncq_tfs
->cmdh
= &((AHCICmdHdr
*)ad
->lst
)[slot
];
1021 ncq_tfs
->cmd
= ncq_fis
->command
;
1022 ncq_tfs
->lba
= ((uint64_t)ncq_fis
->lba5
<< 40) |
1023 ((uint64_t)ncq_fis
->lba4
<< 32) |
1024 ((uint64_t)ncq_fis
->lba3
<< 24) |
1025 ((uint64_t)ncq_fis
->lba2
<< 16) |
1026 ((uint64_t)ncq_fis
->lba1
<< 8) |
1027 (uint64_t)ncq_fis
->lba0
;
1030 /* Sanity-check the NCQ packet */
1032 DPRINTF(port
, "Warn: NCQ slot (%d) did not match the given tag (%d)\n",
1036 if (ncq_fis
->aux0
|| ncq_fis
->aux1
|| ncq_fis
->aux2
|| ncq_fis
->aux3
) {
1037 DPRINTF(port
, "Warn: Attempt to use NCQ auxiliary fields.\n");
1039 if (ncq_fis
->prio
|| ncq_fis
->icc
) {
1040 DPRINTF(port
, "Warn: Unsupported attempt to use PRIO/ICC fields\n");
1042 if (ncq_fis
->fua
& NCQ_FIS_FUA_MASK
) {
1043 DPRINTF(port
, "Warn: Unsupported attempt to use Force Unit Access\n");
1045 if (ncq_fis
->tag
& NCQ_FIS_RARC_MASK
) {
1046 DPRINTF(port
, "Warn: Unsupported attempt to use Rebuild Assist\n");
1049 ncq_tfs
->sector_count
= ((ncq_fis
->sector_count_high
<< 8) |
1050 ncq_fis
->sector_count_low
);
1051 if (!ncq_tfs
->sector_count
) {
1052 ncq_tfs
->sector_count
= 0x10000;
1054 size
= ncq_tfs
->sector_count
* 512;
1055 ahci_populate_sglist(ad
, &ncq_tfs
->sglist
, ncq_tfs
->cmdh
, size
, 0);
1057 if (ncq_tfs
->sglist
.size
< size
) {
1058 error_report("ahci: PRDT length for NCQ command (0x%zx) "
1059 "is smaller than the requested size (0x%zx)",
1060 ncq_tfs
->sglist
.size
, size
);
1061 qemu_sglist_destroy(&ncq_tfs
->sglist
);
1063 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_OVERFLOW
);
1065 } else if (ncq_tfs
->sglist
.size
!= size
) {
1066 DPRINTF(port
, "Warn: PRDTL (0x%zx)"
1067 " does not match requested size (0x%zx)",
1068 ncq_tfs
->sglist
.size
, size
);
1071 DPRINTF(port
, "NCQ transfer LBA from %"PRId64
" to %"PRId64
", "
1072 "drive max %"PRId64
"\n",
1073 ncq_tfs
->lba
, ncq_tfs
->lba
+ ncq_tfs
->sector_count
- 1,
1074 ide_state
->nb_sectors
- 1);
1076 execute_ncq_command(ncq_tfs
);
1079 static AHCICmdHdr
*get_cmd_header(AHCIState
*s
, uint8_t port
, uint8_t slot
)
1081 if (port
>= s
->ports
|| slot
>= AHCI_MAX_CMDS
) {
1085 return s
->dev
[port
].lst
? &((AHCICmdHdr
*)s
->dev
[port
].lst
)[slot
] : NULL
;
1088 static void handle_reg_h2d_fis(AHCIState
*s
, int port
,
1089 uint8_t slot
, uint8_t *cmd_fis
)
1091 IDEState
*ide_state
= &s
->dev
[port
].port
.ifs
[0];
1092 AHCICmdHdr
*cmd
= get_cmd_header(s
, port
, slot
);
1093 uint16_t opts
= le16_to_cpu(cmd
->opts
);
1095 if (cmd_fis
[1] & 0x0F) {
1096 DPRINTF(port
, "Port Multiplier not supported."
1097 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
1098 cmd_fis
[0], cmd_fis
[1], cmd_fis
[2]);
1102 if (cmd_fis
[1] & 0x70) {
1103 DPRINTF(port
, "Reserved flags set in H2D Register FIS."
1104 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
1105 cmd_fis
[0], cmd_fis
[1], cmd_fis
[2]);
1109 if (!(cmd_fis
[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
)) {
1110 switch (s
->dev
[port
].port_state
) {
1112 if (cmd_fis
[15] & ATA_SRST
) {
1113 s
->dev
[port
].port_state
= STATE_RESET
;
1117 if (!(cmd_fis
[15] & ATA_SRST
)) {
1118 ahci_reset_port(s
, port
);
1125 /* Check for NCQ command */
1126 if (is_ncq(cmd_fis
[2])) {
1127 process_ncq_command(s
, port
, cmd_fis
, slot
);
1131 /* Decompose the FIS:
1132 * AHCI does not interpret FIS packets, it only forwards them.
1133 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1134 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1136 * ATA4 describes sector number for LBA28/CHS commands.
1137 * ATA6 describes sector number for LBA48 commands.
1138 * ATA8 deprecates CHS fully, describing only LBA28/48.
1140 * We dutifully convert the FIS into IDE registers, and allow the
1141 * core layer to interpret them as needed. */
1142 ide_state
->feature
= cmd_fis
[3];
1143 ide_state
->sector
= cmd_fis
[4]; /* LBA 7:0 */
1144 ide_state
->lcyl
= cmd_fis
[5]; /* LBA 15:8 */
1145 ide_state
->hcyl
= cmd_fis
[6]; /* LBA 23:16 */
1146 ide_state
->select
= cmd_fis
[7]; /* LBA 27:24 (LBA28) */
1147 ide_state
->hob_sector
= cmd_fis
[8]; /* LBA 31:24 */
1148 ide_state
->hob_lcyl
= cmd_fis
[9]; /* LBA 39:32 */
1149 ide_state
->hob_hcyl
= cmd_fis
[10]; /* LBA 47:40 */
1150 ide_state
->hob_feature
= cmd_fis
[11];
1151 ide_state
->nsector
= (int64_t)((cmd_fis
[13] << 8) | cmd_fis
[12]);
1152 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1153 /* 15: Only valid when UPDATE_COMMAND not set. */
1155 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1156 * table to ide_state->io_buffer */
1157 if (opts
& AHCI_CMD_ATAPI
) {
1158 memcpy(ide_state
->io_buffer
, &cmd_fis
[AHCI_COMMAND_TABLE_ACMD
], 0x10);
1159 debug_print_fis(ide_state
->io_buffer
, 0x10);
1160 s
->dev
[port
].done_atapi_packet
= false;
1161 /* XXX send PIO setup FIS */
1164 ide_state
->error
= 0;
1166 /* Reset transferred byte counter */
1169 /* We're ready to process the command in FIS byte 2. */
1170 ide_exec_cmd(&s
->dev
[port
].port
, cmd_fis
[2]);
1173 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
)
1175 IDEState
*ide_state
;
1181 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1182 /* Engine currently busy, try again later */
1183 DPRINTF(port
, "engine busy\n");
1187 if (!s
->dev
[port
].lst
) {
1188 DPRINTF(port
, "error: lst not given but cmd handled");
1191 cmd
= get_cmd_header(s
, port
, slot
);
1192 /* remember current slot handle for later */
1193 s
->dev
[port
].cur_cmd
= cmd
;
1195 /* The device we are working for */
1196 ide_state
= &s
->dev
[port
].port
.ifs
[0];
1197 if (!ide_state
->blk
) {
1198 DPRINTF(port
, "error: guest accessed unused port");
1202 tbl_addr
= le64_to_cpu(cmd
->tbl_addr
);
1204 cmd_fis
= dma_memory_map(s
->as
, tbl_addr
, &cmd_len
,
1205 DMA_DIRECTION_FROM_DEVICE
);
1207 DPRINTF(port
, "error: guest passed us an invalid cmd fis\n");
1209 } else if (cmd_len
!= 0x80) {
1210 ahci_trigger_irq(s
, &s
->dev
[port
], PORT_IRQ_HBUS_ERR
);
1211 DPRINTF(port
, "error: dma_memory_map failed: "
1212 "(len(%02"PRIx64
") != 0x80)\n",
1216 debug_print_fis(cmd_fis
, 0x80);
1218 switch (cmd_fis
[0]) {
1219 case SATA_FIS_TYPE_REGISTER_H2D
:
1220 handle_reg_h2d_fis(s
, port
, slot
, cmd_fis
);
1223 DPRINTF(port
, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
1224 "cmd_fis[2]=%02x\n", cmd_fis
[0], cmd_fis
[1],
1230 dma_memory_unmap(s
->as
, cmd_fis
, cmd_len
, DMA_DIRECTION_FROM_DEVICE
,
1233 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1234 /* async command, complete later */
1235 s
->dev
[port
].busy_slot
= slot
;
1239 /* done handling the command */
1243 /* DMA dev <-> ram */
1244 static void ahci_start_transfer(IDEDMA
*dma
)
1246 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1247 IDEState
*s
= &ad
->port
.ifs
[0];
1248 uint32_t size
= (uint32_t)(s
->data_end
- s
->data_ptr
);
1249 /* write == ram -> device */
1250 uint16_t opts
= le16_to_cpu(ad
->cur_cmd
->opts
);
1251 int is_write
= opts
& AHCI_CMD_WRITE
;
1252 int is_atapi
= opts
& AHCI_CMD_ATAPI
;
1255 if (is_atapi
&& !ad
->done_atapi_packet
) {
1256 /* already prepopulated iobuffer */
1257 ad
->done_atapi_packet
= true;
1262 if (ahci_dma_prepare_buf(dma
, size
)) {
1266 DPRINTF(ad
->port_no
, "%sing %d bytes on %s w/%s sglist\n",
1267 is_write
? "writ" : "read", size
, is_atapi
? "atapi" : "ata",
1268 has_sglist
? "" : "o");
1270 if (has_sglist
&& size
) {
1272 dma_buf_write(s
->data_ptr
, size
, &s
->sg
);
1274 dma_buf_read(s
->data_ptr
, size
, &s
->sg
);
1279 /* declare that we processed everything */
1280 s
->data_ptr
= s
->data_end
;
1282 /* Update number of transferred bytes, destroy sglist */
1283 ahci_commit_buf(dma
, size
);
1285 s
->end_transfer_func(s
);
1287 if (!(s
->status
& DRQ_STAT
)) {
1288 /* done with PIO send/receive */
1289 ahci_write_fis_pio(ad
, le32_to_cpu(ad
->cur_cmd
->status
));
1293 static void ahci_start_dma(IDEDMA
*dma
, IDEState
*s
,
1294 BlockCompletionFunc
*dma_cb
)
1296 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1297 DPRINTF(ad
->port_no
, "\n");
1298 s
->io_buffer_offset
= 0;
1302 static void ahci_restart_dma(IDEDMA
*dma
)
1304 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1308 * IDE/PIO restarts are handled by the core layer, but NCQ commands
1309 * need an extra kick from the AHCI HBA.
1311 static void ahci_restart(IDEDMA
*dma
)
1313 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1316 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
1317 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[i
];
1318 if (ncq_tfs
->halt
) {
1319 execute_ncq_command(ncq_tfs
);
1325 * Called in DMA R/W chains to read the PRDT, utilizing ahci_populate_sglist.
1326 * Not currently invoked by PIO R/W chains,
1327 * which invoke ahci_populate_sglist via ahci_start_transfer.
1329 static int32_t ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
)
1331 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1332 IDEState
*s
= &ad
->port
.ifs
[0];
1334 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
,
1335 limit
, s
->io_buffer_offset
) == -1) {
1336 DPRINTF(ad
->port_no
, "ahci_dma_prepare_buf failed.\n");
1339 s
->io_buffer_size
= s
->sg
.size
;
1341 DPRINTF(ad
->port_no
, "len=%#x\n", s
->io_buffer_size
);
1342 return s
->io_buffer_size
;
1346 * Destroys the scatter-gather list,
1347 * and updates the command header with a bytes-read value.
1348 * called explicitly via ahci_dma_rw_buf (ATAPI DMA),
1349 * and ahci_start_transfer (PIO R/W),
1350 * and called via callback from ide_dma_cb for DMA R/W paths.
1352 static void ahci_commit_buf(IDEDMA
*dma
, uint32_t tx_bytes
)
1354 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1355 IDEState
*s
= &ad
->port
.ifs
[0];
1357 tx_bytes
+= le32_to_cpu(ad
->cur_cmd
->status
);
1358 ad
->cur_cmd
->status
= cpu_to_le32(tx_bytes
);
1360 qemu_sglist_destroy(&s
->sg
);
1363 static int ahci_dma_rw_buf(IDEDMA
*dma
, int is_write
)
1365 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1366 IDEState
*s
= &ad
->port
.ifs
[0];
1367 uint8_t *p
= s
->io_buffer
+ s
->io_buffer_index
;
1368 int l
= s
->io_buffer_size
- s
->io_buffer_index
;
1370 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
, l
, s
->io_buffer_offset
)) {
1375 dma_buf_read(p
, l
, &s
->sg
);
1377 dma_buf_write(p
, l
, &s
->sg
);
1380 /* free sglist, update byte count */
1381 ahci_commit_buf(dma
, l
);
1383 s
->io_buffer_index
+= l
;
1384 s
->io_buffer_offset
+= l
;
1386 DPRINTF(ad
->port_no
, "len=%#x\n", l
);
1391 static void ahci_cmd_done(IDEDMA
*dma
)
1393 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1395 DPRINTF(ad
->port_no
, "cmd done\n");
1397 /* update d2h status */
1398 ahci_write_fis_d2h(ad
, NULL
);
1400 if (!ad
->check_bh
) {
1401 /* maybe we still have something to process, check later */
1402 ad
->check_bh
= qemu_bh_new(ahci_check_cmd_bh
, ad
);
1403 qemu_bh_schedule(ad
->check_bh
);
1407 static void ahci_irq_set(void *opaque
, int n
, int level
)
1411 static const IDEDMAOps ahci_dma_ops
= {
1412 .start_dma
= ahci_start_dma
,
1413 .restart
= ahci_restart
,
1414 .restart_dma
= ahci_restart_dma
,
1415 .start_transfer
= ahci_start_transfer
,
1416 .prepare_buf
= ahci_dma_prepare_buf
,
1417 .commit_buf
= ahci_commit_buf
,
1418 .rw_buf
= ahci_dma_rw_buf
,
1419 .cmd_done
= ahci_cmd_done
,
1422 void ahci_init(AHCIState
*s
, DeviceState
*qdev
, AddressSpace
*as
, int ports
)
1429 s
->dev
= g_new0(AHCIDevice
, ports
);
1431 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1432 memory_region_init_io(&s
->mem
, OBJECT(qdev
), &ahci_mem_ops
, s
,
1433 "ahci", AHCI_MEM_BAR_SIZE
);
1434 memory_region_init_io(&s
->idp
, OBJECT(qdev
), &ahci_idp_ops
, s
,
1437 irqs
= qemu_allocate_irqs(ahci_irq_set
, s
, s
->ports
);
1439 for (i
= 0; i
< s
->ports
; i
++) {
1440 AHCIDevice
*ad
= &s
->dev
[i
];
1442 ide_bus_new(&ad
->port
, sizeof(ad
->port
), qdev
, i
, 1);
1443 ide_init2(&ad
->port
, irqs
[i
]);
1447 ad
->port
.dma
= &ad
->dma
;
1448 ad
->port
.dma
->ops
= &ahci_dma_ops
;
1449 ide_register_restart_cb(&ad
->port
);
1453 void ahci_uninit(AHCIState
*s
)
1458 void ahci_reset(AHCIState
*s
)
1463 s
->control_regs
.irqstatus
= 0;
1465 * The implementation of this bit is dependent upon the value of the
1466 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1467 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1468 * read-only and shall have a reset value of '1'.
1470 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1472 s
->control_regs
.ghc
= HOST_CTL_AHCI_EN
;
1474 for (i
= 0; i
< s
->ports
; i
++) {
1475 pr
= &s
->dev
[i
].port_regs
;
1479 pr
->cmd
= PORT_CMD_SPIN_UP
| PORT_CMD_POWER_ON
;
1480 ahci_reset_port(s
, i
);
1484 static const VMStateDescription vmstate_ncq_tfs
= {
1485 .name
= "ncq state",
1487 .fields
= (VMStateField
[]) {
1488 VMSTATE_UINT32(sector_count
, NCQTransferState
),
1489 VMSTATE_UINT64(lba
, NCQTransferState
),
1490 VMSTATE_UINT8(tag
, NCQTransferState
),
1491 VMSTATE_UINT8(cmd
, NCQTransferState
),
1492 VMSTATE_UINT8(slot
, NCQTransferState
),
1493 VMSTATE_BOOL(used
, NCQTransferState
),
1494 VMSTATE_BOOL(halt
, NCQTransferState
),
1495 VMSTATE_END_OF_LIST()
1499 static const VMStateDescription vmstate_ahci_device
= {
1500 .name
= "ahci port",
1502 .fields
= (VMStateField
[]) {
1503 VMSTATE_IDE_BUS(port
, AHCIDevice
),
1504 VMSTATE_IDE_DRIVE(port
.ifs
[0], AHCIDevice
),
1505 VMSTATE_UINT32(port_state
, AHCIDevice
),
1506 VMSTATE_UINT32(finished
, AHCIDevice
),
1507 VMSTATE_UINT32(port_regs
.lst_addr
, AHCIDevice
),
1508 VMSTATE_UINT32(port_regs
.lst_addr_hi
, AHCIDevice
),
1509 VMSTATE_UINT32(port_regs
.fis_addr
, AHCIDevice
),
1510 VMSTATE_UINT32(port_regs
.fis_addr_hi
, AHCIDevice
),
1511 VMSTATE_UINT32(port_regs
.irq_stat
, AHCIDevice
),
1512 VMSTATE_UINT32(port_regs
.irq_mask
, AHCIDevice
),
1513 VMSTATE_UINT32(port_regs
.cmd
, AHCIDevice
),
1514 VMSTATE_UINT32(port_regs
.tfdata
, AHCIDevice
),
1515 VMSTATE_UINT32(port_regs
.sig
, AHCIDevice
),
1516 VMSTATE_UINT32(port_regs
.scr_stat
, AHCIDevice
),
1517 VMSTATE_UINT32(port_regs
.scr_ctl
, AHCIDevice
),
1518 VMSTATE_UINT32(port_regs
.scr_err
, AHCIDevice
),
1519 VMSTATE_UINT32(port_regs
.scr_act
, AHCIDevice
),
1520 VMSTATE_UINT32(port_regs
.cmd_issue
, AHCIDevice
),
1521 VMSTATE_BOOL(done_atapi_packet
, AHCIDevice
),
1522 VMSTATE_INT32(busy_slot
, AHCIDevice
),
1523 VMSTATE_BOOL(init_d2h_sent
, AHCIDevice
),
1524 VMSTATE_STRUCT_ARRAY(ncq_tfs
, AHCIDevice
, AHCI_MAX_CMDS
,
1525 1, vmstate_ncq_tfs
, NCQTransferState
),
1526 VMSTATE_END_OF_LIST()
1530 static int ahci_state_post_load(void *opaque
, int version_id
)
1533 struct AHCIDevice
*ad
;
1534 NCQTransferState
*ncq_tfs
;
1535 AHCIState
*s
= opaque
;
1537 for (i
= 0; i
< s
->ports
; i
++) {
1540 /* Only remap the CLB address if appropriate, disallowing a state
1541 * transition from 'on' to 'off' it should be consistent here. */
1542 if (ahci_cond_start_engines(ad
, false) != 0) {
1546 for (j
= 0; j
< AHCI_MAX_CMDS
; j
++) {
1547 ncq_tfs
= &ad
->ncq_tfs
[j
];
1548 ncq_tfs
->drive
= ad
;
1550 if (ncq_tfs
->used
!= ncq_tfs
->halt
) {
1553 if (!ncq_tfs
->halt
) {
1556 if (!is_ncq(ncq_tfs
->cmd
)) {
1559 if (ncq_tfs
->slot
!= ncq_tfs
->tag
) {
1562 /* If ncq_tfs->halt is justly set, the engine should be engaged,
1563 * and the command list buffer should be mapped. */
1564 ncq_tfs
->cmdh
= get_cmd_header(s
, i
, ncq_tfs
->slot
);
1565 if (!ncq_tfs
->cmdh
) {
1568 ahci_populate_sglist(ncq_tfs
->drive
, &ncq_tfs
->sglist
,
1569 ncq_tfs
->cmdh
, ncq_tfs
->sector_count
* 512,
1571 if (ncq_tfs
->sector_count
!= ncq_tfs
->sglist
.size
>> 9) {
1578 * If an error is present, ad->busy_slot will be valid and not -1.
1579 * In this case, an operation is waiting to resume and will re-check
1580 * for additional AHCI commands to execute upon completion.
1582 * In the case where no error was present, busy_slot will be -1,
1583 * and we should check to see if there are additional commands waiting.
1585 if (ad
->busy_slot
== -1) {
1588 /* We are in the middle of a command, and may need to access
1589 * the command header in guest memory again. */
1590 if (ad
->busy_slot
< 0 || ad
->busy_slot
>= AHCI_MAX_CMDS
) {
1593 ad
->cur_cmd
= get_cmd_header(s
, i
, ad
->busy_slot
);
1600 const VMStateDescription vmstate_ahci
= {
1603 .post_load
= ahci_state_post_load
,
1604 .fields
= (VMStateField
[]) {
1605 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev
, AHCIState
, ports
,
1606 vmstate_ahci_device
, AHCIDevice
),
1607 VMSTATE_UINT32(control_regs
.cap
, AHCIState
),
1608 VMSTATE_UINT32(control_regs
.ghc
, AHCIState
),
1609 VMSTATE_UINT32(control_regs
.irqstatus
, AHCIState
),
1610 VMSTATE_UINT32(control_regs
.impl
, AHCIState
),
1611 VMSTATE_UINT32(control_regs
.version
, AHCIState
),
1612 VMSTATE_UINT32(idp_index
, AHCIState
),
1613 VMSTATE_INT32_EQUAL(ports
, AHCIState
),
1614 VMSTATE_END_OF_LIST()
1618 #define TYPE_SYSBUS_AHCI "sysbus-ahci"
1619 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
1621 typedef struct SysbusAHCIState
{
1623 SysBusDevice parent_obj
;
1630 static const VMStateDescription vmstate_sysbus_ahci
= {
1631 .name
= "sysbus-ahci",
1632 .fields
= (VMStateField
[]) {
1633 VMSTATE_AHCI(ahci
, SysbusAHCIState
),
1634 VMSTATE_END_OF_LIST()
1638 static void sysbus_ahci_reset(DeviceState
*dev
)
1640 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1642 ahci_reset(&s
->ahci
);
1645 static void sysbus_ahci_realize(DeviceState
*dev
, Error
**errp
)
1647 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1648 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1650 ahci_init(&s
->ahci
, dev
, &address_space_memory
, s
->num_ports
);
1652 sysbus_init_mmio(sbd
, &s
->ahci
.mem
);
1653 sysbus_init_irq(sbd
, &s
->ahci
.irq
);
1656 static Property sysbus_ahci_properties
[] = {
1657 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState
, num_ports
, 1),
1658 DEFINE_PROP_END_OF_LIST(),
1661 static void sysbus_ahci_class_init(ObjectClass
*klass
, void *data
)
1663 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1665 dc
->realize
= sysbus_ahci_realize
;
1666 dc
->vmsd
= &vmstate_sysbus_ahci
;
1667 dc
->props
= sysbus_ahci_properties
;
1668 dc
->reset
= sysbus_ahci_reset
;
1669 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1672 static const TypeInfo sysbus_ahci_info
= {
1673 .name
= TYPE_SYSBUS_AHCI
,
1674 .parent
= TYPE_SYS_BUS_DEVICE
,
1675 .instance_size
= sizeof(SysbusAHCIState
),
1676 .class_init
= sysbus_ahci_class_init
,
1679 static void sysbus_ahci_register_types(void)
1681 type_register_static(&sysbus_ahci_info
);
1684 type_init(sysbus_ahci_register_types
)
1686 void ahci_ide_create_devs(PCIDevice
*dev
, DriveInfo
**hd
)
1688 AHCIPCIState
*d
= ICH_AHCI(dev
);
1689 AHCIState
*ahci
= &d
->ahci
;
1692 for (i
= 0; i
< ahci
->ports
; i
++) {
1693 if (hd
[i
] == NULL
) {
1696 ide_create_drive(&ahci
->dev
[i
].port
, 0, hd
[i
]);