3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41 #include "exec/translator.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
46 #include "trace-tcg.h"
50 /* is_jmp field values */
51 #define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */
54 const XtensaConfig
*config
;
63 int singlestep_enabled
;
67 bool sar_m32_allocated
;
79 xtensa_insnbuf insnbuf
;
80 xtensa_insnbuf slotbuf
;
83 static TCGv_i32 cpu_pc
;
84 static TCGv_i32 cpu_R
[16];
85 static TCGv_i32 cpu_FR
[16];
86 static TCGv_i32 cpu_SR
[256];
87 static TCGv_i32 cpu_UR
[256];
89 #include "exec/gen-icount.h"
91 typedef struct XtensaReg
{
103 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
105 .opt_bits = XTENSA_OPTION_BIT(opt), \
109 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
111 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
117 #define XTENSA_REG_BITS(regname, opt) \
118 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
120 static const XtensaReg sregnames
[256] = {
121 [LBEG
] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP
),
122 [LEND
] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP
),
123 [LCOUNT
] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP
),
124 [SAR
] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL
),
125 [BR
] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN
),
126 [LITBASE
] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R
),
127 [SCOMPARE1
] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE
),
128 [ACCLO
] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16
),
129 [ACCHI
] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16
),
130 [MR
] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16
),
131 [MR
+ 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16
),
132 [MR
+ 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16
),
133 [MR
+ 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16
),
134 [WINDOW_BASE
] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER
),
135 [WINDOW_START
] = XTENSA_REG("WINDOW_START",
136 XTENSA_OPTION_WINDOWED_REGISTER
),
137 [PTEVADDR
] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU
),
138 [MMID
] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL
),
139 [RASID
] = XTENSA_REG("RASID", XTENSA_OPTION_MMU
),
140 [ITLBCFG
] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU
),
141 [DTLBCFG
] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU
),
142 [IBREAKENABLE
] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG
),
143 [MEMCTL
] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL
),
144 [CACHEATTR
] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR
),
145 [ATOMCTL
] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL
),
146 [DDR
] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG
),
147 [IBREAKA
] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG
),
148 [IBREAKA
+ 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG
),
149 [DBREAKA
] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG
),
150 [DBREAKA
+ 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG
),
151 [DBREAKC
] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG
),
152 [DBREAKC
+ 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG
),
153 [CONFIGID0
] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL
, SR_R
),
154 [EPC1
] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION
),
155 [EPC1
+ 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
156 [EPC1
+ 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
157 [EPC1
+ 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
158 [EPC1
+ 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
159 [EPC1
+ 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
160 [EPC1
+ 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
161 [DEPC
] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION
),
162 [EPS2
] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
163 [EPS2
+ 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
164 [EPS2
+ 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
165 [EPS2
+ 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
166 [EPS2
+ 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
167 [EPS2
+ 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
168 [CONFIGID1
] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL
, SR_R
),
169 [EXCSAVE1
] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION
),
170 [EXCSAVE1
+ 1] = XTENSA_REG("EXCSAVE2",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
172 [EXCSAVE1
+ 2] = XTENSA_REG("EXCSAVE3",
173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
174 [EXCSAVE1
+ 3] = XTENSA_REG("EXCSAVE4",
175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
176 [EXCSAVE1
+ 4] = XTENSA_REG("EXCSAVE5",
177 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
178 [EXCSAVE1
+ 5] = XTENSA_REG("EXCSAVE6",
179 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
180 [EXCSAVE1
+ 6] = XTENSA_REG("EXCSAVE7",
181 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
182 [CPENABLE
] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR
),
183 [INTSET
] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT
, SR_RW
),
184 [INTCLEAR
] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT
, SR_W
),
185 [INTENABLE
] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT
),
186 [PS
] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL
),
187 [VECBASE
] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR
),
188 [EXCCAUSE
] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION
),
189 [DEBUGCAUSE
] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG
, SR_R
),
190 [CCOUNT
] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT
),
191 [PRID
] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID
, SR_R
),
192 [ICOUNT
] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG
),
193 [ICOUNTLEVEL
] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG
),
194 [EXCVADDR
] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION
),
195 [CCOMPARE
] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT
),
196 [CCOMPARE
+ 1] = XTENSA_REG("CCOMPARE1",
197 XTENSA_OPTION_TIMER_INTERRUPT
),
198 [CCOMPARE
+ 2] = XTENSA_REG("CCOMPARE2",
199 XTENSA_OPTION_TIMER_INTERRUPT
),
200 [MISC
] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR
),
201 [MISC
+ 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR
),
202 [MISC
+ 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR
),
203 [MISC
+ 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR
),
206 static const XtensaReg uregnames
[256] = {
207 [EXPSTATE
] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL
),
208 [THREADPTR
] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER
),
209 [FCR
] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR
),
210 [FSR
] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR
),
213 void xtensa_translate_init(void)
215 static const char * const regnames
[] = {
216 "ar0", "ar1", "ar2", "ar3",
217 "ar4", "ar5", "ar6", "ar7",
218 "ar8", "ar9", "ar10", "ar11",
219 "ar12", "ar13", "ar14", "ar15",
221 static const char * const fregnames
[] = {
222 "f0", "f1", "f2", "f3",
223 "f4", "f5", "f6", "f7",
224 "f8", "f9", "f10", "f11",
225 "f12", "f13", "f14", "f15",
229 cpu_pc
= tcg_global_mem_new_i32(cpu_env
,
230 offsetof(CPUXtensaState
, pc
), "pc");
232 for (i
= 0; i
< 16; i
++) {
233 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
234 offsetof(CPUXtensaState
, regs
[i
]),
238 for (i
= 0; i
< 16; i
++) {
239 cpu_FR
[i
] = tcg_global_mem_new_i32(cpu_env
,
240 offsetof(CPUXtensaState
, fregs
[i
].f32
[FP_F32_LOW
]),
244 for (i
= 0; i
< 256; ++i
) {
245 if (sregnames
[i
].name
) {
246 cpu_SR
[i
] = tcg_global_mem_new_i32(cpu_env
,
247 offsetof(CPUXtensaState
, sregs
[i
]),
252 for (i
= 0; i
< 256; ++i
) {
253 if (uregnames
[i
].name
) {
254 cpu_UR
[i
] = tcg_global_mem_new_i32(cpu_env
,
255 offsetof(CPUXtensaState
, uregs
[i
]),
261 static inline bool option_enabled(DisasContext
*dc
, int opt
)
263 return xtensa_option_enabled(dc
->config
, opt
);
266 static void init_sar_tracker(DisasContext
*dc
)
268 dc
->sar_5bit
= false;
269 dc
->sar_m32_5bit
= false;
270 dc
->sar_m32_allocated
= false;
273 static void reset_sar_tracker(DisasContext
*dc
)
275 if (dc
->sar_m32_allocated
) {
276 tcg_temp_free(dc
->sar_m32
);
280 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
282 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
283 if (dc
->sar_m32_5bit
) {
284 tcg_gen_discard_i32(dc
->sar_m32
);
287 dc
->sar_m32_5bit
= false;
290 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
292 TCGv_i32 tmp
= tcg_const_i32(32);
293 if (!dc
->sar_m32_allocated
) {
294 dc
->sar_m32
= tcg_temp_local_new_i32();
295 dc
->sar_m32_allocated
= true;
297 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
298 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
299 dc
->sar_5bit
= false;
300 dc
->sar_m32_5bit
= true;
304 static void gen_exception(DisasContext
*dc
, int excp
)
306 TCGv_i32 tmp
= tcg_const_i32(excp
);
307 gen_helper_exception(cpu_env
, tmp
);
311 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
313 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
314 TCGv_i32 tcause
= tcg_const_i32(cause
);
315 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
317 tcg_temp_free(tcause
);
318 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
319 cause
== SYSCALL_CAUSE
) {
320 dc
->is_jmp
= DISAS_UPDATE
;
324 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
327 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
328 TCGv_i32 tcause
= tcg_const_i32(cause
);
329 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
331 tcg_temp_free(tcause
);
334 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
336 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
337 TCGv_i32 tcause
= tcg_const_i32(cause
);
338 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
340 tcg_temp_free(tcause
);
341 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
342 dc
->is_jmp
= DISAS_UPDATE
;
346 static bool gen_check_privilege(DisasContext
*dc
)
349 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
350 dc
->is_jmp
= DISAS_UPDATE
;
356 static bool gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
358 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
359 !(dc
->cpenable
& (1 << cp
))) {
360 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
361 dc
->is_jmp
= DISAS_UPDATE
;
367 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
369 tcg_gen_mov_i32(cpu_pc
, dest
);
371 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
373 if (dc
->singlestep_enabled
) {
374 gen_exception(dc
, EXCP_DEBUG
);
377 tcg_gen_goto_tb(slot
);
378 tcg_gen_exit_tb((uintptr_t)dc
->tb
+ slot
);
383 dc
->is_jmp
= DISAS_UPDATE
;
386 static void gen_jump(DisasContext
*dc
, TCGv dest
)
388 gen_jump_slot(dc
, dest
, -1);
391 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
393 TCGv_i32 tmp
= tcg_const_i32(dest
);
394 #ifndef CONFIG_USER_ONLY
395 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
399 gen_jump_slot(dc
, tmp
, slot
);
403 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
406 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
408 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
409 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
410 tcg_temp_free(tcallinc
);
411 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
412 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
413 gen_jump_slot(dc
, dest
, slot
);
416 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
418 gen_callw_slot(dc
, callinc
, dest
, -1);
421 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
423 TCGv_i32 tmp
= tcg_const_i32(dest
);
424 #ifndef CONFIG_USER_ONLY
425 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
429 gen_callw_slot(dc
, callinc
, tmp
, slot
);
433 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
435 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
436 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
437 dc
->next_pc
== dc
->lend
) {
438 TCGLabel
*label
= gen_new_label();
440 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
441 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
442 gen_jumpi(dc
, dc
->lbeg
, slot
);
443 gen_set_label(label
);
444 gen_jumpi(dc
, dc
->next_pc
, -1);
450 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
452 if (!gen_check_loop_end(dc
, slot
)) {
453 gen_jumpi(dc
, dc
->next_pc
, slot
);
457 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
458 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t addr
)
460 TCGLabel
*label
= gen_new_label();
462 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
463 gen_jumpi_check_loop_end(dc
, 0);
464 gen_set_label(label
);
465 gen_jumpi(dc
, addr
, 1);
468 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
469 TCGv_i32 t0
, uint32_t t1
, uint32_t addr
)
471 TCGv_i32 tmp
= tcg_const_i32(t1
);
472 gen_brcond(dc
, cond
, t0
, tmp
, addr
);
476 static bool gen_check_sr(DisasContext
*dc
, uint32_t sr
, unsigned access
)
478 if (!xtensa_option_bits_enabled(dc
->config
, sregnames
[sr
].opt_bits
)) {
479 if (sregnames
[sr
].name
) {
480 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not configured\n", sregnames
[sr
].name
);
482 qemu_log_mask(LOG_UNIMP
, "SR %d is not implemented\n", sr
);
484 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
486 } else if (!(sregnames
[sr
].access
& access
)) {
487 static const char * const access_text
[] = {
492 assert(access
< ARRAY_SIZE(access_text
) && access_text
[access
]);
493 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not available for %s\n", sregnames
[sr
].name
,
494 access_text
[access
]);
495 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
501 static bool gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
503 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
506 gen_helper_update_ccount(cpu_env
);
507 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
508 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
515 static bool gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
517 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
518 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
519 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
523 static bool gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
525 static bool (* const rsr_handler
[256])(DisasContext
*dc
,
526 TCGv_i32 d
, uint32_t sr
) = {
527 [CCOUNT
] = gen_rsr_ccount
,
528 [INTSET
] = gen_rsr_ccount
,
529 [PTEVADDR
] = gen_rsr_ptevaddr
,
532 if (rsr_handler
[sr
]) {
533 return rsr_handler
[sr
](dc
, d
, sr
);
535 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
540 static bool gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
542 gen_helper_wsr_lbeg(cpu_env
, s
);
543 gen_jumpi_check_loop_end(dc
, 0);
547 static bool gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
549 gen_helper_wsr_lend(cpu_env
, s
);
550 gen_jumpi_check_loop_end(dc
, 0);
554 static bool gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
556 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
557 if (dc
->sar_m32_5bit
) {
558 tcg_gen_discard_i32(dc
->sar_m32
);
560 dc
->sar_5bit
= false;
561 dc
->sar_m32_5bit
= false;
565 static bool gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
567 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
571 static bool gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
573 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
574 /* This can change tb->flags, so exit tb */
575 gen_jumpi_check_loop_end(dc
, -1);
579 static bool gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
581 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
585 static bool gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
587 gen_helper_wsr_windowbase(cpu_env
, v
);
588 /* This can change tb->flags, so exit tb */
589 gen_jumpi_check_loop_end(dc
, -1);
593 static bool gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
595 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
596 /* This can change tb->flags, so exit tb */
597 gen_jumpi_check_loop_end(dc
, -1);
601 static bool gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
603 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
607 static bool gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
609 gen_helper_wsr_rasid(cpu_env
, v
);
610 /* This can change tb->flags, so exit tb */
611 gen_jumpi_check_loop_end(dc
, -1);
615 static bool gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
617 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
621 static bool gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
623 gen_helper_wsr_ibreakenable(cpu_env
, v
);
624 gen_jumpi_check_loop_end(dc
, 0);
628 static bool gen_wsr_memctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
630 gen_helper_wsr_memctl(cpu_env
, v
);
634 static bool gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
636 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
640 static bool gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
642 unsigned id
= sr
- IBREAKA
;
644 if (id
< dc
->config
->nibreak
) {
645 TCGv_i32 tmp
= tcg_const_i32(id
);
646 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
648 gen_jumpi_check_loop_end(dc
, 0);
654 static bool gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
656 unsigned id
= sr
- DBREAKA
;
658 if (id
< dc
->config
->ndbreak
) {
659 TCGv_i32 tmp
= tcg_const_i32(id
);
660 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
666 static bool gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
668 unsigned id
= sr
- DBREAKC
;
670 if (id
< dc
->config
->ndbreak
) {
671 TCGv_i32 tmp
= tcg_const_i32(id
);
672 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
678 static bool gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
680 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
681 /* This can change tb->flags, so exit tb */
682 gen_jumpi_check_loop_end(dc
, -1);
686 static void gen_check_interrupts(DisasContext
*dc
)
688 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
691 gen_helper_check_interrupts(cpu_env
);
692 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
697 static bool gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
699 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
700 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
701 gen_check_interrupts(dc
);
702 gen_jumpi_check_loop_end(dc
, 0);
706 static bool gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
708 TCGv_i32 tmp
= tcg_temp_new_i32();
710 tcg_gen_andi_i32(tmp
, v
,
711 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
712 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
713 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
714 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
716 gen_check_interrupts(dc
);
717 gen_jumpi_check_loop_end(dc
, 0);
721 static bool gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
723 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
724 gen_check_interrupts(dc
);
725 gen_jumpi_check_loop_end(dc
, 0);
729 static bool gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
731 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
732 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
734 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
737 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
738 gen_check_interrupts(dc
);
739 /* This can change mmu index and tb->flags, so exit tb */
740 gen_jumpi_check_loop_end(dc
, -1);
744 static bool gen_wsr_ccount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
746 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
749 gen_helper_wsr_ccount(cpu_env
, v
);
750 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
752 gen_jumpi_check_loop_end(dc
, 0);
758 static bool gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
761 tcg_gen_mov_i32(dc
->next_icount
, v
);
763 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
768 static bool gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
770 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
771 /* This can change tb->flags, so exit tb */
772 gen_jumpi_check_loop_end(dc
, -1);
776 static bool gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
778 uint32_t id
= sr
- CCOMPARE
;
781 if (id
< dc
->config
->nccompare
) {
782 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
783 TCGv_i32 tmp
= tcg_const_i32(id
);
785 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
786 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
787 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
790 gen_helper_update_ccompare(cpu_env
, tmp
);
791 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
793 gen_jumpi_check_loop_end(dc
, 0);
801 static bool gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
803 static bool (* const wsr_handler
[256])(DisasContext
*dc
,
804 uint32_t sr
, TCGv_i32 v
) = {
805 [LBEG
] = gen_wsr_lbeg
,
806 [LEND
] = gen_wsr_lend
,
809 [LITBASE
] = gen_wsr_litbase
,
810 [ACCHI
] = gen_wsr_acchi
,
811 [WINDOW_BASE
] = gen_wsr_windowbase
,
812 [WINDOW_START
] = gen_wsr_windowstart
,
813 [PTEVADDR
] = gen_wsr_ptevaddr
,
814 [RASID
] = gen_wsr_rasid
,
815 [ITLBCFG
] = gen_wsr_tlbcfg
,
816 [DTLBCFG
] = gen_wsr_tlbcfg
,
817 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
818 [MEMCTL
] = gen_wsr_memctl
,
819 [ATOMCTL
] = gen_wsr_atomctl
,
820 [IBREAKA
] = gen_wsr_ibreaka
,
821 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
822 [DBREAKA
] = gen_wsr_dbreaka
,
823 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
824 [DBREAKC
] = gen_wsr_dbreakc
,
825 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
826 [CPENABLE
] = gen_wsr_cpenable
,
827 [INTSET
] = gen_wsr_intset
,
828 [INTCLEAR
] = gen_wsr_intclear
,
829 [INTENABLE
] = gen_wsr_intenable
,
831 [CCOUNT
] = gen_wsr_ccount
,
832 [ICOUNT
] = gen_wsr_icount
,
833 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
834 [CCOMPARE
] = gen_wsr_ccompare
,
835 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
836 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
839 if (wsr_handler
[sr
]) {
840 return wsr_handler
[sr
](dc
, sr
, s
);
842 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
847 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
851 gen_helper_wur_fcr(cpu_env
, s
);
855 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
859 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
864 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
865 TCGv_i32 addr
, bool no_hw_alignment
)
867 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
868 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
869 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
871 TCGLabel
*label
= gen_new_label();
872 TCGv_i32 tmp
= tcg_temp_new_i32();
873 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
874 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
875 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
876 gen_set_label(label
);
881 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
883 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
884 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
886 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
889 gen_helper_waiti(cpu_env
, pc
, intlevel
);
890 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
894 tcg_temp_free(intlevel
);
895 gen_jumpi_check_loop_end(dc
, 0);
898 static bool gen_window_check1(DisasContext
*dc
, unsigned r1
)
900 if (r1
/ 4 > dc
->window
) {
901 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
902 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
904 gen_helper_window_check(cpu_env
, pc
, w
);
905 dc
->is_jmp
= DISAS_UPDATE
;
911 static bool gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
913 return gen_window_check1(dc
, r1
> r2
? r1
: r2
);
916 static bool gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
919 return gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
922 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
924 TCGv_i32 m
= tcg_temp_new_i32();
927 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
929 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
934 static inline unsigned xtensa_op0_insn_len(DisasContext
*dc
, uint8_t op0
)
936 return xtensa_isa_length_from_chars(dc
->config
->isa
, &op0
);
939 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
941 xtensa_isa isa
= dc
->config
->isa
;
942 unsigned char b
[MAX_INSN_LENGTH
] = {cpu_ldub_code(env
, dc
->pc
)};
943 unsigned len
= xtensa_op0_insn_len(dc
, b
[0]);
945 unsigned slot
, slots
;
948 if (len
== XTENSA_UNDEFINED
) {
949 qemu_log_mask(LOG_GUEST_ERROR
,
950 "unknown instruction length (pc = %08x)\n",
952 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
956 dc
->next_pc
= dc
->pc
+ len
;
957 for (i
= 1; i
< len
; ++i
) {
958 b
[i
] = cpu_ldub_code(env
, dc
->pc
+ i
);
960 xtensa_insnbuf_from_chars(isa
, dc
->insnbuf
, b
, len
);
961 fmt
= xtensa_format_decode(isa
, dc
->insnbuf
);
962 if (fmt
== XTENSA_UNDEFINED
) {
963 qemu_log_mask(LOG_GUEST_ERROR
,
964 "unrecognized instruction format (pc = %08x)\n",
966 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
969 slots
= xtensa_format_num_slots(isa
, fmt
);
970 for (slot
= 0; slot
< slots
; ++slot
) {
972 unsigned opnd
, vopnd
, opnds
;
973 uint32_t raw_arg
[MAX_OPCODE_ARGS
];
974 uint32_t arg
[MAX_OPCODE_ARGS
];
975 XtensaOpcodeOps
*ops
;
977 dc
->raw_arg
= raw_arg
;
979 xtensa_format_get_slot(isa
, fmt
, slot
, dc
->insnbuf
, dc
->slotbuf
);
980 opc
= xtensa_opcode_decode(isa
, fmt
, slot
, dc
->slotbuf
);
981 if (opc
== XTENSA_UNDEFINED
) {
982 qemu_log_mask(LOG_GUEST_ERROR
,
983 "unrecognized opcode in slot %d (pc = %08x)\n",
985 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
988 opnds
= xtensa_opcode_num_operands(isa
, opc
);
990 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
991 if (xtensa_operand_is_visible(isa
, opc
, opnd
)) {
994 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
996 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
998 if (xtensa_operand_is_PCrelative(isa
, opc
, opnd
)) {
999 xtensa_operand_undo_reloc(isa
, opc
, opnd
, &v
, dc
->pc
);
1005 ops
= dc
->config
->opcode_ops
[opc
];
1007 ops
->translate(dc
, arg
, ops
->par
);
1009 qemu_log_mask(LOG_GUEST_ERROR
,
1010 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
1011 xtensa_opcode_name(isa
, opc
), slot
, dc
->pc
);
1012 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1016 if (dc
->is_jmp
== DISAS_NEXT
) {
1017 gen_check_loop_end(dc
, 0);
1019 dc
->pc
= dc
->next_pc
;
1022 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
1024 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
1025 return xtensa_op0_insn_len(dc
, b0
);
1028 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
1032 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
1033 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
1034 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
1035 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
1041 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
1043 CPUXtensaState
*env
= cs
->env_ptr
;
1046 int max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
1047 uint32_t pc_start
= tb
->pc
;
1048 uint32_t next_page_start
=
1049 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1051 if (max_insns
== 0) {
1052 max_insns
= CF_COUNT_MASK
;
1054 if (max_insns
> TCG_MAX_INSNS
) {
1055 max_insns
= TCG_MAX_INSNS
;
1058 dc
.config
= env
->config
;
1059 dc
.singlestep_enabled
= cs
->singlestep_enabled
;
1062 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
1063 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
1064 dc
.lbeg
= env
->sregs
[LBEG
];
1065 dc
.lend
= env
->sregs
[LEND
];
1066 dc
.is_jmp
= DISAS_NEXT
;
1067 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
1068 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
1069 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
1070 XTENSA_TBFLAG_CPENABLE_SHIFT
;
1071 dc
.window
= ((tb
->flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
1072 XTENSA_TBFLAG_WINDOW_SHIFT
);
1074 if (dc
.config
->isa
) {
1075 dc
.insnbuf
= xtensa_insnbuf_alloc(dc
.config
->isa
);
1076 dc
.slotbuf
= xtensa_insnbuf_alloc(dc
.config
->isa
);
1079 init_sar_tracker(&dc
);
1081 dc
.next_icount
= tcg_temp_local_new_i32();
1086 if ((tb_cflags(tb
) & CF_USE_ICOUNT
) &&
1087 (tb
->flags
& XTENSA_TBFLAG_YIELD
)) {
1088 tcg_gen_insn_start(dc
.pc
);
1090 gen_exception(&dc
, EXCP_YIELD
);
1091 dc
.is_jmp
= DISAS_UPDATE
;
1094 if (tb
->flags
& XTENSA_TBFLAG_EXCEPTION
) {
1095 tcg_gen_insn_start(dc
.pc
);
1097 gen_exception(&dc
, EXCP_DEBUG
);
1098 dc
.is_jmp
= DISAS_UPDATE
;
1103 tcg_gen_insn_start(dc
.pc
);
1106 if (unlikely(cpu_breakpoint_test(cs
, dc
.pc
, BP_ANY
))) {
1107 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1108 gen_exception(&dc
, EXCP_DEBUG
);
1109 dc
.is_jmp
= DISAS_UPDATE
;
1110 /* The address covered by the breakpoint must be included in
1111 [tb->pc, tb->pc + tb->size) in order to for it to be
1112 properly cleared -- thus we increment the PC here so that
1113 the logic setting tb->size below does the right thing. */
1118 if (insn_count
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
1123 TCGLabel
*label
= gen_new_label();
1125 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
1126 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
1127 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
1129 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
1131 gen_set_label(label
);
1135 gen_ibreak_check(env
, &dc
);
1138 disas_xtensa_insn(env
, &dc
);
1140 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
1142 if (cs
->singlestep_enabled
) {
1143 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1144 gen_exception(&dc
, EXCP_DEBUG
);
1147 } while (dc
.is_jmp
== DISAS_NEXT
&&
1148 insn_count
< max_insns
&&
1149 dc
.pc
< next_page_start
&&
1150 dc
.pc
+ xtensa_insn_len(env
, &dc
) <= next_page_start
&&
1151 !tcg_op_buf_full());
1153 reset_sar_tracker(&dc
);
1155 tcg_temp_free(dc
.next_icount
);
1157 if (dc
.config
->isa
) {
1158 xtensa_insnbuf_free(dc
.config
->isa
, dc
.insnbuf
);
1159 xtensa_insnbuf_free(dc
.config
->isa
, dc
.slotbuf
);
1162 if (tb_cflags(tb
) & CF_LAST_IO
) {
1166 if (dc
.is_jmp
== DISAS_NEXT
) {
1167 gen_jumpi(&dc
, dc
.pc
, 0);
1169 gen_tb_end(tb
, insn_count
);
1172 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
1173 && qemu_log_in_addr_range(pc_start
)) {
1175 qemu_log("----------------\n");
1176 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
1177 log_target_disas(cs
, pc_start
, dc
.pc
- pc_start
);
1182 tb
->size
= dc
.pc
- pc_start
;
1183 tb
->icount
= insn_count
;
1186 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
,
1187 fprintf_function cpu_fprintf
, int flags
)
1189 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
1190 CPUXtensaState
*env
= &cpu
->env
;
1193 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1195 for (i
= j
= 0; i
< 256; ++i
) {
1196 if (xtensa_option_bits_enabled(env
->config
, sregnames
[i
].opt_bits
)) {
1197 cpu_fprintf(f
, "%12s=%08x%c", sregnames
[i
].name
, env
->sregs
[i
],
1198 (j
++ % 4) == 3 ? '\n' : ' ');
1202 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1204 for (i
= j
= 0; i
< 256; ++i
) {
1205 if (xtensa_option_bits_enabled(env
->config
, uregnames
[i
].opt_bits
)) {
1206 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
].name
, env
->uregs
[i
],
1207 (j
++ % 4) == 3 ? '\n' : ' ');
1211 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1213 for (i
= 0; i
< 16; ++i
) {
1214 cpu_fprintf(f
, " A%02d=%08x%c", i
, env
->regs
[i
],
1215 (i
% 4) == 3 ? '\n' : ' ');
1218 cpu_fprintf(f
, "\n");
1220 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
1221 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
1222 (i
% 4) == 3 ? '\n' : ' ');
1225 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
1226 cpu_fprintf(f
, "\n");
1228 for (i
= 0; i
< 16; ++i
) {
1229 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
1230 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
1231 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
1232 (i
% 2) == 1 ? '\n' : ' ');
1237 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
,
1243 static int compare_opcode_ops(const void *a
, const void *b
)
1245 return strcmp((const char *)a
,
1246 ((const XtensaOpcodeOps
*)b
)->name
);
1250 xtensa_find_opcode_ops(const XtensaOpcodeTranslators
*t
,
1253 XtensaOpcodeOps
*ops
;
1255 ops
= bsearch(name
, t
->opcode
, t
->num_opcodes
,
1256 sizeof(XtensaOpcodeOps
), compare_opcode_ops
);
1260 static void translate_abs(DisasContext
*dc
, const uint32_t arg
[],
1261 const uint32_t par
[])
1263 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1264 TCGv_i32 zero
= tcg_const_i32(0);
1265 TCGv_i32 neg
= tcg_temp_new_i32();
1267 tcg_gen_neg_i32(neg
, cpu_R
[arg
[1]]);
1268 tcg_gen_movcond_i32(TCG_COND_GE
, cpu_R
[arg
[0]],
1269 cpu_R
[arg
[1]], zero
, cpu_R
[arg
[1]], neg
);
1271 tcg_temp_free(zero
);
1275 static void translate_add(DisasContext
*dc
, const uint32_t arg
[],
1276 const uint32_t par
[])
1278 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1279 tcg_gen_add_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1283 static void translate_addi(DisasContext
*dc
, const uint32_t arg
[],
1284 const uint32_t par
[])
1286 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1287 tcg_gen_addi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1291 static void translate_addx(DisasContext
*dc
, const uint32_t arg
[],
1292 const uint32_t par
[])
1294 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1295 TCGv_i32 tmp
= tcg_temp_new_i32();
1296 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
1297 tcg_gen_add_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
1302 static void translate_all(DisasContext
*dc
, const uint32_t arg
[],
1303 const uint32_t par
[])
1305 uint32_t shift
= par
[1];
1306 TCGv_i32 mask
= tcg_const_i32(((1 << shift
) - 1) << arg
[1]);
1307 TCGv_i32 tmp
= tcg_temp_new_i32();
1309 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1311 tcg_gen_addi_i32(tmp
, tmp
, 1 << arg
[1]);
1313 tcg_gen_add_i32(tmp
, tmp
, mask
);
1315 tcg_gen_shri_i32(tmp
, tmp
, arg
[1] + shift
);
1316 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1318 tcg_temp_free(mask
);
1322 static void translate_and(DisasContext
*dc
, const uint32_t arg
[],
1323 const uint32_t par
[])
1325 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1326 tcg_gen_and_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1330 static void translate_ball(DisasContext
*dc
, const uint32_t arg
[],
1331 const uint32_t par
[])
1333 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1334 TCGv_i32 tmp
= tcg_temp_new_i32();
1335 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1336 gen_brcond(dc
, par
[0], tmp
, cpu_R
[arg
[1]], arg
[2]);
1341 static void translate_bany(DisasContext
*dc
, const uint32_t arg
[],
1342 const uint32_t par
[])
1344 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1345 TCGv_i32 tmp
= tcg_temp_new_i32();
1346 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1347 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1352 static void translate_b(DisasContext
*dc
, const uint32_t arg
[],
1353 const uint32_t par
[])
1355 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1356 gen_brcond(dc
, par
[0], cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1360 static void translate_bb(DisasContext
*dc
, const uint32_t arg
[],
1361 const uint32_t par
[])
1363 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1364 #ifdef TARGET_WORDS_BIGENDIAN
1365 TCGv_i32 bit
= tcg_const_i32(0x80000000u
);
1367 TCGv_i32 bit
= tcg_const_i32(0x00000001u
);
1369 TCGv_i32 tmp
= tcg_temp_new_i32();
1370 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[1]], 0x1f);
1371 #ifdef TARGET_WORDS_BIGENDIAN
1372 tcg_gen_shr_i32(bit
, bit
, tmp
);
1374 tcg_gen_shl_i32(bit
, bit
, tmp
);
1376 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], bit
);
1377 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1383 static void translate_bbi(DisasContext
*dc
, const uint32_t arg
[],
1384 const uint32_t par
[])
1386 if (gen_window_check1(dc
, arg
[0])) {
1387 TCGv_i32 tmp
= tcg_temp_new_i32();
1388 #ifdef TARGET_WORDS_BIGENDIAN
1389 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x80000000u
>> arg
[1]);
1391 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x00000001u
<< arg
[1]);
1393 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1398 static void translate_bi(DisasContext
*dc
, const uint32_t arg
[],
1399 const uint32_t par
[])
1401 if (gen_window_check1(dc
, arg
[0])) {
1402 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], arg
[1], arg
[2]);
1406 static void translate_bz(DisasContext
*dc
, const uint32_t arg
[],
1407 const uint32_t par
[])
1409 if (gen_window_check1(dc
, arg
[0])) {
1410 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], 0, arg
[1]);
1422 static void translate_boolean(DisasContext
*dc
, const uint32_t arg
[],
1423 const uint32_t par
[])
1425 static void (* const op
[])(TCGv_i32
, TCGv_i32
, TCGv_i32
) = {
1426 [BOOLEAN_AND
] = tcg_gen_and_i32
,
1427 [BOOLEAN_ANDC
] = tcg_gen_andc_i32
,
1428 [BOOLEAN_OR
] = tcg_gen_or_i32
,
1429 [BOOLEAN_ORC
] = tcg_gen_orc_i32
,
1430 [BOOLEAN_XOR
] = tcg_gen_xor_i32
,
1433 TCGv_i32 tmp1
= tcg_temp_new_i32();
1434 TCGv_i32 tmp2
= tcg_temp_new_i32();
1436 tcg_gen_shri_i32(tmp1
, cpu_SR
[BR
], arg
[1]);
1437 tcg_gen_shri_i32(tmp2
, cpu_SR
[BR
], arg
[2]);
1438 op
[par
[0]](tmp1
, tmp1
, tmp2
);
1439 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
], tmp1
, arg
[0], 1);
1440 tcg_temp_free(tmp1
);
1441 tcg_temp_free(tmp2
);
1444 static void translate_bp(DisasContext
*dc
, const uint32_t arg
[],
1445 const uint32_t par
[])
1447 TCGv_i32 tmp
= tcg_temp_new_i32();
1449 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[0]);
1450 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[1]);
1454 static void translate_break(DisasContext
*dc
, const uint32_t arg
[],
1455 const uint32_t par
[])
1458 gen_debug_exception(dc
, par
[0]);
1462 static void translate_call0(DisasContext
*dc
, const uint32_t arg
[],
1463 const uint32_t par
[])
1465 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1466 gen_jumpi(dc
, arg
[0], 0);
1469 static void translate_callw(DisasContext
*dc
, const uint32_t arg
[],
1470 const uint32_t par
[])
1472 if (gen_window_check1(dc
, par
[0] << 2)) {
1473 gen_callwi(dc
, par
[0], arg
[0], 0);
1477 static void translate_callx0(DisasContext
*dc
, const uint32_t arg
[],
1478 const uint32_t par
[])
1480 if (gen_window_check1(dc
, arg
[0])) {
1481 TCGv_i32 tmp
= tcg_temp_new_i32();
1482 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1483 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1489 static void translate_callxw(DisasContext
*dc
, const uint32_t arg
[],
1490 const uint32_t par
[])
1492 if (gen_window_check2(dc
, arg
[0], par
[0] << 2)) {
1493 TCGv_i32 tmp
= tcg_temp_new_i32();
1495 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1496 gen_callw(dc
, par
[0], tmp
);
1501 static void translate_clamps(DisasContext
*dc
, const uint32_t arg
[],
1502 const uint32_t par
[])
1504 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1505 TCGv_i32 tmp1
= tcg_const_i32(-1u << arg
[2]);
1506 TCGv_i32 tmp2
= tcg_const_i32((1 << arg
[2]) - 1);
1508 tcg_gen_movcond_i32(TCG_COND_GT
, tmp1
,
1509 cpu_R
[arg
[1]], tmp1
, cpu_R
[arg
[1]], tmp1
);
1510 tcg_gen_movcond_i32(TCG_COND_LT
, cpu_R
[arg
[0]],
1511 tmp1
, tmp2
, tmp1
, tmp2
);
1512 tcg_temp_free(tmp1
);
1513 tcg_temp_free(tmp2
);
1517 static void translate_clrb_expstate(DisasContext
*dc
, const uint32_t arg
[],
1518 const uint32_t par
[])
1520 /* TODO: GPIO32 may be a part of coprocessor */
1521 tcg_gen_andi_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], ~(1u << arg
[0]));
1524 static void translate_const16(DisasContext
*dc
, const uint32_t arg
[],
1525 const uint32_t par
[])
1527 if (gen_window_check1(dc
, arg
[0])) {
1528 TCGv_i32 c
= tcg_const_i32(arg
[1]);
1530 tcg_gen_deposit_i32(cpu_R
[arg
[0]], c
, cpu_R
[arg
[0]], 16, 16);
1535 /* par[0]: privileged, par[1]: check memory access */
1536 static void translate_dcache(DisasContext
*dc
, const uint32_t arg
[],
1537 const uint32_t par
[])
1539 if ((!par
[0] || gen_check_privilege(dc
)) &&
1540 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1541 TCGv_i32 addr
= tcg_temp_new_i32();
1542 TCGv_i32 res
= tcg_temp_new_i32();
1544 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1545 tcg_gen_qemu_ld8u(res
, addr
, dc
->cring
);
1546 tcg_temp_free(addr
);
1551 static void translate_depbits(DisasContext
*dc
, const uint32_t arg
[],
1552 const uint32_t par
[])
1554 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1555 tcg_gen_deposit_i32(cpu_R
[arg
[1]], cpu_R
[arg
[1]], cpu_R
[arg
[0]],
1560 static void translate_entry(DisasContext
*dc
, const uint32_t arg
[],
1561 const uint32_t par
[])
1563 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1564 TCGv_i32 s
= tcg_const_i32(arg
[0]);
1565 TCGv_i32 imm
= tcg_const_i32(arg
[1]);
1566 gen_helper_entry(cpu_env
, pc
, s
, imm
);
1570 /* This can change tb->flags, so exit tb */
1571 gen_jumpi_check_loop_end(dc
, -1);
1574 static void translate_extui(DisasContext
*dc
, const uint32_t arg
[],
1575 const uint32_t par
[])
1577 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1578 int maskimm
= (1 << arg
[3]) - 1;
1580 TCGv_i32 tmp
= tcg_temp_new_i32();
1581 tcg_gen_shri_i32(tmp
, cpu_R
[arg
[1]], arg
[2]);
1582 tcg_gen_andi_i32(cpu_R
[arg
[0]], tmp
, maskimm
);
1587 /* par[0]: privileged, par[1]: check memory access */
1588 static void translate_icache(DisasContext
*dc
, const uint32_t arg
[],
1589 const uint32_t par
[])
1591 if ((!par
[0] || gen_check_privilege(dc
)) &&
1592 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1593 TCGv_i32 addr
= tcg_temp_new_i32();
1595 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1596 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1597 gen_helper_itlb_hit_test(cpu_env
, addr
);
1598 tcg_temp_free(addr
);
1602 static void translate_itlb(DisasContext
*dc
, const uint32_t arg
[],
1603 const uint32_t par
[])
1605 if (gen_check_privilege(dc
) &&
1606 gen_window_check1(dc
, arg
[0])) {
1607 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
1609 gen_helper_itlb(cpu_env
, cpu_R
[arg
[0]], dtlb
);
1610 /* This could change memory mapping, so exit tb */
1611 gen_jumpi_check_loop_end(dc
, -1);
1612 tcg_temp_free(dtlb
);
1616 static void translate_ill(DisasContext
*dc
, const uint32_t arg
[],
1617 const uint32_t par
[])
1619 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1622 static void translate_j(DisasContext
*dc
, const uint32_t arg
[],
1623 const uint32_t par
[])
1625 gen_jumpi(dc
, arg
[0], 0);
1628 static void translate_jx(DisasContext
*dc
, const uint32_t arg
[],
1629 const uint32_t par
[])
1631 if (gen_window_check1(dc
, arg
[0])) {
1632 gen_jump(dc
, cpu_R
[arg
[0]]);
1636 static void translate_l32e(DisasContext
*dc
, const uint32_t arg
[],
1637 const uint32_t par
[])
1639 if (gen_check_privilege(dc
) &&
1640 gen_window_check2(dc
, arg
[0], arg
[1])) {
1641 TCGv_i32 addr
= tcg_temp_new_i32();
1643 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1644 gen_load_store_alignment(dc
, 2, addr
, false);
1645 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
1646 tcg_temp_free(addr
);
1650 static void translate_ldst(DisasContext
*dc
, const uint32_t arg
[],
1651 const uint32_t par
[])
1653 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1654 TCGv_i32 addr
= tcg_temp_new_i32();
1656 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1657 if (par
[0] & MO_SIZE
) {
1658 gen_load_store_alignment(dc
, par
[0] & MO_SIZE
, addr
, par
[1]);
1661 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1663 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1665 tcg_temp_free(addr
);
1669 static void translate_l32r(DisasContext
*dc
, const uint32_t arg
[],
1670 const uint32_t par
[])
1672 if (gen_window_check1(dc
, arg
[0])) {
1675 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1676 tmp
= tcg_const_i32(dc
->raw_arg
[1] - 1);
1677 tcg_gen_add_i32(tmp
, cpu_SR
[LITBASE
], tmp
);
1679 tmp
= tcg_const_i32(arg
[1]);
1681 tcg_gen_qemu_ld32u(cpu_R
[arg
[0]], tmp
, dc
->cring
);
1686 static void translate_loop(DisasContext
*dc
, const uint32_t arg
[],
1687 const uint32_t par
[])
1689 if (gen_window_check1(dc
, arg
[0])) {
1690 uint32_t lend
= arg
[1];
1691 TCGv_i32 tmp
= tcg_const_i32(lend
);
1693 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[arg
[0]], 1);
1694 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
1695 gen_helper_wsr_lend(cpu_env
, tmp
);
1698 if (par
[0] != TCG_COND_NEVER
) {
1699 TCGLabel
*label
= gen_new_label();
1700 tcg_gen_brcondi_i32(par
[0], cpu_R
[arg
[0]], 0, label
);
1701 gen_jumpi(dc
, lend
, 1);
1702 gen_set_label(label
);
1705 gen_jumpi(dc
, dc
->next_pc
, 0);
1737 static void translate_mac16(DisasContext
*dc
, const uint32_t arg
[],
1738 const uint32_t par
[])
1741 bool is_m1_sr
= par
[1] & MAC16_DX
;
1742 bool is_m2_sr
= par
[1] & MAC16_XD
;
1743 unsigned half
= par
[2];
1744 uint32_t ld_offset
= par
[3];
1745 unsigned off
= ld_offset
? 2 : 0;
1746 uint32_t ar
[3] = {0};
1749 if (op
!= MAC16_NONE
) {
1751 ar
[n_ar
++] = arg
[off
];
1754 ar
[n_ar
++] = arg
[off
+ 1];
1759 ar
[n_ar
++] = arg
[1];
1762 if (gen_window_check3(dc
, ar
[0], ar
[1], ar
[2])) {
1763 TCGv_i32 vaddr
= tcg_temp_new_i32();
1764 TCGv_i32 mem32
= tcg_temp_new_i32();
1767 tcg_gen_addi_i32(vaddr
, cpu_R
[arg
[1]], ld_offset
);
1768 gen_load_store_alignment(dc
, 2, vaddr
, false);
1769 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
1771 if (op
!= MAC16_NONE
) {
1772 TCGv_i32 m1
= gen_mac16_m(is_m1_sr
?
1773 cpu_SR
[MR
+ arg
[off
]] :
1775 half
& MAC16_HX
, op
== MAC16_UMUL
);
1776 TCGv_i32 m2
= gen_mac16_m(is_m2_sr
?
1777 cpu_SR
[MR
+ arg
[off
+ 1]] :
1778 cpu_R
[arg
[off
+ 1]],
1779 half
& MAC16_XH
, op
== MAC16_UMUL
);
1781 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
1782 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
1783 if (op
== MAC16_UMUL
) {
1784 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
1786 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
1789 TCGv_i32 lo
= tcg_temp_new_i32();
1790 TCGv_i32 hi
= tcg_temp_new_i32();
1792 tcg_gen_mul_i32(lo
, m1
, m2
);
1793 tcg_gen_sari_i32(hi
, lo
, 31);
1794 if (op
== MAC16_MULA
) {
1795 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1796 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1799 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1800 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1803 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
1805 tcg_temp_free_i32(lo
);
1806 tcg_temp_free_i32(hi
);
1812 tcg_gen_mov_i32(cpu_R
[arg
[1]], vaddr
);
1813 tcg_gen_mov_i32(cpu_SR
[MR
+ arg
[0]], mem32
);
1815 tcg_temp_free(vaddr
);
1816 tcg_temp_free(mem32
);
1820 static void translate_minmax(DisasContext
*dc
, const uint32_t arg
[],
1821 const uint32_t par
[])
1823 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1824 tcg_gen_movcond_i32(par
[0], cpu_R
[arg
[0]],
1825 cpu_R
[arg
[1]], cpu_R
[arg
[2]],
1826 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1830 static void translate_mov(DisasContext
*dc
, const uint32_t arg
[],
1831 const uint32_t par
[])
1833 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1834 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1838 static void translate_movcond(DisasContext
*dc
, const uint32_t arg
[],
1839 const uint32_t par
[])
1841 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1842 TCGv_i32 zero
= tcg_const_i32(0);
1844 tcg_gen_movcond_i32(par
[0], cpu_R
[arg
[0]],
1845 cpu_R
[arg
[2]], zero
, cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1846 tcg_temp_free(zero
);
1850 static void translate_movi(DisasContext
*dc
, const uint32_t arg
[],
1851 const uint32_t par
[])
1853 if (gen_window_check1(dc
, arg
[0])) {
1854 tcg_gen_movi_i32(cpu_R
[arg
[0]], arg
[1]);
1858 static void translate_movp(DisasContext
*dc
, const uint32_t arg
[],
1859 const uint32_t par
[])
1861 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1862 TCGv_i32 zero
= tcg_const_i32(0);
1863 TCGv_i32 tmp
= tcg_temp_new_i32();
1865 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
1866 tcg_gen_movcond_i32(par
[0],
1867 cpu_R
[arg
[0]], tmp
, zero
,
1868 cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1870 tcg_temp_free(zero
);
1874 static void translate_movsp(DisasContext
*dc
, const uint32_t arg
[],
1875 const uint32_t par
[])
1877 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1878 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1879 gen_helper_movsp(cpu_env
, pc
);
1880 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1885 static void translate_mul16(DisasContext
*dc
, const uint32_t arg
[],
1886 const uint32_t par
[])
1888 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1889 TCGv_i32 v1
= tcg_temp_new_i32();
1890 TCGv_i32 v2
= tcg_temp_new_i32();
1893 tcg_gen_ext16s_i32(v1
, cpu_R
[arg
[1]]);
1894 tcg_gen_ext16s_i32(v2
, cpu_R
[arg
[2]]);
1896 tcg_gen_ext16u_i32(v1
, cpu_R
[arg
[1]]);
1897 tcg_gen_ext16u_i32(v2
, cpu_R
[arg
[2]]);
1899 tcg_gen_mul_i32(cpu_R
[arg
[0]], v1
, v2
);
1905 static void translate_mull(DisasContext
*dc
, const uint32_t arg
[],
1906 const uint32_t par
[])
1908 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1909 tcg_gen_mul_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1913 static void translate_mulh(DisasContext
*dc
, const uint32_t arg
[],
1914 const uint32_t par
[])
1916 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1917 TCGv_i32 lo
= tcg_temp_new();
1920 tcg_gen_muls2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1922 tcg_gen_mulu2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1928 static void translate_neg(DisasContext
*dc
, const uint32_t arg
[],
1929 const uint32_t par
[])
1931 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1932 tcg_gen_neg_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1936 static void translate_nop(DisasContext
*dc
, const uint32_t arg
[],
1937 const uint32_t par
[])
1941 static void translate_nsa(DisasContext
*dc
, const uint32_t arg
[],
1942 const uint32_t par
[])
1944 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1945 tcg_gen_clrsb_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1949 static void translate_nsau(DisasContext
*dc
, const uint32_t arg
[],
1950 const uint32_t par
[])
1952 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1953 tcg_gen_clzi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], 32);
1957 static void translate_or(DisasContext
*dc
, const uint32_t arg
[],
1958 const uint32_t par
[])
1960 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1961 tcg_gen_or_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1965 static void translate_ptlb(DisasContext
*dc
, const uint32_t arg
[],
1966 const uint32_t par
[])
1968 if (gen_check_privilege(dc
) &&
1969 gen_window_check2(dc
, arg
[0], arg
[1])) {
1970 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
1972 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1973 gen_helper_ptlb(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
1974 tcg_temp_free(dtlb
);
1978 static void gen_zero_check(DisasContext
*dc
, const uint32_t arg
[])
1980 TCGLabel
*label
= gen_new_label();
1982 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0, label
);
1983 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1984 gen_set_label(label
);
1987 static void translate_quos(DisasContext
*dc
, const uint32_t arg
[],
1988 const uint32_t par
[])
1990 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1991 TCGLabel
*label1
= gen_new_label();
1992 TCGLabel
*label2
= gen_new_label();
1994 gen_zero_check(dc
, arg
);
1996 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[1]], 0x80000000,
1998 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0xffffffff,
2000 tcg_gen_movi_i32(cpu_R
[arg
[0]],
2001 par
[0] ? 0x80000000 : 0);
2003 gen_set_label(label1
);
2005 tcg_gen_div_i32(cpu_R
[arg
[0]],
2006 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2008 tcg_gen_rem_i32(cpu_R
[arg
[0]],
2009 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2011 gen_set_label(label2
);
2015 static void translate_quou(DisasContext
*dc
, const uint32_t arg
[],
2016 const uint32_t par
[])
2018 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2019 gen_zero_check(dc
, arg
);
2021 tcg_gen_divu_i32(cpu_R
[arg
[0]],
2022 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2024 tcg_gen_remu_i32(cpu_R
[arg
[0]],
2025 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2030 static void translate_read_impwire(DisasContext
*dc
, const uint32_t arg
[],
2031 const uint32_t par
[])
2033 if (gen_window_check1(dc
, arg
[0])) {
2034 /* TODO: GPIO32 may be a part of coprocessor */
2035 tcg_gen_movi_i32(cpu_R
[arg
[0]], 0);
2039 static void translate_rer(DisasContext
*dc
, const uint32_t arg
[],
2040 const uint32_t par
[])
2042 if (gen_check_privilege(dc
) &&
2043 gen_window_check2(dc
, arg
[0], arg
[1])) {
2044 gen_helper_rer(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]]);
2048 static void translate_ret(DisasContext
*dc
, const uint32_t arg
[],
2049 const uint32_t par
[])
2051 gen_jump(dc
, cpu_R
[0]);
2054 static void translate_retw(DisasContext
*dc
, const uint32_t arg
[],
2055 const uint32_t par
[])
2057 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2058 gen_helper_retw(tmp
, cpu_env
, tmp
);
2063 static void translate_rfde(DisasContext
*dc
, const uint32_t arg
[],
2064 const uint32_t par
[])
2066 if (gen_check_privilege(dc
)) {
2067 gen_jump(dc
, cpu_SR
[dc
->config
->ndepc
? DEPC
: EPC1
]);
2071 static void translate_rfe(DisasContext
*dc
, const uint32_t arg
[],
2072 const uint32_t par
[])
2074 if (gen_check_privilege(dc
)) {
2075 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2076 gen_check_interrupts(dc
);
2077 gen_jump(dc
, cpu_SR
[EPC1
]);
2081 static void translate_rfi(DisasContext
*dc
, const uint32_t arg
[],
2082 const uint32_t par
[])
2084 if (gen_check_privilege(dc
)) {
2085 tcg_gen_mov_i32(cpu_SR
[PS
], cpu_SR
[EPS2
+ arg
[0] - 2]);
2086 gen_check_interrupts(dc
);
2087 gen_jump(dc
, cpu_SR
[EPC1
+ arg
[0] - 1]);
2091 static void translate_rfw(DisasContext
*dc
, const uint32_t arg
[],
2092 const uint32_t par
[])
2094 if (gen_check_privilege(dc
)) {
2095 TCGv_i32 tmp
= tcg_const_i32(1);
2097 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2098 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
2101 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2102 cpu_SR
[WINDOW_START
], tmp
);
2104 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
2105 cpu_SR
[WINDOW_START
], tmp
);
2108 gen_helper_restore_owb(cpu_env
);
2109 gen_check_interrupts(dc
);
2110 gen_jump(dc
, cpu_SR
[EPC1
]);
2116 static void translate_rotw(DisasContext
*dc
, const uint32_t arg
[],
2117 const uint32_t par
[])
2119 if (gen_check_privilege(dc
)) {
2120 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2121 gen_helper_rotw(cpu_env
, tmp
);
2123 /* This can change tb->flags, so exit tb */
2124 gen_jumpi_check_loop_end(dc
, -1);
2128 static void translate_rsil(DisasContext
*dc
, const uint32_t arg
[],
2129 const uint32_t par
[])
2131 if (gen_check_privilege(dc
) &&
2132 gen_window_check1(dc
, arg
[0])) {
2133 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_SR
[PS
]);
2134 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
2135 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], arg
[1]);
2136 gen_check_interrupts(dc
);
2137 gen_jumpi_check_loop_end(dc
, 0);
2141 static void translate_rsr(DisasContext
*dc
, const uint32_t arg
[],
2142 const uint32_t par
[])
2144 if (gen_check_sr(dc
, par
[0], SR_R
) &&
2145 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2146 gen_window_check1(dc
, arg
[0])) {
2147 if (gen_rsr(dc
, cpu_R
[arg
[0]], par
[0])) {
2148 gen_jumpi_check_loop_end(dc
, 0);
2153 static void translate_rtlb(DisasContext
*dc
, const uint32_t arg
[],
2154 const uint32_t par
[])
2156 static void (* const helper
[])(TCGv_i32 r
, TCGv_env env
, TCGv_i32 a1
,
2162 if (gen_check_privilege(dc
) &&
2163 gen_window_check2(dc
, arg
[0], arg
[1])) {
2164 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2166 helper
[par
[1]](cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
2167 tcg_temp_free(dtlb
);
2171 static void translate_rur(DisasContext
*dc
, const uint32_t arg
[],
2172 const uint32_t par
[])
2174 if (gen_window_check1(dc
, arg
[0])) {
2175 if (uregnames
[par
[0]].name
) {
2176 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_UR
[par
[0]]);
2178 qemu_log_mask(LOG_UNIMP
, "RUR %d not implemented, ", par
[0]);
2183 static void translate_setb_expstate(DisasContext
*dc
, const uint32_t arg
[],
2184 const uint32_t par
[])
2186 /* TODO: GPIO32 may be a part of coprocessor */
2187 tcg_gen_ori_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], 1u << arg
[0]);
2190 static void translate_s32c1i(DisasContext
*dc
, const uint32_t arg
[],
2191 const uint32_t par
[])
2193 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2194 TCGLabel
*label
= gen_new_label();
2195 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2196 TCGv_i32 addr
= tcg_temp_local_new_i32();
2199 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2200 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2201 gen_load_store_alignment(dc
, 2, addr
, true);
2203 tpc
= tcg_const_i32(dc
->pc
);
2204 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2205 tcg_gen_qemu_ld32u(cpu_R
[arg
[0]], addr
, dc
->cring
);
2206 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[arg
[0]],
2207 cpu_SR
[SCOMPARE1
], label
);
2209 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2211 gen_set_label(label
);
2213 tcg_temp_free(addr
);
2218 static void translate_s32e(DisasContext
*dc
, const uint32_t arg
[],
2219 const uint32_t par
[])
2221 if (gen_check_privilege(dc
) &&
2222 gen_window_check2(dc
, arg
[0], arg
[1])) {
2223 TCGv_i32 addr
= tcg_temp_new_i32();
2225 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2226 gen_load_store_alignment(dc
, 2, addr
, false);
2227 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
2228 tcg_temp_free(addr
);
2232 static void translate_salt(DisasContext
*dc
, const uint32_t arg
[],
2233 const uint32_t par
[])
2235 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2236 tcg_gen_setcond_i32(par
[0],
2238 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2242 static void translate_sext(DisasContext
*dc
, const uint32_t arg
[],
2243 const uint32_t par
[])
2245 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2246 int shift
= 31 - arg
[2];
2249 tcg_gen_ext8s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2250 } else if (shift
== 16) {
2251 tcg_gen_ext16s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2253 TCGv_i32 tmp
= tcg_temp_new_i32();
2254 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], shift
);
2255 tcg_gen_sari_i32(cpu_R
[arg
[0]], tmp
, shift
);
2261 static void translate_simcall(DisasContext
*dc
, const uint32_t arg
[],
2262 const uint32_t par
[])
2264 if (semihosting_enabled()) {
2265 if (gen_check_privilege(dc
)) {
2266 gen_helper_simcall(cpu_env
);
2269 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
2270 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2275 * Note: 64 bit ops are used here solely because SAR values
2278 #define gen_shift_reg(cmd, reg) do { \
2279 TCGv_i64 tmp = tcg_temp_new_i64(); \
2280 tcg_gen_extu_i32_i64(tmp, reg); \
2281 tcg_gen_##cmd##_i64(v, v, tmp); \
2282 tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \
2283 tcg_temp_free_i64(v); \
2284 tcg_temp_free_i64(tmp); \
2287 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2289 static void translate_sll(DisasContext
*dc
, const uint32_t arg
[],
2290 const uint32_t par
[])
2292 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2293 if (dc
->sar_m32_5bit
) {
2294 tcg_gen_shl_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], dc
->sar_m32
);
2296 TCGv_i64 v
= tcg_temp_new_i64();
2297 TCGv_i32 s
= tcg_const_i32(32);
2298 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
2299 tcg_gen_andi_i32(s
, s
, 0x3f);
2300 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2301 gen_shift_reg(shl
, s
);
2307 static void translate_slli(DisasContext
*dc
, const uint32_t arg
[],
2308 const uint32_t par
[])
2310 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2312 qemu_log_mask(LOG_GUEST_ERROR
, "slli a%d, a%d, 32 is undefined",
2315 tcg_gen_shli_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2] & 0x1f);
2319 static void translate_sra(DisasContext
*dc
, const uint32_t arg
[],
2320 const uint32_t par
[])
2322 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2323 if (dc
->sar_m32_5bit
) {
2324 tcg_gen_sar_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2326 TCGv_i64 v
= tcg_temp_new_i64();
2327 tcg_gen_ext_i32_i64(v
, cpu_R
[arg
[1]]);
2333 static void translate_srai(DisasContext
*dc
, const uint32_t arg
[],
2334 const uint32_t par
[])
2336 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2337 tcg_gen_sari_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2341 static void translate_src(DisasContext
*dc
, const uint32_t arg
[],
2342 const uint32_t par
[])
2344 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2345 TCGv_i64 v
= tcg_temp_new_i64();
2346 tcg_gen_concat_i32_i64(v
, cpu_R
[arg
[2]], cpu_R
[arg
[1]]);
2351 static void translate_srl(DisasContext
*dc
, const uint32_t arg
[],
2352 const uint32_t par
[])
2354 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2355 if (dc
->sar_m32_5bit
) {
2356 tcg_gen_shr_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2358 TCGv_i64 v
= tcg_temp_new_i64();
2359 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2366 #undef gen_shift_reg
2368 static void translate_srli(DisasContext
*dc
, const uint32_t arg
[],
2369 const uint32_t par
[])
2371 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2372 tcg_gen_shri_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2376 static void translate_ssa8b(DisasContext
*dc
, const uint32_t arg
[],
2377 const uint32_t par
[])
2379 if (gen_window_check1(dc
, arg
[0])) {
2380 TCGv_i32 tmp
= tcg_temp_new_i32();
2381 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2382 gen_left_shift_sar(dc
, tmp
);
2387 static void translate_ssa8l(DisasContext
*dc
, const uint32_t arg
[],
2388 const uint32_t par
[])
2390 if (gen_window_check1(dc
, arg
[0])) {
2391 TCGv_i32 tmp
= tcg_temp_new_i32();
2392 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2393 gen_right_shift_sar(dc
, tmp
);
2398 static void translate_ssai(DisasContext
*dc
, const uint32_t arg
[],
2399 const uint32_t par
[])
2401 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2402 gen_right_shift_sar(dc
, tmp
);
2406 static void translate_ssl(DisasContext
*dc
, const uint32_t arg
[],
2407 const uint32_t par
[])
2409 if (gen_window_check1(dc
, arg
[0])) {
2410 gen_left_shift_sar(dc
, cpu_R
[arg
[0]]);
2414 static void translate_ssr(DisasContext
*dc
, const uint32_t arg
[],
2415 const uint32_t par
[])
2417 if (gen_window_check1(dc
, arg
[0])) {
2418 gen_right_shift_sar(dc
, cpu_R
[arg
[0]]);
2422 static void translate_sub(DisasContext
*dc
, const uint32_t arg
[],
2423 const uint32_t par
[])
2425 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2426 tcg_gen_sub_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2430 static void translate_subx(DisasContext
*dc
, const uint32_t arg
[],
2431 const uint32_t par
[])
2433 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2434 TCGv_i32 tmp
= tcg_temp_new_i32();
2435 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
2436 tcg_gen_sub_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
2441 static void translate_syscall(DisasContext
*dc
, const uint32_t arg
[],
2442 const uint32_t par
[])
2444 gen_exception_cause(dc
, SYSCALL_CAUSE
);
2447 static void translate_waiti(DisasContext
*dc
, const uint32_t arg
[],
2448 const uint32_t par
[])
2450 if (gen_check_privilege(dc
)) {
2451 gen_waiti(dc
, arg
[0]);
2455 static void translate_wtlb(DisasContext
*dc
, const uint32_t arg
[],
2456 const uint32_t par
[])
2458 if (gen_check_privilege(dc
) &&
2459 gen_window_check2(dc
, arg
[0], arg
[1])) {
2460 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2462 gen_helper_wtlb(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], dtlb
);
2463 /* This could change memory mapping, so exit tb */
2464 gen_jumpi_check_loop_end(dc
, -1);
2465 tcg_temp_free(dtlb
);
2469 static void translate_wer(DisasContext
*dc
, const uint32_t arg
[],
2470 const uint32_t par
[])
2472 if (gen_check_privilege(dc
) &&
2473 gen_window_check2(dc
, arg
[0], arg
[1])) {
2474 gen_helper_wer(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2478 static void translate_wrmsk_expstate(DisasContext
*dc
, const uint32_t arg
[],
2479 const uint32_t par
[])
2481 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2482 /* TODO: GPIO32 may be a part of coprocessor */
2483 tcg_gen_and_i32(cpu_UR
[EXPSTATE
], cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2487 static void translate_wsr(DisasContext
*dc
, const uint32_t arg
[],
2488 const uint32_t par
[])
2490 if (gen_check_sr(dc
, par
[0], SR_W
) &&
2491 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2492 gen_window_check1(dc
, arg
[0])) {
2493 gen_wsr(dc
, par
[0], cpu_R
[arg
[0]]);
2497 static void translate_wur(DisasContext
*dc
, const uint32_t arg
[],
2498 const uint32_t par
[])
2500 if (gen_window_check1(dc
, arg
[0])) {
2501 if (uregnames
[par
[0]].name
) {
2502 gen_wur(par
[0], cpu_R
[arg
[0]]);
2504 qemu_log_mask(LOG_UNIMP
, "WUR %d not implemented, ", par
[0]);
2509 static void translate_xor(DisasContext
*dc
, const uint32_t arg
[],
2510 const uint32_t par
[])
2512 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2513 tcg_gen_xor_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2517 static void translate_xsr(DisasContext
*dc
, const uint32_t arg
[],
2518 const uint32_t par
[])
2520 if (gen_check_sr(dc
, par
[0], SR_X
) &&
2521 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2522 gen_window_check1(dc
, arg
[0])) {
2523 TCGv_i32 tmp
= tcg_temp_new_i32();
2524 bool rsr_end
, wsr_end
;
2526 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2527 rsr_end
= gen_rsr(dc
, cpu_R
[arg
[0]], par
[0]);
2528 wsr_end
= gen_wsr(dc
, par
[0], tmp
);
2530 if (rsr_end
&& !wsr_end
) {
2531 gen_jumpi_check_loop_end(dc
, 0);
2536 static const XtensaOpcodeOps core_ops
[] = {
2539 .translate
= translate_abs
,
2542 .translate
= translate_add
,
2545 .translate
= translate_add
,
2548 .translate
= translate_addi
,
2551 .translate
= translate_addi
,
2554 .translate
= translate_addi
,
2557 .translate
= translate_addx
,
2558 .par
= (const uint32_t[]){1},
2561 .translate
= translate_addx
,
2562 .par
= (const uint32_t[]){2},
2565 .translate
= translate_addx
,
2566 .par
= (const uint32_t[]){3},
2569 .translate
= translate_all
,
2570 .par
= (const uint32_t[]){true, 4},
2573 .translate
= translate_all
,
2574 .par
= (const uint32_t[]){true, 8},
2577 .translate
= translate_and
,
2580 .translate
= translate_boolean
,
2581 .par
= (const uint32_t[]){BOOLEAN_AND
},
2584 .translate
= translate_boolean
,
2585 .par
= (const uint32_t[]){BOOLEAN_ANDC
},
2588 .translate
= translate_all
,
2589 .par
= (const uint32_t[]){false, 4},
2592 .translate
= translate_all
,
2593 .par
= (const uint32_t[]){false, 8},
2596 .translate
= translate_ball
,
2597 .par
= (const uint32_t[]){TCG_COND_EQ
},
2600 .translate
= translate_bany
,
2601 .par
= (const uint32_t[]){TCG_COND_NE
},
2604 .translate
= translate_bb
,
2605 .par
= (const uint32_t[]){TCG_COND_EQ
},
2608 .translate
= translate_bbi
,
2609 .par
= (const uint32_t[]){TCG_COND_EQ
},
2612 .translate
= translate_bb
,
2613 .par
= (const uint32_t[]){TCG_COND_NE
},
2616 .translate
= translate_bbi
,
2617 .par
= (const uint32_t[]){TCG_COND_NE
},
2620 .translate
= translate_b
,
2621 .par
= (const uint32_t[]){TCG_COND_EQ
},
2624 .translate
= translate_bi
,
2625 .par
= (const uint32_t[]){TCG_COND_EQ
},
2628 .translate
= translate_bz
,
2629 .par
= (const uint32_t[]){TCG_COND_EQ
},
2632 .translate
= translate_bz
,
2633 .par
= (const uint32_t[]){TCG_COND_EQ
},
2636 .translate
= translate_bp
,
2637 .par
= (const uint32_t[]){TCG_COND_EQ
},
2640 .translate
= translate_b
,
2641 .par
= (const uint32_t[]){TCG_COND_GE
},
2644 .translate
= translate_bi
,
2645 .par
= (const uint32_t[]){TCG_COND_GE
},
2648 .translate
= translate_b
,
2649 .par
= (const uint32_t[]){TCG_COND_GEU
},
2652 .translate
= translate_bi
,
2653 .par
= (const uint32_t[]){TCG_COND_GEU
},
2656 .translate
= translate_bz
,
2657 .par
= (const uint32_t[]){TCG_COND_GE
},
2660 .translate
= translate_b
,
2661 .par
= (const uint32_t[]){TCG_COND_LT
},
2664 .translate
= translate_bi
,
2665 .par
= (const uint32_t[]){TCG_COND_LT
},
2668 .translate
= translate_b
,
2669 .par
= (const uint32_t[]){TCG_COND_LTU
},
2672 .translate
= translate_bi
,
2673 .par
= (const uint32_t[]){TCG_COND_LTU
},
2676 .translate
= translate_bz
,
2677 .par
= (const uint32_t[]){TCG_COND_LT
},
2680 .translate
= translate_ball
,
2681 .par
= (const uint32_t[]){TCG_COND_NE
},
2684 .translate
= translate_b
,
2685 .par
= (const uint32_t[]){TCG_COND_NE
},
2688 .translate
= translate_bi
,
2689 .par
= (const uint32_t[]){TCG_COND_NE
},
2692 .translate
= translate_bz
,
2693 .par
= (const uint32_t[]){TCG_COND_NE
},
2696 .translate
= translate_bz
,
2697 .par
= (const uint32_t[]){TCG_COND_NE
},
2700 .translate
= translate_bany
,
2701 .par
= (const uint32_t[]){TCG_COND_EQ
},
2704 .translate
= translate_break
,
2705 .par
= (const uint32_t[]){DEBUGCAUSE_BI
},
2708 .translate
= translate_break
,
2709 .par
= (const uint32_t[]){DEBUGCAUSE_BN
},
2712 .translate
= translate_bp
,
2713 .par
= (const uint32_t[]){TCG_COND_NE
},
2716 .translate
= translate_call0
,
2719 .translate
= translate_callw
,
2720 .par
= (const uint32_t[]){3},
2723 .translate
= translate_callw
,
2724 .par
= (const uint32_t[]){1},
2727 .translate
= translate_callw
,
2728 .par
= (const uint32_t[]){2},
2731 .translate
= translate_callx0
,
2734 .translate
= translate_callxw
,
2735 .par
= (const uint32_t[]){3},
2738 .translate
= translate_callxw
,
2739 .par
= (const uint32_t[]){1},
2742 .translate
= translate_callxw
,
2743 .par
= (const uint32_t[]){2},
2746 .translate
= translate_clamps
,
2748 .name
= "clrb_expstate",
2749 .translate
= translate_clrb_expstate
,
2752 .translate
= translate_const16
,
2755 .translate
= translate_depbits
,
2758 .translate
= translate_dcache
,
2759 .par
= (const uint32_t[]){true, true},
2762 .translate
= translate_dcache
,
2763 .par
= (const uint32_t[]){true, true},
2766 .translate
= translate_dcache
,
2767 .par
= (const uint32_t[]){false, true},
2770 .translate
= translate_dcache
,
2771 .par
= (const uint32_t[]){false, true},
2774 .translate
= translate_dcache
,
2775 .par
= (const uint32_t[]){true, false},
2778 .translate
= translate_dcache
,
2779 .par
= (const uint32_t[]){true, false},
2782 .translate
= translate_dcache
,
2783 .par
= (const uint32_t[]){true, false},
2786 .translate
= translate_dcache
,
2787 .par
= (const uint32_t[]){true, false},
2790 .translate
= translate_dcache
,
2791 .par
= (const uint32_t[]){true, true},
2794 .translate
= translate_dcache
,
2795 .par
= (const uint32_t[]){false, false},
2798 .translate
= translate_dcache
,
2799 .par
= (const uint32_t[]){false, false},
2802 .translate
= translate_dcache
,
2803 .par
= (const uint32_t[]){false, false},
2806 .translate
= translate_dcache
,
2807 .par
= (const uint32_t[]){false, false},
2810 .translate
= translate_nop
,
2813 .translate
= translate_entry
,
2816 .translate
= translate_nop
,
2819 .translate
= translate_nop
,
2822 .translate
= translate_extui
,
2825 .translate
= translate_nop
,
2828 .translate
= translate_ill
,
2831 .translate
= translate_ill
,
2834 .translate
= translate_itlb
,
2835 .par
= (const uint32_t[]){true},
2838 .translate
= translate_icache
,
2839 .par
= (const uint32_t[]){false, true},
2842 .translate
= translate_icache
,
2843 .par
= (const uint32_t[]){true, true},
2846 .translate
= translate_icache
,
2847 .par
= (const uint32_t[]){true, false},
2850 .translate
= translate_itlb
,
2851 .par
= (const uint32_t[]){false},
2854 .translate
= translate_icache
,
2855 .par
= (const uint32_t[]){true, false},
2858 .translate
= translate_ill
,
2861 .translate
= translate_ill
,
2864 .translate
= translate_icache
,
2865 .par
= (const uint32_t[]){false, false},
2868 .translate
= translate_icache
,
2869 .par
= (const uint32_t[]){true, true},
2872 .translate
= translate_nop
,
2875 .translate
= translate_j
,
2878 .translate
= translate_jx
,
2881 .translate
= translate_ldst
,
2882 .par
= (const uint32_t[]){MO_TESW
, false, false},
2885 .translate
= translate_ldst
,
2886 .par
= (const uint32_t[]){MO_TEUW
, false, false},
2889 .translate
= translate_ldst
,
2890 .par
= (const uint32_t[]){MO_TEUL
, true, false},
2893 .translate
= translate_l32e
,
2896 .translate
= translate_ldst
,
2897 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2900 .translate
= translate_ldst
,
2901 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2904 .translate
= translate_l32r
,
2907 .translate
= translate_ldst
,
2908 .par
= (const uint32_t[]){MO_UB
, false, false},
2911 .translate
= translate_mac16
,
2912 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, -4},
2915 .translate
= translate_mac16
,
2916 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, 4},
2919 .translate
= translate_ill
,
2922 .translate
= translate_loop
,
2923 .par
= (const uint32_t[]){TCG_COND_NEVER
},
2926 .translate
= translate_loop
,
2927 .par
= (const uint32_t[]){TCG_COND_GT
},
2930 .translate
= translate_loop
,
2931 .par
= (const uint32_t[]){TCG_COND_NE
},
2934 .translate
= translate_minmax
,
2935 .par
= (const uint32_t[]){TCG_COND_GE
},
2938 .translate
= translate_minmax
,
2939 .par
= (const uint32_t[]){TCG_COND_GEU
},
2942 .translate
= translate_nop
,
2945 .translate
= translate_minmax
,
2946 .par
= (const uint32_t[]){TCG_COND_LT
},
2949 .translate
= translate_minmax
,
2950 .par
= (const uint32_t[]){TCG_COND_LTU
},
2953 .translate
= translate_mov
,
2956 .translate
= translate_mov
,
2959 .translate
= translate_movcond
,
2960 .par
= (const uint32_t[]){TCG_COND_EQ
},
2963 .translate
= translate_movp
,
2964 .par
= (const uint32_t[]){TCG_COND_EQ
},
2967 .translate
= translate_movcond
,
2968 .par
= (const uint32_t[]){TCG_COND_GE
},
2971 .translate
= translate_movi
,
2974 .translate
= translate_movi
,
2977 .translate
= translate_movcond
,
2978 .par
= (const uint32_t[]){TCG_COND_LT
},
2981 .translate
= translate_movcond
,
2982 .par
= (const uint32_t[]){TCG_COND_NE
},
2985 .translate
= translate_movsp
,
2988 .translate
= translate_movp
,
2989 .par
= (const uint32_t[]){TCG_COND_NE
},
2991 .name
= "mul.aa.hh",
2992 .translate
= translate_mac16
,
2993 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HH
, 0},
2995 .name
= "mul.aa.hl",
2996 .translate
= translate_mac16
,
2997 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HL
, 0},
2999 .name
= "mul.aa.lh",
3000 .translate
= translate_mac16
,
3001 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LH
, 0},
3003 .name
= "mul.aa.ll",
3004 .translate
= translate_mac16
,
3005 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LL
, 0},
3007 .name
= "mul.ad.hh",
3008 .translate
= translate_mac16
,
3009 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HH
, 0},
3011 .name
= "mul.ad.hl",
3012 .translate
= translate_mac16
,
3013 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HL
, 0},
3015 .name
= "mul.ad.lh",
3016 .translate
= translate_mac16
,
3017 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LH
, 0},
3019 .name
= "mul.ad.ll",
3020 .translate
= translate_mac16
,
3021 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LL
, 0},
3023 .name
= "mul.da.hh",
3024 .translate
= translate_mac16
,
3025 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HH
, 0},
3027 .name
= "mul.da.hl",
3028 .translate
= translate_mac16
,
3029 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HL
, 0},
3031 .name
= "mul.da.lh",
3032 .translate
= translate_mac16
,
3033 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LH
, 0},
3035 .name
= "mul.da.ll",
3036 .translate
= translate_mac16
,
3037 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LL
, 0},
3039 .name
= "mul.dd.hh",
3040 .translate
= translate_mac16
,
3041 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HH
, 0},
3043 .name
= "mul.dd.hl",
3044 .translate
= translate_mac16
,
3045 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HL
, 0},
3047 .name
= "mul.dd.lh",
3048 .translate
= translate_mac16
,
3049 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LH
, 0},
3051 .name
= "mul.dd.ll",
3052 .translate
= translate_mac16
,
3053 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LL
, 0},
3056 .translate
= translate_mul16
,
3057 .par
= (const uint32_t[]){true},
3060 .translate
= translate_mul16
,
3061 .par
= (const uint32_t[]){false},
3063 .name
= "mula.aa.hh",
3064 .translate
= translate_mac16
,
3065 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HH
, 0},
3067 .name
= "mula.aa.hl",
3068 .translate
= translate_mac16
,
3069 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HL
, 0},
3071 .name
= "mula.aa.lh",
3072 .translate
= translate_mac16
,
3073 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LH
, 0},
3075 .name
= "mula.aa.ll",
3076 .translate
= translate_mac16
,
3077 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LL
, 0},
3079 .name
= "mula.ad.hh",
3080 .translate
= translate_mac16
,
3081 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HH
, 0},
3083 .name
= "mula.ad.hl",
3084 .translate
= translate_mac16
,
3085 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HL
, 0},
3087 .name
= "mula.ad.lh",
3088 .translate
= translate_mac16
,
3089 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LH
, 0},
3091 .name
= "mula.ad.ll",
3092 .translate
= translate_mac16
,
3093 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LL
, 0},
3095 .name
= "mula.da.hh",
3096 .translate
= translate_mac16
,
3097 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 0},
3099 .name
= "mula.da.hh.lddec",
3100 .translate
= translate_mac16
,
3101 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, -4},
3103 .name
= "mula.da.hh.ldinc",
3104 .translate
= translate_mac16
,
3105 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 4},
3107 .name
= "mula.da.hl",
3108 .translate
= translate_mac16
,
3109 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 0},
3111 .name
= "mula.da.hl.lddec",
3112 .translate
= translate_mac16
,
3113 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, -4},
3115 .name
= "mula.da.hl.ldinc",
3116 .translate
= translate_mac16
,
3117 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 4},
3119 .name
= "mula.da.lh",
3120 .translate
= translate_mac16
,
3121 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 0},
3123 .name
= "mula.da.lh.lddec",
3124 .translate
= translate_mac16
,
3125 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, -4},
3127 .name
= "mula.da.lh.ldinc",
3128 .translate
= translate_mac16
,
3129 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 4},
3131 .name
= "mula.da.ll",
3132 .translate
= translate_mac16
,
3133 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 0},
3135 .name
= "mula.da.ll.lddec",
3136 .translate
= translate_mac16
,
3137 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, -4},
3139 .name
= "mula.da.ll.ldinc",
3140 .translate
= translate_mac16
,
3141 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 4},
3143 .name
= "mula.dd.hh",
3144 .translate
= translate_mac16
,
3145 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 0},
3147 .name
= "mula.dd.hh.lddec",
3148 .translate
= translate_mac16
,
3149 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, -4},
3151 .name
= "mula.dd.hh.ldinc",
3152 .translate
= translate_mac16
,
3153 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 4},
3155 .name
= "mula.dd.hl",
3156 .translate
= translate_mac16
,
3157 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 0},
3159 .name
= "mula.dd.hl.lddec",
3160 .translate
= translate_mac16
,
3161 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, -4},
3163 .name
= "mula.dd.hl.ldinc",
3164 .translate
= translate_mac16
,
3165 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 4},
3167 .name
= "mula.dd.lh",
3168 .translate
= translate_mac16
,
3169 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 0},
3171 .name
= "mula.dd.lh.lddec",
3172 .translate
= translate_mac16
,
3173 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, -4},
3175 .name
= "mula.dd.lh.ldinc",
3176 .translate
= translate_mac16
,
3177 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 4},
3179 .name
= "mula.dd.ll",
3180 .translate
= translate_mac16
,
3181 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 0},
3183 .name
= "mula.dd.ll.lddec",
3184 .translate
= translate_mac16
,
3185 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, -4},
3187 .name
= "mula.dd.ll.ldinc",
3188 .translate
= translate_mac16
,
3189 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 4},
3192 .translate
= translate_mull
,
3194 .name
= "muls.aa.hh",
3195 .translate
= translate_mac16
,
3196 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HH
, 0},
3198 .name
= "muls.aa.hl",
3199 .translate
= translate_mac16
,
3200 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HL
, 0},
3202 .name
= "muls.aa.lh",
3203 .translate
= translate_mac16
,
3204 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LH
, 0},
3206 .name
= "muls.aa.ll",
3207 .translate
= translate_mac16
,
3208 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LL
, 0},
3210 .name
= "muls.ad.hh",
3211 .translate
= translate_mac16
,
3212 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HH
, 0},
3214 .name
= "muls.ad.hl",
3215 .translate
= translate_mac16
,
3216 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HL
, 0},
3218 .name
= "muls.ad.lh",
3219 .translate
= translate_mac16
,
3220 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LH
, 0},
3222 .name
= "muls.ad.ll",
3223 .translate
= translate_mac16
,
3224 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LL
, 0},
3226 .name
= "muls.da.hh",
3227 .translate
= translate_mac16
,
3228 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HH
, 0},
3230 .name
= "muls.da.hl",
3231 .translate
= translate_mac16
,
3232 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HL
, 0},
3234 .name
= "muls.da.lh",
3235 .translate
= translate_mac16
,
3236 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LH
, 0},
3238 .name
= "muls.da.ll",
3239 .translate
= translate_mac16
,
3240 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LL
, 0},
3242 .name
= "muls.dd.hh",
3243 .translate
= translate_mac16
,
3244 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HH
, 0},
3246 .name
= "muls.dd.hl",
3247 .translate
= translate_mac16
,
3248 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HL
, 0},
3250 .name
= "muls.dd.lh",
3251 .translate
= translate_mac16
,
3252 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LH
, 0},
3254 .name
= "muls.dd.ll",
3255 .translate
= translate_mac16
,
3256 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LL
, 0},
3259 .translate
= translate_mulh
,
3260 .par
= (const uint32_t[]){true},
3263 .translate
= translate_mulh
,
3264 .par
= (const uint32_t[]){false},
3267 .translate
= translate_neg
,
3270 .translate
= translate_nop
,
3273 .translate
= translate_nop
,
3276 .translate
= translate_nsa
,
3279 .translate
= translate_nsau
,
3282 .translate
= translate_or
,
3285 .translate
= translate_boolean
,
3286 .par
= (const uint32_t[]){BOOLEAN_OR
},
3289 .translate
= translate_boolean
,
3290 .par
= (const uint32_t[]){BOOLEAN_ORC
},
3293 .translate
= translate_ptlb
,
3294 .par
= (const uint32_t[]){true},
3297 .translate
= translate_ptlb
,
3298 .par
= (const uint32_t[]){false},
3301 .translate
= translate_quos
,
3302 .par
= (const uint32_t[]){true},
3305 .translate
= translate_quou
,
3306 .par
= (const uint32_t[]){true},
3309 .translate
= translate_rtlb
,
3310 .par
= (const uint32_t[]){true, 0},
3313 .translate
= translate_rtlb
,
3314 .par
= (const uint32_t[]){true, 1},
3316 .name
= "read_impwire",
3317 .translate
= translate_read_impwire
,
3320 .translate
= translate_quos
,
3321 .par
= (const uint32_t[]){false},
3324 .translate
= translate_quou
,
3325 .par
= (const uint32_t[]){false},
3328 .translate
= translate_rer
,
3331 .translate
= translate_ret
,
3334 .translate
= translate_ret
,
3337 .translate
= translate_retw
,
3340 .translate
= translate_retw
,
3343 .translate
= translate_ill
,
3346 .translate
= translate_rfde
,
3349 .translate
= translate_ill
,
3352 .translate
= translate_rfe
,
3355 .translate
= translate_rfi
,
3358 .translate
= translate_rfw
,
3359 .par
= (const uint32_t[]){true},
3362 .translate
= translate_rfw
,
3363 .par
= (const uint32_t[]){false},
3366 .translate
= translate_rtlb
,
3367 .par
= (const uint32_t[]){false, 0},
3370 .translate
= translate_rtlb
,
3371 .par
= (const uint32_t[]){false, 1},
3374 .translate
= translate_rotw
,
3377 .translate
= translate_rsil
,
3380 .translate
= translate_rsr
,
3381 .par
= (const uint32_t[]){176},
3384 .translate
= translate_rsr
,
3385 .par
= (const uint32_t[]){208},
3387 .name
= "rsr.acchi",
3388 .translate
= translate_rsr
,
3389 .par
= (const uint32_t[]){ACCHI
},
3391 .name
= "rsr.acclo",
3392 .translate
= translate_rsr
,
3393 .par
= (const uint32_t[]){ACCLO
},
3395 .name
= "rsr.atomctl",
3396 .translate
= translate_rsr
,
3397 .par
= (const uint32_t[]){ATOMCTL
},
3400 .translate
= translate_rsr
,
3401 .par
= (const uint32_t[]){BR
},
3403 .name
= "rsr.cacheattr",
3404 .translate
= translate_rsr
,
3405 .par
= (const uint32_t[]){CACHEATTR
},
3407 .name
= "rsr.ccompare0",
3408 .translate
= translate_rsr
,
3409 .par
= (const uint32_t[]){CCOMPARE
},
3411 .name
= "rsr.ccompare1",
3412 .translate
= translate_rsr
,
3413 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3415 .name
= "rsr.ccompare2",
3416 .translate
= translate_rsr
,
3417 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3419 .name
= "rsr.ccount",
3420 .translate
= translate_rsr
,
3421 .par
= (const uint32_t[]){CCOUNT
},
3423 .name
= "rsr.configid0",
3424 .translate
= translate_rsr
,
3425 .par
= (const uint32_t[]){CONFIGID0
},
3427 .name
= "rsr.configid1",
3428 .translate
= translate_rsr
,
3429 .par
= (const uint32_t[]){CONFIGID1
},
3431 .name
= "rsr.cpenable",
3432 .translate
= translate_rsr
,
3433 .par
= (const uint32_t[]){CPENABLE
},
3435 .name
= "rsr.dbreaka0",
3436 .translate
= translate_rsr
,
3437 .par
= (const uint32_t[]){DBREAKA
},
3439 .name
= "rsr.dbreaka1",
3440 .translate
= translate_rsr
,
3441 .par
= (const uint32_t[]){DBREAKA
+ 1},
3443 .name
= "rsr.dbreakc0",
3444 .translate
= translate_rsr
,
3445 .par
= (const uint32_t[]){DBREAKC
},
3447 .name
= "rsr.dbreakc1",
3448 .translate
= translate_rsr
,
3449 .par
= (const uint32_t[]){DBREAKC
+ 1},
3452 .translate
= translate_rsr
,
3453 .par
= (const uint32_t[]){DDR
},
3455 .name
= "rsr.debugcause",
3456 .translate
= translate_rsr
,
3457 .par
= (const uint32_t[]){DEBUGCAUSE
},
3460 .translate
= translate_rsr
,
3461 .par
= (const uint32_t[]){DEPC
},
3463 .name
= "rsr.dtlbcfg",
3464 .translate
= translate_rsr
,
3465 .par
= (const uint32_t[]){DTLBCFG
},
3468 .translate
= translate_rsr
,
3469 .par
= (const uint32_t[]){EPC1
},
3472 .translate
= translate_rsr
,
3473 .par
= (const uint32_t[]){EPC1
+ 1},
3476 .translate
= translate_rsr
,
3477 .par
= (const uint32_t[]){EPC1
+ 2},
3480 .translate
= translate_rsr
,
3481 .par
= (const uint32_t[]){EPC1
+ 3},
3484 .translate
= translate_rsr
,
3485 .par
= (const uint32_t[]){EPC1
+ 4},
3488 .translate
= translate_rsr
,
3489 .par
= (const uint32_t[]){EPC1
+ 5},
3492 .translate
= translate_rsr
,
3493 .par
= (const uint32_t[]){EPC1
+ 6},
3496 .translate
= translate_rsr
,
3497 .par
= (const uint32_t[]){EPS2
},
3500 .translate
= translate_rsr
,
3501 .par
= (const uint32_t[]){EPS2
+ 1},
3504 .translate
= translate_rsr
,
3505 .par
= (const uint32_t[]){EPS2
+ 2},
3508 .translate
= translate_rsr
,
3509 .par
= (const uint32_t[]){EPS2
+ 3},
3512 .translate
= translate_rsr
,
3513 .par
= (const uint32_t[]){EPS2
+ 4},
3516 .translate
= translate_rsr
,
3517 .par
= (const uint32_t[]){EPS2
+ 5},
3519 .name
= "rsr.exccause",
3520 .translate
= translate_rsr
,
3521 .par
= (const uint32_t[]){EXCCAUSE
},
3523 .name
= "rsr.excsave1",
3524 .translate
= translate_rsr
,
3525 .par
= (const uint32_t[]){EXCSAVE1
},
3527 .name
= "rsr.excsave2",
3528 .translate
= translate_rsr
,
3529 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
3531 .name
= "rsr.excsave3",
3532 .translate
= translate_rsr
,
3533 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
3535 .name
= "rsr.excsave4",
3536 .translate
= translate_rsr
,
3537 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
3539 .name
= "rsr.excsave5",
3540 .translate
= translate_rsr
,
3541 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
3543 .name
= "rsr.excsave6",
3544 .translate
= translate_rsr
,
3545 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
3547 .name
= "rsr.excsave7",
3548 .translate
= translate_rsr
,
3549 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
3551 .name
= "rsr.excvaddr",
3552 .translate
= translate_rsr
,
3553 .par
= (const uint32_t[]){EXCVADDR
},
3555 .name
= "rsr.ibreaka0",
3556 .translate
= translate_rsr
,
3557 .par
= (const uint32_t[]){IBREAKA
},
3559 .name
= "rsr.ibreaka1",
3560 .translate
= translate_rsr
,
3561 .par
= (const uint32_t[]){IBREAKA
+ 1},
3563 .name
= "rsr.ibreakenable",
3564 .translate
= translate_rsr
,
3565 .par
= (const uint32_t[]){IBREAKENABLE
},
3567 .name
= "rsr.icount",
3568 .translate
= translate_rsr
,
3569 .par
= (const uint32_t[]){ICOUNT
},
3571 .name
= "rsr.icountlevel",
3572 .translate
= translate_rsr
,
3573 .par
= (const uint32_t[]){ICOUNTLEVEL
},
3575 .name
= "rsr.intclear",
3576 .translate
= translate_rsr
,
3577 .par
= (const uint32_t[]){INTCLEAR
},
3579 .name
= "rsr.intenable",
3580 .translate
= translate_rsr
,
3581 .par
= (const uint32_t[]){INTENABLE
},
3583 .name
= "rsr.interrupt",
3584 .translate
= translate_rsr
,
3585 .par
= (const uint32_t[]){INTSET
},
3587 .name
= "rsr.intset",
3588 .translate
= translate_rsr
,
3589 .par
= (const uint32_t[]){INTSET
},
3591 .name
= "rsr.itlbcfg",
3592 .translate
= translate_rsr
,
3593 .par
= (const uint32_t[]){ITLBCFG
},
3596 .translate
= translate_rsr
,
3597 .par
= (const uint32_t[]){LBEG
},
3599 .name
= "rsr.lcount",
3600 .translate
= translate_rsr
,
3601 .par
= (const uint32_t[]){LCOUNT
},
3604 .translate
= translate_rsr
,
3605 .par
= (const uint32_t[]){LEND
},
3607 .name
= "rsr.litbase",
3608 .translate
= translate_rsr
,
3609 .par
= (const uint32_t[]){LITBASE
},
3612 .translate
= translate_rsr
,
3613 .par
= (const uint32_t[]){MR
},
3616 .translate
= translate_rsr
,
3617 .par
= (const uint32_t[]){MR
+ 1},
3620 .translate
= translate_rsr
,
3621 .par
= (const uint32_t[]){MR
+ 2},
3624 .translate
= translate_rsr
,
3625 .par
= (const uint32_t[]){MR
+ 3},
3627 .name
= "rsr.memctl",
3628 .translate
= translate_rsr
,
3629 .par
= (const uint32_t[]){MEMCTL
},
3631 .name
= "rsr.misc0",
3632 .translate
= translate_rsr
,
3633 .par
= (const uint32_t[]){MISC
},
3635 .name
= "rsr.misc1",
3636 .translate
= translate_rsr
,
3637 .par
= (const uint32_t[]){MISC
+ 1},
3639 .name
= "rsr.misc2",
3640 .translate
= translate_rsr
,
3641 .par
= (const uint32_t[]){MISC
+ 2},
3643 .name
= "rsr.misc3",
3644 .translate
= translate_rsr
,
3645 .par
= (const uint32_t[]){MISC
+ 3},
3648 .translate
= translate_rsr
,
3649 .par
= (const uint32_t[]){PRID
},
3652 .translate
= translate_rsr
,
3653 .par
= (const uint32_t[]){PS
},
3655 .name
= "rsr.ptevaddr",
3656 .translate
= translate_rsr
,
3657 .par
= (const uint32_t[]){PTEVADDR
},
3659 .name
= "rsr.rasid",
3660 .translate
= translate_rsr
,
3661 .par
= (const uint32_t[]){RASID
},
3664 .translate
= translate_rsr
,
3665 .par
= (const uint32_t[]){SAR
},
3667 .name
= "rsr.scompare1",
3668 .translate
= translate_rsr
,
3669 .par
= (const uint32_t[]){SCOMPARE1
},
3671 .name
= "rsr.vecbase",
3672 .translate
= translate_rsr
,
3673 .par
= (const uint32_t[]){VECBASE
},
3675 .name
= "rsr.windowbase",
3676 .translate
= translate_rsr
,
3677 .par
= (const uint32_t[]){WINDOW_BASE
},
3679 .name
= "rsr.windowstart",
3680 .translate
= translate_rsr
,
3681 .par
= (const uint32_t[]){WINDOW_START
},
3684 .translate
= translate_nop
,
3686 .name
= "rur.expstate",
3687 .translate
= translate_rur
,
3688 .par
= (const uint32_t[]){EXPSTATE
},
3691 .translate
= translate_rur
,
3692 .par
= (const uint32_t[]){FCR
},
3695 .translate
= translate_rur
,
3696 .par
= (const uint32_t[]){FSR
},
3698 .name
= "rur.threadptr",
3699 .translate
= translate_rur
,
3700 .par
= (const uint32_t[]){THREADPTR
},
3703 .translate
= translate_ldst
,
3704 .par
= (const uint32_t[]){MO_TEUW
, false, true},
3707 .translate
= translate_s32c1i
,
3710 .translate
= translate_s32e
,
3713 .translate
= translate_ldst
,
3714 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3717 .translate
= translate_ldst
,
3718 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3721 .translate
= translate_ldst
,
3722 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3725 .translate
= translate_ldst
,
3726 .par
= (const uint32_t[]){MO_TEUL
, true, true},
3729 .translate
= translate_ldst
,
3730 .par
= (const uint32_t[]){MO_UB
, false, true},
3733 .translate
= translate_salt
,
3734 .par
= (const uint32_t[]){TCG_COND_LT
},
3737 .translate
= translate_salt
,
3738 .par
= (const uint32_t[]){TCG_COND_LTU
},
3740 .name
= "setb_expstate",
3741 .translate
= translate_setb_expstate
,
3744 .translate
= translate_sext
,
3747 .translate
= translate_simcall
,
3750 .translate
= translate_sll
,
3753 .translate
= translate_slli
,
3756 .translate
= translate_sra
,
3759 .translate
= translate_srai
,
3762 .translate
= translate_src
,
3765 .translate
= translate_srl
,
3768 .translate
= translate_srli
,
3771 .translate
= translate_ssa8b
,
3774 .translate
= translate_ssa8l
,
3777 .translate
= translate_ssai
,
3780 .translate
= translate_ssl
,
3783 .translate
= translate_ssr
,
3786 .translate
= translate_sub
,
3789 .translate
= translate_subx
,
3790 .par
= (const uint32_t[]){1},
3793 .translate
= translate_subx
,
3794 .par
= (const uint32_t[]){2},
3797 .translate
= translate_subx
,
3798 .par
= (const uint32_t[]){3},
3801 .translate
= translate_syscall
,
3803 .name
= "umul.aa.hh",
3804 .translate
= translate_mac16
,
3805 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HH
, 0},
3807 .name
= "umul.aa.hl",
3808 .translate
= translate_mac16
,
3809 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HL
, 0},
3811 .name
= "umul.aa.lh",
3812 .translate
= translate_mac16
,
3813 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LH
, 0},
3815 .name
= "umul.aa.ll",
3816 .translate
= translate_mac16
,
3817 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LL
, 0},
3820 .translate
= translate_waiti
,
3823 .translate
= translate_wtlb
,
3824 .par
= (const uint32_t[]){true},
3827 .translate
= translate_wer
,
3830 .translate
= translate_wtlb
,
3831 .par
= (const uint32_t[]){false},
3833 .name
= "wrmsk_expstate",
3834 .translate
= translate_wrmsk_expstate
,
3837 .translate
= translate_wsr
,
3838 .par
= (const uint32_t[]){176},
3841 .translate
= translate_wsr
,
3842 .par
= (const uint32_t[]){208},
3844 .name
= "wsr.acchi",
3845 .translate
= translate_wsr
,
3846 .par
= (const uint32_t[]){ACCHI
},
3848 .name
= "wsr.acclo",
3849 .translate
= translate_wsr
,
3850 .par
= (const uint32_t[]){ACCLO
},
3852 .name
= "wsr.atomctl",
3853 .translate
= translate_wsr
,
3854 .par
= (const uint32_t[]){ATOMCTL
},
3857 .translate
= translate_wsr
,
3858 .par
= (const uint32_t[]){BR
},
3860 .name
= "wsr.cacheattr",
3861 .translate
= translate_wsr
,
3862 .par
= (const uint32_t[]){CACHEATTR
},
3864 .name
= "wsr.ccompare0",
3865 .translate
= translate_wsr
,
3866 .par
= (const uint32_t[]){CCOMPARE
},
3868 .name
= "wsr.ccompare1",
3869 .translate
= translate_wsr
,
3870 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3872 .name
= "wsr.ccompare2",
3873 .translate
= translate_wsr
,
3874 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3876 .name
= "wsr.ccount",
3877 .translate
= translate_wsr
,
3878 .par
= (const uint32_t[]){CCOUNT
},
3880 .name
= "wsr.configid0",
3881 .translate
= translate_wsr
,
3882 .par
= (const uint32_t[]){CONFIGID0
},
3884 .name
= "wsr.configid1",
3885 .translate
= translate_wsr
,
3886 .par
= (const uint32_t[]){CONFIGID1
},
3888 .name
= "wsr.cpenable",
3889 .translate
= translate_wsr
,
3890 .par
= (const uint32_t[]){CPENABLE
},
3892 .name
= "wsr.dbreaka0",
3893 .translate
= translate_wsr
,
3894 .par
= (const uint32_t[]){DBREAKA
},
3896 .name
= "wsr.dbreaka1",
3897 .translate
= translate_wsr
,
3898 .par
= (const uint32_t[]){DBREAKA
+ 1},
3900 .name
= "wsr.dbreakc0",
3901 .translate
= translate_wsr
,
3902 .par
= (const uint32_t[]){DBREAKC
},
3904 .name
= "wsr.dbreakc1",
3905 .translate
= translate_wsr
,
3906 .par
= (const uint32_t[]){DBREAKC
+ 1},
3909 .translate
= translate_wsr
,
3910 .par
= (const uint32_t[]){DDR
},
3912 .name
= "wsr.debugcause",
3913 .translate
= translate_wsr
,
3914 .par
= (const uint32_t[]){DEBUGCAUSE
},
3917 .translate
= translate_wsr
,
3918 .par
= (const uint32_t[]){DEPC
},
3920 .name
= "wsr.dtlbcfg",
3921 .translate
= translate_wsr
,
3922 .par
= (const uint32_t[]){DTLBCFG
},
3925 .translate
= translate_wsr
,
3926 .par
= (const uint32_t[]){EPC1
},
3929 .translate
= translate_wsr
,
3930 .par
= (const uint32_t[]){EPC1
+ 1},
3933 .translate
= translate_wsr
,
3934 .par
= (const uint32_t[]){EPC1
+ 2},
3937 .translate
= translate_wsr
,
3938 .par
= (const uint32_t[]){EPC1
+ 3},
3941 .translate
= translate_wsr
,
3942 .par
= (const uint32_t[]){EPC1
+ 4},
3945 .translate
= translate_wsr
,
3946 .par
= (const uint32_t[]){EPC1
+ 5},
3949 .translate
= translate_wsr
,
3950 .par
= (const uint32_t[]){EPC1
+ 6},
3953 .translate
= translate_wsr
,
3954 .par
= (const uint32_t[]){EPS2
},
3957 .translate
= translate_wsr
,
3958 .par
= (const uint32_t[]){EPS2
+ 1},
3961 .translate
= translate_wsr
,
3962 .par
= (const uint32_t[]){EPS2
+ 2},
3965 .translate
= translate_wsr
,
3966 .par
= (const uint32_t[]){EPS2
+ 3},
3969 .translate
= translate_wsr
,
3970 .par
= (const uint32_t[]){EPS2
+ 4},
3973 .translate
= translate_wsr
,
3974 .par
= (const uint32_t[]){EPS2
+ 5},
3976 .name
= "wsr.exccause",
3977 .translate
= translate_wsr
,
3978 .par
= (const uint32_t[]){EXCCAUSE
},
3980 .name
= "wsr.excsave1",
3981 .translate
= translate_wsr
,
3982 .par
= (const uint32_t[]){EXCSAVE1
},
3984 .name
= "wsr.excsave2",
3985 .translate
= translate_wsr
,
3986 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
3988 .name
= "wsr.excsave3",
3989 .translate
= translate_wsr
,
3990 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
3992 .name
= "wsr.excsave4",
3993 .translate
= translate_wsr
,
3994 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
3996 .name
= "wsr.excsave5",
3997 .translate
= translate_wsr
,
3998 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4000 .name
= "wsr.excsave6",
4001 .translate
= translate_wsr
,
4002 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4004 .name
= "wsr.excsave7",
4005 .translate
= translate_wsr
,
4006 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4008 .name
= "wsr.excvaddr",
4009 .translate
= translate_wsr
,
4010 .par
= (const uint32_t[]){EXCVADDR
},
4012 .name
= "wsr.ibreaka0",
4013 .translate
= translate_wsr
,
4014 .par
= (const uint32_t[]){IBREAKA
},
4016 .name
= "wsr.ibreaka1",
4017 .translate
= translate_wsr
,
4018 .par
= (const uint32_t[]){IBREAKA
+ 1},
4020 .name
= "wsr.ibreakenable",
4021 .translate
= translate_wsr
,
4022 .par
= (const uint32_t[]){IBREAKENABLE
},
4024 .name
= "wsr.icount",
4025 .translate
= translate_wsr
,
4026 .par
= (const uint32_t[]){ICOUNT
},
4028 .name
= "wsr.icountlevel",
4029 .translate
= translate_wsr
,
4030 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4032 .name
= "wsr.intclear",
4033 .translate
= translate_wsr
,
4034 .par
= (const uint32_t[]){INTCLEAR
},
4036 .name
= "wsr.intenable",
4037 .translate
= translate_wsr
,
4038 .par
= (const uint32_t[]){INTENABLE
},
4040 .name
= "wsr.interrupt",
4041 .translate
= translate_wsr
,
4042 .par
= (const uint32_t[]){INTSET
},
4044 .name
= "wsr.intset",
4045 .translate
= translate_wsr
,
4046 .par
= (const uint32_t[]){INTSET
},
4048 .name
= "wsr.itlbcfg",
4049 .translate
= translate_wsr
,
4050 .par
= (const uint32_t[]){ITLBCFG
},
4053 .translate
= translate_wsr
,
4054 .par
= (const uint32_t[]){LBEG
},
4056 .name
= "wsr.lcount",
4057 .translate
= translate_wsr
,
4058 .par
= (const uint32_t[]){LCOUNT
},
4061 .translate
= translate_wsr
,
4062 .par
= (const uint32_t[]){LEND
},
4064 .name
= "wsr.litbase",
4065 .translate
= translate_wsr
,
4066 .par
= (const uint32_t[]){LITBASE
},
4069 .translate
= translate_wsr
,
4070 .par
= (const uint32_t[]){MR
},
4073 .translate
= translate_wsr
,
4074 .par
= (const uint32_t[]){MR
+ 1},
4077 .translate
= translate_wsr
,
4078 .par
= (const uint32_t[]){MR
+ 2},
4081 .translate
= translate_wsr
,
4082 .par
= (const uint32_t[]){MR
+ 3},
4084 .name
= "wsr.memctl",
4085 .translate
= translate_wsr
,
4086 .par
= (const uint32_t[]){MEMCTL
},
4088 .name
= "wsr.misc0",
4089 .translate
= translate_wsr
,
4090 .par
= (const uint32_t[]){MISC
},
4092 .name
= "wsr.misc1",
4093 .translate
= translate_wsr
,
4094 .par
= (const uint32_t[]){MISC
+ 1},
4096 .name
= "wsr.misc2",
4097 .translate
= translate_wsr
,
4098 .par
= (const uint32_t[]){MISC
+ 2},
4100 .name
= "wsr.misc3",
4101 .translate
= translate_wsr
,
4102 .par
= (const uint32_t[]){MISC
+ 3},
4105 .translate
= translate_wsr
,
4106 .par
= (const uint32_t[]){MMID
},
4109 .translate
= translate_wsr
,
4110 .par
= (const uint32_t[]){PRID
},
4113 .translate
= translate_wsr
,
4114 .par
= (const uint32_t[]){PS
},
4116 .name
= "wsr.ptevaddr",
4117 .translate
= translate_wsr
,
4118 .par
= (const uint32_t[]){PTEVADDR
},
4120 .name
= "wsr.rasid",
4121 .translate
= translate_wsr
,
4122 .par
= (const uint32_t[]){RASID
},
4125 .translate
= translate_wsr
,
4126 .par
= (const uint32_t[]){SAR
},
4128 .name
= "wsr.scompare1",
4129 .translate
= translate_wsr
,
4130 .par
= (const uint32_t[]){SCOMPARE1
},
4132 .name
= "wsr.vecbase",
4133 .translate
= translate_wsr
,
4134 .par
= (const uint32_t[]){VECBASE
},
4136 .name
= "wsr.windowbase",
4137 .translate
= translate_wsr
,
4138 .par
= (const uint32_t[]){WINDOW_BASE
},
4140 .name
= "wsr.windowstart",
4141 .translate
= translate_wsr
,
4142 .par
= (const uint32_t[]){WINDOW_START
},
4144 .name
= "wur.expstate",
4145 .translate
= translate_wur
,
4146 .par
= (const uint32_t[]){EXPSTATE
},
4149 .translate
= translate_wur
,
4150 .par
= (const uint32_t[]){FCR
},
4153 .translate
= translate_wur
,
4154 .par
= (const uint32_t[]){FSR
},
4156 .name
= "wur.threadptr",
4157 .translate
= translate_wur
,
4158 .par
= (const uint32_t[]){THREADPTR
},
4161 .translate
= translate_xor
,
4164 .translate
= translate_boolean
,
4165 .par
= (const uint32_t[]){BOOLEAN_XOR
},
4168 .translate
= translate_xsr
,
4169 .par
= (const uint32_t[]){176},
4172 .translate
= translate_xsr
,
4173 .par
= (const uint32_t[]){208},
4175 .name
= "xsr.acchi",
4176 .translate
= translate_xsr
,
4177 .par
= (const uint32_t[]){ACCHI
},
4179 .name
= "xsr.acclo",
4180 .translate
= translate_xsr
,
4181 .par
= (const uint32_t[]){ACCLO
},
4183 .name
= "xsr.atomctl",
4184 .translate
= translate_xsr
,
4185 .par
= (const uint32_t[]){ATOMCTL
},
4188 .translate
= translate_xsr
,
4189 .par
= (const uint32_t[]){BR
},
4191 .name
= "xsr.cacheattr",
4192 .translate
= translate_xsr
,
4193 .par
= (const uint32_t[]){CACHEATTR
},
4195 .name
= "xsr.ccompare0",
4196 .translate
= translate_xsr
,
4197 .par
= (const uint32_t[]){CCOMPARE
},
4199 .name
= "xsr.ccompare1",
4200 .translate
= translate_xsr
,
4201 .par
= (const uint32_t[]){CCOMPARE
+ 1},
4203 .name
= "xsr.ccompare2",
4204 .translate
= translate_xsr
,
4205 .par
= (const uint32_t[]){CCOMPARE
+ 2},
4207 .name
= "xsr.ccount",
4208 .translate
= translate_xsr
,
4209 .par
= (const uint32_t[]){CCOUNT
},
4211 .name
= "xsr.configid0",
4212 .translate
= translate_xsr
,
4213 .par
= (const uint32_t[]){CONFIGID0
},
4215 .name
= "xsr.configid1",
4216 .translate
= translate_xsr
,
4217 .par
= (const uint32_t[]){CONFIGID1
},
4219 .name
= "xsr.cpenable",
4220 .translate
= translate_xsr
,
4221 .par
= (const uint32_t[]){CPENABLE
},
4223 .name
= "xsr.dbreaka0",
4224 .translate
= translate_xsr
,
4225 .par
= (const uint32_t[]){DBREAKA
},
4227 .name
= "xsr.dbreaka1",
4228 .translate
= translate_xsr
,
4229 .par
= (const uint32_t[]){DBREAKA
+ 1},
4231 .name
= "xsr.dbreakc0",
4232 .translate
= translate_xsr
,
4233 .par
= (const uint32_t[]){DBREAKC
},
4235 .name
= "xsr.dbreakc1",
4236 .translate
= translate_xsr
,
4237 .par
= (const uint32_t[]){DBREAKC
+ 1},
4240 .translate
= translate_xsr
,
4241 .par
= (const uint32_t[]){DDR
},
4243 .name
= "xsr.debugcause",
4244 .translate
= translate_xsr
,
4245 .par
= (const uint32_t[]){DEBUGCAUSE
},
4248 .translate
= translate_xsr
,
4249 .par
= (const uint32_t[]){DEPC
},
4251 .name
= "xsr.dtlbcfg",
4252 .translate
= translate_xsr
,
4253 .par
= (const uint32_t[]){DTLBCFG
},
4256 .translate
= translate_xsr
,
4257 .par
= (const uint32_t[]){EPC1
},
4260 .translate
= translate_xsr
,
4261 .par
= (const uint32_t[]){EPC1
+ 1},
4264 .translate
= translate_xsr
,
4265 .par
= (const uint32_t[]){EPC1
+ 2},
4268 .translate
= translate_xsr
,
4269 .par
= (const uint32_t[]){EPC1
+ 3},
4272 .translate
= translate_xsr
,
4273 .par
= (const uint32_t[]){EPC1
+ 4},
4276 .translate
= translate_xsr
,
4277 .par
= (const uint32_t[]){EPC1
+ 5},
4280 .translate
= translate_xsr
,
4281 .par
= (const uint32_t[]){EPC1
+ 6},
4284 .translate
= translate_xsr
,
4285 .par
= (const uint32_t[]){EPS2
},
4288 .translate
= translate_xsr
,
4289 .par
= (const uint32_t[]){EPS2
+ 1},
4292 .translate
= translate_xsr
,
4293 .par
= (const uint32_t[]){EPS2
+ 2},
4296 .translate
= translate_xsr
,
4297 .par
= (const uint32_t[]){EPS2
+ 3},
4300 .translate
= translate_xsr
,
4301 .par
= (const uint32_t[]){EPS2
+ 4},
4304 .translate
= translate_xsr
,
4305 .par
= (const uint32_t[]){EPS2
+ 5},
4307 .name
= "xsr.exccause",
4308 .translate
= translate_xsr
,
4309 .par
= (const uint32_t[]){EXCCAUSE
},
4311 .name
= "xsr.excsave1",
4312 .translate
= translate_xsr
,
4313 .par
= (const uint32_t[]){EXCSAVE1
},
4315 .name
= "xsr.excsave2",
4316 .translate
= translate_xsr
,
4317 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
4319 .name
= "xsr.excsave3",
4320 .translate
= translate_xsr
,
4321 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
4323 .name
= "xsr.excsave4",
4324 .translate
= translate_xsr
,
4325 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
4327 .name
= "xsr.excsave5",
4328 .translate
= translate_xsr
,
4329 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4331 .name
= "xsr.excsave6",
4332 .translate
= translate_xsr
,
4333 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4335 .name
= "xsr.excsave7",
4336 .translate
= translate_xsr
,
4337 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4339 .name
= "xsr.excvaddr",
4340 .translate
= translate_xsr
,
4341 .par
= (const uint32_t[]){EXCVADDR
},
4343 .name
= "xsr.ibreaka0",
4344 .translate
= translate_xsr
,
4345 .par
= (const uint32_t[]){IBREAKA
},
4347 .name
= "xsr.ibreaka1",
4348 .translate
= translate_xsr
,
4349 .par
= (const uint32_t[]){IBREAKA
+ 1},
4351 .name
= "xsr.ibreakenable",
4352 .translate
= translate_xsr
,
4353 .par
= (const uint32_t[]){IBREAKENABLE
},
4355 .name
= "xsr.icount",
4356 .translate
= translate_xsr
,
4357 .par
= (const uint32_t[]){ICOUNT
},
4359 .name
= "xsr.icountlevel",
4360 .translate
= translate_xsr
,
4361 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4363 .name
= "xsr.intclear",
4364 .translate
= translate_xsr
,
4365 .par
= (const uint32_t[]){INTCLEAR
},
4367 .name
= "xsr.intenable",
4368 .translate
= translate_xsr
,
4369 .par
= (const uint32_t[]){INTENABLE
},
4371 .name
= "xsr.interrupt",
4372 .translate
= translate_xsr
,
4373 .par
= (const uint32_t[]){INTSET
},
4375 .name
= "xsr.intset",
4376 .translate
= translate_xsr
,
4377 .par
= (const uint32_t[]){INTSET
},
4379 .name
= "xsr.itlbcfg",
4380 .translate
= translate_xsr
,
4381 .par
= (const uint32_t[]){ITLBCFG
},
4384 .translate
= translate_xsr
,
4385 .par
= (const uint32_t[]){LBEG
},
4387 .name
= "xsr.lcount",
4388 .translate
= translate_xsr
,
4389 .par
= (const uint32_t[]){LCOUNT
},
4392 .translate
= translate_xsr
,
4393 .par
= (const uint32_t[]){LEND
},
4395 .name
= "xsr.litbase",
4396 .translate
= translate_xsr
,
4397 .par
= (const uint32_t[]){LITBASE
},
4400 .translate
= translate_xsr
,
4401 .par
= (const uint32_t[]){MR
},
4404 .translate
= translate_xsr
,
4405 .par
= (const uint32_t[]){MR
+ 1},
4408 .translate
= translate_xsr
,
4409 .par
= (const uint32_t[]){MR
+ 2},
4412 .translate
= translate_xsr
,
4413 .par
= (const uint32_t[]){MR
+ 3},
4415 .name
= "xsr.memctl",
4416 .translate
= translate_xsr
,
4417 .par
= (const uint32_t[]){MEMCTL
},
4419 .name
= "xsr.misc0",
4420 .translate
= translate_xsr
,
4421 .par
= (const uint32_t[]){MISC
},
4423 .name
= "xsr.misc1",
4424 .translate
= translate_xsr
,
4425 .par
= (const uint32_t[]){MISC
+ 1},
4427 .name
= "xsr.misc2",
4428 .translate
= translate_xsr
,
4429 .par
= (const uint32_t[]){MISC
+ 2},
4431 .name
= "xsr.misc3",
4432 .translate
= translate_xsr
,
4433 .par
= (const uint32_t[]){MISC
+ 3},
4436 .translate
= translate_xsr
,
4437 .par
= (const uint32_t[]){PRID
},
4440 .translate
= translate_xsr
,
4441 .par
= (const uint32_t[]){PS
},
4443 .name
= "xsr.ptevaddr",
4444 .translate
= translate_xsr
,
4445 .par
= (const uint32_t[]){PTEVADDR
},
4447 .name
= "xsr.rasid",
4448 .translate
= translate_xsr
,
4449 .par
= (const uint32_t[]){RASID
},
4452 .translate
= translate_xsr
,
4453 .par
= (const uint32_t[]){SAR
},
4455 .name
= "xsr.scompare1",
4456 .translate
= translate_xsr
,
4457 .par
= (const uint32_t[]){SCOMPARE1
},
4459 .name
= "xsr.vecbase",
4460 .translate
= translate_xsr
,
4461 .par
= (const uint32_t[]){VECBASE
},
4463 .name
= "xsr.windowbase",
4464 .translate
= translate_xsr
,
4465 .par
= (const uint32_t[]){WINDOW_BASE
},
4467 .name
= "xsr.windowstart",
4468 .translate
= translate_xsr
,
4469 .par
= (const uint32_t[]){WINDOW_START
},
4473 const XtensaOpcodeTranslators xtensa_core_opcodes
= {
4474 .num_opcodes
= ARRAY_SIZE(core_ops
),
4479 static void translate_abs_s(DisasContext
*dc
, const uint32_t arg
[],
4480 const uint32_t par
[])
4482 if (gen_check_cpenable(dc
, 0)) {
4483 gen_helper_abs_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4487 static void translate_add_s(DisasContext
*dc
, const uint32_t arg
[],
4488 const uint32_t par
[])
4490 if (gen_check_cpenable(dc
, 0)) {
4491 gen_helper_add_s(cpu_FR
[arg
[0]], cpu_env
,
4492 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4506 static void translate_compare_s(DisasContext
*dc
, const uint32_t arg
[],
4507 const uint32_t par
[])
4509 static void (* const helper
[])(TCGv_env env
, TCGv_i32 bit
,
4510 TCGv_i32 s
, TCGv_i32 t
) = {
4511 [COMPARE_UN
] = gen_helper_un_s
,
4512 [COMPARE_OEQ
] = gen_helper_oeq_s
,
4513 [COMPARE_UEQ
] = gen_helper_ueq_s
,
4514 [COMPARE_OLT
] = gen_helper_olt_s
,
4515 [COMPARE_ULT
] = gen_helper_ult_s
,
4516 [COMPARE_OLE
] = gen_helper_ole_s
,
4517 [COMPARE_ULE
] = gen_helper_ule_s
,
4520 if (gen_check_cpenable(dc
, 0)) {
4521 TCGv_i32 bit
= tcg_const_i32(1 << arg
[0]);
4523 helper
[par
[0]](cpu_env
, bit
, cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4528 static void translate_float_s(DisasContext
*dc
, const uint32_t arg
[],
4529 const uint32_t par
[])
4531 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4532 TCGv_i32 scale
= tcg_const_i32(-arg
[2]);
4535 gen_helper_uitof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4537 gen_helper_itof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4539 tcg_temp_free(scale
);
4543 static void translate_ftoi_s(DisasContext
*dc
, const uint32_t arg
[],
4544 const uint32_t par
[])
4546 if (gen_window_check1(dc
, arg
[0]) && gen_check_cpenable(dc
, 0)) {
4547 TCGv_i32 rounding_mode
= tcg_const_i32(par
[0]);
4548 TCGv_i32 scale
= tcg_const_i32(arg
[2]);
4551 gen_helper_ftoui(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4552 rounding_mode
, scale
);
4554 gen_helper_ftoi(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4555 rounding_mode
, scale
);
4557 tcg_temp_free(rounding_mode
);
4558 tcg_temp_free(scale
);
4562 static void translate_ldsti(DisasContext
*dc
, const uint32_t arg
[],
4563 const uint32_t par
[])
4565 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4566 TCGv_i32 addr
= tcg_temp_new_i32();
4568 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
4569 gen_load_store_alignment(dc
, 2, addr
, false);
4571 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4573 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4576 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4578 tcg_temp_free(addr
);
4582 static void translate_ldstx(DisasContext
*dc
, const uint32_t arg
[],
4583 const uint32_t par
[])
4585 if (gen_window_check2(dc
, arg
[1], arg
[2]) && gen_check_cpenable(dc
, 0)) {
4586 TCGv_i32 addr
= tcg_temp_new_i32();
4588 tcg_gen_add_i32(addr
, cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
4589 gen_load_store_alignment(dc
, 2, addr
, false);
4591 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4593 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4596 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4598 tcg_temp_free(addr
);
4602 static void translate_madd_s(DisasContext
*dc
, const uint32_t arg
[],
4603 const uint32_t par
[])
4605 if (gen_check_cpenable(dc
, 0)) {
4606 gen_helper_madd_s(cpu_FR
[arg
[0]], cpu_env
,
4607 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4611 static void translate_mov_s(DisasContext
*dc
, const uint32_t arg
[],
4612 const uint32_t par
[])
4614 if (gen_check_cpenable(dc
, 0)) {
4615 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4619 static void translate_movcond_s(DisasContext
*dc
, const uint32_t arg
[],
4620 const uint32_t par
[])
4622 if (gen_window_check1(dc
, arg
[2]) && gen_check_cpenable(dc
, 0)) {
4623 TCGv_i32 zero
= tcg_const_i32(0);
4625 tcg_gen_movcond_i32(par
[0], cpu_FR
[arg
[0]],
4626 cpu_R
[arg
[2]], zero
,
4627 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4628 tcg_temp_free(zero
);
4632 static void translate_movp_s(DisasContext
*dc
, const uint32_t arg
[],
4633 const uint32_t par
[])
4635 if (gen_check_cpenable(dc
, 0)) {
4636 TCGv_i32 zero
= tcg_const_i32(0);
4637 TCGv_i32 tmp
= tcg_temp_new_i32();
4639 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
4640 tcg_gen_movcond_i32(par
[0],
4641 cpu_FR
[arg
[0]], tmp
, zero
,
4642 cpu_FR
[arg
[1]], cpu_FR
[arg
[0]]);
4644 tcg_temp_free(zero
);
4648 static void translate_mul_s(DisasContext
*dc
, const uint32_t arg
[],
4649 const uint32_t par
[])
4651 if (gen_check_cpenable(dc
, 0)) {
4652 gen_helper_mul_s(cpu_FR
[arg
[0]], cpu_env
,
4653 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4657 static void translate_msub_s(DisasContext
*dc
, const uint32_t arg
[],
4658 const uint32_t par
[])
4660 if (gen_check_cpenable(dc
, 0)) {
4661 gen_helper_msub_s(cpu_FR
[arg
[0]], cpu_env
,
4662 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4666 static void translate_neg_s(DisasContext
*dc
, const uint32_t arg
[],
4667 const uint32_t par
[])
4669 if (gen_check_cpenable(dc
, 0)) {
4670 gen_helper_neg_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4674 static void translate_rfr_s(DisasContext
*dc
, const uint32_t arg
[],
4675 const uint32_t par
[])
4677 if (gen_window_check1(dc
, arg
[0]) &&
4678 gen_check_cpenable(dc
, 0)) {
4679 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_FR
[arg
[1]]);
4683 static void translate_sub_s(DisasContext
*dc
, const uint32_t arg
[],
4684 const uint32_t par
[])
4686 if (gen_check_cpenable(dc
, 0)) {
4687 gen_helper_sub_s(cpu_FR
[arg
[0]], cpu_env
,
4688 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4692 static void translate_wfr_s(DisasContext
*dc
, const uint32_t arg
[],
4693 const uint32_t par
[])
4695 if (gen_window_check1(dc
, arg
[1]) &&
4696 gen_check_cpenable(dc
, 0)) {
4697 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_R
[arg
[1]]);
4701 static const XtensaOpcodeOps fpu2000_ops
[] = {
4704 .translate
= translate_abs_s
,
4707 .translate
= translate_add_s
,
4710 .translate
= translate_ftoi_s
,
4711 .par
= (const uint32_t[]){float_round_up
, false},
4714 .translate
= translate_float_s
,
4715 .par
= (const uint32_t[]){false},
4718 .translate
= translate_ftoi_s
,
4719 .par
= (const uint32_t[]){float_round_down
, false},
4722 .translate
= translate_ldsti
,
4723 .par
= (const uint32_t[]){false, false},
4726 .translate
= translate_ldsti
,
4727 .par
= (const uint32_t[]){false, true},
4730 .translate
= translate_ldstx
,
4731 .par
= (const uint32_t[]){false, false},
4734 .translate
= translate_ldstx
,
4735 .par
= (const uint32_t[]){false, true},
4738 .translate
= translate_madd_s
,
4741 .translate
= translate_mov_s
,
4744 .translate
= translate_movcond_s
,
4745 .par
= (const uint32_t[]){TCG_COND_EQ
},
4748 .translate
= translate_movp_s
,
4749 .par
= (const uint32_t[]){TCG_COND_EQ
},
4752 .translate
= translate_movcond_s
,
4753 .par
= (const uint32_t[]){TCG_COND_GE
},
4756 .translate
= translate_movcond_s
,
4757 .par
= (const uint32_t[]){TCG_COND_LT
},
4760 .translate
= translate_movcond_s
,
4761 .par
= (const uint32_t[]){TCG_COND_NE
},
4764 .translate
= translate_movp_s
,
4765 .par
= (const uint32_t[]){TCG_COND_NE
},
4768 .translate
= translate_msub_s
,
4771 .translate
= translate_mul_s
,
4774 .translate
= translate_neg_s
,
4777 .translate
= translate_compare_s
,
4778 .par
= (const uint32_t[]){COMPARE_OEQ
},
4781 .translate
= translate_compare_s
,
4782 .par
= (const uint32_t[]){COMPARE_OLE
},
4785 .translate
= translate_compare_s
,
4786 .par
= (const uint32_t[]){COMPARE_OLT
},
4789 .translate
= translate_rfr_s
,
4792 .translate
= translate_ftoi_s
,
4793 .par
= (const uint32_t[]){float_round_nearest_even
, false},
4796 .translate
= translate_ldsti
,
4797 .par
= (const uint32_t[]){true, false},
4800 .translate
= translate_ldsti
,
4801 .par
= (const uint32_t[]){true, true},
4804 .translate
= translate_ldstx
,
4805 .par
= (const uint32_t[]){true, false},
4808 .translate
= translate_ldstx
,
4809 .par
= (const uint32_t[]){true, true},
4812 .translate
= translate_sub_s
,
4815 .translate
= translate_ftoi_s
,
4816 .par
= (const uint32_t[]){float_round_to_zero
, false},
4819 .translate
= translate_compare_s
,
4820 .par
= (const uint32_t[]){COMPARE_UEQ
},
4823 .translate
= translate_float_s
,
4824 .par
= (const uint32_t[]){true},
4827 .translate
= translate_compare_s
,
4828 .par
= (const uint32_t[]){COMPARE_ULE
},
4831 .translate
= translate_compare_s
,
4832 .par
= (const uint32_t[]){COMPARE_ULT
},
4835 .translate
= translate_compare_s
,
4836 .par
= (const uint32_t[]){COMPARE_UN
},
4839 .translate
= translate_ftoi_s
,
4840 .par
= (const uint32_t[]){float_round_to_zero
, true},
4843 .translate
= translate_wfr_s
,
4847 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
= {
4848 .num_opcodes
= ARRAY_SIZE(fpu2000_ops
),
4849 .opcode
= fpu2000_ops
,