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pc: Move APIC and NUMA data from PcGuestInfo to PCMachineState
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob35582a761dce1478ffc91c11d9761eae50df909c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "acpi-build.h"
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/nvram/fw_cfg.h"
37 #include "hw/acpi/bios-linker-loader.h"
38 #include "hw/loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/acpi/memory_hotplug.h"
41 #include "hw/mem/nvdimm.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
45 #include "hw/timer/mc146818rtc_regs.h"
46
47 /* Supported chipsets: */
48 #include "hw/acpi/piix4.h"
49 #include "hw/acpi/pcihp.h"
50 #include "hw/i386/ich9.h"
51 #include "hw/pci/pci_bus.h"
52 #include "hw/pci-host/q35.h"
53 #include "hw/i386/intel_iommu.h"
54 #include "hw/timer/hpet.h"
55
56 #include "hw/acpi/aml-build.h"
57
58 #include "qapi/qmp/qint.h"
59 #include "qom/qom-qobject.h"
60
61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
65 */
66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67 #define ACPI_BUILD_ALIGN_SIZE 0x1000
68
69 #define ACPI_BUILD_TABLE_SIZE 0x20000
70
71 /* #define DEBUG_ACPI_BUILD */
72 #ifdef DEBUG_ACPI_BUILD
73 #define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
75 #else
76 #define ACPI_BUILD_DPRINTF(fmt, ...)
77 #endif
78
79 typedef struct AcpiCpuInfo {
80 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
81 } AcpiCpuInfo;
82
83 typedef struct AcpiMcfgInfo {
84 uint64_t mcfg_base;
85 uint32_t mcfg_size;
86 } AcpiMcfgInfo;
87
88 typedef struct AcpiPmInfo {
89 bool s3_disabled;
90 bool s4_disabled;
91 bool pcihp_bridge_en;
92 uint8_t s4_val;
93 uint16_t sci_int;
94 uint8_t acpi_enable_cmd;
95 uint8_t acpi_disable_cmd;
96 uint32_t gpe0_blk;
97 uint32_t gpe0_blk_len;
98 uint32_t io_base;
99 uint16_t cpu_hp_io_base;
100 uint16_t cpu_hp_io_len;
101 uint16_t mem_hp_io_base;
102 uint16_t mem_hp_io_len;
103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
105 } AcpiPmInfo;
106
107 typedef struct AcpiMiscInfo {
108 bool is_piix4;
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 static
125 int acpi_add_cpu_info(Object *o, void *opaque)
126 {
127 AcpiCpuInfo *cpu = opaque;
128 uint64_t apic_id;
129
130 if (object_dynamic_cast(o, TYPE_CPU)) {
131 apic_id = object_property_get_int(o, "apic-id", NULL);
132 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
133
134 set_bit(apic_id, cpu->found_cpus);
135 }
136
137 object_child_foreach(o, acpi_add_cpu_info, opaque);
138 return 0;
139 }
140
141 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
142 {
143 Object *root = object_get_root();
144
145 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
146 object_child_foreach(root, acpi_add_cpu_info, cpu);
147 }
148
149 static void acpi_get_pm_info(AcpiPmInfo *pm)
150 {
151 Object *piix = piix4_pm_find();
152 Object *lpc = ich9_lpc_find();
153 Object *obj = NULL;
154 QObject *o;
155
156 pm->cpu_hp_io_base = 0;
157 pm->pcihp_io_base = 0;
158 pm->pcihp_io_len = 0;
159 if (piix) {
160 obj = piix;
161 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
162 pm->pcihp_io_base =
163 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
164 pm->pcihp_io_len =
165 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
166 }
167 if (lpc) {
168 obj = lpc;
169 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
170 }
171 assert(obj);
172
173 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
174 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
175 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
176
177 /* Fill in optional s3/s4 related properties */
178 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
179 if (o) {
180 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
181 } else {
182 pm->s3_disabled = false;
183 }
184 qobject_decref(o);
185 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
186 if (o) {
187 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
188 } else {
189 pm->s4_disabled = false;
190 }
191 qobject_decref(o);
192 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
193 if (o) {
194 pm->s4_val = qint_get_int(qobject_to_qint(o));
195 } else {
196 pm->s4_val = false;
197 }
198 qobject_decref(o);
199
200 /* Fill in mandatory properties */
201 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
202
203 pm->acpi_enable_cmd = object_property_get_int(obj,
204 ACPI_PM_PROP_ACPI_ENABLE_CMD,
205 NULL);
206 pm->acpi_disable_cmd = object_property_get_int(obj,
207 ACPI_PM_PROP_ACPI_DISABLE_CMD,
208 NULL);
209 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
210 NULL);
211 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
212 NULL);
213 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
214 NULL);
215 pm->pcihp_bridge_en =
216 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
217 NULL);
218 }
219
220 static void acpi_get_misc_info(AcpiMiscInfo *info)
221 {
222 Object *piix = piix4_pm_find();
223 Object *lpc = ich9_lpc_find();
224 assert(!!piix != !!lpc);
225
226 if (piix) {
227 info->is_piix4 = true;
228 }
229 if (lpc) {
230 info->is_piix4 = false;
231 }
232
233 info->has_hpet = hpet_find();
234 info->tpm_version = tpm_get_version();
235 info->pvpanic_port = pvpanic_port();
236 info->applesmc_io_base = applesmc_port();
237 }
238
239 /*
240 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
241 * On i386 arch we only have two pci hosts, so we can look only for them.
242 */
243 static Object *acpi_get_i386_pci_host(void)
244 {
245 PCIHostState *host;
246
247 host = OBJECT_CHECK(PCIHostState,
248 object_resolve_path("/machine/i440fx", NULL),
249 TYPE_PCI_HOST_BRIDGE);
250 if (!host) {
251 host = OBJECT_CHECK(PCIHostState,
252 object_resolve_path("/machine/q35", NULL),
253 TYPE_PCI_HOST_BRIDGE);
254 }
255
256 return OBJECT(host);
257 }
258
259 static void acpi_get_pci_info(PcPciInfo *info)
260 {
261 Object *pci_host;
262
263
264 pci_host = acpi_get_i386_pci_host();
265 g_assert(pci_host);
266
267 info->w32.begin = object_property_get_int(pci_host,
268 PCI_HOST_PROP_PCI_HOLE_START,
269 NULL);
270 info->w32.end = object_property_get_int(pci_host,
271 PCI_HOST_PROP_PCI_HOLE_END,
272 NULL);
273 info->w64.begin = object_property_get_int(pci_host,
274 PCI_HOST_PROP_PCI_HOLE64_START,
275 NULL);
276 info->w64.end = object_property_get_int(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_END,
278 NULL);
279 }
280
281 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
282
283 static void acpi_align_size(GArray *blob, unsigned align)
284 {
285 /* Align size to multiple of given size. This reduces the chance
286 * we need to change size in the future (breaking cross version migration).
287 */
288 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
289 }
290
291 /* FACS */
292 static void
293 build_facs(GArray *table_data, GArray *linker)
294 {
295 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
296 memcpy(&facs->signature, "FACS", 4);
297 facs->length = cpu_to_le32(sizeof(*facs));
298 }
299
300 /* Load chipset information in FADT */
301 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
302 {
303 fadt->model = 1;
304 fadt->reserved1 = 0;
305 fadt->sci_int = cpu_to_le16(pm->sci_int);
306 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
307 fadt->acpi_enable = pm->acpi_enable_cmd;
308 fadt->acpi_disable = pm->acpi_disable_cmd;
309 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
310 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
311 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
312 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
313 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
314 /* EVT, CNT, TMR length matches hw/acpi/core.c */
315 fadt->pm1_evt_len = 4;
316 fadt->pm1_cnt_len = 2;
317 fadt->pm_tmr_len = 4;
318 fadt->gpe0_blk_len = pm->gpe0_blk_len;
319 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
320 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
321 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
322 (1 << ACPI_FADT_F_PROC_C1) |
323 (1 << ACPI_FADT_F_SLP_BUTTON) |
324 (1 << ACPI_FADT_F_RTC_S4));
325 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
326 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
327 * For more than 8 CPUs, "Clustered Logical" mode has to be used
328 */
329 if (max_cpus > 8) {
330 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
331 }
332 fadt->century = RTC_CENTURY;
333 }
334
335
336 /* FADT */
337 static void
338 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
339 unsigned facs, unsigned dsdt)
340 {
341 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
342
343 fadt->firmware_ctrl = cpu_to_le32(facs);
344 /* FACS address to be filled by Guest linker */
345 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
346 ACPI_BUILD_TABLE_FILE,
347 table_data, &fadt->firmware_ctrl,
348 sizeof fadt->firmware_ctrl);
349
350 fadt->dsdt = cpu_to_le32(dsdt);
351 /* DSDT address to be filled by Guest linker */
352 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
353 ACPI_BUILD_TABLE_FILE,
354 table_data, &fadt->dsdt,
355 sizeof fadt->dsdt);
356
357 fadt_setup(fadt, pm);
358
359 build_header(linker, table_data,
360 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL);
361 }
362
363 static void
364 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu)
365 {
366 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
367 int madt_start = table_data->len;
368
369 AcpiMultipleApicTable *madt;
370 AcpiMadtIoApic *io_apic;
371 AcpiMadtIntsrcovr *intsrcovr;
372 AcpiMadtLocalNmi *local_nmi;
373 int i;
374
375 madt = acpi_data_push(table_data, sizeof *madt);
376 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
377 madt->flags = cpu_to_le32(1);
378
379 for (i = 0; i < pcms->apic_id_limit; i++) {
380 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
381 apic->type = ACPI_APIC_PROCESSOR;
382 apic->length = sizeof(*apic);
383 apic->processor_id = i;
384 apic->local_apic_id = i;
385 if (test_bit(i, cpu->found_cpus)) {
386 apic->flags = cpu_to_le32(1);
387 } else {
388 apic->flags = cpu_to_le32(0);
389 }
390 }
391 io_apic = acpi_data_push(table_data, sizeof *io_apic);
392 io_apic->type = ACPI_APIC_IO;
393 io_apic->length = sizeof(*io_apic);
394 #define ACPI_BUILD_IOAPIC_ID 0x0
395 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
396 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
397 io_apic->interrupt = cpu_to_le32(0);
398
399 if (pcms->apic_xrupt_override) {
400 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
401 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
402 intsrcovr->length = sizeof(*intsrcovr);
403 intsrcovr->source = 0;
404 intsrcovr->gsi = cpu_to_le32(2);
405 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
406 }
407 for (i = 1; i < 16; i++) {
408 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
409 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
410 /* No need for a INT source override structure. */
411 continue;
412 }
413 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
414 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
415 intsrcovr->length = sizeof(*intsrcovr);
416 intsrcovr->source = i;
417 intsrcovr->gsi = cpu_to_le32(i);
418 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
419 }
420
421 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
422 local_nmi->type = ACPI_APIC_LOCAL_NMI;
423 local_nmi->length = sizeof(*local_nmi);
424 local_nmi->processor_id = 0xff; /* all processors */
425 local_nmi->flags = cpu_to_le16(0);
426 local_nmi->lint = 1; /* ACPI_LINT1 */
427
428 build_header(linker, table_data,
429 (void *)(table_data->data + madt_start), "APIC",
430 table_data->len - madt_start, 1, NULL);
431 }
432
433 /* Assign BSEL property to all buses. In the future, this can be changed
434 * to only assign to buses that support hotplug.
435 */
436 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
437 {
438 unsigned *bsel_alloc = opaque;
439 unsigned *bus_bsel;
440
441 if (qbus_is_hotpluggable(BUS(bus))) {
442 bus_bsel = g_malloc(sizeof *bus_bsel);
443
444 *bus_bsel = (*bsel_alloc)++;
445 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
446 bus_bsel, NULL);
447 }
448
449 return bsel_alloc;
450 }
451
452 static void acpi_set_pci_info(void)
453 {
454 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
455 unsigned bsel_alloc = 0;
456
457 if (bus) {
458 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
459 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
460 }
461 }
462
463 static void build_append_pcihp_notify_entry(Aml *method, int slot)
464 {
465 Aml *if_ctx;
466 int32_t devfn = PCI_DEVFN(slot, 0);
467
468 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
469 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
470 aml_append(method, if_ctx);
471 }
472
473 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
474 bool pcihp_bridge_en)
475 {
476 Aml *dev, *notify_method, *method;
477 QObject *bsel;
478 PCIBus *sec;
479 int i;
480
481 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
482 if (bsel) {
483 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
484
485 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
486 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
487 }
488
489 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
490 DeviceClass *dc;
491 PCIDeviceClass *pc;
492 PCIDevice *pdev = bus->devices[i];
493 int slot = PCI_SLOT(i);
494 bool hotplug_enabled_dev;
495 bool bridge_in_acpi;
496
497 if (!pdev) {
498 if (bsel) { /* add hotplug slots for non present devices */
499 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
500 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
501 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
502 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
503 aml_append(method,
504 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
505 );
506 aml_append(dev, method);
507 aml_append(parent_scope, dev);
508
509 build_append_pcihp_notify_entry(notify_method, slot);
510 }
511 continue;
512 }
513
514 pc = PCI_DEVICE_GET_CLASS(pdev);
515 dc = DEVICE_GET_CLASS(pdev);
516
517 /* When hotplug for bridges is enabled, bridges are
518 * described in ACPI separately (see build_pci_bus_end).
519 * In this case they aren't themselves hot-pluggable.
520 * Hotplugged bridges *are* hot-pluggable.
521 */
522 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
523 !DEVICE(pdev)->hotplugged;
524
525 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
526
527 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
528 continue;
529 }
530
531 /* start to compose PCI slot descriptor */
532 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
533 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
534
535 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
536 /* add VGA specific AML methods */
537 int s3d;
538
539 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
540 s3d = 3;
541 } else {
542 s3d = 0;
543 }
544
545 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
546 aml_append(method, aml_return(aml_int(0)));
547 aml_append(dev, method);
548
549 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
550 aml_append(method, aml_return(aml_int(0)));
551 aml_append(dev, method);
552
553 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
554 aml_append(method, aml_return(aml_int(s3d)));
555 aml_append(dev, method);
556 } else if (hotplug_enabled_dev) {
557 /* add _SUN/_EJ0 to make slot hotpluggable */
558 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
559
560 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
561 aml_append(method,
562 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
563 );
564 aml_append(dev, method);
565
566 if (bsel) {
567 build_append_pcihp_notify_entry(notify_method, slot);
568 }
569 } else if (bridge_in_acpi) {
570 /*
571 * device is coldplugged bridge,
572 * add child device descriptions into its scope
573 */
574 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
575
576 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
577 }
578 /* slot descriptor has been composed, add it into parent context */
579 aml_append(parent_scope, dev);
580 }
581
582 if (bsel) {
583 aml_append(parent_scope, notify_method);
584 }
585
586 /* Append PCNT method to notify about events on local and child buses.
587 * Add unconditionally for root since DSDT expects it.
588 */
589 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
590
591 /* If bus supports hotplug select it and notify about local events */
592 if (bsel) {
593 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
594 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
595 aml_append(method,
596 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
597 );
598 aml_append(method,
599 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
600 );
601 }
602
603 /* Notify about child bus events in any case */
604 if (pcihp_bridge_en) {
605 QLIST_FOREACH(sec, &bus->child, sibling) {
606 int32_t devfn = sec->parent_dev->devfn;
607
608 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
609 }
610 }
611 aml_append(parent_scope, method);
612 qobject_decref(bsel);
613 }
614
615 /**
616 * build_prt_entry:
617 * @link_name: link name for PCI route entry
618 *
619 * build AML package containing a PCI route entry for @link_name
620 */
621 static Aml *build_prt_entry(const char *link_name)
622 {
623 Aml *a_zero = aml_int(0);
624 Aml *pkg = aml_package(4);
625 aml_append(pkg, a_zero);
626 aml_append(pkg, a_zero);
627 aml_append(pkg, aml_name("%s", link_name));
628 aml_append(pkg, a_zero);
629 return pkg;
630 }
631
632 /*
633 * initialize_route - Initialize the interrupt routing rule
634 * through a specific LINK:
635 * if (lnk_idx == idx)
636 * route using link 'link_name'
637 */
638 static Aml *initialize_route(Aml *route, const char *link_name,
639 Aml *lnk_idx, int idx)
640 {
641 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
642 Aml *pkg = build_prt_entry(link_name);
643
644 aml_append(if_ctx, aml_store(pkg, route));
645
646 return if_ctx;
647 }
648
649 /*
650 * build_prt - Define interrupt rounting rules
651 *
652 * Returns an array of 128 routes, one for each device,
653 * based on device location.
654 * The main goal is to equaly distribute the interrupts
655 * over the 4 existing ACPI links (works only for i440fx).
656 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
657 *
658 */
659 static Aml *build_prt(bool is_pci0_prt)
660 {
661 Aml *method, *while_ctx, *pin, *res;
662
663 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
664 res = aml_local(0);
665 pin = aml_local(1);
666 aml_append(method, aml_store(aml_package(128), res));
667 aml_append(method, aml_store(aml_int(0), pin));
668
669 /* while (pin < 128) */
670 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
671 {
672 Aml *slot = aml_local(2);
673 Aml *lnk_idx = aml_local(3);
674 Aml *route = aml_local(4);
675
676 /* slot = pin >> 2 */
677 aml_append(while_ctx,
678 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
679 /* lnk_idx = (slot + pin) & 3 */
680 aml_append(while_ctx,
681 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
682 lnk_idx));
683
684 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
685 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
686 if (is_pci0_prt) {
687 Aml *if_device_1, *if_pin_4, *else_pin_4;
688
689 /* device 1 is the power-management device, needs SCI */
690 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
691 {
692 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
693 {
694 aml_append(if_pin_4,
695 aml_store(build_prt_entry("LNKS"), route));
696 }
697 aml_append(if_device_1, if_pin_4);
698 else_pin_4 = aml_else();
699 {
700 aml_append(else_pin_4,
701 aml_store(build_prt_entry("LNKA"), route));
702 }
703 aml_append(if_device_1, else_pin_4);
704 }
705 aml_append(while_ctx, if_device_1);
706 } else {
707 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
708 }
709 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
710 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
711
712 /* route[0] = 0x[slot]FFFF */
713 aml_append(while_ctx,
714 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
715 NULL),
716 aml_index(route, aml_int(0))));
717 /* route[1] = pin & 3 */
718 aml_append(while_ctx,
719 aml_store(aml_and(pin, aml_int(3), NULL),
720 aml_index(route, aml_int(1))));
721 /* res[pin] = route */
722 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
723 /* pin++ */
724 aml_append(while_ctx, aml_increment(pin));
725 }
726 aml_append(method, while_ctx);
727 /* return res*/
728 aml_append(method, aml_return(res));
729
730 return method;
731 }
732
733 typedef struct CrsRangeEntry {
734 uint64_t base;
735 uint64_t limit;
736 } CrsRangeEntry;
737
738 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
739 {
740 CrsRangeEntry *entry;
741
742 entry = g_malloc(sizeof(*entry));
743 entry->base = base;
744 entry->limit = limit;
745
746 g_ptr_array_add(ranges, entry);
747 }
748
749 static void crs_range_free(gpointer data)
750 {
751 CrsRangeEntry *entry = (CrsRangeEntry *)data;
752 g_free(entry);
753 }
754
755 static gint crs_range_compare(gconstpointer a, gconstpointer b)
756 {
757 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
758 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
759
760 return (int64_t)entry_a->base - (int64_t)entry_b->base;
761 }
762
763 /*
764 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
765 * interval, computes the 'free' ranges from the same interval.
766 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
767 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
768 */
769 static void crs_replace_with_free_ranges(GPtrArray *ranges,
770 uint64_t start, uint64_t end)
771 {
772 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
773 uint64_t free_base = start;
774 int i;
775
776 g_ptr_array_sort(ranges, crs_range_compare);
777 for (i = 0; i < ranges->len; i++) {
778 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
779
780 if (free_base < used->base) {
781 crs_range_insert(free_ranges, free_base, used->base - 1);
782 }
783
784 free_base = used->limit + 1;
785 }
786
787 if (free_base < end) {
788 crs_range_insert(free_ranges, free_base, end);
789 }
790
791 g_ptr_array_set_size(ranges, 0);
792 for (i = 0; i < free_ranges->len; i++) {
793 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
794 }
795
796 g_ptr_array_free(free_ranges, false);
797 }
798
799 /*
800 * crs_range_merge - merges adjacent ranges in the given array.
801 * Array elements are deleted and replaced with the merged ranges.
802 */
803 static void crs_range_merge(GPtrArray *range)
804 {
805 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
806 CrsRangeEntry *entry;
807 uint64_t range_base, range_limit;
808 int i;
809
810 if (!range->len) {
811 return;
812 }
813
814 g_ptr_array_sort(range, crs_range_compare);
815
816 entry = g_ptr_array_index(range, 0);
817 range_base = entry->base;
818 range_limit = entry->limit;
819 for (i = 1; i < range->len; i++) {
820 entry = g_ptr_array_index(range, i);
821 if (entry->base - 1 == range_limit) {
822 range_limit = entry->limit;
823 } else {
824 crs_range_insert(tmp, range_base, range_limit);
825 range_base = entry->base;
826 range_limit = entry->limit;
827 }
828 }
829 crs_range_insert(tmp, range_base, range_limit);
830
831 g_ptr_array_set_size(range, 0);
832 for (i = 0; i < tmp->len; i++) {
833 entry = g_ptr_array_index(tmp, i);
834 crs_range_insert(range, entry->base, entry->limit);
835 }
836 g_ptr_array_free(tmp, true);
837 }
838
839 static Aml *build_crs(PCIHostState *host,
840 GPtrArray *io_ranges, GPtrArray *mem_ranges)
841 {
842 Aml *crs = aml_resource_template();
843 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
844 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
845 CrsRangeEntry *entry;
846 uint8_t max_bus = pci_bus_num(host->bus);
847 uint8_t type;
848 int devfn;
849 int i;
850
851 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
852 uint64_t range_base, range_limit;
853 PCIDevice *dev = host->bus->devices[devfn];
854
855 if (!dev) {
856 continue;
857 }
858
859 for (i = 0; i < PCI_NUM_REGIONS; i++) {
860 PCIIORegion *r = &dev->io_regions[i];
861
862 range_base = r->addr;
863 range_limit = r->addr + r->size - 1;
864
865 /*
866 * Work-around for old bioses
867 * that do not support multiple root buses
868 */
869 if (!range_base || range_base > range_limit) {
870 continue;
871 }
872
873 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
874 crs_range_insert(host_io_ranges, range_base, range_limit);
875 } else { /* "memory" */
876 crs_range_insert(host_mem_ranges, range_base, range_limit);
877 }
878 }
879
880 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
881 if (type == PCI_HEADER_TYPE_BRIDGE) {
882 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
883 if (subordinate > max_bus) {
884 max_bus = subordinate;
885 }
886
887 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
888 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
889
890 /*
891 * Work-around for old bioses
892 * that do not support multiple root buses
893 */
894 if (range_base && range_base <= range_limit) {
895 crs_range_insert(host_io_ranges, range_base, range_limit);
896 }
897
898 range_base =
899 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
900 range_limit =
901 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
902
903 /*
904 * Work-around for old bioses
905 * that do not support multiple root buses
906 */
907 if (range_base && range_base <= range_limit) {
908 crs_range_insert(host_mem_ranges, range_base, range_limit);
909 }
910
911 range_base =
912 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
913 range_limit =
914 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
915
916 /*
917 * Work-around for old bioses
918 * that do not support multiple root buses
919 */
920 if (range_base && range_base <= range_limit) {
921 crs_range_insert(host_mem_ranges, range_base, range_limit);
922 }
923 }
924 }
925
926 crs_range_merge(host_io_ranges);
927 for (i = 0; i < host_io_ranges->len; i++) {
928 entry = g_ptr_array_index(host_io_ranges, i);
929 aml_append(crs,
930 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
931 AML_POS_DECODE, AML_ENTIRE_RANGE,
932 0, entry->base, entry->limit, 0,
933 entry->limit - entry->base + 1));
934 crs_range_insert(io_ranges, entry->base, entry->limit);
935 }
936 g_ptr_array_free(host_io_ranges, true);
937
938 crs_range_merge(host_mem_ranges);
939 for (i = 0; i < host_mem_ranges->len; i++) {
940 entry = g_ptr_array_index(host_mem_ranges, i);
941 aml_append(crs,
942 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
943 AML_MAX_FIXED, AML_NON_CACHEABLE,
944 AML_READ_WRITE,
945 0, entry->base, entry->limit, 0,
946 entry->limit - entry->base + 1));
947 crs_range_insert(mem_ranges, entry->base, entry->limit);
948 }
949 g_ptr_array_free(host_mem_ranges, true);
950
951 aml_append(crs,
952 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
953 0,
954 pci_bus_num(host->bus),
955 max_bus,
956 0,
957 max_bus - pci_bus_num(host->bus) + 1));
958
959 return crs;
960 }
961
962 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
963 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
964 {
965 int i;
966 Aml *dev;
967 Aml *crs;
968 Aml *pkg;
969 Aml *field;
970 Aml *ifctx;
971 Aml *method;
972
973 /* The current AML generator can cover the APIC ID range [0..255],
974 * inclusive, for VCPU hotplug. */
975 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
976 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
977
978 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
979 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
980 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
981 aml_append(dev,
982 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
983 );
984 /* device present, functioning, decoding, not shown in UI */
985 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
986 crs = aml_resource_template();
987 aml_append(crs,
988 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
989 pm->cpu_hp_io_len)
990 );
991 aml_append(dev, aml_name_decl("_CRS", crs));
992 aml_append(sb_scope, dev);
993 /* declare CPU hotplug MMIO region and PRS field to access it */
994 aml_append(sb_scope, aml_operation_region(
995 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
996 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
997 aml_append(field, aml_named_field("PRS", 256));
998 aml_append(sb_scope, field);
999
1000 /* build Processor object for each processor */
1001 for (i = 0; i < acpi_cpus; i++) {
1002 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1003
1004 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1005 aml_append(method,
1006 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
1007 aml_append(dev, method);
1008
1009 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1010 aml_append(method,
1011 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
1012 aml_append(dev, method);
1013
1014 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1015 aml_append(method,
1016 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
1017 );
1018 aml_append(dev, method);
1019
1020 aml_append(sb_scope, dev);
1021 }
1022
1023 /* build this code:
1024 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1025 */
1026 /* Arg0 = Processor ID = APIC ID */
1027 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1028 for (i = 0; i < acpi_cpus; i++) {
1029 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1030 aml_append(ifctx,
1031 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1032 );
1033 aml_append(method, ifctx);
1034 }
1035 aml_append(sb_scope, method);
1036
1037 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1038 *
1039 * Note: The ability to create variable-sized packages was first
1040 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1041 * ith up to 255 elements. Windows guests up to win2k8 fail when
1042 * VarPackageOp is used.
1043 */
1044 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1045 aml_varpackage(acpi_cpus);
1046
1047 for (i = 0; i < acpi_cpus; i++) {
1048 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1049 aml_append(pkg, aml_int(b));
1050 }
1051 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1052 }
1053
1054 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1055 uint16_t io_base, uint16_t io_len)
1056 {
1057 int i;
1058 Aml *scope;
1059 Aml *crs;
1060 Aml *field;
1061 Aml *dev;
1062 Aml *method;
1063 Aml *ifctx;
1064
1065 /* build memory devices */
1066 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1067 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1068 aml_append(scope,
1069 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1070 );
1071
1072 crs = aml_resource_template();
1073 aml_append(crs,
1074 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1075 );
1076 aml_append(scope, aml_name_decl("_CRS", crs));
1077
1078 aml_append(scope, aml_operation_region(
1079 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1080 io_base, io_len)
1081 );
1082
1083 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1084 AML_NOLOCK, AML_PRESERVE);
1085 aml_append(field, /* read only */
1086 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1087 aml_append(field, /* read only */
1088 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1089 aml_append(field, /* read only */
1090 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1091 aml_append(field, /* read only */
1092 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1093 aml_append(field, /* read only */
1094 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1095 aml_append(scope, field);
1096
1097 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1098 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1099 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1100 aml_append(field, /* 1 if enabled, read only */
1101 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1102 aml_append(field,
1103 /*(read) 1 if has a insert event. (write) 1 to clear event */
1104 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1105 aml_append(field,
1106 /* (read) 1 if has a remove event. (write) 1 to clear event */
1107 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1108 aml_append(field,
1109 /* initiates device eject, write only */
1110 aml_named_field(MEMORY_SLOT_EJECT, 1));
1111 aml_append(scope, field);
1112
1113 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1114 AML_NOLOCK, AML_PRESERVE);
1115 aml_append(field, /* DIMM selector, write only */
1116 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1117 aml_append(field, /* _OST event code, write only */
1118 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1119 aml_append(field, /* _OST status code, write only */
1120 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1121 aml_append(scope, field);
1122 aml_append(sb_scope, scope);
1123
1124 for (i = 0; i < nr_mem; i++) {
1125 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1126 const char *s;
1127
1128 dev = aml_device("MP%02X", i);
1129 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1130 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1131
1132 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1133 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1134 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1135 aml_append(dev, method);
1136
1137 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1138 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1139 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1140 aml_append(dev, method);
1141
1142 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1143 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1144 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1145 aml_append(dev, method);
1146
1147 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1148 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1149
1150 aml_append(method, aml_return(aml_call4(
1151 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1152 )));
1153 aml_append(dev, method);
1154
1155 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1156 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1157 aml_append(method, aml_return(aml_call2(
1158 s, aml_name("_UID"), aml_arg(0))));
1159 aml_append(dev, method);
1160
1161 aml_append(sb_scope, dev);
1162 }
1163
1164 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1165 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1166 */
1167 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1168 for (i = 0; i < nr_mem; i++) {
1169 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1170 aml_append(ifctx,
1171 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1172 );
1173 aml_append(method, ifctx);
1174 }
1175 aml_append(sb_scope, method);
1176 }
1177
1178 static void build_hpet_aml(Aml *table)
1179 {
1180 Aml *crs;
1181 Aml *field;
1182 Aml *method;
1183 Aml *if_ctx;
1184 Aml *scope = aml_scope("_SB");
1185 Aml *dev = aml_device("HPET");
1186 Aml *zero = aml_int(0);
1187 Aml *id = aml_local(0);
1188 Aml *period = aml_local(1);
1189
1190 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1191 aml_append(dev, aml_name_decl("_UID", zero));
1192
1193 aml_append(dev,
1194 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, HPET_BASE, HPET_LEN));
1195 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1196 aml_append(field, aml_named_field("VEND", 32));
1197 aml_append(field, aml_named_field("PRD", 32));
1198 aml_append(dev, field);
1199
1200 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1201 aml_append(method, aml_store(aml_name("VEND"), id));
1202 aml_append(method, aml_store(aml_name("PRD"), period));
1203 aml_append(method, aml_shiftright(id, aml_int(16), id));
1204 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1205 aml_equal(id, aml_int(0xffff))));
1206 {
1207 aml_append(if_ctx, aml_return(zero));
1208 }
1209 aml_append(method, if_ctx);
1210
1211 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1212 aml_lgreater(period, aml_int(100000000))));
1213 {
1214 aml_append(if_ctx, aml_return(zero));
1215 }
1216 aml_append(method, if_ctx);
1217
1218 aml_append(method, aml_return(aml_int(0x0F)));
1219 aml_append(dev, method);
1220
1221 crs = aml_resource_template();
1222 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1223 aml_append(dev, aml_name_decl("_CRS", crs));
1224
1225 aml_append(scope, dev);
1226 aml_append(table, scope);
1227 }
1228
1229 static Aml *build_fdc_device_aml(void)
1230 {
1231 Aml *dev;
1232 Aml *crs;
1233 Aml *method;
1234 Aml *if_ctx;
1235 Aml *else_ctx;
1236 Aml *zero = aml_int(0);
1237 Aml *is_present = aml_local(0);
1238
1239 dev = aml_device("FDC0");
1240 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1241
1242 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1243 aml_append(method, aml_store(aml_name("FDEN"), is_present));
1244 if_ctx = aml_if(aml_equal(is_present, zero));
1245 {
1246 aml_append(if_ctx, aml_return(aml_int(0x00)));
1247 }
1248 aml_append(method, if_ctx);
1249 else_ctx = aml_else();
1250 {
1251 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1252 }
1253 aml_append(method, else_ctx);
1254 aml_append(dev, method);
1255
1256 crs = aml_resource_template();
1257 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1258 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1259 aml_append(crs, aml_irq_no_flags(6));
1260 aml_append(crs,
1261 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1262 aml_append(dev, aml_name_decl("_CRS", crs));
1263
1264 return dev;
1265 }
1266
1267 static Aml *build_rtc_device_aml(void)
1268 {
1269 Aml *dev;
1270 Aml *crs;
1271
1272 dev = aml_device("RTC");
1273 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1274 crs = aml_resource_template();
1275 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1276 aml_append(crs, aml_irq_no_flags(8));
1277 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1278 aml_append(dev, aml_name_decl("_CRS", crs));
1279
1280 return dev;
1281 }
1282
1283 static Aml *build_kbd_device_aml(void)
1284 {
1285 Aml *dev;
1286 Aml *crs;
1287 Aml *method;
1288
1289 dev = aml_device("KBD");
1290 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1291
1292 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1293 aml_append(method, aml_return(aml_int(0x0f)));
1294 aml_append(dev, method);
1295
1296 crs = aml_resource_template();
1297 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1298 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1299 aml_append(crs, aml_irq_no_flags(1));
1300 aml_append(dev, aml_name_decl("_CRS", crs));
1301
1302 return dev;
1303 }
1304
1305 static Aml *build_mouse_device_aml(void)
1306 {
1307 Aml *dev;
1308 Aml *crs;
1309 Aml *method;
1310
1311 dev = aml_device("MOU");
1312 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1313
1314 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1315 aml_append(method, aml_return(aml_int(0x0f)));
1316 aml_append(dev, method);
1317
1318 crs = aml_resource_template();
1319 aml_append(crs, aml_irq_no_flags(12));
1320 aml_append(dev, aml_name_decl("_CRS", crs));
1321
1322 return dev;
1323 }
1324
1325 static Aml *build_lpt_device_aml(void)
1326 {
1327 Aml *dev;
1328 Aml *crs;
1329 Aml *method;
1330 Aml *if_ctx;
1331 Aml *else_ctx;
1332 Aml *zero = aml_int(0);
1333 Aml *is_present = aml_local(0);
1334
1335 dev = aml_device("LPT");
1336 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1337
1338 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1339 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1340 if_ctx = aml_if(aml_equal(is_present, zero));
1341 {
1342 aml_append(if_ctx, aml_return(aml_int(0x00)));
1343 }
1344 aml_append(method, if_ctx);
1345 else_ctx = aml_else();
1346 {
1347 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1348 }
1349 aml_append(method, else_ctx);
1350 aml_append(dev, method);
1351
1352 crs = aml_resource_template();
1353 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1354 aml_append(crs, aml_irq_no_flags(7));
1355 aml_append(dev, aml_name_decl("_CRS", crs));
1356
1357 return dev;
1358 }
1359
1360 static Aml *build_com_device_aml(uint8_t uid)
1361 {
1362 Aml *dev;
1363 Aml *crs;
1364 Aml *method;
1365 Aml *if_ctx;
1366 Aml *else_ctx;
1367 Aml *zero = aml_int(0);
1368 Aml *is_present = aml_local(0);
1369 const char *enabled_field = "CAEN";
1370 uint8_t irq = 4;
1371 uint16_t io_port = 0x03F8;
1372
1373 assert(uid == 1 || uid == 2);
1374 if (uid == 2) {
1375 enabled_field = "CBEN";
1376 irq = 3;
1377 io_port = 0x02F8;
1378 }
1379
1380 dev = aml_device("COM%d", uid);
1381 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1382 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1383
1384 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1385 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1386 if_ctx = aml_if(aml_equal(is_present, zero));
1387 {
1388 aml_append(if_ctx, aml_return(aml_int(0x00)));
1389 }
1390 aml_append(method, if_ctx);
1391 else_ctx = aml_else();
1392 {
1393 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1394 }
1395 aml_append(method, else_ctx);
1396 aml_append(dev, method);
1397
1398 crs = aml_resource_template();
1399 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1400 aml_append(crs, aml_irq_no_flags(irq));
1401 aml_append(dev, aml_name_decl("_CRS", crs));
1402
1403 return dev;
1404 }
1405
1406 static void build_isa_devices_aml(Aml *table)
1407 {
1408 Aml *scope = aml_scope("_SB.PCI0.ISA");
1409
1410 aml_append(scope, build_rtc_device_aml());
1411 aml_append(scope, build_kbd_device_aml());
1412 aml_append(scope, build_mouse_device_aml());
1413 aml_append(scope, build_fdc_device_aml());
1414 aml_append(scope, build_lpt_device_aml());
1415 aml_append(scope, build_com_device_aml(1));
1416 aml_append(scope, build_com_device_aml(2));
1417
1418 aml_append(table, scope);
1419 }
1420
1421 static void build_dbg_aml(Aml *table)
1422 {
1423 Aml *field;
1424 Aml *method;
1425 Aml *while_ctx;
1426 Aml *scope = aml_scope("\\");
1427 Aml *buf = aml_local(0);
1428 Aml *len = aml_local(1);
1429 Aml *idx = aml_local(2);
1430
1431 aml_append(scope,
1432 aml_operation_region("DBG", AML_SYSTEM_IO, 0x0402, 0x01));
1433 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1434 aml_append(field, aml_named_field("DBGB", 8));
1435 aml_append(scope, field);
1436
1437 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1438
1439 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1440 aml_append(method, aml_to_buffer(buf, buf));
1441 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1442 aml_append(method, aml_store(aml_int(0), idx));
1443
1444 while_ctx = aml_while(aml_lless(idx, len));
1445 aml_append(while_ctx,
1446 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1447 aml_append(while_ctx, aml_increment(idx));
1448 aml_append(method, while_ctx);
1449
1450 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1451 aml_append(scope, method);
1452
1453 aml_append(table, scope);
1454 }
1455
1456 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1457 {
1458 Aml *dev;
1459 Aml *crs;
1460 Aml *method;
1461 uint32_t irqs[] = {5, 10, 11};
1462
1463 dev = aml_device("%s", name);
1464 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1465 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1466
1467 crs = aml_resource_template();
1468 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1469 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1470 aml_append(dev, aml_name_decl("_PRS", crs));
1471
1472 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1473 aml_append(method, aml_return(aml_call1("IQST", reg)));
1474 aml_append(dev, method);
1475
1476 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1477 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1478 aml_append(dev, method);
1479
1480 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1481 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1482 aml_append(dev, method);
1483
1484 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1485 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1486 aml_append(method, aml_store(aml_name("PRRI"), reg));
1487 aml_append(dev, method);
1488
1489 return dev;
1490 }
1491
1492 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1493 {
1494 Aml *dev;
1495 Aml *crs;
1496 Aml *method;
1497 uint32_t irqs;
1498
1499 dev = aml_device("%s", name);
1500 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1501 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1502
1503 crs = aml_resource_template();
1504 irqs = gsi;
1505 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1506 AML_SHARED, &irqs, 1));
1507 aml_append(dev, aml_name_decl("_PRS", crs));
1508
1509 aml_append(dev, aml_name_decl("_CRS", crs));
1510
1511 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1512 aml_append(dev, method);
1513
1514 return dev;
1515 }
1516
1517 /* _CRS method - get current settings */
1518 static Aml *build_iqcr_method(bool is_piix4)
1519 {
1520 Aml *if_ctx;
1521 uint32_t irqs;
1522 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1523 Aml *crs = aml_resource_template();
1524
1525 irqs = 0;
1526 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1527 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1528 aml_append(method, aml_name_decl("PRR0", crs));
1529
1530 aml_append(method,
1531 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1532
1533 if (is_piix4) {
1534 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1535 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1536 aml_append(method, if_ctx);
1537 } else {
1538 aml_append(method,
1539 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1540 aml_name("PRRI")));
1541 }
1542
1543 aml_append(method, aml_return(aml_name("PRR0")));
1544 return method;
1545 }
1546
1547 /* _STA method - get status */
1548 static Aml *build_irq_status_method(void)
1549 {
1550 Aml *if_ctx;
1551 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1552
1553 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1554 aml_append(if_ctx, aml_return(aml_int(0x09)));
1555 aml_append(method, if_ctx);
1556 aml_append(method, aml_return(aml_int(0x0B)));
1557 return method;
1558 }
1559
1560 static void build_piix4_pci0_int(Aml *table)
1561 {
1562 Aml *dev;
1563 Aml *crs;
1564 Aml *field;
1565 Aml *method;
1566 uint32_t irqs;
1567 Aml *sb_scope = aml_scope("_SB");
1568 Aml *pci0_scope = aml_scope("PCI0");
1569
1570 aml_append(pci0_scope, build_prt(true));
1571 aml_append(sb_scope, pci0_scope);
1572
1573 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1574 aml_append(field, aml_named_field("PRQ0", 8));
1575 aml_append(field, aml_named_field("PRQ1", 8));
1576 aml_append(field, aml_named_field("PRQ2", 8));
1577 aml_append(field, aml_named_field("PRQ3", 8));
1578 aml_append(sb_scope, field);
1579
1580 aml_append(sb_scope, build_irq_status_method());
1581 aml_append(sb_scope, build_iqcr_method(true));
1582
1583 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1584 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1585 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1586 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1587
1588 dev = aml_device("LNKS");
1589 {
1590 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1591 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1592
1593 crs = aml_resource_template();
1594 irqs = 9;
1595 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1596 AML_ACTIVE_HIGH, AML_SHARED,
1597 &irqs, 1));
1598 aml_append(dev, aml_name_decl("_PRS", crs));
1599
1600 /* The SCI cannot be disabled and is always attached to GSI 9,
1601 * so these are no-ops. We only need this link to override the
1602 * polarity to active high and match the content of the MADT.
1603 */
1604 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1605 aml_append(method, aml_return(aml_int(0x0b)));
1606 aml_append(dev, method);
1607
1608 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1609 aml_append(dev, method);
1610
1611 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1612 aml_append(method, aml_return(aml_name("_PRS")));
1613 aml_append(dev, method);
1614
1615 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1616 aml_append(dev, method);
1617 }
1618 aml_append(sb_scope, dev);
1619
1620 aml_append(table, sb_scope);
1621 }
1622
1623 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1624 {
1625 int i;
1626 int head;
1627 Aml *pkg;
1628 char base = name[3] < 'E' ? 'A' : 'E';
1629 char *s = g_strdup(name);
1630 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1631
1632 assert(strlen(s) == 4);
1633
1634 head = name[3] - base;
1635 for (i = 0; i < 4; i++) {
1636 if (head + i > 3) {
1637 head = i * -1;
1638 }
1639 s[3] = base + head + i;
1640 pkg = aml_package(4);
1641 aml_append(pkg, a_nr);
1642 aml_append(pkg, aml_int(i));
1643 aml_append(pkg, aml_name("%s", s));
1644 aml_append(pkg, aml_int(0));
1645 aml_append(ctx, pkg);
1646 }
1647 g_free(s);
1648 }
1649
1650 static Aml *build_q35_routing_table(const char *str)
1651 {
1652 int i;
1653 Aml *pkg;
1654 char *name = g_strdup_printf("%s ", str);
1655
1656 pkg = aml_package(128);
1657 for (i = 0; i < 0x18; i++) {
1658 name[3] = 'E' + (i & 0x3);
1659 append_q35_prt_entry(pkg, i, name);
1660 }
1661
1662 name[3] = 'E';
1663 append_q35_prt_entry(pkg, 0x18, name);
1664
1665 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1666 for (i = 0x0019; i < 0x1e; i++) {
1667 name[3] = 'A';
1668 append_q35_prt_entry(pkg, i, name);
1669 }
1670
1671 /* PCIe->PCI bridge. use PIRQ[E-H] */
1672 name[3] = 'E';
1673 append_q35_prt_entry(pkg, 0x1e, name);
1674 name[3] = 'A';
1675 append_q35_prt_entry(pkg, 0x1f, name);
1676
1677 g_free(name);
1678 return pkg;
1679 }
1680
1681 static void build_q35_pci0_int(Aml *table)
1682 {
1683 Aml *field;
1684 Aml *method;
1685 Aml *sb_scope = aml_scope("_SB");
1686 Aml *pci0_scope = aml_scope("PCI0");
1687
1688 /* Zero => PIC mode, One => APIC Mode */
1689 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1690 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1691 {
1692 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1693 }
1694 aml_append(table, method);
1695
1696 aml_append(pci0_scope,
1697 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1698 aml_append(pci0_scope,
1699 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1700
1701 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1702 {
1703 Aml *if_ctx;
1704 Aml *else_ctx;
1705
1706 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1707 section 6.2.8.1 */
1708 /* Note: we provide the same info as the PCI routing
1709 table of the Bochs BIOS */
1710 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1711 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1712 aml_append(method, if_ctx);
1713 else_ctx = aml_else();
1714 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1715 aml_append(method, else_ctx);
1716 }
1717 aml_append(pci0_scope, method);
1718 aml_append(sb_scope, pci0_scope);
1719
1720 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1721 aml_append(field, aml_named_field("PRQA", 8));
1722 aml_append(field, aml_named_field("PRQB", 8));
1723 aml_append(field, aml_named_field("PRQC", 8));
1724 aml_append(field, aml_named_field("PRQD", 8));
1725 aml_append(field, aml_reserved_field(0x20));
1726 aml_append(field, aml_named_field("PRQE", 8));
1727 aml_append(field, aml_named_field("PRQF", 8));
1728 aml_append(field, aml_named_field("PRQG", 8));
1729 aml_append(field, aml_named_field("PRQH", 8));
1730 aml_append(sb_scope, field);
1731
1732 aml_append(sb_scope, build_irq_status_method());
1733 aml_append(sb_scope, build_iqcr_method(false));
1734
1735 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1736 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1737 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1738 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1739 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1740 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1741 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1742 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1743
1744 /*
1745 * TODO: UID probably shouldn't be the same for GSIx devices
1746 * but that's how it was in original ASL so keep it for now
1747 */
1748 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
1749 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
1750 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
1751 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
1752 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
1753 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
1754 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
1755 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
1756
1757 aml_append(table, sb_scope);
1758 }
1759
1760 static void build_q35_isa_bridge(Aml *table)
1761 {
1762 Aml *dev;
1763 Aml *scope;
1764 Aml *field;
1765
1766 scope = aml_scope("_SB.PCI0");
1767 dev = aml_device("ISA");
1768 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1769
1770 /* ICH9 PCI to ISA irq remapping */
1771 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1772 0x60, 0x0C));
1773
1774 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1775 0x80, 0x02));
1776 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1777 aml_append(field, aml_named_field("COMA", 3));
1778 aml_append(field, aml_reserved_field(1));
1779 aml_append(field, aml_named_field("COMB", 3));
1780 aml_append(field, aml_reserved_field(1));
1781 aml_append(field, aml_named_field("LPTD", 2));
1782 aml_append(field, aml_reserved_field(2));
1783 aml_append(field, aml_named_field("FDCD", 2));
1784 aml_append(dev, field);
1785
1786 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1787 0x82, 0x02));
1788 /* enable bits */
1789 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1790 aml_append(field, aml_named_field("CAEN", 1));
1791 aml_append(field, aml_named_field("CBEN", 1));
1792 aml_append(field, aml_named_field("LPEN", 1));
1793 aml_append(field, aml_named_field("FDEN", 1));
1794 aml_append(dev, field);
1795
1796 aml_append(scope, dev);
1797 aml_append(table, scope);
1798 }
1799
1800 static void build_piix4_pm(Aml *table)
1801 {
1802 Aml *dev;
1803 Aml *scope;
1804
1805 scope = aml_scope("_SB.PCI0");
1806 dev = aml_device("PX13");
1807 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1808
1809 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1810 0x00, 0xff));
1811 aml_append(scope, dev);
1812 aml_append(table, scope);
1813 }
1814
1815 static void build_piix4_isa_bridge(Aml *table)
1816 {
1817 Aml *dev;
1818 Aml *scope;
1819 Aml *field;
1820
1821 scope = aml_scope("_SB.PCI0");
1822 dev = aml_device("ISA");
1823 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1824
1825 /* PIIX PCI to ISA irq remapping */
1826 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1827 0x60, 0x04));
1828 /* enable bits */
1829 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1830 /* Offset(0x5f),, 7, */
1831 aml_append(field, aml_reserved_field(0x2f8));
1832 aml_append(field, aml_reserved_field(7));
1833 aml_append(field, aml_named_field("LPEN", 1));
1834 /* Offset(0x67),, 3, */
1835 aml_append(field, aml_reserved_field(0x38));
1836 aml_append(field, aml_reserved_field(3));
1837 aml_append(field, aml_named_field("CAEN", 1));
1838 aml_append(field, aml_reserved_field(3));
1839 aml_append(field, aml_named_field("CBEN", 1));
1840 aml_append(dev, field);
1841 aml_append(dev, aml_name_decl("FDEN", aml_int(1)));
1842
1843 aml_append(scope, dev);
1844 aml_append(table, scope);
1845 }
1846
1847 static void build_piix4_pci_hotplug(Aml *table)
1848 {
1849 Aml *scope;
1850 Aml *field;
1851 Aml *method;
1852
1853 scope = aml_scope("_SB.PCI0");
1854
1855 aml_append(scope,
1856 aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x08));
1857 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1858 aml_append(field, aml_named_field("PCIU", 32));
1859 aml_append(field, aml_named_field("PCID", 32));
1860 aml_append(scope, field);
1861
1862 aml_append(scope,
1863 aml_operation_region("SEJ", AML_SYSTEM_IO, 0xae08, 0x04));
1864 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1865 aml_append(field, aml_named_field("B0EJ", 32));
1866 aml_append(scope, field);
1867
1868 aml_append(scope,
1869 aml_operation_region("BNMR", AML_SYSTEM_IO, 0xae10, 0x04));
1870 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1871 aml_append(field, aml_named_field("BNUM", 32));
1872 aml_append(scope, field);
1873
1874 aml_append(scope, aml_mutex("BLCK", 0));
1875
1876 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1877 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1878 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1879 aml_append(method,
1880 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1881 aml_append(method, aml_release(aml_name("BLCK")));
1882 aml_append(method, aml_return(aml_int(0)));
1883 aml_append(scope, method);
1884
1885 aml_append(table, scope);
1886 }
1887
1888 static Aml *build_q35_osc_method(void)
1889 {
1890 Aml *if_ctx;
1891 Aml *if_ctx2;
1892 Aml *else_ctx;
1893 Aml *method;
1894 Aml *a_cwd1 = aml_name("CDW1");
1895 Aml *a_ctrl = aml_name("CTRL");
1896
1897 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1898 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1899
1900 if_ctx = aml_if(aml_equal(
1901 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1902 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1903 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1904
1905 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1906 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1907
1908 /*
1909 * Always allow native PME, AER (no dependencies)
1910 * Never allow SHPC (no SHPC controller in this system)
1911 */
1912 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1913
1914 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1915 /* Unknown revision */
1916 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1917 aml_append(if_ctx, if_ctx2);
1918
1919 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1920 /* Capabilities bits were masked */
1921 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1922 aml_append(if_ctx, if_ctx2);
1923
1924 /* Update DWORD3 in the buffer */
1925 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1926 aml_append(method, if_ctx);
1927
1928 else_ctx = aml_else();
1929 /* Unrecognized UUID */
1930 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1931 aml_append(method, else_ctx);
1932
1933 aml_append(method, aml_return(aml_arg(3)));
1934 return method;
1935 }
1936
1937 static void
1938 build_dsdt(GArray *table_data, GArray *linker,
1939 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
1940 PcPciInfo *pci)
1941 {
1942 CrsRangeEntry *entry;
1943 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1944 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1945 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1946 MachineState *machine = MACHINE(qdev_get_machine());
1947 PCMachineState *pcms = PC_MACHINE(machine);
1948 uint32_t nr_mem = machine->ram_slots;
1949 int root_bus_limit = 0xFF;
1950 PCIBus *bus = NULL;
1951 int i;
1952
1953 dsdt = init_aml_allocator();
1954
1955 /* Reserve space for header */
1956 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1957
1958 build_dbg_aml(dsdt);
1959 if (misc->is_piix4) {
1960 sb_scope = aml_scope("_SB");
1961 dev = aml_device("PCI0");
1962 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1963 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1964 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1965 aml_append(sb_scope, dev);
1966 aml_append(dsdt, sb_scope);
1967
1968 build_hpet_aml(dsdt);
1969 build_piix4_pm(dsdt);
1970 build_piix4_isa_bridge(dsdt);
1971 build_isa_devices_aml(dsdt);
1972 build_piix4_pci_hotplug(dsdt);
1973 build_piix4_pci0_int(dsdt);
1974 } else {
1975 sb_scope = aml_scope("_SB");
1976 aml_append(sb_scope,
1977 aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x0c));
1978 aml_append(sb_scope,
1979 aml_operation_region("PCSB", AML_SYSTEM_IO, 0xae0c, 0x01));
1980 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1981 aml_append(field, aml_named_field("PCIB", 8));
1982 aml_append(sb_scope, field);
1983 aml_append(dsdt, sb_scope);
1984
1985 sb_scope = aml_scope("_SB");
1986 dev = aml_device("PCI0");
1987 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1988 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1989 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1990 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1991 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1992 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1993 aml_append(dev, build_q35_osc_method());
1994 aml_append(sb_scope, dev);
1995 aml_append(dsdt, sb_scope);
1996
1997 build_hpet_aml(dsdt);
1998 build_q35_isa_bridge(dsdt);
1999 build_isa_devices_aml(dsdt);
2000 build_q35_pci0_int(dsdt);
2001 }
2002
2003 build_cpu_hotplug_aml(dsdt);
2004 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2005 pm->mem_hp_io_len);
2006
2007 scope = aml_scope("_GPE");
2008 {
2009 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2010
2011 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
2012
2013 if (misc->is_piix4) {
2014 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2015 aml_append(method,
2016 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2017 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2018 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2019 aml_append(scope, method);
2020 } else {
2021 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
2022 }
2023
2024 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
2025 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
2026 aml_append(scope, method);
2027
2028 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2029 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2030 aml_append(scope, method);
2031
2032 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
2033 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
2034 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
2035 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
2036 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
2037 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
2038 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
2039 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
2040 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
2041 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
2042 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
2043 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
2044 }
2045 aml_append(dsdt, scope);
2046
2047 bus = PC_MACHINE(machine)->bus;
2048 if (bus) {
2049 QLIST_FOREACH(bus, &bus->child, sibling) {
2050 uint8_t bus_num = pci_bus_num(bus);
2051 uint8_t numa_node = pci_bus_numa_node(bus);
2052
2053 /* look only for expander root buses */
2054 if (!pci_bus_is_root(bus)) {
2055 continue;
2056 }
2057
2058 if (bus_num < root_bus_limit) {
2059 root_bus_limit = bus_num - 1;
2060 }
2061
2062 scope = aml_scope("\\_SB");
2063 dev = aml_device("PC%.02X", bus_num);
2064 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2065 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2066 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2067
2068 if (numa_node != NUMA_NODE_UNASSIGNED) {
2069 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2070 }
2071
2072 aml_append(dev, build_prt(false));
2073 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2074 io_ranges, mem_ranges);
2075 aml_append(dev, aml_name_decl("_CRS", crs));
2076 aml_append(scope, dev);
2077 aml_append(dsdt, scope);
2078 }
2079 }
2080
2081 scope = aml_scope("\\_SB.PCI0");
2082 /* build PCI0._CRS */
2083 crs = aml_resource_template();
2084 aml_append(crs,
2085 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2086 0x0000, 0x0, root_bus_limit,
2087 0x0000, root_bus_limit + 1));
2088 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2089
2090 aml_append(crs,
2091 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2092 AML_POS_DECODE, AML_ENTIRE_RANGE,
2093 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2094
2095 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2096 for (i = 0; i < io_ranges->len; i++) {
2097 entry = g_ptr_array_index(io_ranges, i);
2098 aml_append(crs,
2099 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2100 AML_POS_DECODE, AML_ENTIRE_RANGE,
2101 0x0000, entry->base, entry->limit,
2102 0x0000, entry->limit - entry->base + 1));
2103 }
2104
2105 aml_append(crs,
2106 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2107 AML_CACHEABLE, AML_READ_WRITE,
2108 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2109
2110 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2111 for (i = 0; i < mem_ranges->len; i++) {
2112 entry = g_ptr_array_index(mem_ranges, i);
2113 aml_append(crs,
2114 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2115 AML_NON_CACHEABLE, AML_READ_WRITE,
2116 0, entry->base, entry->limit,
2117 0, entry->limit - entry->base + 1));
2118 }
2119
2120 if (pci->w64.begin) {
2121 aml_append(crs,
2122 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2123 AML_CACHEABLE, AML_READ_WRITE,
2124 0, pci->w64.begin, pci->w64.end - 1, 0,
2125 pci->w64.end - pci->w64.begin));
2126 }
2127 aml_append(scope, aml_name_decl("_CRS", crs));
2128
2129 /* reserve GPE0 block resources */
2130 dev = aml_device("GPE0");
2131 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2132 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2133 /* device present, functioning, decoding, not shown in UI */
2134 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2135 crs = aml_resource_template();
2136 aml_append(crs,
2137 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2138 );
2139 aml_append(dev, aml_name_decl("_CRS", crs));
2140 aml_append(scope, dev);
2141
2142 g_ptr_array_free(io_ranges, true);
2143 g_ptr_array_free(mem_ranges, true);
2144
2145 /* reserve PCIHP resources */
2146 if (pm->pcihp_io_len) {
2147 dev = aml_device("PHPR");
2148 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2149 aml_append(dev,
2150 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2151 /* device present, functioning, decoding, not shown in UI */
2152 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2153 crs = aml_resource_template();
2154 aml_append(crs,
2155 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2156 pm->pcihp_io_len)
2157 );
2158 aml_append(dev, aml_name_decl("_CRS", crs));
2159 aml_append(scope, dev);
2160 }
2161 aml_append(dsdt, scope);
2162
2163 /* create S3_ / S4_ / S5_ packages if necessary */
2164 scope = aml_scope("\\");
2165 if (!pm->s3_disabled) {
2166 pkg = aml_package(4);
2167 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2168 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2169 aml_append(pkg, aml_int(0)); /* reserved */
2170 aml_append(pkg, aml_int(0)); /* reserved */
2171 aml_append(scope, aml_name_decl("_S3", pkg));
2172 }
2173
2174 if (!pm->s4_disabled) {
2175 pkg = aml_package(4);
2176 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2177 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2178 aml_append(pkg, aml_int(pm->s4_val));
2179 aml_append(pkg, aml_int(0)); /* reserved */
2180 aml_append(pkg, aml_int(0)); /* reserved */
2181 aml_append(scope, aml_name_decl("_S4", pkg));
2182 }
2183
2184 pkg = aml_package(4);
2185 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2186 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2187 aml_append(pkg, aml_int(0)); /* reserved */
2188 aml_append(pkg, aml_int(0)); /* reserved */
2189 aml_append(scope, aml_name_decl("_S5", pkg));
2190 aml_append(dsdt, scope);
2191
2192 if (misc->applesmc_io_base) {
2193 scope = aml_scope("\\_SB.PCI0.ISA");
2194 dev = aml_device("SMC");
2195
2196 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2197 /* device present, functioning, decoding, not shown in UI */
2198 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2199
2200 crs = aml_resource_template();
2201 aml_append(crs,
2202 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2203 0x01, APPLESMC_MAX_DATA_LENGTH)
2204 );
2205 aml_append(crs, aml_irq_no_flags(6));
2206 aml_append(dev, aml_name_decl("_CRS", crs));
2207
2208 aml_append(scope, dev);
2209 aml_append(dsdt, scope);
2210 }
2211
2212 if (misc->pvpanic_port) {
2213 scope = aml_scope("\\_SB.PCI0.ISA");
2214
2215 dev = aml_device("PEVT");
2216 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2217
2218 crs = aml_resource_template();
2219 aml_append(crs,
2220 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2221 );
2222 aml_append(dev, aml_name_decl("_CRS", crs));
2223
2224 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2225 misc->pvpanic_port, 1));
2226 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2227 aml_append(field, aml_named_field("PEPT", 8));
2228 aml_append(dev, field);
2229
2230 /* device present, functioning, decoding, shown in UI */
2231 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2232
2233 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2234 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2235 aml_append(method, aml_return(aml_local(0)));
2236 aml_append(dev, method);
2237
2238 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2239 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2240 aml_append(dev, method);
2241
2242 aml_append(scope, dev);
2243 aml_append(dsdt, scope);
2244 }
2245
2246 sb_scope = aml_scope("\\_SB");
2247 {
2248 build_processor_devices(sb_scope, pcms->apic_id_limit, cpu, pm);
2249
2250 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2251 pm->mem_hp_io_len);
2252
2253 {
2254 Object *pci_host;
2255 PCIBus *bus = NULL;
2256
2257 pci_host = acpi_get_i386_pci_host();
2258 if (pci_host) {
2259 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2260 }
2261
2262 if (bus) {
2263 Aml *scope = aml_scope("PCI0");
2264 /* Scan all PCI buses. Generate tables to support hotplug. */
2265 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2266
2267 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2268 dev = aml_device("ISA.TPM");
2269 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2270 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2271 crs = aml_resource_template();
2272 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2273 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2274 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
2275 aml_append(dev, aml_name_decl("_CRS", crs));
2276 aml_append(scope, dev);
2277 }
2278
2279 aml_append(sb_scope, scope);
2280 }
2281 }
2282 aml_append(dsdt, sb_scope);
2283 }
2284
2285 /* copy AML table into ACPI tables blob and patch header there */
2286 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2287 build_header(linker, table_data,
2288 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2289 "DSDT", dsdt->buf->len, 1, NULL);
2290 free_aml_allocator();
2291 }
2292
2293 static void
2294 build_hpet(GArray *table_data, GArray *linker)
2295 {
2296 Acpi20Hpet *hpet;
2297
2298 hpet = acpi_data_push(table_data, sizeof(*hpet));
2299 /* Note timer_block_id value must be kept in sync with value advertised by
2300 * emulated hpet
2301 */
2302 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2303 hpet->addr.address = cpu_to_le64(HPET_BASE);
2304 build_header(linker, table_data,
2305 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL);
2306 }
2307
2308 static void
2309 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
2310 {
2311 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2312 uint64_t log_area_start_address = acpi_data_len(tcpalog);
2313
2314 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2315 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2316 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
2317
2318 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
2319 false /* high memory */);
2320
2321 /* log area start address to be filled by Guest linker */
2322 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2323 ACPI_BUILD_TPMLOG_FILE,
2324 table_data, &tcpa->log_area_start_address,
2325 sizeof(tcpa->log_area_start_address));
2326
2327 build_header(linker, table_data,
2328 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL);
2329
2330 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
2331 }
2332
2333 static void
2334 build_tpm2(GArray *table_data, GArray *linker)
2335 {
2336 Acpi20TPM2 *tpm2_ptr;
2337
2338 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2339
2340 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2341 tpm2_ptr->control_area_address = cpu_to_le64(0);
2342 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2343
2344 build_header(linker, table_data,
2345 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL);
2346 }
2347
2348 typedef enum {
2349 MEM_AFFINITY_NOFLAGS = 0,
2350 MEM_AFFINITY_ENABLED = (1 << 0),
2351 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
2352 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
2353 } MemoryAffinityFlags;
2354
2355 static void
2356 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
2357 uint64_t len, int node, MemoryAffinityFlags flags)
2358 {
2359 numamem->type = ACPI_SRAT_MEMORY;
2360 numamem->length = sizeof(*numamem);
2361 memset(numamem->proximity, 0, 4);
2362 numamem->proximity[0] = node;
2363 numamem->flags = cpu_to_le32(flags);
2364 numamem->base_addr = cpu_to_le64(base);
2365 numamem->range_length = cpu_to_le64(len);
2366 }
2367
2368 static void
2369 build_srat(GArray *table_data, GArray *linker)
2370 {
2371 AcpiSystemResourceAffinityTable *srat;
2372 AcpiSratProcessorAffinity *core;
2373 AcpiSratMemoryAffinity *numamem;
2374
2375 int i;
2376 uint64_t curnode;
2377 int srat_start, numa_start, slots;
2378 uint64_t mem_len, mem_base, next_base;
2379 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2380 ram_addr_t hotplugabble_address_space_size =
2381 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2382 NULL);
2383
2384 srat_start = table_data->len;
2385
2386 srat = acpi_data_push(table_data, sizeof *srat);
2387 srat->reserved1 = cpu_to_le32(1);
2388 core = (void *)(srat + 1);
2389
2390 for (i = 0; i < pcms->apic_id_limit; ++i) {
2391 core = acpi_data_push(table_data, sizeof *core);
2392 core->type = ACPI_SRAT_PROCESSOR;
2393 core->length = sizeof(*core);
2394 core->local_apic_id = i;
2395 curnode = pcms->node_cpu[i];
2396 core->proximity_lo = curnode;
2397 memset(core->proximity_hi, 0, 3);
2398 core->local_sapic_eid = 0;
2399 core->flags = cpu_to_le32(1);
2400 }
2401
2402
2403 /* the memory map is a bit tricky, it contains at least one hole
2404 * from 640k-1M and possibly another one from 3.5G-4G.
2405 */
2406 next_base = 0;
2407 numa_start = table_data->len;
2408
2409 numamem = acpi_data_push(table_data, sizeof *numamem);
2410 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
2411 next_base = 1024 * 1024;
2412 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2413 mem_base = next_base;
2414 mem_len = pcms->node_mem[i - 1];
2415 if (i == 1) {
2416 mem_len -= 1024 * 1024;
2417 }
2418 next_base = mem_base + mem_len;
2419
2420 /* Cut out the ACPI_PCI hole */
2421 if (mem_base <= pcms->below_4g_mem_size &&
2422 next_base > pcms->below_4g_mem_size) {
2423 mem_len -= next_base - pcms->below_4g_mem_size;
2424 if (mem_len > 0) {
2425 numamem = acpi_data_push(table_data, sizeof *numamem);
2426 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2427 MEM_AFFINITY_ENABLED);
2428 }
2429 mem_base = 1ULL << 32;
2430 mem_len = next_base - pcms->below_4g_mem_size;
2431 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2432 }
2433 numamem = acpi_data_push(table_data, sizeof *numamem);
2434 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2435 MEM_AFFINITY_ENABLED);
2436 }
2437 slots = (table_data->len - numa_start) / sizeof *numamem;
2438 for (; slots < pcms->numa_nodes + 2; slots++) {
2439 numamem = acpi_data_push(table_data, sizeof *numamem);
2440 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2441 }
2442
2443 /*
2444 * Entry is required for Windows to enable memory hotplug in OS.
2445 * Memory devices may override proximity set by this entry,
2446 * providing _PXM method if necessary.
2447 */
2448 if (hotplugabble_address_space_size) {
2449 numamem = acpi_data_push(table_data, sizeof *numamem);
2450 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
2451 hotplugabble_address_space_size, 0,
2452 MEM_AFFINITY_HOTPLUGGABLE |
2453 MEM_AFFINITY_ENABLED);
2454 }
2455
2456 build_header(linker, table_data,
2457 (void *)(table_data->data + srat_start),
2458 "SRAT",
2459 table_data->len - srat_start, 1, NULL);
2460 }
2461
2462 static void
2463 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2464 {
2465 AcpiTableMcfg *mcfg;
2466 const char *sig;
2467 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2468
2469 mcfg = acpi_data_push(table_data, len);
2470 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2471 /* Only a single allocation so no need to play with segments */
2472 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2473 mcfg->allocation[0].start_bus_number = 0;
2474 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2475
2476 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2477 * To avoid table size changes (which create migration issues),
2478 * always create the table even if there are no allocations,
2479 * but set the signature to a reserved value in this case.
2480 * ACPI spec requires OSPMs to ignore such tables.
2481 */
2482 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2483 /* Reserved signature: ignored by OSPM */
2484 sig = "QEMU";
2485 } else {
2486 sig = "MCFG";
2487 }
2488 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL);
2489 }
2490
2491 static void
2492 build_dmar_q35(GArray *table_data, GArray *linker)
2493 {
2494 int dmar_start = table_data->len;
2495
2496 AcpiTableDmar *dmar;
2497 AcpiDmarHardwareUnit *drhd;
2498
2499 dmar = acpi_data_push(table_data, sizeof(*dmar));
2500 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2501 dmar->flags = 0; /* No intr_remap for now */
2502
2503 /* DMAR Remapping Hardware Unit Definition structure */
2504 drhd = acpi_data_push(table_data, sizeof(*drhd));
2505 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2506 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2507 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2508 drhd->pci_segment = cpu_to_le16(0);
2509 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2510
2511 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2512 "DMAR", table_data->len - dmar_start, 1, NULL);
2513 }
2514
2515 static GArray *
2516 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2517 {
2518 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2519
2520 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
2521 true /* fseg memory */);
2522
2523 memcpy(&rsdp->signature, "RSD PTR ", 8);
2524 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2525 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2526 /* Address to be filled by Guest linker */
2527 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2528 ACPI_BUILD_TABLE_FILE,
2529 rsdp_table, &rsdp->rsdt_physical_address,
2530 sizeof rsdp->rsdt_physical_address);
2531 rsdp->checksum = 0;
2532 /* Checksum to be filled by Guest linker */
2533 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2534 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
2535
2536 return rsdp_table;
2537 }
2538
2539 typedef
2540 struct AcpiBuildState {
2541 /* Copy of table in RAM (for patching). */
2542 MemoryRegion *table_mr;
2543 /* Is table patched? */
2544 uint8_t patched;
2545 void *rsdp;
2546 MemoryRegion *rsdp_mr;
2547 MemoryRegion *linker_mr;
2548 } AcpiBuildState;
2549
2550 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2551 {
2552 Object *pci_host;
2553 QObject *o;
2554
2555 pci_host = acpi_get_i386_pci_host();
2556 g_assert(pci_host);
2557
2558 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2559 if (!o) {
2560 return false;
2561 }
2562 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2563 qobject_decref(o);
2564
2565 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2566 assert(o);
2567 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2568 qobject_decref(o);
2569 return true;
2570 }
2571
2572 static bool acpi_has_iommu(void)
2573 {
2574 bool ambiguous;
2575 Object *intel_iommu;
2576
2577 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2578 &ambiguous);
2579 return intel_iommu && !ambiguous;
2580 }
2581
2582 static bool acpi_has_nvdimm(void)
2583 {
2584 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2585
2586 return pcms->nvdimm;
2587 }
2588
2589 static
2590 void acpi_build(AcpiBuildTables *tables)
2591 {
2592 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2593 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2594 GArray *table_offsets;
2595 unsigned facs, dsdt, rsdt, fadt;
2596 AcpiCpuInfo cpu;
2597 AcpiPmInfo pm;
2598 AcpiMiscInfo misc;
2599 AcpiMcfgInfo mcfg;
2600 PcPciInfo pci;
2601 uint8_t *u;
2602 size_t aml_len = 0;
2603 GArray *tables_blob = tables->table_data;
2604
2605 acpi_get_cpu_info(&cpu);
2606 acpi_get_pm_info(&pm);
2607 acpi_get_misc_info(&misc);
2608 acpi_get_pci_info(&pci);
2609
2610 table_offsets = g_array_new(false, true /* clear */,
2611 sizeof(uint32_t));
2612 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2613
2614 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2615 64 /* Ensure FACS is aligned */,
2616 false /* high memory */);
2617
2618 /*
2619 * FACS is pointed to by FADT.
2620 * We place it first since it's the only table that has alignment
2621 * requirements.
2622 */
2623 facs = tables_blob->len;
2624 build_facs(tables_blob, tables->linker);
2625
2626 /* DSDT is pointed to by FADT */
2627 dsdt = tables_blob->len;
2628 build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci);
2629
2630 /* Count the size of the DSDT and SSDT, we will need it for legacy
2631 * sizing of ACPI tables.
2632 */
2633 aml_len += tables_blob->len - dsdt;
2634
2635 /* ACPI tables pointed to by RSDT */
2636 fadt = tables_blob->len;
2637 acpi_add_table(table_offsets, tables_blob);
2638 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
2639 aml_len += tables_blob->len - fadt;
2640
2641 acpi_add_table(table_offsets, tables_blob);
2642 build_madt(tables_blob, tables->linker, &cpu);
2643
2644 if (misc.has_hpet) {
2645 acpi_add_table(table_offsets, tables_blob);
2646 build_hpet(tables_blob, tables->linker);
2647 }
2648 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2649 acpi_add_table(table_offsets, tables_blob);
2650 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2651
2652 if (misc.tpm_version == TPM_VERSION_2_0) {
2653 acpi_add_table(table_offsets, tables_blob);
2654 build_tpm2(tables_blob, tables->linker);
2655 }
2656 }
2657 if (pcms->numa_nodes) {
2658 acpi_add_table(table_offsets, tables_blob);
2659 build_srat(tables_blob, tables->linker);
2660 }
2661 if (acpi_get_mcfg(&mcfg)) {
2662 acpi_add_table(table_offsets, tables_blob);
2663 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2664 }
2665 if (acpi_has_iommu()) {
2666 acpi_add_table(table_offsets, tables_blob);
2667 build_dmar_q35(tables_blob, tables->linker);
2668 }
2669
2670 if (acpi_has_nvdimm()) {
2671 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2672 }
2673
2674 /* Add tables supplied by user (if any) */
2675 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2676 unsigned len = acpi_table_len(u);
2677
2678 acpi_add_table(table_offsets, tables_blob);
2679 g_array_append_vals(tables_blob, u, len);
2680 }
2681
2682 /* RSDT is pointed to by RSDP */
2683 rsdt = tables_blob->len;
2684 build_rsdt(tables_blob, tables->linker, table_offsets);
2685
2686 /* RSDP is in FSEG memory, so allocate it separately */
2687 build_rsdp(tables->rsdp, tables->linker, rsdt);
2688
2689 /* We'll expose it all to Guest so we want to reduce
2690 * chance of size changes.
2691 *
2692 * We used to align the tables to 4k, but of course this would
2693 * too simple to be enough. 4k turned out to be too small an
2694 * alignment very soon, and in fact it is almost impossible to
2695 * keep the table size stable for all (max_cpus, max_memory_slots)
2696 * combinations. So the table size is always 64k for pc-i440fx-2.1
2697 * and we give an error if the table grows beyond that limit.
2698 *
2699 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2700 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2701 * than 2.0 and we can always pad the smaller tables with zeros. We can
2702 * then use the exact size of the 2.0 tables.
2703 *
2704 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2705 */
2706 if (pcmc->legacy_acpi_table_size) {
2707 /* Subtracting aml_len gives the size of fixed tables. Then add the
2708 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2709 */
2710 int legacy_aml_len =
2711 pcmc->legacy_acpi_table_size +
2712 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2713 int legacy_table_size =
2714 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2715 ACPI_BUILD_ALIGN_SIZE);
2716 if (tables_blob->len > legacy_table_size) {
2717 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2718 error_report("Warning: migration may not work.");
2719 }
2720 g_array_set_size(tables_blob, legacy_table_size);
2721 } else {
2722 /* Make sure we have a buffer in case we need to resize the tables. */
2723 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2724 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2725 error_report("Warning: ACPI tables are larger than 64k.");
2726 error_report("Warning: migration may not work.");
2727 error_report("Warning: please remove CPUs, NUMA nodes, "
2728 "memory slots or PCI bridges.");
2729 }
2730 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2731 }
2732
2733 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
2734
2735 /* Cleanup memory that's no longer used. */
2736 g_array_free(table_offsets, true);
2737 }
2738
2739 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2740 {
2741 uint32_t size = acpi_data_len(data);
2742
2743 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2744 memory_region_ram_resize(mr, size, &error_abort);
2745
2746 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2747 memory_region_set_dirty(mr, 0, size);
2748 }
2749
2750 static void acpi_build_update(void *build_opaque)
2751 {
2752 AcpiBuildState *build_state = build_opaque;
2753 AcpiBuildTables tables;
2754
2755 /* No state to update or already patched? Nothing to do. */
2756 if (!build_state || build_state->patched) {
2757 return;
2758 }
2759 build_state->patched = 1;
2760
2761 acpi_build_tables_init(&tables);
2762
2763 acpi_build(&tables);
2764
2765 acpi_ram_update(build_state->table_mr, tables.table_data);
2766
2767 if (build_state->rsdp) {
2768 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2769 } else {
2770 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2771 }
2772
2773 acpi_ram_update(build_state->linker_mr, tables.linker);
2774 acpi_build_tables_cleanup(&tables, true);
2775 }
2776
2777 static void acpi_build_reset(void *build_opaque)
2778 {
2779 AcpiBuildState *build_state = build_opaque;
2780 build_state->patched = 0;
2781 }
2782
2783 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2784 GArray *blob, const char *name,
2785 uint64_t max_size)
2786 {
2787 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2788 name, acpi_build_update, build_state);
2789 }
2790
2791 static const VMStateDescription vmstate_acpi_build = {
2792 .name = "acpi_build",
2793 .version_id = 1,
2794 .minimum_version_id = 1,
2795 .fields = (VMStateField[]) {
2796 VMSTATE_UINT8(patched, AcpiBuildState),
2797 VMSTATE_END_OF_LIST()
2798 },
2799 };
2800
2801 void acpi_setup(void)
2802 {
2803 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2804 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2805 AcpiBuildTables tables;
2806 AcpiBuildState *build_state;
2807
2808 if (!pcms->fw_cfg) {
2809 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2810 return;
2811 }
2812
2813 if (!pcmc->has_acpi_build) {
2814 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2815 return;
2816 }
2817
2818 if (!acpi_enabled) {
2819 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2820 return;
2821 }
2822
2823 build_state = g_malloc0(sizeof *build_state);
2824
2825 acpi_set_pci_info();
2826
2827 acpi_build_tables_init(&tables);
2828 acpi_build(&tables);
2829
2830 /* Now expose it all to Guest */
2831 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2832 ACPI_BUILD_TABLE_FILE,
2833 ACPI_BUILD_TABLE_MAX_SIZE);
2834 assert(build_state->table_mr != NULL);
2835
2836 build_state->linker_mr =
2837 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
2838
2839 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2840 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2841
2842 if (!pcmc->rsdp_in_ram) {
2843 /*
2844 * Keep for compatibility with old machine types.
2845 * Though RSDP is small, its contents isn't immutable, so
2846 * we'll update it along with the rest of tables on guest access.
2847 */
2848 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2849
2850 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2851 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2852 acpi_build_update, build_state,
2853 build_state->rsdp, rsdp_size);
2854 build_state->rsdp_mr = NULL;
2855 } else {
2856 build_state->rsdp = NULL;
2857 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2858 ACPI_BUILD_RSDP_FILE, 0);
2859 }
2860
2861 qemu_register_reset(acpi_build_reset, build_state);
2862 acpi_build_reset(build_state);
2863 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2864
2865 /* Cleanup tables but don't free the memory: we track it
2866 * in build_state.
2867 */
2868 acpi_build_tables_cleanup(&tables, false);
2869 }
AR7 emulation for QEMU