block/nbd: allow drain during reconnect attempt
[qemu/ar7.git] / tests / qtest / pnv-xscom-test.c
blob2c46d5cf6de3c9e85e700d6e884ad8c6e01f769a
1 /*
2 * QTest testcase for PowerNV XSCOM bus
4 * Copyright (c) 2016, IBM Corporation.
6 * This work is licensed under the terms of the GNU GPL, version 2 or
7 * later. See the COPYING file in the top-level directory.
8 */
9 #include "qemu/osdep.h"
11 #include "libqtest.h"
13 typedef enum PnvChipType {
14 PNV_CHIP_POWER8E, /* AKA Murano (default) */
15 PNV_CHIP_POWER8, /* AKA Venice */
16 PNV_CHIP_POWER8NVL, /* AKA Naples */
17 PNV_CHIP_POWER9, /* AKA Nimbus */
18 } PnvChipType;
20 typedef struct PnvChip {
21 PnvChipType chip_type;
22 const char *cpu_model;
23 uint64_t xscom_base;
24 uint64_t cfam_id;
25 uint32_t first_core;
26 } PnvChip;
28 static const PnvChip pnv_chips[] = {
30 .chip_type = PNV_CHIP_POWER8,
31 .cpu_model = "POWER8",
32 .xscom_base = 0x0003fc0000000000ull,
33 .cfam_id = 0x220ea04980000000ull,
34 .first_core = 0x1,
35 }, {
36 .chip_type = PNV_CHIP_POWER8NVL,
37 .cpu_model = "POWER8NVL",
38 .xscom_base = 0x0003fc0000000000ull,
39 .cfam_id = 0x120d304980000000ull,
40 .first_core = 0x1,
43 .chip_type = PNV_CHIP_POWER9,
44 .cpu_model = "POWER9",
45 .xscom_base = 0x000603fc00000000ull,
46 .cfam_id = 0x220d104900008000ull,
47 .first_core = 0x0,
51 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
53 uint64_t addr = chip->xscom_base;
55 if (chip->chip_type == PNV_CHIP_POWER9) {
56 addr |= ((uint64_t) pcba << 3);
57 } else {
58 addr |= (((uint64_t) pcba << 4) & ~0xffull) |
59 (((uint64_t) pcba << 3) & 0x78);
61 return addr;
64 static uint64_t pnv_xscom_read(QTestState *qts, const PnvChip *chip,
65 uint32_t pcba)
67 return qtest_readq(qts, pnv_xscom_addr(chip, pcba));
70 static void test_xscom_cfam_id(QTestState *qts, const PnvChip *chip)
72 uint64_t f000f = pnv_xscom_read(qts, chip, 0xf000f);
74 g_assert_cmphex(f000f, ==, chip->cfam_id);
77 static void test_cfam_id(const void *data)
79 const PnvChip *chip = data;
80 const char *machine = "powernv8";
81 QTestState *qts;
83 if (chip->chip_type == PNV_CHIP_POWER9) {
84 machine = "powernv9";
87 qts = qtest_initf("-M %s -accel tcg -cpu %s",
88 machine, chip->cpu_model);
89 test_xscom_cfam_id(qts, chip);
90 qtest_quit(qts);
94 #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
95 #define PNV_XSCOM_EX_BASE(core) \
96 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
97 #define PNV_XSCOM_P9_EC_BASE(core) \
98 ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
100 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
102 static void test_xscom_core(QTestState *qts, const PnvChip *chip)
104 uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
105 uint64_t dts0;
107 if (chip->chip_type != PNV_CHIP_POWER9) {
108 first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
109 } else {
110 first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
113 dts0 = pnv_xscom_read(qts, chip, first_core_dts0);
115 g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
118 static void test_core(const void *data)
120 const PnvChip *chip = data;
121 QTestState *qts;
122 const char *machine = "powernv8";
124 if (chip->chip_type == PNV_CHIP_POWER9) {
125 machine = "powernv9";
128 qts = qtest_initf("-M %s -accel tcg -cpu %s",
129 machine, chip->cpu_model);
130 test_xscom_core(qts, chip);
131 qtest_quit(qts);
134 static void add_test(const char *name, void (*test)(const void *data))
136 int i;
138 for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
139 char *tname = g_strdup_printf("pnv-xscom/%s/%s", name,
140 pnv_chips[i].cpu_model);
141 qtest_add_data_func(tname, &pnv_chips[i], test);
142 g_free(tname);
146 int main(int argc, char **argv)
148 g_test_init(&argc, &argv, NULL);
150 add_test("cfam_id", test_cfam_id);
151 add_test("core", test_core);
152 return g_test_run();