hw/misc/aspeed_sdmc.c

   1 /*
   2  * ASPEED SDRAM Memory Controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later.  See
   7  * the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/module.h"
  13 #include "qemu/error-report.h"
  14 #include "hw/misc/aspeed_sdmc.h"
  15 #include "hw/misc/aspeed_scu.h"
  16 #include "hw/qdev-properties.h"
  17 #include "migration/vmstate.h"
  18 #include "qapi/error.h"
  19 #include "trace.h"
  20 #include "qemu/units.h"
  21 #include "qemu/cutils.h"
  22 #include "qapi/visitor.h"
  23
  24 /* Protection Key Register */
  25 #define R_PROT            (0x00 / 4)
  26 #define   PROT_UNLOCKED      0x01
  27 #define   PROT_HARDLOCKED    0x10  /* AST2600 */
  28 #define   PROT_SOFTLOCKED    0x00
  29
  30 #define   PROT_KEY_UNLOCK     0xFC600309
  31 #define   PROT_KEY_HARDLOCK   0xDEADDEAD /* AST2600 */
  32
  33 /* Configuration Register */
  34 #define R_CONF            (0x04 / 4)
  35
  36 /* Control/Status Register #1 (ast2500) */
  37 #define R_STATUS1         (0x60 / 4)
  38 #define   PHY_BUSY_STATE      BIT(0)
  39 #define   PHY_PLL_LOCK_STATUS BIT(4)
  40
  41 #define R_ECC_TEST_CTRL   (0x70 / 4)
  42 #define   ECC_TEST_FINISHED   BIT(12)
  43 #define   ECC_TEST_FAIL       BIT(13)
  44
  45 /*
  46  * Configuration register Ox4 (for Aspeed AST2400 SOC)
  47  *
  48  * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
  49  * what we care about right now as it is checked by U-Boot to
  50  * determine the RAM size.
  51  */
  52
  53 #define ASPEED_SDMC_RESERVED            0xFFFFF800 /* 31:11 reserved */
  54 #define ASPEED_SDMC_AST2300_COMPAT      (1 << 10)
  55 #define ASPEED_SDMC_SCRAMBLE_PATTERN    (1 << 9)
  56 #define ASPEED_SDMC_DATA_SCRAMBLE       (1 << 8)
  57 #define ASPEED_SDMC_ECC_ENABLE          (1 << 7)
  58 #define ASPEED_SDMC_VGA_COMPAT          (1 << 6) /* readonly */
  59 #define ASPEED_SDMC_DRAM_BANK           (1 << 5)
  60 #define ASPEED_SDMC_DRAM_BURST          (1 << 4)
  61 #define ASPEED_SDMC_VGA_APERTURE(x)     ((x & 0x3) << 2) /* readonly */
  62 #define     ASPEED_SDMC_VGA_8MB             0x0
  63 #define     ASPEED_SDMC_VGA_16MB            0x1
  64 #define     ASPEED_SDMC_VGA_32MB            0x2
  65 #define     ASPEED_SDMC_VGA_64MB            0x3
  66 #define ASPEED_SDMC_DRAM_SIZE(x)        (x & 0x3)
  67 #define     ASPEED_SDMC_DRAM_64MB           0x0
  68 #define     ASPEED_SDMC_DRAM_128MB          0x1
  69 #define     ASPEED_SDMC_DRAM_256MB          0x2
  70 #define     ASPEED_SDMC_DRAM_512MB          0x3
  71
  72 #define ASPEED_SDMC_READONLY_MASK                       \
  73     (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT |    \
  74      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  75 /*
  76  * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
  77  *
  78  * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
  79  * should be set to 1 for the AST2500 SOC.
  80  */
  81 #define ASPEED_SDMC_HW_VERSION(x)       ((x & 0xf) << 28) /* readonly */
  82 #define ASPEED_SDMC_SW_VERSION          ((x & 0xff) << 20)
  83 #define ASPEED_SDMC_CACHE_INITIAL_DONE  (1 << 19)  /* readonly */
  84 #define ASPEED_SDMC_AST2500_RESERVED    0x7C000 /* 18:14 reserved */
  85 #define ASPEED_SDMC_CACHE_DDR4_CONF     (1 << 13)
  86 #define ASPEED_SDMC_CACHE_INITIAL       (1 << 12)
  87 #define ASPEED_SDMC_CACHE_RANGE_CTRL    (1 << 11)
  88 #define ASPEED_SDMC_CACHE_ENABLE        (1 << 10) /* differs from AST2400 */
  89 #define ASPEED_SDMC_DRAM_TYPE           (1 << 4)  /* differs from AST2400 */
  90
  91 /* DRAM size definitions differs */
  92 #define     ASPEED_SDMC_AST2500_128MB       0x0
  93 #define     ASPEED_SDMC_AST2500_256MB       0x1
  94 #define     ASPEED_SDMC_AST2500_512MB       0x2
  95 #define     ASPEED_SDMC_AST2500_1024MB      0x3
  96
  97 #define     ASPEED_SDMC_AST2600_256MB       0x0
  98 #define     ASPEED_SDMC_AST2600_512MB       0x1
  99 #define     ASPEED_SDMC_AST2600_1024MB      0x2
 100 #define     ASPEED_SDMC_AST2600_2048MB      0x3
 101
 102 #define ASPEED_SDMC_AST2500_READONLY_MASK                               \
 103     (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE |     \
 104      ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |            \
 105      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
 106
 107 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
 108 {
 109     AspeedSDMCState *s = ASPEED_SDMC(opaque);
 110
 111     addr >>= 2;
 112
 113     if (addr >= ARRAY_SIZE(s->regs)) {
 114         qemu_log_mask(LOG_GUEST_ERROR,
 115                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 116                       __func__, addr);
 117         return 0;
 118     }
 119
 120     return s->regs[addr];
 121 }
 122
 123 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
 124                              unsigned int size)
 125 {
 126     AspeedSDMCState *s = ASPEED_SDMC(opaque);
 127     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 128
 129     addr >>= 2;
 130
 131     if (addr >= ARRAY_SIZE(s->regs)) {
 132         qemu_log_mask(LOG_GUEST_ERROR,
 133                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 134                       __func__, addr);
 135         return;
 136     }
 137
 138     asc->write(s, addr, data);
 139 }
 140
 141 static const MemoryRegionOps aspeed_sdmc_ops = {
 142     .read = aspeed_sdmc_read,
 143     .write = aspeed_sdmc_write,
 144     .endianness = DEVICE_LITTLE_ENDIAN,
 145     .valid.min_access_size = 4,
 146     .valid.max_access_size = 4,
 147 };
 148
 149 static int ast2400_rambits(AspeedSDMCState *s)
 150 {
 151     switch (s->ram_size >> 20) {
 152     case 64:
 153         return ASPEED_SDMC_DRAM_64MB;
 154     case 128:
 155         return ASPEED_SDMC_DRAM_128MB;
 156     case 256:
 157         return ASPEED_SDMC_DRAM_256MB;
 158     case 512:
 159         return ASPEED_SDMC_DRAM_512MB;
 160     default:
 161         g_assert_not_reached();
 162         break;
 163     }
 164 }
 165
 166 static int ast2500_rambits(AspeedSDMCState *s)
 167 {
 168     switch (s->ram_size >> 20) {
 169     case 128:
 170         return ASPEED_SDMC_AST2500_128MB;
 171     case 256:
 172         return ASPEED_SDMC_AST2500_256MB;
 173     case 512:
 174         return ASPEED_SDMC_AST2500_512MB;
 175     case 1024:
 176         return ASPEED_SDMC_AST2500_1024MB;
 177     default:
 178         g_assert_not_reached();
 179         break;
 180     }
 181 }
 182
 183 static int ast2600_rambits(AspeedSDMCState *s)
 184 {
 185     switch (s->ram_size >> 20) {
 186     case 256:
 187         return ASPEED_SDMC_AST2600_256MB;
 188     case 512:
 189         return ASPEED_SDMC_AST2600_512MB;
 190     case 1024:
 191         return ASPEED_SDMC_AST2600_1024MB;
 192     case 2048:
 193         return ASPEED_SDMC_AST2600_2048MB;
 194     default:
 195         g_assert_not_reached();
 196         break;
 197     }
 198 }
 199
 200 static void aspeed_sdmc_reset(DeviceState *dev)
 201 {
 202     AspeedSDMCState *s = ASPEED_SDMC(dev);
 203     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 204
 205     memset(s->regs, 0, sizeof(s->regs));
 206
 207     /* Set ram size bit and defaults values */
 208     s->regs[R_CONF] = asc->compute_conf(s, 0);
 209 }
 210
 211 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
 212                                      void *opaque, Error **errp)
 213 {
 214     AspeedSDMCState *s = ASPEED_SDMC(obj);
 215     int64_t value = s->ram_size;
 216
 217     visit_type_int(v, name, &value, errp);
 218 }
 219
 220 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
 221                                      void *opaque, Error **errp)
 222 {
 223     int i;
 224     char *sz;
 225     int64_t value;
 226     Error *local_err = NULL;
 227     AspeedSDMCState *s = ASPEED_SDMC(obj);
 228     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 229
 230     if (!visit_type_int(v, name, &value, &local_err)) {
 231         error_propagate(errp, local_err);
 232         return;
 233     }
 234
 235     for (i = 0; asc->valid_ram_sizes[i]; i++) {
 236         if (value == asc->valid_ram_sizes[i]) {
 237             s->ram_size = value;
 238             return;
 239         }
 240     }
 241
 242     sz = size_to_str(value);
 243     error_setg(errp, "Invalid RAM size %s", sz);
 244     g_free(sz);
 245 }
 246
 247 static void aspeed_sdmc_initfn(Object *obj)
 248 {
 249     object_property_add(obj, "ram-size", "int",
 250                         aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
 251                         NULL, NULL);
 252 }
 253
 254 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
 255 {
 256     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 257     AspeedSDMCState *s = ASPEED_SDMC(dev);
 258     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 259
 260     s->max_ram_size = asc->max_ram_size;
 261
 262     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
 263                           TYPE_ASPEED_SDMC, 0x1000);
 264     sysbus_init_mmio(sbd, &s->iomem);
 265 }
 266
 267 static const VMStateDescription vmstate_aspeed_sdmc = {
 268     .name = "aspeed.sdmc",
 269     .version_id = 1,
 270     .minimum_version_id = 1,
 271     .fields = (VMStateField[]) {
 272         VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
 273         VMSTATE_END_OF_LIST()
 274     }
 275 };
 276
 277 static Property aspeed_sdmc_properties[] = {
 278     DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
 279     DEFINE_PROP_END_OF_LIST(),
 280 };
 281
 282 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
 283 {
 284     DeviceClass *dc = DEVICE_CLASS(klass);
 285     dc->realize = aspeed_sdmc_realize;
 286     dc->reset = aspeed_sdmc_reset;
 287     dc->desc = "ASPEED SDRAM Memory Controller";
 288     dc->vmsd = &vmstate_aspeed_sdmc;
 289     device_class_set_props(dc, aspeed_sdmc_properties);
 290 }
 291
 292 static const TypeInfo aspeed_sdmc_info = {
 293     .name = TYPE_ASPEED_SDMC,
 294     .parent = TYPE_SYS_BUS_DEVICE,
 295     .instance_size = sizeof(AspeedSDMCState),
 296     .instance_init = aspeed_sdmc_initfn,
 297     .class_init = aspeed_sdmc_class_init,
 298     .class_size = sizeof(AspeedSDMCClass),
 299     .abstract   = true,
 300 };
 301
 302 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 303 {
 304     uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
 305         ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));
 306
 307     /* Make sure readonly bits are kept */
 308     data &= ~ASPEED_SDMC_READONLY_MASK;
 309
 310     return data | fixed_conf;
 311 }
 312
 313 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 314                                    uint32_t data)
 315 {
 316     if (reg == R_PROT) {
 317         s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
 318         return;
 319     }
 320
 321     if (!s->regs[R_PROT]) {
 322         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 323         return;
 324     }
 325
 326     switch (reg) {
 327     case R_CONF:
 328         data = aspeed_2400_sdmc_compute_conf(s, data);
 329         break;
 330     default:
 331         break;
 332     }
 333
 334     s->regs[reg] = data;
 335 }
 336
 337 static const uint64_t
 338 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
 339
 340 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
 341 {
 342     DeviceClass *dc = DEVICE_CLASS(klass);
 343     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 344
 345     dc->desc = "ASPEED 2400 SDRAM Memory Controller";
 346     asc->max_ram_size = 512 << 20;
 347     asc->compute_conf = aspeed_2400_sdmc_compute_conf;
 348     asc->write = aspeed_2400_sdmc_write;
 349     asc->valid_ram_sizes = aspeed_2400_ram_sizes;
 350 }
 351
 352 static const TypeInfo aspeed_2400_sdmc_info = {
 353     .name = TYPE_ASPEED_2400_SDMC,
 354     .parent = TYPE_ASPEED_SDMC,
 355     .class_init = aspeed_2400_sdmc_class_init,
 356 };
 357
 358 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 359 {
 360     uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
 361         ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 362         ASPEED_SDMC_CACHE_INITIAL_DONE |
 363         ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));
 364
 365     /* Make sure readonly bits are kept */
 366     data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 367
 368     return data | fixed_conf;
 369 }
 370
 371 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 372                                    uint32_t data)
 373 {
 374     if (reg == R_PROT) {
 375         s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
 376         return;
 377     }
 378
 379     if (!s->regs[R_PROT]) {
 380         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 381         return;
 382     }
 383
 384     switch (reg) {
 385     case R_CONF:
 386         data = aspeed_2500_sdmc_compute_conf(s, data);
 387         break;
 388     case R_STATUS1:
 389         /* Will never return 'busy' */
 390         data &= ~PHY_BUSY_STATE;
 391         break;
 392     case R_ECC_TEST_CTRL:
 393         /* Always done, always happy */
 394         data |= ECC_TEST_FINISHED;
 395         data &= ~ECC_TEST_FAIL;
 396         break;
 397     default:
 398         break;
 399     }
 400
 401     s->regs[reg] = data;
 402 }
 403
 404 static const uint64_t
 405 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
 406
 407 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
 408 {
 409     DeviceClass *dc = DEVICE_CLASS(klass);
 410     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 411
 412     dc->desc = "ASPEED 2500 SDRAM Memory Controller";
 413     asc->max_ram_size = 1024 << 20;
 414     asc->compute_conf = aspeed_2500_sdmc_compute_conf;
 415     asc->write = aspeed_2500_sdmc_write;
 416     asc->valid_ram_sizes = aspeed_2500_ram_sizes;
 417 }
 418
 419 static const TypeInfo aspeed_2500_sdmc_info = {
 420     .name = TYPE_ASPEED_2500_SDMC,
 421     .parent = TYPE_ASPEED_SDMC,
 422     .class_init = aspeed_2500_sdmc_class_init,
 423 };
 424
 425 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 426 {
 427     uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
 428         ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 429         ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s));
 430
 431     /* Make sure readonly bits are kept (use ast2500 mask) */
 432     data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 433
 434     return data | fixed_conf;
 435 }
 436
 437 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 438                                    uint32_t data)
 439 {
 440     if (s->regs[R_PROT] == PROT_HARDLOCKED) {
 441         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
 442                 __func__);
 443         return;
 444     }
 445
 446     if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
 447         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 448         return;
 449     }
 450
 451     switch (reg) {
 452     case R_PROT:
 453         if (data == PROT_KEY_UNLOCK)  {
 454             data = PROT_UNLOCKED;
 455         } else if (data == PROT_KEY_HARDLOCK) {
 456             data = PROT_HARDLOCKED;
 457         } else {
 458             data = PROT_SOFTLOCKED;
 459         }
 460         break;
 461     case R_CONF:
 462         data = aspeed_2600_sdmc_compute_conf(s, data);
 463         break;
 464     case R_STATUS1:
 465         /* Will never return 'busy'. 'lock status' is always set */
 466         data &= ~PHY_BUSY_STATE;
 467         data |= PHY_PLL_LOCK_STATUS;
 468         break;
 469     case R_ECC_TEST_CTRL:
 470         /* Always done, always happy */
 471         data |= ECC_TEST_FINISHED;
 472         data &= ~ECC_TEST_FAIL;
 473         break;
 474     default:
 475         break;
 476     }
 477
 478     s->regs[reg] = data;
 479 }
 480
 481 static const uint64_t
 482 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
 483
 484 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
 485 {
 486     DeviceClass *dc = DEVICE_CLASS(klass);
 487     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 488
 489     dc->desc = "ASPEED 2600 SDRAM Memory Controller";
 490     asc->max_ram_size = 2048 << 20;
 491     asc->compute_conf = aspeed_2600_sdmc_compute_conf;
 492     asc->write = aspeed_2600_sdmc_write;
 493     asc->valid_ram_sizes = aspeed_2600_ram_sizes;
 494 }
 495
 496 static const TypeInfo aspeed_2600_sdmc_info = {
 497     .name = TYPE_ASPEED_2600_SDMC,
 498     .parent = TYPE_ASPEED_SDMC,
 499     .class_init = aspeed_2600_sdmc_class_init,
 500 };
 501
 502 static void aspeed_sdmc_register_types(void)
 503 {
 504     type_register_static(&aspeed_sdmc_info);
 505     type_register_static(&aspeed_2400_sdmc_info);
 506     type_register_static(&aspeed_2500_sdmc_info);
 507     type_register_static(&aspeed_2600_sdmc_info);
 508 }
 509
 510 type_init(aspeed_sdmc_register_types);