target/ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_CPU_H
  21 #define PPC_CPU_H
  22
  23 #include "qemu-common.h"
  24 #include "qemu/int128.h"
  25
  26 //#define PPC_EMULATE_32BITS_HYPV
  27
  28 #if defined (TARGET_PPC64)
  29 /* PowerPC 64 definitions */
  30 #define TARGET_LONG_BITS 64
  31 #define TARGET_PAGE_BITS 12
  32
  33 #define TCG_GUEST_DEFAULT_MO 0
  34
  35 /* Note that the official physical address space bits is 62-M where M
  36    is implementation dependent.  I've not looked up M for the set of
  37    cpus we emulate at the system level.  */
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  39
  40 /* Note that the PPC environment architecture talks about 80 bit virtual
  41    addresses, with segmentation.  Obviously that's not all visible to a
  42    single process, which is all we're concerned with here.  */
  43 #ifdef TARGET_ABI32
  44 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  45 #else
  46 # define TARGET_VIRT_ADDR_SPACE_BITS 64
  47 #endif
  48
  49 #define TARGET_PAGE_BITS_64K 16
  50 #define TARGET_PAGE_BITS_16M 24
  51
  52 #else /* defined (TARGET_PPC64) */
  53 /* PowerPC 32 definitions */
  54 #define TARGET_LONG_BITS 32
  55
  56 #if defined(TARGET_PPCEMB)
  57 /* Specific definitions for PowerPC embedded */
  58 /* BookE have 36 bits physical address space */
  59 #if defined(CONFIG_USER_ONLY)
  60 /* It looks like a lot of Linux programs assume page size
  61  * is 4kB long. This is evil, but we have to deal with it...
  62  */
  63 #define TARGET_PAGE_BITS 12
  64 #else /* defined(CONFIG_USER_ONLY) */
  65 /* Pages can be 1 kB small */
  66 #define TARGET_PAGE_BITS 10
  67 #endif /* defined(CONFIG_USER_ONLY) */
  68 #else /* defined(TARGET_PPCEMB) */
  69 /* "standard" PowerPC 32 definitions */
  70 #define TARGET_PAGE_BITS 12
  71 #endif /* defined(TARGET_PPCEMB) */
  72
  73 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  74 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  75
  76 #endif /* defined (TARGET_PPC64) */
  77
  78 #define CPUArchState struct CPUPPCState
  79
  80 #include "exec/cpu-defs.h"
  81 #include "cpu-qom.h"
  82 #include "fpu/softfloat.h"
  83
  84 #if defined (TARGET_PPC64)
  85 #define PPC_ELF_MACHINE     EM_PPC64
  86 #else
  87 #define PPC_ELF_MACHINE     EM_PPC
  88 #endif
  89
  90 #define PPC_BIT(bit)            (0x8000000000000000UL >> (bit))
  91 #define PPC_BIT32(bit)          (0x80000000UL >> (bit))
  92 #define PPC_BIT8(bit)           (0x80UL >> (bit))
  93 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
  94 #define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
  95                                  PPC_BIT32(bs))
  96 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
  97
  98 #if HOST_LONG_BITS == 32
  99 # define MASK_TO_LSH(m)          (__builtin_ffsll(m) - 1)
 100 #elif HOST_LONG_BITS == 64
 101 # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
 102 #else
 103 # error Unknown sizeof long
 104 #endif
 105
 106 #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
 107 #define SETFIELD(m, v, val)                             \
 108         (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
 109
 110 /*****************************************************************************/
 111 /* Exception vectors definitions                                             */
 112 enum {
 113     POWERPC_EXCP_NONE    = -1,
 114     /* The 64 first entries are used by the PowerPC embedded specification   */
 115     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 116     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 117     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 118     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 119     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 120     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 121     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 122     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 123     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 124     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 125     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 126     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 127     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 128     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 129     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 130     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 131     /* Vectors 16 to 31 are reserved                                         */
 132     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 133     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 134     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 135     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 136     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 137     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 138     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
 139     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
 140     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
 141     /* Vectors 42 to 63 are reserved                                         */
 142     /* Exceptions defined in the PowerPC server specification                */
 143     /* Server doorbell variants */
 144 #define POWERPC_EXCP_SDOOR      POWERPC_EXCP_GDOORI
 145 #define POWERPC_EXCP_SDOOR_HV   POWERPC_EXCP_DOORI
 146     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 147     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 148     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 149     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 150     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 151     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 152     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 153     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 154     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 155     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 156     /* 40x specific exceptions                                               */
 157     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 158     /* 601 specific exceptions                                               */
 159     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 160     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 161     /* 602 specific exceptions                                               */
 162     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 163     /* 602/603 specific exceptions                                           */
 164     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 165     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 166     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 167     /* Exceptions available on most PowerPC                                  */
 168     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 169     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 170     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 171     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 172     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 173     /* 7xx/74xx specific exceptions                                          */
 174     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 175     /* 74xx specific exceptions                                              */
 176     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 177     /* 970FX specific exceptions                                             */
 178     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 179     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 180     /* Freescale embedded cores specific exceptions                          */
 181     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 182     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 183     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 184     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 185     /* VSX Unavailable (Power ISA 2.06 and later)                            */
 186     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 187     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 188     /* Additional ISA 2.06 and later server exceptions                       */
 189     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 190     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 191     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 192     /* EOL                                                                   */
 193     POWERPC_EXCP_NB       = 99,
 194     /* QEMU exceptions: used internally during code translation              */
 195     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 196     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 197     /* QEMU exceptions: special cases we want to stop translation            */
 198     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 199     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 200     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
 201 };
 202
 203 /* Exceptions error codes                                                    */
 204 enum {
 205     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 206     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 207     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 208     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 209     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 210     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 211     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 212     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 213     /* FP exceptions                                                         */
 214     POWERPC_EXCP_FP            = 0x10,
 215     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 216     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 217     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 218     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 219     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 220     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 221     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 222     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 223     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 224     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 225     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 226     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 227     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 228     /* Invalid instruction                                                   */
 229     POWERPC_EXCP_INVAL         = 0x20,
 230     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 231     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 232     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 233     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 234     /* Privileged instruction                                                */
 235     POWERPC_EXCP_PRIV          = 0x30,
 236     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 237     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 238     /* Trap                                                                  */
 239     POWERPC_EXCP_TRAP          = 0x40,
 240 };
 241
 242 #define PPC_INPUT(env) (env->bus_model)
 243
 244 /*****************************************************************************/
 245 typedef struct opc_handler_t opc_handler_t;
 246
 247 /*****************************************************************************/
 248 /* Types used to describe some PowerPC registers etc. */
 249 typedef struct DisasContext DisasContext;
 250 typedef struct ppc_spr_t ppc_spr_t;
 251 typedef union ppc_avr_t ppc_avr_t;
 252 typedef union ppc_tlb_t ppc_tlb_t;
 253 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
 254
 255 /* SPR access micro-ops generations callbacks */
 256 struct ppc_spr_t {
 257     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 258     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 259 #if !defined(CONFIG_USER_ONLY)
 260     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 261     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 262     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 263     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 264 #endif
 265     const char *name;
 266     target_ulong default_value;
 267 #ifdef CONFIG_KVM
 268     /* We (ab)use the fact that all the SPRs will have ids for the
 269      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 270      * don't sync this */
 271     uint64_t one_reg_id;
 272 #endif
 273 };
 274
 275 /* Altivec registers (128 bits) */
 276 union ppc_avr_t {
 277     float32 f[4];
 278     uint8_t u8[16];
 279     uint16_t u16[8];
 280     uint32_t u32[4];
 281     int8_t s8[16];
 282     int16_t s16[8];
 283     int32_t s32[4];
 284     uint64_t u64[2];
 285     int64_t s64[2];
 286 #ifdef CONFIG_INT128
 287     __uint128_t u128;
 288 #endif
 289     Int128 s128;
 290 };
 291
 292 #if !defined(CONFIG_USER_ONLY)
 293 /* Software TLB cache */
 294 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 295 struct ppc6xx_tlb_t {
 296     target_ulong pte0;
 297     target_ulong pte1;
 298     target_ulong EPN;
 299 };
 300
 301 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 302 struct ppcemb_tlb_t {
 303     uint64_t RPN;
 304     target_ulong EPN;
 305     target_ulong PID;
 306     target_ulong size;
 307     uint32_t prot;
 308     uint32_t attr; /* Storage attributes */
 309 };
 310
 311 typedef struct ppcmas_tlb_t {
 312      uint32_t mas8;
 313      uint32_t mas1;
 314      uint64_t mas2;
 315      uint64_t mas7_3;
 316 } ppcmas_tlb_t;
 317
 318 union ppc_tlb_t {
 319     ppc6xx_tlb_t *tlb6;
 320     ppcemb_tlb_t *tlbe;
 321     ppcmas_tlb_t *tlbm;
 322 };
 323
 324 /* possible TLB variants */
 325 #define TLB_NONE               0
 326 #define TLB_6XX                1
 327 #define TLB_EMB                2
 328 #define TLB_MAS                3
 329 #endif
 330
 331 typedef struct ppc_slb_t ppc_slb_t;
 332 struct ppc_slb_t {
 333     uint64_t esid;
 334     uint64_t vsid;
 335     const struct ppc_one_seg_page_size *sps;
 336 };
 337
 338 #define MAX_SLB_ENTRIES         64
 339 #define SEGMENT_SHIFT_256M      28
 340 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 341
 342 #define SEGMENT_SHIFT_1T        40
 343 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 344
 345
 346 /*****************************************************************************/
 347 /* Machine state register bits definition                                    */
 348 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 349 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 350 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 351 #define MSR_SHV  60 /* hypervisor state                               hflags */
 352 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 353 #define MSR_TS1  33
 354 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 355 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 356 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 357 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 358 #define MSR_GS   28 /* guest state for BookE                                 */
 359 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 360 #define MSR_VR   25 /* altivec available                            x hflags */
 361 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 362 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 363 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 364 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 365 #define MSR_KEY  19 /* key bit on 603e                                       */
 366 #define MSR_POW  18 /* Power management                                      */
 367 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 368 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 369 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 370 #define MSR_EE   15 /* External interrupt enable                             */
 371 #define MSR_PR   14 /* Problem state                                  hflags */
 372 #define MSR_FP   13 /* Floating point available                       hflags */
 373 #define MSR_ME   12 /* Machine check interrupt enable                        */
 374 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 375 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 376 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 377 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 378 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 379 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 380 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 381 #define MSR_AL   7  /* AL bit on POWER                                       */
 382 #define MSR_EP   6  /* Exception prefix on 601                               */
 383 #define MSR_IR   5  /* Instruction relocate                                  */
 384 #define MSR_DR   4  /* Data relocate                                         */
 385 #define MSR_IS   5  /* Instruction address space (BookE)                     */
 386 #define MSR_DS   4  /* Data address space (BookE)                            */
 387 #define MSR_PE   3  /* Protection enable on 403                              */
 388 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 389 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 390 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 391 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 392
 393 /* LPCR bits */
 394 #define LPCR_VPM0         PPC_BIT(0)
 395 #define LPCR_VPM1         PPC_BIT(1)
 396 #define LPCR_ISL          PPC_BIT(2)
 397 #define LPCR_KBV          PPC_BIT(3)
 398 #define LPCR_DPFD_SHIFT   (63 - 11)
 399 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 400 #define LPCR_VRMASD_SHIFT (63 - 16)
 401 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 402 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
 403 #define LPCR_PECE_U_SHIFT (63 - 19)
 404 #define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
 405 #define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
 406 #define LPCR_RMLS_SHIFT   (63 - 37)
 407 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 408 #define LPCR_ILE          PPC_BIT(38)
 409 #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
 410 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 411 #define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
 412 #define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
 413 #define LPCR_ONL          PPC_BIT(45)
 414 #define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
 415 #define LPCR_P7_PECE0     PPC_BIT(49)
 416 #define LPCR_P7_PECE1     PPC_BIT(50)
 417 #define LPCR_P7_PECE2     PPC_BIT(51)
 418 #define LPCR_P8_PECE0     PPC_BIT(47)
 419 #define LPCR_P8_PECE1     PPC_BIT(48)
 420 #define LPCR_P8_PECE2     PPC_BIT(49)
 421 #define LPCR_P8_PECE3     PPC_BIT(50)
 422 #define LPCR_P8_PECE4     PPC_BIT(51)
 423 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
 424 #define LPCR_PECE_L_SHIFT (63 - 51)
 425 #define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
 426 #define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
 427 #define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
 428 #define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
 429 #define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
 430 #define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
 431 #define LPCR_MER          PPC_BIT(52)
 432 #define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
 433 #define LPCR_TC           PPC_BIT(54)
 434 #define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
 435 #define LPCR_LPES0        PPC_BIT(60)
 436 #define LPCR_LPES1        PPC_BIT(61)
 437 #define LPCR_RMI          PPC_BIT(62)
 438 #define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
 439 #define LPCR_HDICE        PPC_BIT(63)
 440
 441 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 442 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 443 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 444 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 445 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 446 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 447 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 448 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 449 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 450 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 451 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 452 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 453 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 454 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 455 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 456 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 457 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 458 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 459 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 460 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 461 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 462 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 463 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 464 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 465 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 466 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 467 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 468 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 469 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 470 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 471 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 472 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 473 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 474 #define msr_is   ((env->msr >> MSR_IS)   & 1)
 475 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
 476 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 477 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 478 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 479 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 480 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 481 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 482 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
 483
 484 /* Hypervisor bit is more specific */
 485 #if defined(TARGET_PPC64)
 486 #define MSR_HVB (1ULL << MSR_SHV)
 487 #define msr_hv  msr_shv
 488 #else
 489 #if defined(PPC_EMULATE_32BITS_HYPV)
 490 #define MSR_HVB (1ULL << MSR_THV)
 491 #define msr_hv  msr_thv
 492 #else
 493 #define MSR_HVB (0ULL)
 494 #define msr_hv  (0)
 495 #endif
 496 #endif
 497
 498 /* DSISR */
 499 #define DSISR_NOPTE              0x40000000
 500 /* Not permitted by access authority of encoded access authority */
 501 #define DSISR_PROTFAULT          0x08000000
 502 #define DSISR_ISSTORE            0x02000000
 503 /* Not permitted by virtual page class key protection */
 504 #define DSISR_AMR                0x00200000
 505 /* Unsupported Radix Tree Configuration */
 506 #define DSISR_R_BADCONFIG        0x00080000
 507
 508 /* SRR1 error code fields */
 509
 510 #define SRR1_NOPTE               DSISR_NOPTE
 511 /* Not permitted due to no-execute or guard bit set */
 512 #define SRR1_NOEXEC_GUARD        0x10000000
 513 #define SRR1_PROTFAULT           DSISR_PROTFAULT
 514 #define SRR1_IAMR                DSISR_AMR
 515
 516 /* Facility Status and Control (FSCR) bits */
 517 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 518 #define FSCR_TAR        (63 - 55) /* Target Address Register */
 519 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 520 #define FSCR_IC_MASK    (0xFFULL)
 521 #define FSCR_IC_POS     (63 - 7)
 522 #define FSCR_IC_DSCR_SPR3   2
 523 #define FSCR_IC_PMU         3
 524 #define FSCR_IC_BHRB        4
 525 #define FSCR_IC_TM          5
 526 #define FSCR_IC_EBB         7
 527 #define FSCR_IC_TAR         8
 528
 529 /* Exception state register bits definition                                  */
 530 #define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
 531 #define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
 532 #define ESR_PTR   PPC_BIT(38) /* Trap                                   */
 533 #define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
 534 #define ESR_ST    PPC_BIT(40) /* Store Operation                        */
 535 #define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
 536 #define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
 537 #define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
 538 #define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
 539 #define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
 540 #define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
 541 #define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
 542 #define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
 543 #define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
 544 #define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
 545 #define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
 546
 547 /* Transaction EXception And Summary Register bits                           */
 548 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 549 #define TEXASR_DISALLOWED                        (63 - 8)
 550 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 551 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 552 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 553 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 554 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 555 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 556 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 557 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 558 #define TEXASR_ABORT                             (63 - 31)
 559 #define TEXASR_SUSPENDED                         (63 - 32)
 560 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
 561 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
 562 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 563 #define TEXASR_TFIAR_EXACT                       (63 - 37)
 564 #define TEXASR_ROT                               (63 - 38)
 565 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 566
 567 enum {
 568     POWERPC_FLAG_NONE     = 0x00000000,
 569     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 570     POWERPC_FLAG_SPE      = 0x00000001,
 571     POWERPC_FLAG_VRE      = 0x00000002,
 572     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 573     POWERPC_FLAG_TGPR     = 0x00000004,
 574     POWERPC_FLAG_CE       = 0x00000008,
 575     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 576     POWERPC_FLAG_SE       = 0x00000010,
 577     POWERPC_FLAG_DWE      = 0x00000020,
 578     POWERPC_FLAG_UBLE     = 0x00000040,
 579     /* Flag for MSR bit 9 signification (BE/DE)                              */
 580     POWERPC_FLAG_BE       = 0x00000080,
 581     POWERPC_FLAG_DE       = 0x00000100,
 582     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 583     POWERPC_FLAG_PX       = 0x00000200,
 584     POWERPC_FLAG_PMM      = 0x00000400,
 585     /* Flag for special features                                             */
 586     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 587     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 588     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 589     /* Has CFAR                                                              */
 590     POWERPC_FLAG_CFAR     = 0x00040000,
 591     /* Has VSX                                                               */
 592     POWERPC_FLAG_VSX      = 0x00080000,
 593     /* Has Transaction Memory (ISA 2.07)                                     */
 594     POWERPC_FLAG_TM       = 0x00100000,
 595 };
 596
 597 /*****************************************************************************/
 598 /* Floating point status and control register                                */
 599 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 600 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 601 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 602 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 603 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 604 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 605 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 606 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 607 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 608 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 609 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 610 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 611 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 612 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 613 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 614 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 615 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 616 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 617 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 618 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 619 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 620 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 621 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 622 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 623 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 624 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 625 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 626 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 627 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 628 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 629 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 630 #define FPSCR_RN1    1
 631 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 632 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 633 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 634 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 635 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 636 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 637 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 638 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 639 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 640 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 641 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 642 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 643 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 644 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 645 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 646 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 647 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 648 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 649 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 650 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 651 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 652 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 653 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 654 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 655 /* Invalid operation exception summary */
 656 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 657                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 658                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 659                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 660                                   (1 << FPSCR_VXCVI)))
 661 /* exception summary */
 662 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 663 /* enabled exception summary */
 664 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 665                    0x1F)
 666
 667 #define FP_FX           (1ull << FPSCR_FX)
 668 #define FP_FEX          (1ull << FPSCR_FEX)
 669 #define FP_VX           (1ull << FPSCR_VX)
 670 #define FP_OX           (1ull << FPSCR_OX)
 671 #define FP_UX           (1ull << FPSCR_UX)
 672 #define FP_ZX           (1ull << FPSCR_ZX)
 673 #define FP_XX           (1ull << FPSCR_XX)
 674 #define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 675 #define FP_VXISI        (1ull << FPSCR_VXISI)
 676 #define FP_VXIDI        (1ull << FPSCR_VXIDI)
 677 #define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 678 #define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 679 #define FP_VXVC         (1ull << FPSCR_VXVC)
 680 #define FP_FR           (1ull << FSPCR_FR)
 681 #define FP_FI           (1ull << FPSCR_FI)
 682 #define FP_C            (1ull << FPSCR_C)
 683 #define FP_FL           (1ull << FPSCR_FL)
 684 #define FP_FG           (1ull << FPSCR_FG)
 685 #define FP_FE           (1ull << FPSCR_FE)
 686 #define FP_FU           (1ull << FPSCR_FU)
 687 #define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 688 #define FP_FPRF         (FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
 689 #define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 690 #define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 691 #define FP_VXCVI        (1ull << FPSCR_VXCVI)
 692 #define FP_VE           (1ull << FPSCR_VE)
 693 #define FP_OE           (1ull << FPSCR_OE)
 694 #define FP_UE           (1ull << FPSCR_UE)
 695 #define FP_ZE           (1ull << FPSCR_ZE)
 696 #define FP_XE           (1ull << FPSCR_XE)
 697 #define FP_NI           (1ull << FPSCR_NI)
 698 #define FP_RN1          (1ull << FPSCR_RN1)
 699 #define FP_RN           (1ull << FPSCR_RN)
 700
 701 /* the exception bits which can be cleared by mcrfs - includes FX */
 702 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 703                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 704                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 705                           FP_VXSQRT | FP_VXCVI)
 706
 707 /*****************************************************************************/
 708 /* Vector status and control register */
 709 #define VSCR_NJ         16 /* Vector non-java */
 710 #define VSCR_SAT        0 /* Vector saturation */
 711 #define vscr_nj         (((env->vscr) >> VSCR_NJ)       & 0x1)
 712 #define vscr_sat        (((env->vscr) >> VSCR_SAT)      & 0x1)
 713
 714 /*****************************************************************************/
 715 /* BookE e500 MMU registers */
 716
 717 #define MAS0_NV_SHIFT      0
 718 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 719
 720 #define MAS0_WQ_SHIFT      12
 721 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 722 /* Write TLB entry regardless of reservation */
 723 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 724 /* Write TLB entry only already in use */
 725 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 726 /* Clear TLB entry */
 727 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 728
 729 #define MAS0_HES_SHIFT     14
 730 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
 731
 732 #define MAS0_ESEL_SHIFT    16
 733 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 734
 735 #define MAS0_TLBSEL_SHIFT  28
 736 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 737 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 738 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 739 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 740 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 741
 742 #define MAS0_ATSEL_SHIFT   31
 743 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 744 #define MAS0_ATSEL_TLB     0
 745 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 746
 747 #define MAS1_TSIZE_SHIFT   7
 748 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 749
 750 #define MAS1_TS_SHIFT      12
 751 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
 752
 753 #define MAS1_IND_SHIFT     13
 754 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
 755
 756 #define MAS1_TID_SHIFT     16
 757 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 758
 759 #define MAS1_IPROT_SHIFT   30
 760 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 761
 762 #define MAS1_VALID_SHIFT   31
 763 #define MAS1_VALID         0x80000000
 764
 765 #define MAS2_EPN_SHIFT     12
 766 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 767
 768 #define MAS2_ACM_SHIFT     6
 769 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 770
 771 #define MAS2_VLE_SHIFT     5
 772 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 773
 774 #define MAS2_W_SHIFT       4
 775 #define MAS2_W             (1 << MAS2_W_SHIFT)
 776
 777 #define MAS2_I_SHIFT       3
 778 #define MAS2_I             (1 << MAS2_I_SHIFT)
 779
 780 #define MAS2_M_SHIFT       2
 781 #define MAS2_M             (1 << MAS2_M_SHIFT)
 782
 783 #define MAS2_G_SHIFT       1
 784 #define MAS2_G             (1 << MAS2_G_SHIFT)
 785
 786 #define MAS2_E_SHIFT       0
 787 #define MAS2_E             (1 << MAS2_E_SHIFT)
 788
 789 #define MAS3_RPN_SHIFT     12
 790 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 791
 792 #define MAS3_U0                 0x00000200
 793 #define MAS3_U1                 0x00000100
 794 #define MAS3_U2                 0x00000080
 795 #define MAS3_U3                 0x00000040
 796 #define MAS3_UX                 0x00000020
 797 #define MAS3_SX                 0x00000010
 798 #define MAS3_UW                 0x00000008
 799 #define MAS3_SW                 0x00000004
 800 #define MAS3_UR                 0x00000002
 801 #define MAS3_SR                 0x00000001
 802 #define MAS3_SPSIZE_SHIFT       1
 803 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 804
 805 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 806 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 807 #define MAS4_TIDSELD_MASK       0x00030000
 808 #define MAS4_TIDSELD_PID0       0x00000000
 809 #define MAS4_TIDSELD_PID1       0x00010000
 810 #define MAS4_TIDSELD_PID2       0x00020000
 811 #define MAS4_TIDSELD_PIDZ       0x00030000
 812 #define MAS4_INDD               0x00008000      /* Default IND */
 813 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 814 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 815 #define MAS4_ACMD               0x00000040
 816 #define MAS4_VLED               0x00000020
 817 #define MAS4_WD                 0x00000010
 818 #define MAS4_ID                 0x00000008
 819 #define MAS4_MD                 0x00000004
 820 #define MAS4_GD                 0x00000002
 821 #define MAS4_ED                 0x00000001
 822 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 823 #define MAS4_WIMGED_SHIFT       0
 824
 825 #define MAS5_SGS                0x80000000
 826 #define MAS5_SLPID_MASK         0x00000fff
 827
 828 #define MAS6_SPID0              0x3fff0000
 829 #define MAS6_SPID1              0x00007ffe
 830 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 831 #define MAS6_SAS                0x00000001
 832 #define MAS6_SPID               MAS6_SPID0
 833 #define MAS6_SIND               0x00000002      /* Indirect page */
 834 #define MAS6_SIND_SHIFT         1
 835 #define MAS6_SPID_MASK          0x3fff0000
 836 #define MAS6_SPID_SHIFT         16
 837 #define MAS6_ISIZE_MASK         0x00000f80
 838 #define MAS6_ISIZE_SHIFT        7
 839
 840 #define MAS7_RPN                0xffffffff
 841
 842 #define MAS8_TGS                0x80000000
 843 #define MAS8_VF                 0x40000000
 844 #define MAS8_TLBPID             0x00000fff
 845
 846 /* Bit definitions for MMUCFG */
 847 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 848 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 849 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 850 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 851 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 852 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 853 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 854 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 855 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 856
 857 /* Bit definitions for MMUCSR0 */
 858 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 859 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 860 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 861 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 862 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 863                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 864 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 865 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 866 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 867 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 868
 869 /* TLBnCFG encoding */
 870 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 871 #define TLBnCFG_HES             0x00002000      /* HW select supported */
 872 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 873 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 874 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 875 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 876 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
 877 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 878 #define TLBnCFG_MINSIZE_SHIFT   20
 879 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 880 #define TLBnCFG_MAXSIZE_SHIFT   16
 881 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 882 #define TLBnCFG_ASSOC_SHIFT     24
 883
 884 /* TLBnPS encoding */
 885 #define TLBnPS_4K               0x00000004
 886 #define TLBnPS_8K               0x00000008
 887 #define TLBnPS_16K              0x00000010
 888 #define TLBnPS_32K              0x00000020
 889 #define TLBnPS_64K              0x00000040
 890 #define TLBnPS_128K             0x00000080
 891 #define TLBnPS_256K             0x00000100
 892 #define TLBnPS_512K             0x00000200
 893 #define TLBnPS_1M               0x00000400
 894 #define TLBnPS_2M               0x00000800
 895 #define TLBnPS_4M               0x00001000
 896 #define TLBnPS_8M               0x00002000
 897 #define TLBnPS_16M              0x00004000
 898 #define TLBnPS_32M              0x00008000
 899 #define TLBnPS_64M              0x00010000
 900 #define TLBnPS_128M             0x00020000
 901 #define TLBnPS_256M             0x00040000
 902 #define TLBnPS_512M             0x00080000
 903 #define TLBnPS_1G               0x00100000
 904 #define TLBnPS_2G               0x00200000
 905 #define TLBnPS_4G               0x00400000
 906 #define TLBnPS_8G               0x00800000
 907 #define TLBnPS_16G              0x01000000
 908 #define TLBnPS_32G              0x02000000
 909 #define TLBnPS_64G              0x04000000
 910 #define TLBnPS_128G             0x08000000
 911 #define TLBnPS_256G             0x10000000
 912
 913 /* tlbilx action encoding */
 914 #define TLBILX_T_ALL                    0
 915 #define TLBILX_T_TID                    1
 916 #define TLBILX_T_FULLMATCH              3
 917 #define TLBILX_T_CLASS0                 4
 918 #define TLBILX_T_CLASS1                 5
 919 #define TLBILX_T_CLASS2                 6
 920 #define TLBILX_T_CLASS3                 7
 921
 922 /* BookE 2.06 helper defines */
 923
 924 #define BOOKE206_FLUSH_TLB0    (1 << 0)
 925 #define BOOKE206_FLUSH_TLB1    (1 << 1)
 926 #define BOOKE206_FLUSH_TLB2    (1 << 2)
 927 #define BOOKE206_FLUSH_TLB3    (1 << 3)
 928
 929 /* number of possible TLBs */
 930 #define BOOKE206_MAX_TLBN      4
 931
 932 /*****************************************************************************/
 933 /* Embedded.Processor Control */
 934
 935 #define DBELL_TYPE_SHIFT               27
 936 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 937 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 938 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 939 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 940 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 941 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 942
 943 #define DBELL_BRDCAST                  (1 << 26)
 944 #define DBELL_LPIDTAG_SHIFT            14
 945 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 946 #define DBELL_PIRTAG_MASK              0x3fff
 947
 948 /*****************************************************************************/
 949 /* Segment page size information, used by recent hash MMUs
 950  * The format of this structure mirrors kvm_ppc_smmu_info
 951  */
 952
 953 #define PPC_PAGE_SIZES_MAX_SZ   8
 954
 955 struct ppc_one_page_size {
 956     uint32_t page_shift;  /* Page shift (or 0) */
 957     uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
 958 };
 959
 960 struct ppc_one_seg_page_size {
 961     uint32_t page_shift;  /* Base page shift of segment (or 0) */
 962     uint32_t slb_enc;     /* SLB encoding for BookS */
 963     struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
 964 };
 965
 966 struct ppc_segment_page_sizes {
 967     struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
 968 };
 969
 970 struct ppc_radix_page_info {
 971     uint32_t count;
 972     uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
 973 };
 974
 975 /*****************************************************************************/
 976 /* The whole PowerPC CPU context */
 977 #define NB_MMU_MODES    8
 978
 979 #define PPC_CPU_OPCODES_LEN          0x40
 980 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 981
 982 struct CPUPPCState {
 983     /* First are the most commonly used resources
 984      * during translated code execution
 985      */
 986     /* general purpose registers */
 987     target_ulong gpr[32];
 988     /* Storage for GPR MSB, used by the SPE extension */
 989     target_ulong gprh[32];
 990     /* LR */
 991     target_ulong lr;
 992     /* CTR */
 993     target_ulong ctr;
 994     /* condition register */
 995     uint32_t crf[8];
 996 #if defined(TARGET_PPC64)
 997     /* CFAR */
 998     target_ulong cfar;
 999 #endif
1000     /* XER (with SO, OV, CA split out) */
1001     target_ulong xer;
1002     target_ulong so;
1003     target_ulong ov;
1004     target_ulong ca;
1005     target_ulong ov32;
1006     target_ulong ca32;
1007     /* Reservation address */
1008     target_ulong reserve_addr;
1009     /* Reservation value */
1010     target_ulong reserve_val;
1011     target_ulong reserve_val2;
1012     /* Reservation store address */
1013     target_ulong reserve_ea;
1014     /* Reserved store source register and size */
1015     target_ulong reserve_info;
1016
1017     /* Those ones are used in supervisor mode only */
1018     /* machine state register */
1019     target_ulong msr;
1020     /* temporary general purpose registers */
1021     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1022
1023     /* Floating point execution context */
1024     float_status fp_status;
1025     /* floating point registers */
1026     float64 fpr[32];
1027     /* floating point status and control register */
1028     target_ulong fpscr;
1029
1030     /* Next instruction pointer */
1031     target_ulong nip;
1032
1033     int access_type; /* when a memory exception occurs, the access
1034                         type is stored here */
1035
1036     CPU_COMMON
1037
1038     /* MMU context - only relevant for full system emulation */
1039 #if !defined(CONFIG_USER_ONLY)
1040 #if defined(TARGET_PPC64)
1041     /* PowerPC 64 SLB area */
1042     ppc_slb_t slb[MAX_SLB_ENTRIES];
1043     int32_t slb_nr;
1044     /* tcg TLB needs flush (deferred slb inval instruction typically) */
1045 #endif
1046     /* segment registers */
1047     target_ulong sr[32];
1048     /* BATs */
1049     uint32_t nb_BATs;
1050     target_ulong DBAT[2][8];
1051     target_ulong IBAT[2][8];
1052     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1053     int32_t nb_tlb;      /* Total number of TLB                              */
1054     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1055     int nb_ways;     /* Number of ways in the TLB set                        */
1056     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1057     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1058     int nb_pids;     /* Number of available PID registers                    */
1059     int tlb_type;    /* Type of TLB we're dealing with                       */
1060     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1061     /* 403 dedicated access protection registers */
1062     target_ulong pb[4];
1063     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1064     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1065     uint32_t tlb_need_flush; /* Delayed flush needed */
1066 #define TLB_NEED_LOCAL_FLUSH   0x1
1067 #define TLB_NEED_GLOBAL_FLUSH  0x2
1068 #endif
1069
1070     /* Other registers */
1071     /* Special purpose registers */
1072     target_ulong spr[1024];
1073     ppc_spr_t spr_cb[1024];
1074     /* Altivec registers */
1075     ppc_avr_t avr[32];
1076     uint32_t vscr;
1077     /* VSX registers */
1078     uint64_t vsr[32];
1079     /* SPE registers */
1080     uint64_t spe_acc;
1081     uint32_t spe_fscr;
1082     /* SPE and Altivec can share a status since they will never be used
1083      * simultaneously */
1084     float_status vec_status;
1085
1086     /* Internal devices resources */
1087     /* Time base and decrementer */
1088     ppc_tb_t *tb_env;
1089     /* Device control registers */
1090     ppc_dcr_t *dcr_env;
1091
1092     int dcache_line_size;
1093     int icache_line_size;
1094
1095     /* Those resources are used during exception processing */
1096     /* CPU model definition */
1097     target_ulong msr_mask;
1098     powerpc_mmu_t mmu_model;
1099     powerpc_excp_t excp_model;
1100     powerpc_input_t bus_model;
1101     int bfd_mach;
1102     uint32_t flags;
1103     uint64_t insns_flags;
1104     uint64_t insns_flags2;
1105 #if defined(TARGET_PPC64)
1106     struct ppc_segment_page_sizes sps;
1107     ppc_slb_t vrma_slb;
1108     target_ulong rmls;
1109     bool ci_large_pages;
1110 #endif
1111
1112 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1113     uint64_t vpa_addr;
1114     uint64_t slb_shadow_addr, slb_shadow_size;
1115     uint64_t dtl_addr, dtl_size;
1116 #endif /* TARGET_PPC64 */
1117
1118     int error_code;
1119     uint32_t pending_interrupts;
1120 #if !defined(CONFIG_USER_ONLY)
1121     /* This is the IRQ controller, which is implementation dependent
1122      * and only relevant when emulating a complete machine.
1123      */
1124     uint32_t irq_input_state;
1125     void **irq_inputs;
1126     /* Exception vectors */
1127     target_ulong excp_vectors[POWERPC_EXCP_NB];
1128     target_ulong excp_prefix;
1129     target_ulong ivor_mask;
1130     target_ulong ivpr_mask;
1131     target_ulong hreset_vector;
1132     hwaddr mpic_iack;
1133     /* true when the external proxy facility mode is enabled */
1134     bool mpic_proxy;
1135     /* set when the processor has an HV mode, thus HV priv
1136      * instructions and SPRs are diallowed if MSR:HV is 0
1137      */
1138     bool has_hv_mode;
1139     /* On P7/P8, set when in PM state, we need to handle resume
1140      * in a special way (such as routing some resume causes to
1141      * 0x100), so flag this here.
1142      */
1143     bool in_pm_state;
1144 #endif
1145
1146     /* Those resources are used only during code translation */
1147     /* opcode handlers */
1148     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1149
1150     /* Those resources are used only in QEMU core */
1151     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1152     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1153     int immu_idx;         /* precomputed MMU index to speed up insn access */
1154     int dmmu_idx;         /* precomputed MMU index to speed up data accesses */
1155
1156     /* Power management */
1157     int (*check_pow)(CPUPPCState *env);
1158
1159 #if !defined(CONFIG_USER_ONLY)
1160     void *load_info;    /* Holds boot loading state.  */
1161 #endif
1162
1163     /* booke timers */
1164
1165     /* Specifies bit locations of the Time Base used to signal a fixed timer
1166      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1167      *
1168      * 0 selects the least significant bit.
1169      * 63 selects the most significant bit.
1170      */
1171     uint8_t fit_period[4];
1172     uint8_t wdt_period[4];
1173
1174     /* Transactional memory state */
1175     target_ulong tm_gpr[32];
1176     ppc_avr_t tm_vsr[64];
1177     uint64_t tm_cr;
1178     uint64_t tm_lr;
1179     uint64_t tm_ctr;
1180     uint64_t tm_fpscr;
1181     uint64_t tm_amr;
1182     uint64_t tm_ppr;
1183     uint64_t tm_vrsave;
1184     uint32_t tm_vscr;
1185     uint64_t tm_dscr;
1186     uint64_t tm_tar;
1187 };
1188
1189 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1190 do {                                            \
1191     env->fit_period[0] = (a_);                  \
1192     env->fit_period[1] = (b_);                  \
1193     env->fit_period[2] = (c_);                  \
1194     env->fit_period[3] = (d_);                  \
1195  } while (0)
1196
1197 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1198 do {                                            \
1199     env->wdt_period[0] = (a_);                  \
1200     env->wdt_period[1] = (b_);                  \
1201     env->wdt_period[2] = (c_);                  \
1202     env->wdt_period[3] = (d_);                  \
1203  } while (0)
1204
1205 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1206 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1207
1208 /**
1209  * PowerPCCPU:
1210  * @env: #CPUPPCState
1211  * @vcpu_id: vCPU identifier given to KVM
1212  * @compat_pvr: Current logical PVR, zero if in "raw" mode
1213  *
1214  * A PowerPC CPU.
1215  */
1216 struct PowerPCCPU {
1217     /*< private >*/
1218     CPUState parent_obj;
1219     /*< public >*/
1220
1221     CPUPPCState env;
1222     int vcpu_id;
1223     uint32_t compat_pvr;
1224     PPCVirtualHypervisor *vhyp;
1225     Object *intc;
1226     int32_t node_id; /* NUMA node this CPU belongs to */
1227
1228     /* Fields related to migration compatibility hacks */
1229     bool pre_2_8_migration;
1230     target_ulong mig_msr_mask;
1231     uint64_t mig_insns_flags;
1232     uint64_t mig_insns_flags2;
1233     uint32_t mig_nb_BATs;
1234     bool pre_2_10_migration;
1235 };
1236
1237 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1238 {
1239     return container_of(env, PowerPCCPU, env);
1240 }
1241
1242 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1243
1244 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1245
1246 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1247 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1248 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1249
1250 struct PPCVirtualHypervisor {
1251     Object parent;
1252 };
1253
1254 struct PPCVirtualHypervisorClass {
1255     InterfaceClass parent;
1256     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1257     hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1258     const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1259                                          hwaddr ptex, int n);
1260     void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1261                         const ppc_hash_pte64_t *hptes,
1262                         hwaddr ptex, int n);
1263     void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1264                        uint64_t pte0, uint64_t pte1);
1265     uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1266     target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1267 };
1268
1269 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1270 #define PPC_VIRTUAL_HYPERVISOR(obj)                 \
1271     OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1272 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass)         \
1273     OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1274                        TYPE_PPC_VIRTUAL_HYPERVISOR)
1275 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1276     OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1277                      TYPE_PPC_VIRTUAL_HYPERVISOR)
1278
1279 void ppc_cpu_do_interrupt(CPUState *cpu);
1280 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1281 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1282                         int flags);
1283 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1284                              fprintf_function cpu_fprintf, int flags);
1285 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1286 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1287 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1288 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1289 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1290 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1291                                int cpuid, void *opaque);
1292 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1293                                int cpuid, void *opaque);
1294 #ifndef CONFIG_USER_ONLY
1295 void ppc_cpu_do_system_reset(CPUState *cs);
1296 extern const struct VMStateDescription vmstate_ppc_cpu;
1297 #endif
1298
1299 /*****************************************************************************/
1300 void ppc_translate_init(void);
1301 /* you can call this signal handler from your SIGBUS and SIGSEGV
1302    signal handlers to inform the virtual CPU of exceptions. non zero
1303    is returned if the signal was handled by the virtual CPU.  */
1304 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1305                             void *puc);
1306 #if defined(CONFIG_USER_ONLY)
1307 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1308                              int mmu_idx);
1309 #endif
1310
1311 #if !defined(CONFIG_USER_ONLY)
1312 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1313 #endif /* !defined(CONFIG_USER_ONLY) */
1314 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1315
1316 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1317 #if defined(TARGET_PPC64)
1318 #endif
1319
1320 /* Time-base and decrementer management */
1321 #ifndef NO_CPU_IO_DEFS
1322 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1323 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1324 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1325 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1326 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1327 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1328 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1329 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1330 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1331 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1332 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1333 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1334 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1335 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1336 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1337 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1338 #if !defined(CONFIG_USER_ONLY)
1339 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1340 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1341 target_ulong load_40x_pit (CPUPPCState *env);
1342 void store_40x_pit (CPUPPCState *env, target_ulong val);
1343 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1344 void store_40x_sler (CPUPPCState *env, uint32_t val);
1345 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1346 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1347 void ppc_tlb_invalidate_all (CPUPPCState *env);
1348 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1349 void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1350 #endif
1351 #endif
1352
1353 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1354
1355 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1356 {
1357     uint64_t gprv;
1358
1359     gprv = env->gpr[gprn];
1360     if (env->flags & POWERPC_FLAG_SPE) {
1361         /* If the CPU implements the SPE extension, we have to get the
1362          * high bits of the GPR from the gprh storage area
1363          */
1364         gprv &= 0xFFFFFFFFULL;
1365         gprv |= (uint64_t)env->gprh[gprn] << 32;
1366     }
1367
1368     return gprv;
1369 }
1370
1371 /* Device control registers */
1372 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1373 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1374
1375 #define cpu_init(cpu_model) cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)
1376
1377 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1378 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1379
1380 #define cpu_signal_handler cpu_ppc_signal_handler
1381 #define cpu_list ppc_cpu_list
1382
1383 /* MMU modes definitions */
1384 #define MMU_USER_IDX 0
1385 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1386 {
1387     return ifetch ? env->immu_idx : env->dmmu_idx;
1388 }
1389
1390 /* Compatibility modes */
1391 #if defined(TARGET_PPC64)
1392 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1393                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1394 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1395 #if !defined(CONFIG_USER_ONLY)
1396 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1397 #endif
1398 int ppc_compat_max_threads(PowerPCCPU *cpu);
1399 void ppc_compat_add_property(Object *obj, const char *name,
1400                              uint32_t *compat_pvr, const char *basedesc,
1401                              Error **errp);
1402 #endif /* defined(TARGET_PPC64) */
1403
1404 #include "exec/cpu-all.h"
1405
1406 /*****************************************************************************/
1407 /* CRF definitions */
1408 #define CRF_LT_BIT    3
1409 #define CRF_GT_BIT    2
1410 #define CRF_EQ_BIT    1
1411 #define CRF_SO_BIT    0
1412 #define CRF_LT        (1 << CRF_LT_BIT)
1413 #define CRF_GT        (1 << CRF_GT_BIT)
1414 #define CRF_EQ        (1 << CRF_EQ_BIT)
1415 #define CRF_SO        (1 << CRF_SO_BIT)
1416 /* For SPE extensions */
1417 #define CRF_CH        (1 << CRF_LT_BIT)
1418 #define CRF_CL        (1 << CRF_GT_BIT)
1419 #define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1420 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1421
1422 /* XER definitions */
1423 #define XER_SO  31
1424 #define XER_OV  30
1425 #define XER_CA  29
1426 #define XER_OV32  19
1427 #define XER_CA32  18
1428 #define XER_CMP  8
1429 #define XER_BC   0
1430 #define xer_so  (env->so)
1431 #define xer_ov  (env->ov)
1432 #define xer_ca  (env->ca)
1433 #define xer_ov32  (env->ov)
1434 #define xer_ca32  (env->ca)
1435 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1436 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1437
1438 /* SPR definitions */
1439 #define SPR_MQ                (0x000)
1440 #define SPR_XER               (0x001)
1441 #define SPR_601_VRTCU         (0x004)
1442 #define SPR_601_VRTCL         (0x005)
1443 #define SPR_601_UDECR         (0x006)
1444 #define SPR_LR                (0x008)
1445 #define SPR_CTR               (0x009)
1446 #define SPR_UAMR              (0x00D)
1447 #define SPR_DSCR              (0x011)
1448 #define SPR_DSISR             (0x012)
1449 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1450 #define SPR_601_RTCU          (0x014)
1451 #define SPR_601_RTCL          (0x015)
1452 #define SPR_DECR              (0x016)
1453 #define SPR_SDR1              (0x019)
1454 #define SPR_SRR0              (0x01A)
1455 #define SPR_SRR1              (0x01B)
1456 #define SPR_CFAR              (0x01C)
1457 #define SPR_AMR               (0x01D)
1458 #define SPR_ACOP              (0x01F)
1459 #define SPR_BOOKE_PID         (0x030)
1460 #define SPR_BOOKS_PID         (0x030)
1461 #define SPR_BOOKE_DECAR       (0x036)
1462 #define SPR_BOOKE_CSRR0       (0x03A)
1463 #define SPR_BOOKE_CSRR1       (0x03B)
1464 #define SPR_BOOKE_DEAR        (0x03D)
1465 #define SPR_IAMR              (0x03D)
1466 #define SPR_BOOKE_ESR         (0x03E)
1467 #define SPR_BOOKE_IVPR        (0x03F)
1468 #define SPR_MPC_EIE           (0x050)
1469 #define SPR_MPC_EID           (0x051)
1470 #define SPR_MPC_NRI           (0x052)
1471 #define SPR_TFHAR             (0x080)
1472 #define SPR_TFIAR             (0x081)
1473 #define SPR_TEXASR            (0x082)
1474 #define SPR_TEXASRU           (0x083)
1475 #define SPR_UCTRL             (0x088)
1476 #define SPR_TIDR              (0x090)
1477 #define SPR_MPC_CMPA          (0x090)
1478 #define SPR_MPC_CMPB          (0x091)
1479 #define SPR_MPC_CMPC          (0x092)
1480 #define SPR_MPC_CMPD          (0x093)
1481 #define SPR_MPC_ECR           (0x094)
1482 #define SPR_MPC_DER           (0x095)
1483 #define SPR_MPC_COUNTA        (0x096)
1484 #define SPR_MPC_COUNTB        (0x097)
1485 #define SPR_CTRL              (0x098)
1486 #define SPR_MPC_CMPE          (0x098)
1487 #define SPR_MPC_CMPF          (0x099)
1488 #define SPR_FSCR              (0x099)
1489 #define SPR_MPC_CMPG          (0x09A)
1490 #define SPR_MPC_CMPH          (0x09B)
1491 #define SPR_MPC_LCTRL1        (0x09C)
1492 #define SPR_MPC_LCTRL2        (0x09D)
1493 #define SPR_UAMOR             (0x09D)
1494 #define SPR_MPC_ICTRL         (0x09E)
1495 #define SPR_MPC_BAR           (0x09F)
1496 #define SPR_PSPB              (0x09F)
1497 #define SPR_DAWR              (0x0B4)
1498 #define SPR_RPR               (0x0BA)
1499 #define SPR_CIABR             (0x0BB)
1500 #define SPR_DAWRX             (0x0BC)
1501 #define SPR_HFSCR             (0x0BE)
1502 #define SPR_VRSAVE            (0x100)
1503 #define SPR_USPRG0            (0x100)
1504 #define SPR_USPRG1            (0x101)
1505 #define SPR_USPRG2            (0x102)
1506 #define SPR_USPRG3            (0x103)
1507 #define SPR_USPRG4            (0x104)
1508 #define SPR_USPRG5            (0x105)
1509 #define SPR_USPRG6            (0x106)
1510 #define SPR_USPRG7            (0x107)
1511 #define SPR_VTBL              (0x10C)
1512 #define SPR_VTBU              (0x10D)
1513 #define SPR_SPRG0             (0x110)
1514 #define SPR_SPRG1             (0x111)
1515 #define SPR_SPRG2             (0x112)
1516 #define SPR_SPRG3             (0x113)
1517 #define SPR_SPRG4             (0x114)
1518 #define SPR_SCOMC             (0x114)
1519 #define SPR_SPRG5             (0x115)
1520 #define SPR_SCOMD             (0x115)
1521 #define SPR_SPRG6             (0x116)
1522 #define SPR_SPRG7             (0x117)
1523 #define SPR_ASR               (0x118)
1524 #define SPR_EAR               (0x11A)
1525 #define SPR_TBL               (0x11C)
1526 #define SPR_TBU               (0x11D)
1527 #define SPR_TBU40             (0x11E)
1528 #define SPR_SVR               (0x11E)
1529 #define SPR_BOOKE_PIR         (0x11E)
1530 #define SPR_PVR               (0x11F)
1531 #define SPR_HSPRG0            (0x130)
1532 #define SPR_BOOKE_DBSR        (0x130)
1533 #define SPR_HSPRG1            (0x131)
1534 #define SPR_HDSISR            (0x132)
1535 #define SPR_HDAR              (0x133)
1536 #define SPR_BOOKE_EPCR        (0x133)
1537 #define SPR_SPURR             (0x134)
1538 #define SPR_BOOKE_DBCR0       (0x134)
1539 #define SPR_IBCR              (0x135)
1540 #define SPR_PURR              (0x135)
1541 #define SPR_BOOKE_DBCR1       (0x135)
1542 #define SPR_DBCR              (0x136)
1543 #define SPR_HDEC              (0x136)
1544 #define SPR_BOOKE_DBCR2       (0x136)
1545 #define SPR_HIOR              (0x137)
1546 #define SPR_MBAR              (0x137)
1547 #define SPR_RMOR              (0x138)
1548 #define SPR_BOOKE_IAC1        (0x138)
1549 #define SPR_HRMOR             (0x139)
1550 #define SPR_BOOKE_IAC2        (0x139)
1551 #define SPR_HSRR0             (0x13A)
1552 #define SPR_BOOKE_IAC3        (0x13A)
1553 #define SPR_HSRR1             (0x13B)
1554 #define SPR_BOOKE_IAC4        (0x13B)
1555 #define SPR_BOOKE_DAC1        (0x13C)
1556 #define SPR_MMCRH             (0x13C)
1557 #define SPR_DABR2             (0x13D)
1558 #define SPR_BOOKE_DAC2        (0x13D)
1559 #define SPR_TFMR              (0x13D)
1560 #define SPR_BOOKE_DVC1        (0x13E)
1561 #define SPR_LPCR              (0x13E)
1562 #define SPR_BOOKE_DVC2        (0x13F)
1563 #define SPR_LPIDR             (0x13F)
1564 #define SPR_BOOKE_TSR         (0x150)
1565 #define SPR_HMER              (0x150)
1566 #define SPR_HMEER             (0x151)
1567 #define SPR_PCR               (0x152)
1568 #define SPR_BOOKE_LPIDR       (0x152)
1569 #define SPR_BOOKE_TCR         (0x154)
1570 #define SPR_BOOKE_TLB0PS      (0x158)
1571 #define SPR_BOOKE_TLB1PS      (0x159)
1572 #define SPR_BOOKE_TLB2PS      (0x15A)
1573 #define SPR_BOOKE_TLB3PS      (0x15B)
1574 #define SPR_AMOR              (0x15D)
1575 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1576 #define SPR_BOOKE_IVOR0       (0x190)
1577 #define SPR_BOOKE_IVOR1       (0x191)
1578 #define SPR_BOOKE_IVOR2       (0x192)
1579 #define SPR_BOOKE_IVOR3       (0x193)
1580 #define SPR_BOOKE_IVOR4       (0x194)
1581 #define SPR_BOOKE_IVOR5       (0x195)
1582 #define SPR_BOOKE_IVOR6       (0x196)
1583 #define SPR_BOOKE_IVOR7       (0x197)
1584 #define SPR_BOOKE_IVOR8       (0x198)
1585 #define SPR_BOOKE_IVOR9       (0x199)
1586 #define SPR_BOOKE_IVOR10      (0x19A)
1587 #define SPR_BOOKE_IVOR11      (0x19B)
1588 #define SPR_BOOKE_IVOR12      (0x19C)
1589 #define SPR_BOOKE_IVOR13      (0x19D)
1590 #define SPR_BOOKE_IVOR14      (0x19E)
1591 #define SPR_BOOKE_IVOR15      (0x19F)
1592 #define SPR_BOOKE_IVOR38      (0x1B0)
1593 #define SPR_BOOKE_IVOR39      (0x1B1)
1594 #define SPR_BOOKE_IVOR40      (0x1B2)
1595 #define SPR_BOOKE_IVOR41      (0x1B3)
1596 #define SPR_BOOKE_IVOR42      (0x1B4)
1597 #define SPR_BOOKE_GIVOR2      (0x1B8)
1598 #define SPR_BOOKE_GIVOR3      (0x1B9)
1599 #define SPR_BOOKE_GIVOR4      (0x1BA)
1600 #define SPR_BOOKE_GIVOR8      (0x1BB)
1601 #define SPR_BOOKE_GIVOR13     (0x1BC)
1602 #define SPR_BOOKE_GIVOR14     (0x1BD)
1603 #define SPR_TIR               (0x1BE)
1604 #define SPR_BOOKE_SPEFSCR     (0x200)
1605 #define SPR_Exxx_BBEAR        (0x201)
1606 #define SPR_Exxx_BBTAR        (0x202)
1607 #define SPR_Exxx_L1CFG0       (0x203)
1608 #define SPR_Exxx_L1CFG1       (0x204)
1609 #define SPR_Exxx_NPIDR        (0x205)
1610 #define SPR_ATBL              (0x20E)
1611 #define SPR_ATBU              (0x20F)
1612 #define SPR_IBAT0U            (0x210)
1613 #define SPR_BOOKE_IVOR32      (0x210)
1614 #define SPR_RCPU_MI_GRA       (0x210)
1615 #define SPR_IBAT0L            (0x211)
1616 #define SPR_BOOKE_IVOR33      (0x211)
1617 #define SPR_IBAT1U            (0x212)
1618 #define SPR_BOOKE_IVOR34      (0x212)
1619 #define SPR_IBAT1L            (0x213)
1620 #define SPR_BOOKE_IVOR35      (0x213)
1621 #define SPR_IBAT2U            (0x214)
1622 #define SPR_BOOKE_IVOR36      (0x214)
1623 #define SPR_IBAT2L            (0x215)
1624 #define SPR_BOOKE_IVOR37      (0x215)
1625 #define SPR_IBAT3U            (0x216)
1626 #define SPR_IBAT3L            (0x217)
1627 #define SPR_DBAT0U            (0x218)
1628 #define SPR_RCPU_L2U_GRA      (0x218)
1629 #define SPR_DBAT0L            (0x219)
1630 #define SPR_DBAT1U            (0x21A)
1631 #define SPR_DBAT1L            (0x21B)
1632 #define SPR_DBAT2U            (0x21C)
1633 #define SPR_DBAT2L            (0x21D)
1634 #define SPR_DBAT3U            (0x21E)
1635 #define SPR_DBAT3L            (0x21F)
1636 #define SPR_IBAT4U            (0x230)
1637 #define SPR_RPCU_BBCMCR       (0x230)
1638 #define SPR_MPC_IC_CST        (0x230)
1639 #define SPR_Exxx_CTXCR        (0x230)
1640 #define SPR_IBAT4L            (0x231)
1641 #define SPR_MPC_IC_ADR        (0x231)
1642 #define SPR_Exxx_DBCR3        (0x231)
1643 #define SPR_IBAT5U            (0x232)
1644 #define SPR_MPC_IC_DAT        (0x232)
1645 #define SPR_Exxx_DBCNT        (0x232)
1646 #define SPR_IBAT5L            (0x233)
1647 #define SPR_IBAT6U            (0x234)
1648 #define SPR_IBAT6L            (0x235)
1649 #define SPR_IBAT7U            (0x236)
1650 #define SPR_IBAT7L            (0x237)
1651 #define SPR_DBAT4U            (0x238)
1652 #define SPR_RCPU_L2U_MCR      (0x238)
1653 #define SPR_MPC_DC_CST        (0x238)
1654 #define SPR_Exxx_ALTCTXCR     (0x238)
1655 #define SPR_DBAT4L            (0x239)
1656 #define SPR_MPC_DC_ADR        (0x239)
1657 #define SPR_DBAT5U            (0x23A)
1658 #define SPR_BOOKE_MCSRR0      (0x23A)
1659 #define SPR_MPC_DC_DAT        (0x23A)
1660 #define SPR_DBAT5L            (0x23B)
1661 #define SPR_BOOKE_MCSRR1      (0x23B)
1662 #define SPR_DBAT6U            (0x23C)
1663 #define SPR_BOOKE_MCSR        (0x23C)
1664 #define SPR_DBAT6L            (0x23D)
1665 #define SPR_Exxx_MCAR         (0x23D)
1666 #define SPR_DBAT7U            (0x23E)
1667 #define SPR_BOOKE_DSRR0       (0x23E)
1668 #define SPR_DBAT7L            (0x23F)
1669 #define SPR_BOOKE_DSRR1       (0x23F)
1670 #define SPR_BOOKE_SPRG8       (0x25C)
1671 #define SPR_BOOKE_SPRG9       (0x25D)
1672 #define SPR_BOOKE_MAS0        (0x270)
1673 #define SPR_BOOKE_MAS1        (0x271)
1674 #define SPR_BOOKE_MAS2        (0x272)
1675 #define SPR_BOOKE_MAS3        (0x273)
1676 #define SPR_BOOKE_MAS4        (0x274)
1677 #define SPR_BOOKE_MAS5        (0x275)
1678 #define SPR_BOOKE_MAS6        (0x276)
1679 #define SPR_BOOKE_PID1        (0x279)
1680 #define SPR_BOOKE_PID2        (0x27A)
1681 #define SPR_MPC_DPDR          (0x280)
1682 #define SPR_MPC_IMMR          (0x288)
1683 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1684 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1685 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1686 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1687 #define SPR_BOOKE_EPR         (0x2BE)
1688 #define SPR_PERF0             (0x300)
1689 #define SPR_RCPU_MI_RBA0      (0x300)
1690 #define SPR_MPC_MI_CTR        (0x300)
1691 #define SPR_POWER_USIER       (0x300)
1692 #define SPR_PERF1             (0x301)
1693 #define SPR_RCPU_MI_RBA1      (0x301)
1694 #define SPR_POWER_UMMCR2      (0x301)
1695 #define SPR_PERF2             (0x302)
1696 #define SPR_RCPU_MI_RBA2      (0x302)
1697 #define SPR_MPC_MI_AP         (0x302)
1698 #define SPR_POWER_UMMCRA      (0x302)
1699 #define SPR_PERF3             (0x303)
1700 #define SPR_RCPU_MI_RBA3      (0x303)
1701 #define SPR_MPC_MI_EPN        (0x303)
1702 #define SPR_POWER_UPMC1       (0x303)
1703 #define SPR_PERF4             (0x304)
1704 #define SPR_POWER_UPMC2       (0x304)
1705 #define SPR_PERF5             (0x305)
1706 #define SPR_MPC_MI_TWC        (0x305)
1707 #define SPR_POWER_UPMC3       (0x305)
1708 #define SPR_PERF6             (0x306)
1709 #define SPR_MPC_MI_RPN        (0x306)
1710 #define SPR_POWER_UPMC4       (0x306)
1711 #define SPR_PERF7             (0x307)
1712 #define SPR_POWER_UPMC5       (0x307)
1713 #define SPR_PERF8             (0x308)
1714 #define SPR_RCPU_L2U_RBA0     (0x308)
1715 #define SPR_MPC_MD_CTR        (0x308)
1716 #define SPR_POWER_UPMC6       (0x308)
1717 #define SPR_PERF9             (0x309)
1718 #define SPR_RCPU_L2U_RBA1     (0x309)
1719 #define SPR_MPC_MD_CASID      (0x309)
1720 #define SPR_970_UPMC7         (0X309)
1721 #define SPR_PERFA             (0x30A)
1722 #define SPR_RCPU_L2U_RBA2     (0x30A)
1723 #define SPR_MPC_MD_AP         (0x30A)
1724 #define SPR_970_UPMC8         (0X30A)
1725 #define SPR_PERFB             (0x30B)
1726 #define SPR_RCPU_L2U_RBA3     (0x30B)
1727 #define SPR_MPC_MD_EPN        (0x30B)
1728 #define SPR_POWER_UMMCR0      (0X30B)
1729 #define SPR_PERFC             (0x30C)
1730 #define SPR_MPC_MD_TWB        (0x30C)
1731 #define SPR_POWER_USIAR       (0X30C)
1732 #define SPR_PERFD             (0x30D)
1733 #define SPR_MPC_MD_TWC        (0x30D)
1734 #define SPR_POWER_USDAR       (0X30D)
1735 #define SPR_PERFE             (0x30E)
1736 #define SPR_MPC_MD_RPN        (0x30E)
1737 #define SPR_POWER_UMMCR1      (0X30E)
1738 #define SPR_PERFF             (0x30F)
1739 #define SPR_MPC_MD_TW         (0x30F)
1740 #define SPR_UPERF0            (0x310)
1741 #define SPR_POWER_SIER        (0x310)
1742 #define SPR_UPERF1            (0x311)
1743 #define SPR_POWER_MMCR2       (0x311)
1744 #define SPR_UPERF2            (0x312)
1745 #define SPR_POWER_MMCRA       (0X312)
1746 #define SPR_UPERF3            (0x313)
1747 #define SPR_POWER_PMC1        (0X313)
1748 #define SPR_UPERF4            (0x314)
1749 #define SPR_POWER_PMC2        (0X314)
1750 #define SPR_UPERF5            (0x315)
1751 #define SPR_POWER_PMC3        (0X315)
1752 #define SPR_UPERF6            (0x316)
1753 #define SPR_POWER_PMC4        (0X316)
1754 #define SPR_UPERF7            (0x317)
1755 #define SPR_POWER_PMC5        (0X317)
1756 #define SPR_UPERF8            (0x318)
1757 #define SPR_POWER_PMC6        (0X318)
1758 #define SPR_UPERF9            (0x319)
1759 #define SPR_970_PMC7          (0X319)
1760 #define SPR_UPERFA            (0x31A)
1761 #define SPR_970_PMC8          (0X31A)
1762 #define SPR_UPERFB            (0x31B)
1763 #define SPR_POWER_MMCR0       (0X31B)
1764 #define SPR_UPERFC            (0x31C)
1765 #define SPR_POWER_SIAR        (0X31C)
1766 #define SPR_UPERFD            (0x31D)
1767 #define SPR_POWER_SDAR        (0X31D)
1768 #define SPR_UPERFE            (0x31E)
1769 #define SPR_POWER_MMCR1       (0X31E)
1770 #define SPR_UPERFF            (0x31F)
1771 #define SPR_RCPU_MI_RA0       (0x320)
1772 #define SPR_MPC_MI_DBCAM      (0x320)
1773 #define SPR_BESCRS            (0x320)
1774 #define SPR_RCPU_MI_RA1       (0x321)
1775 #define SPR_MPC_MI_DBRAM0     (0x321)
1776 #define SPR_BESCRSU           (0x321)
1777 #define SPR_RCPU_MI_RA2       (0x322)
1778 #define SPR_MPC_MI_DBRAM1     (0x322)
1779 #define SPR_BESCRR            (0x322)
1780 #define SPR_RCPU_MI_RA3       (0x323)
1781 #define SPR_BESCRRU           (0x323)
1782 #define SPR_EBBHR             (0x324)
1783 #define SPR_EBBRR             (0x325)
1784 #define SPR_BESCR             (0x326)
1785 #define SPR_RCPU_L2U_RA0      (0x328)
1786 #define SPR_MPC_MD_DBCAM      (0x328)
1787 #define SPR_RCPU_L2U_RA1      (0x329)
1788 #define SPR_MPC_MD_DBRAM0     (0x329)
1789 #define SPR_RCPU_L2U_RA2      (0x32A)
1790 #define SPR_MPC_MD_DBRAM1     (0x32A)
1791 #define SPR_RCPU_L2U_RA3      (0x32B)
1792 #define SPR_TAR               (0x32F)
1793 #define SPR_IC                (0x350)
1794 #define SPR_VTB               (0x351)
1795 #define SPR_MMCRC             (0x353)
1796 #define SPR_PSSCR             (0x357)
1797 #define SPR_440_INV0          (0x370)
1798 #define SPR_440_INV1          (0x371)
1799 #define SPR_440_INV2          (0x372)
1800 #define SPR_440_INV3          (0x373)
1801 #define SPR_440_ITV0          (0x374)
1802 #define SPR_440_ITV1          (0x375)
1803 #define SPR_440_ITV2          (0x376)
1804 #define SPR_440_ITV3          (0x377)
1805 #define SPR_440_CCR1          (0x378)
1806 #define SPR_TACR              (0x378)
1807 #define SPR_TCSCR             (0x379)
1808 #define SPR_CSIGR             (0x37a)
1809 #define SPR_DCRIPR            (0x37B)
1810 #define SPR_POWER_SPMC1       (0x37C)
1811 #define SPR_POWER_SPMC2       (0x37D)
1812 #define SPR_POWER_MMCRS       (0x37E)
1813 #define SPR_WORT              (0x37F)
1814 #define SPR_PPR               (0x380)
1815 #define SPR_750_GQR0          (0x390)
1816 #define SPR_440_DNV0          (0x390)
1817 #define SPR_750_GQR1          (0x391)
1818 #define SPR_440_DNV1          (0x391)
1819 #define SPR_750_GQR2          (0x392)
1820 #define SPR_440_DNV2          (0x392)
1821 #define SPR_750_GQR3          (0x393)
1822 #define SPR_440_DNV3          (0x393)
1823 #define SPR_750_GQR4          (0x394)
1824 #define SPR_440_DTV0          (0x394)
1825 #define SPR_750_GQR5          (0x395)
1826 #define SPR_440_DTV1          (0x395)
1827 #define SPR_750_GQR6          (0x396)
1828 #define SPR_440_DTV2          (0x396)
1829 #define SPR_750_GQR7          (0x397)
1830 #define SPR_440_DTV3          (0x397)
1831 #define SPR_750_THRM4         (0x398)
1832 #define SPR_750CL_HID2        (0x398)
1833 #define SPR_440_DVLIM         (0x398)
1834 #define SPR_750_WPAR          (0x399)
1835 #define SPR_440_IVLIM         (0x399)
1836 #define SPR_TSCR              (0x399)
1837 #define SPR_750_DMAU          (0x39A)
1838 #define SPR_750_DMAL          (0x39B)
1839 #define SPR_440_RSTCFG        (0x39B)
1840 #define SPR_BOOKE_DCDBTRL     (0x39C)
1841 #define SPR_BOOKE_DCDBTRH     (0x39D)
1842 #define SPR_BOOKE_ICDBTRL     (0x39E)
1843 #define SPR_BOOKE_ICDBTRH     (0x39F)
1844 #define SPR_74XX_UMMCR2       (0x3A0)
1845 #define SPR_7XX_UPMC5         (0x3A1)
1846 #define SPR_7XX_UPMC6         (0x3A2)
1847 #define SPR_UBAMR             (0x3A7)
1848 #define SPR_7XX_UMMCR0        (0x3A8)
1849 #define SPR_7XX_UPMC1         (0x3A9)
1850 #define SPR_7XX_UPMC2         (0x3AA)
1851 #define SPR_7XX_USIAR         (0x3AB)
1852 #define SPR_7XX_UMMCR1        (0x3AC)
1853 #define SPR_7XX_UPMC3         (0x3AD)
1854 #define SPR_7XX_UPMC4         (0x3AE)
1855 #define SPR_USDA              (0x3AF)
1856 #define SPR_40x_ZPR           (0x3B0)
1857 #define SPR_BOOKE_MAS7        (0x3B0)
1858 #define SPR_74XX_MMCR2        (0x3B0)
1859 #define SPR_7XX_PMC5          (0x3B1)
1860 #define SPR_40x_PID           (0x3B1)
1861 #define SPR_7XX_PMC6          (0x3B2)
1862 #define SPR_440_MMUCR         (0x3B2)
1863 #define SPR_4xx_CCR0          (0x3B3)
1864 #define SPR_BOOKE_EPLC        (0x3B3)
1865 #define SPR_405_IAC3          (0x3B4)
1866 #define SPR_BOOKE_EPSC        (0x3B4)
1867 #define SPR_405_IAC4          (0x3B5)
1868 #define SPR_405_DVC1          (0x3B6)
1869 #define SPR_405_DVC2          (0x3B7)
1870 #define SPR_BAMR              (0x3B7)
1871 #define SPR_7XX_MMCR0         (0x3B8)
1872 #define SPR_7XX_PMC1          (0x3B9)
1873 #define SPR_40x_SGR           (0x3B9)
1874 #define SPR_7XX_PMC2          (0x3BA)
1875 #define SPR_40x_DCWR          (0x3BA)
1876 #define SPR_7XX_SIAR          (0x3BB)
1877 #define SPR_405_SLER          (0x3BB)
1878 #define SPR_7XX_MMCR1         (0x3BC)
1879 #define SPR_405_SU0R          (0x3BC)
1880 #define SPR_401_SKR           (0x3BC)
1881 #define SPR_7XX_PMC3          (0x3BD)
1882 #define SPR_405_DBCR1         (0x3BD)
1883 #define SPR_7XX_PMC4          (0x3BE)
1884 #define SPR_SDA               (0x3BF)
1885 #define SPR_403_VTBL          (0x3CC)
1886 #define SPR_403_VTBU          (0x3CD)
1887 #define SPR_DMISS             (0x3D0)
1888 #define SPR_DCMP              (0x3D1)
1889 #define SPR_HASH1             (0x3D2)
1890 #define SPR_HASH2             (0x3D3)
1891 #define SPR_BOOKE_ICDBDR      (0x3D3)
1892 #define SPR_TLBMISS           (0x3D4)
1893 #define SPR_IMISS             (0x3D4)
1894 #define SPR_40x_ESR           (0x3D4)
1895 #define SPR_PTEHI             (0x3D5)
1896 #define SPR_ICMP              (0x3D5)
1897 #define SPR_40x_DEAR          (0x3D5)
1898 #define SPR_PTELO             (0x3D6)
1899 #define SPR_RPA               (0x3D6)
1900 #define SPR_40x_EVPR          (0x3D6)
1901 #define SPR_L3PM              (0x3D7)
1902 #define SPR_403_CDBCR         (0x3D7)
1903 #define SPR_L3ITCR0           (0x3D8)
1904 #define SPR_TCR               (0x3D8)
1905 #define SPR_40x_TSR           (0x3D8)
1906 #define SPR_IBR               (0x3DA)
1907 #define SPR_40x_TCR           (0x3DA)
1908 #define SPR_ESASRR            (0x3DB)
1909 #define SPR_40x_PIT           (0x3DB)
1910 #define SPR_403_TBL           (0x3DC)
1911 #define SPR_403_TBU           (0x3DD)
1912 #define SPR_SEBR              (0x3DE)
1913 #define SPR_40x_SRR2          (0x3DE)
1914 #define SPR_SER               (0x3DF)
1915 #define SPR_40x_SRR3          (0x3DF)
1916 #define SPR_L3OHCR            (0x3E8)
1917 #define SPR_L3ITCR1           (0x3E9)
1918 #define SPR_L3ITCR2           (0x3EA)
1919 #define SPR_L3ITCR3           (0x3EB)
1920 #define SPR_HID0              (0x3F0)
1921 #define SPR_40x_DBSR          (0x3F0)
1922 #define SPR_HID1              (0x3F1)
1923 #define SPR_IABR              (0x3F2)
1924 #define SPR_40x_DBCR0         (0x3F2)
1925 #define SPR_601_HID2          (0x3F2)
1926 #define SPR_Exxx_L1CSR0       (0x3F2)
1927 #define SPR_ICTRL             (0x3F3)
1928 #define SPR_HID2              (0x3F3)
1929 #define SPR_750CL_HID4        (0x3F3)
1930 #define SPR_Exxx_L1CSR1       (0x3F3)
1931 #define SPR_440_DBDR          (0x3F3)
1932 #define SPR_LDSTDB            (0x3F4)
1933 #define SPR_750_TDCL          (0x3F4)
1934 #define SPR_40x_IAC1          (0x3F4)
1935 #define SPR_MMUCSR0           (0x3F4)
1936 #define SPR_970_HID4          (0x3F4)
1937 #define SPR_DABR              (0x3F5)
1938 #define DABR_MASK (~(target_ulong)0x7)
1939 #define SPR_Exxx_BUCSR        (0x3F5)
1940 #define SPR_40x_IAC2          (0x3F5)
1941 #define SPR_601_HID5          (0x3F5)
1942 #define SPR_40x_DAC1          (0x3F6)
1943 #define SPR_MSSCR0            (0x3F6)
1944 #define SPR_970_HID5          (0x3F6)
1945 #define SPR_MSSSR0            (0x3F7)
1946 #define SPR_MSSCR1            (0x3F7)
1947 #define SPR_DABRX             (0x3F7)
1948 #define SPR_40x_DAC2          (0x3F7)
1949 #define SPR_MMUCFG            (0x3F7)
1950 #define SPR_LDSTCR            (0x3F8)
1951 #define SPR_L2PMCR            (0x3F8)
1952 #define SPR_750FX_HID2        (0x3F8)
1953 #define SPR_Exxx_L1FINV0      (0x3F8)
1954 #define SPR_L2CR              (0x3F9)
1955 #define SPR_L3CR              (0x3FA)
1956 #define SPR_750_TDCH          (0x3FA)
1957 #define SPR_IABR2             (0x3FA)
1958 #define SPR_40x_DCCR          (0x3FA)
1959 #define SPR_ICTC              (0x3FB)
1960 #define SPR_40x_ICCR          (0x3FB)
1961 #define SPR_THRM1             (0x3FC)
1962 #define SPR_403_PBL1          (0x3FC)
1963 #define SPR_SP                (0x3FD)
1964 #define SPR_THRM2             (0x3FD)
1965 #define SPR_403_PBU1          (0x3FD)
1966 #define SPR_604_HID13         (0x3FD)
1967 #define SPR_LT                (0x3FE)
1968 #define SPR_THRM3             (0x3FE)
1969 #define SPR_RCPU_FPECR        (0x3FE)
1970 #define SPR_403_PBL2          (0x3FE)
1971 #define SPR_PIR               (0x3FF)
1972 #define SPR_403_PBU2          (0x3FF)
1973 #define SPR_601_HID15         (0x3FF)
1974 #define SPR_604_HID15         (0x3FF)
1975 #define SPR_E500_SVR          (0x3FF)
1976
1977 /* Disable MAS Interrupt Updates for Hypervisor */
1978 #define EPCR_DMIUH            (1 << 22)
1979 /* Disable Guest TLB Management Instructions */
1980 #define EPCR_DGTMI            (1 << 23)
1981 /* Guest Interrupt Computation Mode */
1982 #define EPCR_GICM             (1 << 24)
1983 /* Interrupt Computation Mode */
1984 #define EPCR_ICM              (1 << 25)
1985 /* Disable Embedded Hypervisor Debug */
1986 #define EPCR_DUVD             (1 << 26)
1987 /* Instruction Storage Interrupt Directed to Guest State */
1988 #define EPCR_ISIGS            (1 << 27)
1989 /* Data Storage Interrupt Directed to Guest State */
1990 #define EPCR_DSIGS            (1 << 28)
1991 /* Instruction TLB Error Interrupt Directed to Guest State */
1992 #define EPCR_ITLBGS           (1 << 29)
1993 /* Data TLB Error Interrupt Directed to Guest State */
1994 #define EPCR_DTLBGS           (1 << 30)
1995 /* External Input Interrupt Directed to Guest State */
1996 #define EPCR_EXTGS            (1 << 31)
1997
1998 #define   L1CSR0_CPE            0x00010000      /* Data Cache Parity Enable */
1999 #define   L1CSR0_CUL            0x00000400      /* (D-)Cache Unable to Lock */
2000 #define   L1CSR0_DCLFR          0x00000100      /* D-Cache Lock Flash Reset */
2001 #define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
2002 #define   L1CSR0_DCE            0x00000001      /* Data Cache Enable */
2003
2004 #define   L1CSR1_CPE            0x00010000      /* Instruction Cache Parity Enable */
2005 #define   L1CSR1_ICUL           0x00000400      /* I-Cache Unable to Lock */
2006 #define   L1CSR1_ICLFR          0x00000100      /* I-Cache Lock Flash Reset */
2007 #define   L1CSR1_ICFI           0x00000002      /* Instruction Cache Flash Invalidate */
2008 #define   L1CSR1_ICE            0x00000001      /* Instruction Cache Enable */
2009
2010 /* HID0 bits */
2011 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
2012 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
2013 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
2014 #define HID0_HILE           PPC_BIT(19) /* POWER8 */
2015
2016 /*****************************************************************************/
2017 /* PowerPC Instructions types definitions                                    */
2018 enum {
2019     PPC_NONE           = 0x0000000000000000ULL,
2020     /* PowerPC base instructions set                                         */
2021     PPC_INSNS_BASE     = 0x0000000000000001ULL,
2022     /*   integer operations instructions                                     */
2023 #define PPC_INTEGER PPC_INSNS_BASE
2024     /*   flow control instructions                                           */
2025 #define PPC_FLOW    PPC_INSNS_BASE
2026     /*   virtual memory instructions                                         */
2027 #define PPC_MEM     PPC_INSNS_BASE
2028     /*   ld/st with reservation instructions                                 */
2029 #define PPC_RES     PPC_INSNS_BASE
2030     /*   spr/msr access instructions                                         */
2031 #define PPC_MISC    PPC_INSNS_BASE
2032     /* Deprecated instruction sets                                           */
2033     /*   Original POWER instruction set                                      */
2034     PPC_POWER          = 0x0000000000000002ULL,
2035     /*   POWER2 instruction set extension                                    */
2036     PPC_POWER2         = 0x0000000000000004ULL,
2037     /*   Power RTC support                                                   */
2038     PPC_POWER_RTC      = 0x0000000000000008ULL,
2039     /*   Power-to-PowerPC bridge (601)                                       */
2040     PPC_POWER_BR       = 0x0000000000000010ULL,
2041     /* 64 bits PowerPC instruction set                                       */
2042     PPC_64B            = 0x0000000000000020ULL,
2043     /*   New 64 bits extensions (PowerPC 2.0x)                               */
2044     PPC_64BX           = 0x0000000000000040ULL,
2045     /*   64 bits hypervisor extensions                                       */
2046     PPC_64H            = 0x0000000000000080ULL,
2047     /*   New wait instruction (PowerPC 2.0x)                                 */
2048     PPC_WAIT           = 0x0000000000000100ULL,
2049     /*   Time base mftb instruction                                          */
2050     PPC_MFTB           = 0x0000000000000200ULL,
2051
2052     /* Fixed-point unit extensions                                           */
2053     /*   PowerPC 602 specific                                                */
2054     PPC_602_SPEC       = 0x0000000000000400ULL,
2055     /*   isel instruction                                                    */
2056     PPC_ISEL           = 0x0000000000000800ULL,
2057     /*   popcntb instruction                                                 */
2058     PPC_POPCNTB        = 0x0000000000001000ULL,
2059     /*   string load / store                                                 */
2060     PPC_STRING         = 0x0000000000002000ULL,
2061     /*   real mode cache inhibited load / store                              */
2062     PPC_CILDST         = 0x0000000000004000ULL,
2063
2064     /* Floating-point unit extensions                                        */
2065     /*   Optional floating point instructions                                */
2066     PPC_FLOAT          = 0x0000000000010000ULL,
2067     /* New floating-point extensions (PowerPC 2.0x)                          */
2068     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2069     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2070     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2071     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2072     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2073     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2074     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2075
2076     /* Vector/SIMD extensions                                                */
2077     /*   Altivec support                                                     */
2078     PPC_ALTIVEC        = 0x0000000001000000ULL,
2079     /*   PowerPC 2.03 SPE extension                                          */
2080     PPC_SPE            = 0x0000000002000000ULL,
2081     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2082     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2083     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2084     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2085
2086     /* Optional memory control instructions                                  */
2087     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2088     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2089     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2090     /*   sync instruction                                                    */
2091     PPC_MEM_SYNC       = 0x0000000080000000ULL,
2092     /*   eieio instruction                                                   */
2093     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2094
2095     /* Cache control instructions                                            */
2096     PPC_CACHE          = 0x0000000200000000ULL,
2097     /*   icbi instruction                                                    */
2098     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2099     /*   dcbz instruction                                                    */
2100     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2101     /*   dcba instruction                                                    */
2102     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2103     /*   Freescale cache locking instructions                                */
2104     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2105
2106     /* MMU related extensions                                                */
2107     /*   external control instructions                                       */
2108     PPC_EXTERN         = 0x0000010000000000ULL,
2109     /*   segment register access instructions                                */
2110     PPC_SEGMENT        = 0x0000020000000000ULL,
2111     /*   PowerPC 6xx TLB management instructions                             */
2112     PPC_6xx_TLB        = 0x0000040000000000ULL,
2113     /* PowerPC 74xx TLB management instructions                              */
2114     PPC_74xx_TLB       = 0x0000080000000000ULL,
2115     /*   PowerPC 40x TLB management instructions                             */
2116     PPC_40x_TLB        = 0x0000100000000000ULL,
2117     /*   segment register access instructions for PowerPC 64 "bridge"        */
2118     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2119     /*   SLB management                                                      */
2120     PPC_SLBI           = 0x0000400000000000ULL,
2121
2122     /* Embedded PowerPC dedicated instructions                               */
2123     PPC_WRTEE          = 0x0001000000000000ULL,
2124     /* PowerPC 40x exception model                                           */
2125     PPC_40x_EXCP       = 0x0002000000000000ULL,
2126     /* PowerPC 405 Mac instructions                                          */
2127     PPC_405_MAC        = 0x0004000000000000ULL,
2128     /* PowerPC 440 specific instructions                                     */
2129     PPC_440_SPEC       = 0x0008000000000000ULL,
2130     /* BookE (embedded) PowerPC specification                                */
2131     PPC_BOOKE          = 0x0010000000000000ULL,
2132     /* mfapidi instruction                                                   */
2133     PPC_MFAPIDI        = 0x0020000000000000ULL,
2134     /* tlbiva instruction                                                    */
2135     PPC_TLBIVA         = 0x0040000000000000ULL,
2136     /* tlbivax instruction                                                   */
2137     PPC_TLBIVAX        = 0x0080000000000000ULL,
2138     /* PowerPC 4xx dedicated instructions                                    */
2139     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2140     /* PowerPC 40x ibct instructions                                         */
2141     PPC_40x_ICBT       = 0x0200000000000000ULL,
2142     /* rfmci is not implemented in all BookE PowerPC                         */
2143     PPC_RFMCI          = 0x0400000000000000ULL,
2144     /* rfdi instruction                                                      */
2145     PPC_RFDI           = 0x0800000000000000ULL,
2146     /* DCR accesses                                                          */
2147     PPC_DCR            = 0x1000000000000000ULL,
2148     /* DCR extended accesse                                                  */
2149     PPC_DCRX           = 0x2000000000000000ULL,
2150     /* user-mode DCR access, implemented in PowerPC 460                      */
2151     PPC_DCRUX          = 0x4000000000000000ULL,
2152     /* popcntw and popcntd instructions                                      */
2153     PPC_POPCNTWD       = 0x8000000000000000ULL,
2154
2155 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2156                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2157                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2158                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2159                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2160                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2161                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2162                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2163                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2164                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2165                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2166                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2167                         | PPC_CACHE | PPC_CACHE_ICBI \
2168                         | PPC_CACHE_DCBZ \
2169                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2170                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2171                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2172                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2173                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2174                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2175                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2176                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2177                         | PPC_POPCNTWD | PPC_CILDST)
2178
2179     /* extended type values */
2180
2181     /* BookE 2.06 PowerPC specification                                      */
2182     PPC2_BOOKE206      = 0x0000000000000001ULL,
2183     /* VSX (extensions to Altivec / VMX)                                     */
2184     PPC2_VSX           = 0x0000000000000002ULL,
2185     /* Decimal Floating Point (DFP)                                          */
2186     PPC2_DFP           = 0x0000000000000004ULL,
2187     /* Embedded.Processor Control                                            */
2188     PPC2_PRCNTL        = 0x0000000000000008ULL,
2189     /* Byte-reversed, indexed, double-word load and store                    */
2190     PPC2_DBRX          = 0x0000000000000010ULL,
2191     /* Book I 2.05 PowerPC specification                                     */
2192     PPC2_ISA205        = 0x0000000000000020ULL,
2193     /* VSX additions in ISA 2.07                                             */
2194     PPC2_VSX207        = 0x0000000000000040ULL,
2195     /* ISA 2.06B bpermd                                                      */
2196     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2197     /* ISA 2.06B divide extended variants                                    */
2198     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2199     /* ISA 2.06B larx/stcx. instructions                                     */
2200     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2201     /* ISA 2.06B floating point integer conversion                           */
2202     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2203     /* ISA 2.06B floating point test instructions                            */
2204     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2205     /* ISA 2.07 bctar instruction                                            */
2206     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2207     /* ISA 2.07 load/store quadword                                          */
2208     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2209     /* ISA 2.07 Altivec                                                      */
2210     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2211     /* PowerISA 2.07 Book3s specification                                    */
2212     PPC2_ISA207S       = 0x0000000000008000ULL,
2213     /* Double precision floating point conversion for signed integer 64      */
2214     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2215     /* Transactional Memory (ISA 2.07, Book II)                              */
2216     PPC2_TM            = 0x0000000000020000ULL,
2217     /* Server PM instructgions (ISA 2.06, Book III)                          */
2218     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2219     /* POWER ISA 3.0                                                         */
2220     PPC2_ISA300        = 0x0000000000080000ULL,
2221
2222 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2223                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2224                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2225                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2226                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2227                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2228                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2229                         PPC2_ISA300)
2230 };
2231
2232 /*****************************************************************************/
2233 /* Memory access type :
2234  * may be needed for precise access rights control and precise exceptions.
2235  */
2236 enum {
2237     /* 1 bit to define user level / supervisor access */
2238     ACCESS_USER  = 0x00,
2239     ACCESS_SUPER = 0x01,
2240     /* Type of instruction that generated the access */
2241     ACCESS_CODE  = 0x10, /* Code fetch access                */
2242     ACCESS_INT   = 0x20, /* Integer load/store access        */
2243     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2244     ACCESS_RES   = 0x40, /* load/store with reservation      */
2245     ACCESS_EXT   = 0x50, /* external access                  */
2246     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2247 };
2248
2249 /* Hardware interruption sources:
2250  * all those exception can be raised simulteaneously
2251  */
2252 /* Input pins definitions */
2253 enum {
2254     /* 6xx bus input pins */
2255     PPC6xx_INPUT_HRESET     = 0,
2256     PPC6xx_INPUT_SRESET     = 1,
2257     PPC6xx_INPUT_CKSTP_IN   = 2,
2258     PPC6xx_INPUT_MCP        = 3,
2259     PPC6xx_INPUT_SMI        = 4,
2260     PPC6xx_INPUT_INT        = 5,
2261     PPC6xx_INPUT_TBEN       = 6,
2262     PPC6xx_INPUT_WAKEUP     = 7,
2263     PPC6xx_INPUT_NB,
2264 };
2265
2266 enum {
2267     /* Embedded PowerPC input pins */
2268     PPCBookE_INPUT_HRESET     = 0,
2269     PPCBookE_INPUT_SRESET     = 1,
2270     PPCBookE_INPUT_CKSTP_IN   = 2,
2271     PPCBookE_INPUT_MCP        = 3,
2272     PPCBookE_INPUT_SMI        = 4,
2273     PPCBookE_INPUT_INT        = 5,
2274     PPCBookE_INPUT_CINT       = 6,
2275     PPCBookE_INPUT_NB,
2276 };
2277
2278 enum {
2279     /* PowerPC E500 input pins */
2280     PPCE500_INPUT_RESET_CORE = 0,
2281     PPCE500_INPUT_MCK        = 1,
2282     PPCE500_INPUT_CINT       = 3,
2283     PPCE500_INPUT_INT        = 4,
2284     PPCE500_INPUT_DEBUG      = 6,
2285     PPCE500_INPUT_NB,
2286 };
2287
2288 enum {
2289     /* PowerPC 40x input pins */
2290     PPC40x_INPUT_RESET_CORE = 0,
2291     PPC40x_INPUT_RESET_CHIP = 1,
2292     PPC40x_INPUT_RESET_SYS  = 2,
2293     PPC40x_INPUT_CINT       = 3,
2294     PPC40x_INPUT_INT        = 4,
2295     PPC40x_INPUT_HALT       = 5,
2296     PPC40x_INPUT_DEBUG      = 6,
2297     PPC40x_INPUT_NB,
2298 };
2299
2300 enum {
2301     /* RCPU input pins */
2302     PPCRCPU_INPUT_PORESET   = 0,
2303     PPCRCPU_INPUT_HRESET    = 1,
2304     PPCRCPU_INPUT_SRESET    = 2,
2305     PPCRCPU_INPUT_IRQ0      = 3,
2306     PPCRCPU_INPUT_IRQ1      = 4,
2307     PPCRCPU_INPUT_IRQ2      = 5,
2308     PPCRCPU_INPUT_IRQ3      = 6,
2309     PPCRCPU_INPUT_IRQ4      = 7,
2310     PPCRCPU_INPUT_IRQ5      = 8,
2311     PPCRCPU_INPUT_IRQ6      = 9,
2312     PPCRCPU_INPUT_IRQ7      = 10,
2313     PPCRCPU_INPUT_NB,
2314 };
2315
2316 #if defined(TARGET_PPC64)
2317 enum {
2318     /* PowerPC 970 input pins */
2319     PPC970_INPUT_HRESET     = 0,
2320     PPC970_INPUT_SRESET     = 1,
2321     PPC970_INPUT_CKSTP      = 2,
2322     PPC970_INPUT_TBEN       = 3,
2323     PPC970_INPUT_MCP        = 4,
2324     PPC970_INPUT_INT        = 5,
2325     PPC970_INPUT_THINT      = 6,
2326     PPC970_INPUT_NB,
2327 };
2328
2329 enum {
2330     /* POWER7 input pins */
2331     POWER7_INPUT_INT        = 0,
2332     /* POWER7 probably has other inputs, but we don't care about them
2333      * for any existing machine.  We can wire these up when we need
2334      * them */
2335     POWER7_INPUT_NB,
2336 };
2337 #endif
2338
2339 /* Hardware exceptions definitions */
2340 enum {
2341     /* External hardware exception sources */
2342     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2343     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2344     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2345     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2346     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2347     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2348     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2349     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2350     /* Internal hardware exception sources */
2351     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2352     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2353     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2354     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2355     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2356     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2357     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2358     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2359     PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
2360     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2361 };
2362
2363 /* Processor Compatibility mask (PCR) */
2364 enum {
2365     PCR_COMPAT_2_05     = PPC_BIT(62),
2366     PCR_COMPAT_2_06     = PPC_BIT(61),
2367     PCR_COMPAT_2_07     = PPC_BIT(60),
2368     PCR_COMPAT_3_00     = PPC_BIT(59),
2369     PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2370     PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2371     PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2372 };
2373
2374 /* HMER/HMEER */
2375 enum {
2376     HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2377     HMER_PROC_RECV_DONE         = PPC_BIT(2),
2378     HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2379     HMER_TFAC_ERROR             = PPC_BIT(4),
2380     HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2381     HMER_XSCOM_FAIL             = PPC_BIT(8),
2382     HMER_XSCOM_DONE             = PPC_BIT(9),
2383     HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2384     HMER_WARN_RISE              = PPC_BIT(14),
2385     HMER_WARN_FALL              = PPC_BIT(15),
2386     HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2387     HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2388     HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2389     HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2390 };
2391
2392 /* Alternate Interrupt Location (AIL) */
2393 enum {
2394     AIL_NONE                = 0,
2395     AIL_RESERVED            = 1,
2396     AIL_0001_8000           = 2,
2397     AIL_C000_0000_0000_4000 = 3,
2398 };
2399
2400 /*****************************************************************************/
2401
2402 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2403 target_ulong cpu_read_xer(CPUPPCState *env);
2404 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2405
2406 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2407                                         target_ulong *cs_base, uint32_t *flags)
2408 {
2409     *pc = env->nip;
2410     *cs_base = 0;
2411     *flags = env->hflags;
2412 }
2413
2414 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2415 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2416                                       uintptr_t raddr);
2417 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2418                                        uint32_t error_code);
2419 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2420                                           uint32_t error_code, uintptr_t raddr);
2421
2422 #if !defined(CONFIG_USER_ONLY)
2423 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2424 {
2425     uintptr_t tlbml = (uintptr_t)tlbm;
2426     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2427
2428     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2429 }
2430
2431 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2432 {
2433     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2434     int r = tlbncfg & TLBnCFG_N_ENTRY;
2435     return r;
2436 }
2437
2438 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2439 {
2440     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2441     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2442     return r;
2443 }
2444
2445 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2446 {
2447     int id = booke206_tlbm_id(env, tlbm);
2448     int end = 0;
2449     int i;
2450
2451     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2452         end += booke206_tlb_size(env, i);
2453         if (id < end) {
2454             return i;
2455         }
2456     }
2457
2458     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2459     return 0;
2460 }
2461
2462 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2463 {
2464     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2465     int tlbid = booke206_tlbm_id(env, tlb);
2466     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2467 }
2468
2469 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2470                                               target_ulong ea, int way)
2471 {
2472     int r;
2473     uint32_t ways = booke206_tlb_ways(env, tlbn);
2474     int ways_bits = ctz32(ways);
2475     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2476     int i;
2477
2478     way &= ways - 1;
2479     ea >>= MAS2_EPN_SHIFT;
2480     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2481     r = (ea << ways_bits) | way;
2482
2483     if (r >= booke206_tlb_size(env, tlbn)) {
2484         return NULL;
2485     }
2486
2487     /* bump up to tlbn index */
2488     for (i = 0; i < tlbn; i++) {
2489         r += booke206_tlb_size(env, i);
2490     }
2491
2492     return &env->tlb.tlbm[r];
2493 }
2494
2495 /* returns bitmap of supported page sizes for a given TLB */
2496 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2497 {
2498     uint32_t ret = 0;
2499
2500     if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2501         /* MAV2 */
2502         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2503     } else {
2504         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2505         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2506         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2507         int i;
2508         for (i = min; i <= max; i++) {
2509             ret |= (1 << (i << 1));
2510         }
2511     }
2512
2513     return ret;
2514 }
2515
2516 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2517                                             ppcmas_tlb_t *tlb)
2518 {
2519     uint8_t i;
2520     int32_t tsize = -1;
2521
2522     for (i = 0; i < 32; i++) {
2523         if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2524             if (tsize == -1) {
2525                 tsize = i;
2526             } else {
2527                 return;
2528             }
2529         }
2530     }
2531
2532     /* TLBnPS unimplemented? Odd.. */
2533     assert(tsize != -1);
2534     tlb->mas1 &= ~MAS1_TSIZE_MASK;
2535     tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2536 }
2537
2538 #endif
2539
2540 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2541 {
2542     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2543         return msr & (1ULL << MSR_CM);
2544     }
2545
2546     return msr & (1ULL << MSR_SF);
2547 }
2548
2549 /**
2550  * Check whether register rx is in the range between start and
2551  * start + nregs (as needed by the LSWX and LSWI instructions)
2552  */
2553 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2554 {
2555     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2556            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2557 }
2558
2559 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2560
2561 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2562 #endif /* PPC_CPU_H */