Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / exec.c
blob52af1aa741096057d167cca9966f2c851f1086e4
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
26 #include "tcg.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
53 #endif
55 #endif
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
63 #include "exec/log.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
68 #ifndef _WIN32
69 #include "qemu/mmap-alloc.h"
70 #endif
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
82 static MemoryRegion *system_memory;
83 static MemoryRegion *system_io;
85 AddressSpace address_space_io;
86 AddressSpace address_space_memory;
88 MemoryRegion io_mem_rom, io_mem_notdirty;
89 static MemoryRegion io_mem_unassigned;
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
100 #define RAM_RESIZEABLE (1 << 2)
102 #endif
104 #ifdef TARGET_PAGE_BITS_VARY
105 int target_page_bits;
106 bool target_page_bits_decided;
107 #endif
109 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
110 /* current CPU in the current thread. It is only valid inside
111 cpu_exec() */
112 __thread CPUState *current_cpu;
113 /* 0 = Do not count executed instructions.
114 1 = Precise instruction counting.
115 2 = Adaptive rate instruction counting. */
116 int use_icount;
118 uintptr_t qemu_host_page_size;
119 intptr_t qemu_host_page_mask;
121 bool set_preferred_target_page_bits(int bits)
123 /* The target page size is the lowest common denominator for all
124 * the CPUs in the system, so we can only make it smaller, never
125 * larger. And we can't make it smaller once we've committed to
126 * a particular size.
128 #ifdef TARGET_PAGE_BITS_VARY
129 assert(bits >= TARGET_PAGE_BITS_MIN);
130 if (target_page_bits == 0 || target_page_bits > bits) {
131 if (target_page_bits_decided) {
132 return false;
134 target_page_bits = bits;
136 #endif
137 return true;
140 #if !defined(CONFIG_USER_ONLY)
142 static void finalize_target_page_bits(void)
144 #ifdef TARGET_PAGE_BITS_VARY
145 if (target_page_bits == 0) {
146 target_page_bits = TARGET_PAGE_BITS_MIN;
148 target_page_bits_decided = true;
149 #endif
152 typedef struct PhysPageEntry PhysPageEntry;
154 struct PhysPageEntry {
155 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
156 uint32_t skip : 6;
157 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
158 uint32_t ptr : 26;
161 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
163 /* Size of the L2 (and L3, etc) page tables. */
164 #define ADDR_SPACE_BITS 64
166 #define P_L2_BITS 9
167 #define P_L2_SIZE (1 << P_L2_BITS)
169 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
171 typedef PhysPageEntry Node[P_L2_SIZE];
173 typedef struct PhysPageMap {
174 struct rcu_head rcu;
176 unsigned sections_nb;
177 unsigned sections_nb_alloc;
178 unsigned nodes_nb;
179 unsigned nodes_nb_alloc;
180 Node *nodes;
181 MemoryRegionSection *sections;
182 } PhysPageMap;
184 struct AddressSpaceDispatch {
185 MemoryRegionSection *mru_section;
186 /* This is a multi-level map on the physical address space.
187 * The bottom level has pointers to MemoryRegionSections.
189 PhysPageEntry phys_map;
190 PhysPageMap map;
193 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
194 typedef struct subpage_t {
195 MemoryRegion iomem;
196 FlatView *fv;
197 hwaddr base;
198 uint16_t sub_section[];
199 } subpage_t;
201 #define PHYS_SECTION_UNASSIGNED 0
202 #define PHYS_SECTION_NOTDIRTY 1
203 #define PHYS_SECTION_ROM 2
204 #define PHYS_SECTION_WATCH 3
206 static void io_mem_init(void);
207 static void memory_map_init(void);
208 static void tcg_commit(MemoryListener *listener);
210 static MemoryRegion io_mem_watch;
213 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
214 * @cpu: the CPU whose AddressSpace this is
215 * @as: the AddressSpace itself
216 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
217 * @tcg_as_listener: listener for tracking changes to the AddressSpace
219 struct CPUAddressSpace {
220 CPUState *cpu;
221 AddressSpace *as;
222 struct AddressSpaceDispatch *memory_dispatch;
223 MemoryListener tcg_as_listener;
226 struct DirtyBitmapSnapshot {
227 ram_addr_t start;
228 ram_addr_t end;
229 unsigned long dirty[];
232 #endif
234 #if !defined(CONFIG_USER_ONLY)
236 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
238 static unsigned alloc_hint = 16;
239 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
240 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
241 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
242 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
243 alloc_hint = map->nodes_nb_alloc;
247 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
249 unsigned i;
250 uint32_t ret;
251 PhysPageEntry e;
252 PhysPageEntry *p;
254 ret = map->nodes_nb++;
255 p = map->nodes[ret];
256 assert(ret != PHYS_MAP_NODE_NIL);
257 assert(ret != map->nodes_nb_alloc);
259 e.skip = leaf ? 0 : 1;
260 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
261 for (i = 0; i < P_L2_SIZE; ++i) {
262 memcpy(&p[i], &e, sizeof(e));
264 return ret;
267 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
268 hwaddr *index, hwaddr *nb, uint16_t leaf,
269 int level)
271 PhysPageEntry *p;
272 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
274 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
275 lp->ptr = phys_map_node_alloc(map, level == 0);
277 p = map->nodes[lp->ptr];
278 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
280 while (*nb && lp < &p[P_L2_SIZE]) {
281 if ((*index & (step - 1)) == 0 && *nb >= step) {
282 lp->skip = 0;
283 lp->ptr = leaf;
284 *index += step;
285 *nb -= step;
286 } else {
287 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
289 ++lp;
293 static void phys_page_set(AddressSpaceDispatch *d,
294 hwaddr index, hwaddr nb,
295 uint16_t leaf)
297 /* Wildly overreserve - it doesn't matter much. */
298 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
300 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
303 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
304 * and update our entry so we can skip it and go directly to the destination.
306 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
308 unsigned valid_ptr = P_L2_SIZE;
309 int valid = 0;
310 PhysPageEntry *p;
311 int i;
313 if (lp->ptr == PHYS_MAP_NODE_NIL) {
314 return;
317 p = nodes[lp->ptr];
318 for (i = 0; i < P_L2_SIZE; i++) {
319 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
320 continue;
323 valid_ptr = i;
324 valid++;
325 if (p[i].skip) {
326 phys_page_compact(&p[i], nodes);
330 /* We can only compress if there's only one child. */
331 if (valid != 1) {
332 return;
335 assert(valid_ptr < P_L2_SIZE);
337 /* Don't compress if it won't fit in the # of bits we have. */
338 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
339 return;
342 lp->ptr = p[valid_ptr].ptr;
343 if (!p[valid_ptr].skip) {
344 /* If our only child is a leaf, make this a leaf. */
345 /* By design, we should have made this node a leaf to begin with so we
346 * should never reach here.
347 * But since it's so simple to handle this, let's do it just in case we
348 * change this rule.
350 lp->skip = 0;
351 } else {
352 lp->skip += p[valid_ptr].skip;
356 void address_space_dispatch_compact(AddressSpaceDispatch *d)
358 if (d->phys_map.skip) {
359 phys_page_compact(&d->phys_map, d->map.nodes);
363 static inline bool section_covers_addr(const MemoryRegionSection *section,
364 hwaddr addr)
366 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
367 * the section must cover the entire address space.
369 return int128_gethi(section->size) ||
370 range_covers_byte(section->offset_within_address_space,
371 int128_getlo(section->size), addr);
374 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
376 PhysPageEntry lp = d->phys_map, *p;
377 Node *nodes = d->map.nodes;
378 MemoryRegionSection *sections = d->map.sections;
379 hwaddr index = addr >> TARGET_PAGE_BITS;
380 int i;
382 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
383 if (lp.ptr == PHYS_MAP_NODE_NIL) {
384 return &sections[PHYS_SECTION_UNASSIGNED];
386 p = nodes[lp.ptr];
387 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
390 if (section_covers_addr(&sections[lp.ptr], addr)) {
391 return &sections[lp.ptr];
392 } else {
393 return &sections[PHYS_SECTION_UNASSIGNED];
397 bool memory_region_is_unassigned(MemoryRegion *mr)
399 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
400 && mr != &io_mem_watch;
403 /* Called from RCU critical section */
404 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
405 hwaddr addr,
406 bool resolve_subpage)
408 MemoryRegionSection *section = atomic_read(&d->mru_section);
409 subpage_t *subpage;
411 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
412 !section_covers_addr(section, addr)) {
413 section = phys_page_find(d, addr);
414 atomic_set(&d->mru_section, section);
416 if (resolve_subpage && section->mr->subpage) {
417 subpage = container_of(section->mr, subpage_t, iomem);
418 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
420 return section;
423 /* Called from RCU critical section */
424 static MemoryRegionSection *
425 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
426 hwaddr *plen, bool resolve_subpage)
428 MemoryRegionSection *section;
429 MemoryRegion *mr;
430 Int128 diff;
432 section = address_space_lookup_region(d, addr, resolve_subpage);
433 /* Compute offset within MemoryRegionSection */
434 addr -= section->offset_within_address_space;
436 /* Compute offset within MemoryRegion */
437 *xlat = addr + section->offset_within_region;
439 mr = section->mr;
441 /* MMIO registers can be expected to perform full-width accesses based only
442 * on their address, without considering adjacent registers that could
443 * decode to completely different MemoryRegions. When such registers
444 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
445 * regions overlap wildly. For this reason we cannot clamp the accesses
446 * here.
448 * If the length is small (as is the case for address_space_ldl/stl),
449 * everything works fine. If the incoming length is large, however,
450 * the caller really has to do the clamping through memory_access_size.
452 if (memory_region_is_ram(mr)) {
453 diff = int128_sub(section->size, int128_make64(addr));
454 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
456 return section;
460 * flatview_do_translate - translate an address in FlatView
462 * @fv: the flat view that we want to translate on
463 * @addr: the address to be translated in above address space
464 * @xlat: the translated address offset within memory region. It
465 * cannot be @NULL.
466 * @plen_out: valid read/write length of the translated address. It
467 * can be @NULL when we don't care about it.
468 * @page_mask_out: page mask for the translated address. This
469 * should only be meaningful for IOMMU translated
470 * addresses, since there may be huge pages that this bit
471 * would tell. It can be @NULL if we don't care about it.
472 * @is_write: whether the translation operation is for write
473 * @is_mmio: whether this can be MMIO, set true if it can
475 * This function is called from RCU critical section
477 static MemoryRegionSection flatview_do_translate(FlatView *fv,
478 hwaddr addr,
479 hwaddr *xlat,
480 hwaddr *plen_out,
481 hwaddr *page_mask_out,
482 bool is_write,
483 bool is_mmio,
484 AddressSpace **target_as)
486 IOMMUTLBEntry iotlb;
487 MemoryRegionSection *section;
488 IOMMUMemoryRegion *iommu_mr;
489 IOMMUMemoryRegionClass *imrc;
490 hwaddr page_mask = (hwaddr)(-1);
491 hwaddr plen = (hwaddr)(-1);
493 if (plen_out) {
494 plen = *plen_out;
497 for (;;) {
498 section = address_space_translate_internal(
499 flatview_to_dispatch(fv), addr, &addr,
500 &plen, is_mmio);
502 iommu_mr = memory_region_get_iommu(section->mr);
503 if (!iommu_mr) {
504 break;
506 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
508 iotlb = imrc->translate(iommu_mr, addr, is_write ?
509 IOMMU_WO : IOMMU_RO);
510 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
511 | (addr & iotlb.addr_mask));
512 page_mask &= iotlb.addr_mask;
513 plen = MIN(plen, (addr | iotlb.addr_mask) - addr + 1);
514 if (!(iotlb.perm & (1 << is_write))) {
515 goto translate_fail;
518 fv = address_space_to_flatview(iotlb.target_as);
519 *target_as = iotlb.target_as;
522 *xlat = addr;
524 if (page_mask == (hwaddr)(-1)) {
525 /* Not behind an IOMMU, use default page size. */
526 page_mask = ~TARGET_PAGE_MASK;
529 if (page_mask_out) {
530 *page_mask_out = page_mask;
533 if (plen_out) {
534 *plen_out = plen;
537 return *section;
539 translate_fail:
540 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
543 /* Called from RCU critical section */
544 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
545 bool is_write)
547 MemoryRegionSection section;
548 hwaddr xlat, page_mask;
551 * This can never be MMIO, and we don't really care about plen,
552 * but page mask.
554 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
555 NULL, &page_mask, is_write, false, &as);
557 /* Illegal translation */
558 if (section.mr == &io_mem_unassigned) {
559 goto iotlb_fail;
562 /* Convert memory region offset into address space offset */
563 xlat += section.offset_within_address_space -
564 section.offset_within_region;
566 return (IOMMUTLBEntry) {
567 .target_as = as,
568 .iova = addr & ~page_mask,
569 .translated_addr = xlat & ~page_mask,
570 .addr_mask = page_mask,
571 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
572 .perm = IOMMU_RW,
575 iotlb_fail:
576 return (IOMMUTLBEntry) {0};
579 /* Called from RCU critical section */
580 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
581 hwaddr *plen, bool is_write)
583 MemoryRegion *mr;
584 MemoryRegionSection section;
585 AddressSpace *as = NULL;
587 /* This can be MMIO, so setup MMIO bit. */
588 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
589 is_write, true, &as);
590 mr = section.mr;
592 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
593 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
594 *plen = MIN(page, *plen);
597 return mr;
600 /* Called from RCU critical section */
601 MemoryRegionSection *
602 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
603 hwaddr *xlat, hwaddr *plen)
605 MemoryRegionSection *section;
606 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
608 section = address_space_translate_internal(d, addr, xlat, plen, false);
610 assert(!memory_region_is_iommu(section->mr));
611 return section;
613 #endif
615 #if !defined(CONFIG_USER_ONLY)
617 static int cpu_common_post_load(void *opaque, int version_id)
619 CPUState *cpu = opaque;
621 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
622 version_id is increased. */
623 cpu->interrupt_request &= ~0x01;
624 tlb_flush(cpu);
626 return 0;
629 static int cpu_common_pre_load(void *opaque)
631 CPUState *cpu = opaque;
633 cpu->exception_index = -1;
635 return 0;
638 static bool cpu_common_exception_index_needed(void *opaque)
640 CPUState *cpu = opaque;
642 return tcg_enabled() && cpu->exception_index != -1;
645 static const VMStateDescription vmstate_cpu_common_exception_index = {
646 .name = "cpu_common/exception_index",
647 .version_id = 1,
648 .minimum_version_id = 1,
649 .needed = cpu_common_exception_index_needed,
650 .fields = (VMStateField[]) {
651 VMSTATE_INT32(exception_index, CPUState),
652 VMSTATE_END_OF_LIST()
656 static bool cpu_common_crash_occurred_needed(void *opaque)
658 CPUState *cpu = opaque;
660 return cpu->crash_occurred;
663 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
664 .name = "cpu_common/crash_occurred",
665 .version_id = 1,
666 .minimum_version_id = 1,
667 .needed = cpu_common_crash_occurred_needed,
668 .fields = (VMStateField[]) {
669 VMSTATE_BOOL(crash_occurred, CPUState),
670 VMSTATE_END_OF_LIST()
674 const VMStateDescription vmstate_cpu_common = {
675 .name = "cpu_common",
676 .version_id = 1,
677 .minimum_version_id = 1,
678 .pre_load = cpu_common_pre_load,
679 .post_load = cpu_common_post_load,
680 .fields = (VMStateField[]) {
681 VMSTATE_UINT32(halted, CPUState),
682 VMSTATE_UINT32(interrupt_request, CPUState),
683 VMSTATE_END_OF_LIST()
685 .subsections = (const VMStateDescription*[]) {
686 &vmstate_cpu_common_exception_index,
687 &vmstate_cpu_common_crash_occurred,
688 NULL
692 #endif
694 CPUState *qemu_get_cpu(int index)
696 CPUState *cpu;
698 CPU_FOREACH(cpu) {
699 if (cpu->cpu_index == index) {
700 return cpu;
704 return NULL;
707 #if !defined(CONFIG_USER_ONLY)
708 void cpu_address_space_init(CPUState *cpu, int asidx,
709 const char *prefix, MemoryRegion *mr)
711 CPUAddressSpace *newas;
712 AddressSpace *as = g_new0(AddressSpace, 1);
713 char *as_name;
715 assert(mr);
716 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
717 address_space_init(as, mr, as_name);
718 g_free(as_name);
720 /* Target code should have set num_ases before calling us */
721 assert(asidx < cpu->num_ases);
723 if (asidx == 0) {
724 /* address space 0 gets the convenience alias */
725 cpu->as = as;
728 /* KVM cannot currently support multiple address spaces. */
729 assert(asidx == 0 || !kvm_enabled());
731 if (!cpu->cpu_ases) {
732 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
735 newas = &cpu->cpu_ases[asidx];
736 newas->cpu = cpu;
737 newas->as = as;
738 if (tcg_enabled()) {
739 newas->tcg_as_listener.commit = tcg_commit;
740 memory_listener_register(&newas->tcg_as_listener, as);
744 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
746 /* Return the AddressSpace corresponding to the specified index */
747 return cpu->cpu_ases[asidx].as;
749 #endif
751 void cpu_exec_unrealizefn(CPUState *cpu)
753 CPUClass *cc = CPU_GET_CLASS(cpu);
755 cpu_list_remove(cpu);
757 if (cc->vmsd != NULL) {
758 vmstate_unregister(NULL, cc->vmsd, cpu);
760 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
761 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
765 Property cpu_common_props[] = {
766 #ifndef CONFIG_USER_ONLY
767 /* Create a memory property for softmmu CPU object,
768 * so users can wire up its memory. (This can't go in qom/cpu.c
769 * because that file is compiled only once for both user-mode
770 * and system builds.) The default if no link is set up is to use
771 * the system address space.
773 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
774 MemoryRegion *),
775 #endif
776 DEFINE_PROP_END_OF_LIST(),
779 void cpu_exec_initfn(CPUState *cpu)
781 #ifdef TARGET_WORDS_BIGENDIAN
782 cpu->bigendian = true;
783 #else
784 cpu->bigendian = false;
785 #endif
786 cpu->as = NULL;
787 cpu->num_ases = 0;
789 #ifndef CONFIG_USER_ONLY
790 cpu->thread_id = qemu_get_thread_id();
791 cpu->memory = system_memory;
792 object_ref(OBJECT(cpu->memory));
793 #endif
796 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
798 CPUClass *cc = CPU_GET_CLASS(cpu);
799 static bool tcg_target_initialized;
801 cpu_list_add(cpu);
803 if (tcg_enabled() && !tcg_target_initialized) {
804 tcg_target_initialized = true;
805 cc->tcg_initialize();
808 #ifndef CONFIG_USER_ONLY
809 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
810 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
812 if (cc->vmsd != NULL) {
813 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
815 #endif
818 #if defined(CONFIG_USER_ONLY)
819 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
821 mmap_lock();
822 tb_lock();
823 tb_invalidate_phys_page_range(pc, pc + 1, 0);
824 tb_unlock();
825 mmap_unlock();
827 #else
828 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
830 MemTxAttrs attrs;
831 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
832 int asidx = cpu_asidx_from_attrs(cpu, attrs);
833 if (phys != -1) {
834 /* Locks grabbed by tb_invalidate_phys_addr */
835 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
836 phys | (pc & ~TARGET_PAGE_MASK));
839 #endif
841 #if defined(CONFIG_USER_ONLY)
842 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
847 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
848 int flags)
850 return -ENOSYS;
853 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
857 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
858 int flags, CPUWatchpoint **watchpoint)
860 return -ENOSYS;
862 #else
863 /* Add a watchpoint. */
864 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
865 int flags, CPUWatchpoint **watchpoint)
867 CPUWatchpoint *wp;
869 /* forbid ranges which are empty or run off the end of the address space */
870 if (len == 0 || (addr + len - 1) < addr) {
871 error_report("tried to set invalid watchpoint at %"
872 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
873 return -EINVAL;
875 wp = g_malloc(sizeof(*wp));
877 wp->vaddr = addr;
878 wp->len = len;
879 wp->flags = flags;
881 /* keep all GDB-injected watchpoints in front */
882 if (flags & BP_GDB) {
883 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
884 } else {
885 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
888 tlb_flush_page(cpu, addr);
890 if (watchpoint)
891 *watchpoint = wp;
892 return 0;
895 /* Remove a specific watchpoint. */
896 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
897 int flags)
899 CPUWatchpoint *wp;
901 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
902 if (addr == wp->vaddr && len == wp->len
903 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
904 cpu_watchpoint_remove_by_ref(cpu, wp);
905 return 0;
908 return -ENOENT;
911 /* Remove a specific watchpoint by reference. */
912 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
914 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
916 tlb_flush_page(cpu, watchpoint->vaddr);
918 g_free(watchpoint);
921 /* Remove all matching watchpoints. */
922 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
924 CPUWatchpoint *wp, *next;
926 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
927 if (wp->flags & mask) {
928 cpu_watchpoint_remove_by_ref(cpu, wp);
933 /* Return true if this watchpoint address matches the specified
934 * access (ie the address range covered by the watchpoint overlaps
935 * partially or completely with the address range covered by the
936 * access).
938 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
939 vaddr addr,
940 vaddr len)
942 /* We know the lengths are non-zero, but a little caution is
943 * required to avoid errors in the case where the range ends
944 * exactly at the top of the address space and so addr + len
945 * wraps round to zero.
947 vaddr wpend = wp->vaddr + wp->len - 1;
948 vaddr addrend = addr + len - 1;
950 return !(addr > wpend || wp->vaddr > addrend);
953 #endif
955 /* Add a breakpoint. */
956 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
957 CPUBreakpoint **breakpoint)
959 CPUBreakpoint *bp;
961 bp = g_malloc(sizeof(*bp));
963 bp->pc = pc;
964 bp->flags = flags;
966 /* keep all GDB-injected breakpoints in front */
967 if (flags & BP_GDB) {
968 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
969 } else {
970 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
973 breakpoint_invalidate(cpu, pc);
975 if (breakpoint) {
976 *breakpoint = bp;
978 return 0;
981 /* Remove a specific breakpoint. */
982 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
984 CPUBreakpoint *bp;
986 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
987 if (bp->pc == pc && bp->flags == flags) {
988 cpu_breakpoint_remove_by_ref(cpu, bp);
989 return 0;
992 return -ENOENT;
995 /* Remove a specific breakpoint by reference. */
996 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
998 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1000 breakpoint_invalidate(cpu, breakpoint->pc);
1002 g_free(breakpoint);
1005 /* Remove all matching breakpoints. */
1006 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1008 CPUBreakpoint *bp, *next;
1010 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1011 if (bp->flags & mask) {
1012 cpu_breakpoint_remove_by_ref(cpu, bp);
1017 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1018 CPU loop after each instruction */
1019 void cpu_single_step(CPUState *cpu, int enabled)
1021 if (cpu->singlestep_enabled != enabled) {
1022 cpu->singlestep_enabled = enabled;
1023 if (kvm_enabled()) {
1024 kvm_update_guest_debug(cpu, 0);
1025 } else {
1026 /* must flush all the translated code to avoid inconsistencies */
1027 /* XXX: only flush what is necessary */
1028 tb_flush(cpu);
1033 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
1035 va_list ap;
1036 va_list ap2;
1038 va_start(ap, fmt);
1039 va_copy(ap2, ap);
1040 fprintf(stderr, "qemu: fatal: ");
1041 vfprintf(stderr, fmt, ap);
1042 fprintf(stderr, "\n");
1043 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1044 if (qemu_log_separate()) {
1045 qemu_log_lock();
1046 qemu_log("qemu: fatal: ");
1047 qemu_log_vprintf(fmt, ap2);
1048 qemu_log("\n");
1049 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1050 qemu_log_flush();
1051 qemu_log_unlock();
1052 qemu_log_close();
1054 va_end(ap2);
1055 va_end(ap);
1056 replay_finish();
1057 #if defined(CONFIG_USER_ONLY)
1059 struct sigaction act;
1060 sigfillset(&act.sa_mask);
1061 act.sa_handler = SIG_DFL;
1062 sigaction(SIGABRT, &act, NULL);
1064 #endif
1065 abort();
1068 #if !defined(CONFIG_USER_ONLY)
1069 /* Called from RCU critical section */
1070 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1072 RAMBlock *block;
1074 block = atomic_rcu_read(&ram_list.mru_block);
1075 if (block && addr - block->offset < block->max_length) {
1076 return block;
1078 RAMBLOCK_FOREACH(block) {
1079 if (addr - block->offset < block->max_length) {
1080 goto found;
1084 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1085 abort();
1087 found:
1088 /* It is safe to write mru_block outside the iothread lock. This
1089 * is what happens:
1091 * mru_block = xxx
1092 * rcu_read_unlock()
1093 * xxx removed from list
1094 * rcu_read_lock()
1095 * read mru_block
1096 * mru_block = NULL;
1097 * call_rcu(reclaim_ramblock, xxx);
1098 * rcu_read_unlock()
1100 * atomic_rcu_set is not needed here. The block was already published
1101 * when it was placed into the list. Here we're just making an extra
1102 * copy of the pointer.
1104 ram_list.mru_block = block;
1105 return block;
1108 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1110 CPUState *cpu;
1111 ram_addr_t start1;
1112 RAMBlock *block;
1113 ram_addr_t end;
1115 end = TARGET_PAGE_ALIGN(start + length);
1116 start &= TARGET_PAGE_MASK;
1118 rcu_read_lock();
1119 block = qemu_get_ram_block(start);
1120 assert(block == qemu_get_ram_block(end - 1));
1121 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1122 CPU_FOREACH(cpu) {
1123 tlb_reset_dirty(cpu, start1, length);
1125 rcu_read_unlock();
1128 /* Note: start and end must be within the same ram block. */
1129 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1130 ram_addr_t length,
1131 unsigned client)
1133 DirtyMemoryBlocks *blocks;
1134 unsigned long end, page;
1135 bool dirty = false;
1137 if (length == 0) {
1138 return false;
1141 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1142 page = start >> TARGET_PAGE_BITS;
1144 rcu_read_lock();
1146 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1148 while (page < end) {
1149 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1150 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1151 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1153 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1154 offset, num);
1155 page += num;
1158 rcu_read_unlock();
1160 if (dirty && tcg_enabled()) {
1161 tlb_reset_dirty_range_all(start, length);
1164 return dirty;
1167 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1168 (ram_addr_t start, ram_addr_t length, unsigned client)
1170 DirtyMemoryBlocks *blocks;
1171 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1172 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1173 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1174 DirtyBitmapSnapshot *snap;
1175 unsigned long page, end, dest;
1177 snap = g_malloc0(sizeof(*snap) +
1178 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1179 snap->start = first;
1180 snap->end = last;
1182 page = first >> TARGET_PAGE_BITS;
1183 end = last >> TARGET_PAGE_BITS;
1184 dest = 0;
1186 rcu_read_lock();
1188 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1190 while (page < end) {
1191 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1192 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1193 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1195 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1196 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1197 offset >>= BITS_PER_LEVEL;
1199 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1200 blocks->blocks[idx] + offset,
1201 num);
1202 page += num;
1203 dest += num >> BITS_PER_LEVEL;
1206 rcu_read_unlock();
1208 if (tcg_enabled()) {
1209 tlb_reset_dirty_range_all(start, length);
1212 return snap;
1215 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1216 ram_addr_t start,
1217 ram_addr_t length)
1219 unsigned long page, end;
1221 assert(start >= snap->start);
1222 assert(start + length <= snap->end);
1224 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1225 page = (start - snap->start) >> TARGET_PAGE_BITS;
1227 while (page < end) {
1228 if (test_bit(page, snap->dirty)) {
1229 return true;
1231 page++;
1233 return false;
1236 /* Called from RCU critical section */
1237 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1238 MemoryRegionSection *section,
1239 target_ulong vaddr,
1240 hwaddr paddr, hwaddr xlat,
1241 int prot,
1242 target_ulong *address)
1244 hwaddr iotlb;
1245 CPUWatchpoint *wp;
1247 if (memory_region_is_ram(section->mr)) {
1248 /* Normal RAM. */
1249 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1250 if (!section->readonly) {
1251 iotlb |= PHYS_SECTION_NOTDIRTY;
1252 } else {
1253 iotlb |= PHYS_SECTION_ROM;
1255 } else {
1256 AddressSpaceDispatch *d;
1258 d = flatview_to_dispatch(section->fv);
1259 iotlb = section - d->map.sections;
1260 iotlb += xlat;
1263 /* Make accesses to pages with watchpoints go via the
1264 watchpoint trap routines. */
1265 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1266 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1267 /* Avoid trapping reads of pages with a write breakpoint. */
1268 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1269 iotlb = PHYS_SECTION_WATCH + paddr;
1270 *address |= TLB_MMIO;
1271 break;
1276 return iotlb;
1278 #endif /* defined(CONFIG_USER_ONLY) */
1280 #if !defined(CONFIG_USER_ONLY)
1282 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1283 uint16_t section);
1284 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1286 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1287 qemu_anon_ram_alloc;
1290 * Set a custom physical guest memory alloator.
1291 * Accelerators with unusual needs may need this. Hopefully, we can
1292 * get rid of it eventually.
1294 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1296 phys_mem_alloc = alloc;
1299 static uint16_t phys_section_add(PhysPageMap *map,
1300 MemoryRegionSection *section)
1302 /* The physical section number is ORed with a page-aligned
1303 * pointer to produce the iotlb entries. Thus it should
1304 * never overflow into the page-aligned value.
1306 assert(map->sections_nb < TARGET_PAGE_SIZE);
1308 if (map->sections_nb == map->sections_nb_alloc) {
1309 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1310 map->sections = g_renew(MemoryRegionSection, map->sections,
1311 map->sections_nb_alloc);
1313 map->sections[map->sections_nb] = *section;
1314 memory_region_ref(section->mr);
1315 return map->sections_nb++;
1318 static void phys_section_destroy(MemoryRegion *mr)
1320 bool have_sub_page = mr->subpage;
1322 memory_region_unref(mr);
1324 if (have_sub_page) {
1325 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1326 object_unref(OBJECT(&subpage->iomem));
1327 g_free(subpage);
1331 static void phys_sections_free(PhysPageMap *map)
1333 while (map->sections_nb > 0) {
1334 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1335 phys_section_destroy(section->mr);
1337 g_free(map->sections);
1338 g_free(map->nodes);
1341 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1343 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1344 subpage_t *subpage;
1345 hwaddr base = section->offset_within_address_space
1346 & TARGET_PAGE_MASK;
1347 MemoryRegionSection *existing = phys_page_find(d, base);
1348 MemoryRegionSection subsection = {
1349 .offset_within_address_space = base,
1350 .size = int128_make64(TARGET_PAGE_SIZE),
1352 hwaddr start, end;
1354 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1356 if (!(existing->mr->subpage)) {
1357 subpage = subpage_init(fv, base);
1358 subsection.fv = fv;
1359 subsection.mr = &subpage->iomem;
1360 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1361 phys_section_add(&d->map, &subsection));
1362 } else {
1363 subpage = container_of(existing->mr, subpage_t, iomem);
1365 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1366 end = start + int128_get64(section->size) - 1;
1367 subpage_register(subpage, start, end,
1368 phys_section_add(&d->map, section));
1372 static void register_multipage(FlatView *fv,
1373 MemoryRegionSection *section)
1375 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1376 hwaddr start_addr = section->offset_within_address_space;
1377 uint16_t section_index = phys_section_add(&d->map, section);
1378 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1379 TARGET_PAGE_BITS));
1381 assert(num_pages);
1382 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1385 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1387 MemoryRegionSection now = *section, remain = *section;
1388 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1390 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1391 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1392 - now.offset_within_address_space;
1394 now.size = int128_min(int128_make64(left), now.size);
1395 register_subpage(fv, &now);
1396 } else {
1397 now.size = int128_zero();
1399 while (int128_ne(remain.size, now.size)) {
1400 remain.size = int128_sub(remain.size, now.size);
1401 remain.offset_within_address_space += int128_get64(now.size);
1402 remain.offset_within_region += int128_get64(now.size);
1403 now = remain;
1404 if (int128_lt(remain.size, page_size)) {
1405 register_subpage(fv, &now);
1406 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1407 now.size = page_size;
1408 register_subpage(fv, &now);
1409 } else {
1410 now.size = int128_and(now.size, int128_neg(page_size));
1411 register_multipage(fv, &now);
1416 void qemu_flush_coalesced_mmio_buffer(void)
1418 if (kvm_enabled())
1419 kvm_flush_coalesced_mmio_buffer();
1422 void qemu_mutex_lock_ramlist(void)
1424 qemu_mutex_lock(&ram_list.mutex);
1427 void qemu_mutex_unlock_ramlist(void)
1429 qemu_mutex_unlock(&ram_list.mutex);
1432 void ram_block_dump(Monitor *mon)
1434 RAMBlock *block;
1435 char *psize;
1437 rcu_read_lock();
1438 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1439 "Block Name", "PSize", "Offset", "Used", "Total");
1440 RAMBLOCK_FOREACH(block) {
1441 psize = size_to_str(block->page_size);
1442 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1443 " 0x%016" PRIx64 "\n", block->idstr, psize,
1444 (uint64_t)block->offset,
1445 (uint64_t)block->used_length,
1446 (uint64_t)block->max_length);
1447 g_free(psize);
1449 rcu_read_unlock();
1452 #ifdef __linux__
1454 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1455 * may or may not name the same files / on the same filesystem now as
1456 * when we actually open and map them. Iterate over the file
1457 * descriptors instead, and use qemu_fd_getpagesize().
1459 static int find_max_supported_pagesize(Object *obj, void *opaque)
1461 char *mem_path;
1462 long *hpsize_min = opaque;
1464 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1465 mem_path = object_property_get_str(obj, "mem-path", NULL);
1466 if (mem_path) {
1467 long hpsize = qemu_mempath_getpagesize(mem_path);
1468 if (hpsize < *hpsize_min) {
1469 *hpsize_min = hpsize;
1471 } else {
1472 *hpsize_min = getpagesize();
1476 return 0;
1479 long qemu_getrampagesize(void)
1481 long hpsize = LONG_MAX;
1482 long mainrampagesize;
1483 Object *memdev_root;
1485 if (mem_path) {
1486 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1487 } else {
1488 mainrampagesize = getpagesize();
1491 /* it's possible we have memory-backend objects with
1492 * hugepage-backed RAM. these may get mapped into system
1493 * address space via -numa parameters or memory hotplug
1494 * hooks. we want to take these into account, but we
1495 * also want to make sure these supported hugepage
1496 * sizes are applicable across the entire range of memory
1497 * we may boot from, so we take the min across all
1498 * backends, and assume normal pages in cases where a
1499 * backend isn't backed by hugepages.
1501 memdev_root = object_resolve_path("/objects", NULL);
1502 if (memdev_root) {
1503 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1505 if (hpsize == LONG_MAX) {
1506 /* No additional memory regions found ==> Report main RAM page size */
1507 return mainrampagesize;
1510 /* If NUMA is disabled or the NUMA nodes are not backed with a
1511 * memory-backend, then there is at least one node using "normal" RAM,
1512 * so if its page size is smaller we have got to report that size instead.
1514 if (hpsize > mainrampagesize &&
1515 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1516 static bool warned;
1517 if (!warned) {
1518 error_report("Huge page support disabled (n/a for main memory).");
1519 warned = true;
1521 return mainrampagesize;
1524 return hpsize;
1526 #else
1527 long qemu_getrampagesize(void)
1529 return getpagesize();
1531 #endif
1533 #ifdef __linux__
1534 static int64_t get_file_size(int fd)
1536 int64_t size = lseek(fd, 0, SEEK_END);
1537 if (size < 0) {
1538 return -errno;
1540 return size;
1543 static int file_ram_open(const char *path,
1544 const char *region_name,
1545 bool *created,
1546 Error **errp)
1548 char *filename;
1549 char *sanitized_name;
1550 char *c;
1551 int fd = -1;
1553 *created = false;
1554 for (;;) {
1555 fd = open(path, O_RDWR);
1556 if (fd >= 0) {
1557 /* @path names an existing file, use it */
1558 break;
1560 if (errno == ENOENT) {
1561 /* @path names a file that doesn't exist, create it */
1562 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1563 if (fd >= 0) {
1564 *created = true;
1565 break;
1567 } else if (errno == EISDIR) {
1568 /* @path names a directory, create a file there */
1569 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1570 sanitized_name = g_strdup(region_name);
1571 for (c = sanitized_name; *c != '\0'; c++) {
1572 if (*c == '/') {
1573 *c = '_';
1577 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1578 sanitized_name);
1579 g_free(sanitized_name);
1581 fd = mkstemp(filename);
1582 if (fd >= 0) {
1583 unlink(filename);
1584 g_free(filename);
1585 break;
1587 g_free(filename);
1589 if (errno != EEXIST && errno != EINTR) {
1590 error_setg_errno(errp, errno,
1591 "can't open backing store %s for guest RAM",
1592 path);
1593 return -1;
1596 * Try again on EINTR and EEXIST. The latter happens when
1597 * something else creates the file between our two open().
1601 return fd;
1604 static void *file_ram_alloc(RAMBlock *block,
1605 ram_addr_t memory,
1606 int fd,
1607 bool truncate,
1608 Error **errp)
1610 void *area;
1612 block->page_size = qemu_fd_getpagesize(fd);
1613 block->mr->align = block->page_size;
1614 #if defined(__s390x__)
1615 if (kvm_enabled()) {
1616 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1618 #endif
1620 if (memory < block->page_size) {
1621 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1622 "or larger than page size 0x%zx",
1623 memory, block->page_size);
1624 return NULL;
1627 memory = ROUND_UP(memory, block->page_size);
1630 * ftruncate is not supported by hugetlbfs in older
1631 * hosts, so don't bother bailing out on errors.
1632 * If anything goes wrong with it under other filesystems,
1633 * mmap will fail.
1635 * Do not truncate the non-empty backend file to avoid corrupting
1636 * the existing data in the file. Disabling shrinking is not
1637 * enough. For example, the current vNVDIMM implementation stores
1638 * the guest NVDIMM labels at the end of the backend file. If the
1639 * backend file is later extended, QEMU will not be able to find
1640 * those labels. Therefore, extending the non-empty backend file
1641 * is disabled as well.
1643 if (truncate && ftruncate(fd, memory)) {
1644 perror("ftruncate");
1647 area = qemu_ram_mmap(fd, memory, block->mr->align,
1648 block->flags & RAM_SHARED);
1649 if (area == MAP_FAILED) {
1650 error_setg_errno(errp, errno,
1651 "unable to map backing store for guest RAM");
1652 return NULL;
1655 if (mem_prealloc) {
1656 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1657 if (errp && *errp) {
1658 qemu_ram_munmap(area, memory);
1659 return NULL;
1663 block->fd = fd;
1664 return area;
1666 #endif
1668 /* Called with the ramlist lock held. */
1669 static ram_addr_t find_ram_offset(ram_addr_t size)
1671 RAMBlock *block, *next_block;
1672 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1674 assert(size != 0); /* it would hand out same offset multiple times */
1676 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1677 return 0;
1680 RAMBLOCK_FOREACH(block) {
1681 ram_addr_t end, next = RAM_ADDR_MAX;
1683 end = block->offset + block->max_length;
1685 RAMBLOCK_FOREACH(next_block) {
1686 if (next_block->offset >= end) {
1687 next = MIN(next, next_block->offset);
1690 if (next - end >= size && next - end < mingap) {
1691 offset = end;
1692 mingap = next - end;
1696 if (offset == RAM_ADDR_MAX) {
1697 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1698 (uint64_t)size);
1699 abort();
1702 return offset;
1705 unsigned long last_ram_page(void)
1707 RAMBlock *block;
1708 ram_addr_t last = 0;
1710 rcu_read_lock();
1711 RAMBLOCK_FOREACH(block) {
1712 last = MAX(last, block->offset + block->max_length);
1714 rcu_read_unlock();
1715 return last >> TARGET_PAGE_BITS;
1718 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1720 int ret;
1722 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1723 if (!machine_dump_guest_core(current_machine)) {
1724 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1725 if (ret) {
1726 perror("qemu_madvise");
1727 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1728 "but dump_guest_core=off specified\n");
1733 const char *qemu_ram_get_idstr(RAMBlock *rb)
1735 return rb->idstr;
1738 bool qemu_ram_is_shared(RAMBlock *rb)
1740 return rb->flags & RAM_SHARED;
1743 /* Called with iothread lock held. */
1744 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1746 RAMBlock *block;
1748 assert(new_block);
1749 assert(!new_block->idstr[0]);
1751 if (dev) {
1752 char *id = qdev_get_dev_path(dev);
1753 if (id) {
1754 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1755 g_free(id);
1758 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1760 rcu_read_lock();
1761 RAMBLOCK_FOREACH(block) {
1762 if (block != new_block &&
1763 !strcmp(block->idstr, new_block->idstr)) {
1764 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1765 new_block->idstr);
1766 abort();
1769 rcu_read_unlock();
1772 /* Called with iothread lock held. */
1773 void qemu_ram_unset_idstr(RAMBlock *block)
1775 /* FIXME: arch_init.c assumes that this is not called throughout
1776 * migration. Ignore the problem since hot-unplug during migration
1777 * does not work anyway.
1779 if (block) {
1780 memset(block->idstr, 0, sizeof(block->idstr));
1784 size_t qemu_ram_pagesize(RAMBlock *rb)
1786 return rb->page_size;
1789 /* Returns the largest size of page in use */
1790 size_t qemu_ram_pagesize_largest(void)
1792 RAMBlock *block;
1793 size_t largest = 0;
1795 RAMBLOCK_FOREACH(block) {
1796 largest = MAX(largest, qemu_ram_pagesize(block));
1799 return largest;
1802 static int memory_try_enable_merging(void *addr, size_t len)
1804 if (!machine_mem_merge(current_machine)) {
1805 /* disabled by the user */
1806 return 0;
1809 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1812 /* Only legal before guest might have detected the memory size: e.g. on
1813 * incoming migration, or right after reset.
1815 * As memory core doesn't know how is memory accessed, it is up to
1816 * resize callback to update device state and/or add assertions to detect
1817 * misuse, if necessary.
1819 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1821 assert(block);
1823 newsize = HOST_PAGE_ALIGN(newsize);
1825 if (block->used_length == newsize) {
1826 return 0;
1829 if (!(block->flags & RAM_RESIZEABLE)) {
1830 error_setg_errno(errp, EINVAL,
1831 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1832 " in != 0x" RAM_ADDR_FMT, block->idstr,
1833 newsize, block->used_length);
1834 return -EINVAL;
1837 if (block->max_length < newsize) {
1838 error_setg_errno(errp, EINVAL,
1839 "Length too large: %s: 0x" RAM_ADDR_FMT
1840 " > 0x" RAM_ADDR_FMT, block->idstr,
1841 newsize, block->max_length);
1842 return -EINVAL;
1845 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1846 block->used_length = newsize;
1847 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1848 DIRTY_CLIENTS_ALL);
1849 memory_region_set_size(block->mr, newsize);
1850 if (block->resized) {
1851 block->resized(block->idstr, newsize, block->host);
1853 return 0;
1856 /* Called with ram_list.mutex held */
1857 static void dirty_memory_extend(ram_addr_t old_ram_size,
1858 ram_addr_t new_ram_size)
1860 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1861 DIRTY_MEMORY_BLOCK_SIZE);
1862 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1863 DIRTY_MEMORY_BLOCK_SIZE);
1864 int i;
1866 /* Only need to extend if block count increased */
1867 if (new_num_blocks <= old_num_blocks) {
1868 return;
1871 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1872 DirtyMemoryBlocks *old_blocks;
1873 DirtyMemoryBlocks *new_blocks;
1874 int j;
1876 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1877 new_blocks = g_malloc(sizeof(*new_blocks) +
1878 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1880 if (old_num_blocks) {
1881 memcpy(new_blocks->blocks, old_blocks->blocks,
1882 old_num_blocks * sizeof(old_blocks->blocks[0]));
1885 for (j = old_num_blocks; j < new_num_blocks; j++) {
1886 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1889 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1891 if (old_blocks) {
1892 g_free_rcu(old_blocks, rcu);
1897 static void ram_block_add(RAMBlock *new_block, Error **errp)
1899 RAMBlock *block;
1900 RAMBlock *last_block = NULL;
1901 ram_addr_t old_ram_size, new_ram_size;
1902 Error *err = NULL;
1904 old_ram_size = last_ram_page();
1906 qemu_mutex_lock_ramlist();
1907 new_block->offset = find_ram_offset(new_block->max_length);
1909 if (!new_block->host) {
1910 if (xen_enabled()) {
1911 xen_ram_alloc(new_block->offset, new_block->max_length,
1912 new_block->mr, &err);
1913 if (err) {
1914 error_propagate(errp, err);
1915 qemu_mutex_unlock_ramlist();
1916 return;
1918 } else {
1919 new_block->host = phys_mem_alloc(new_block->max_length,
1920 &new_block->mr->align);
1921 if (!new_block->host) {
1922 error_setg_errno(errp, errno,
1923 "cannot set up guest memory '%s'",
1924 memory_region_name(new_block->mr));
1925 qemu_mutex_unlock_ramlist();
1926 return;
1928 memory_try_enable_merging(new_block->host, new_block->max_length);
1932 new_ram_size = MAX(old_ram_size,
1933 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1934 if (new_ram_size > old_ram_size) {
1935 dirty_memory_extend(old_ram_size, new_ram_size);
1937 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1938 * QLIST (which has an RCU-friendly variant) does not have insertion at
1939 * tail, so save the last element in last_block.
1941 RAMBLOCK_FOREACH(block) {
1942 last_block = block;
1943 if (block->max_length < new_block->max_length) {
1944 break;
1947 if (block) {
1948 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1949 } else if (last_block) {
1950 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1951 } else { /* list is empty */
1952 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1954 ram_list.mru_block = NULL;
1956 /* Write list before version */
1957 smp_wmb();
1958 ram_list.version++;
1959 qemu_mutex_unlock_ramlist();
1961 cpu_physical_memory_set_dirty_range(new_block->offset,
1962 new_block->used_length,
1963 DIRTY_CLIENTS_ALL);
1965 if (new_block->host) {
1966 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1967 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1968 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1969 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1970 ram_block_notify_add(new_block->host, new_block->max_length);
1974 #ifdef __linux__
1975 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
1976 bool share, int fd,
1977 Error **errp)
1979 RAMBlock *new_block;
1980 Error *local_err = NULL;
1981 int64_t file_size;
1983 if (xen_enabled()) {
1984 error_setg(errp, "-mem-path not supported with Xen");
1985 return NULL;
1988 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1989 error_setg(errp,
1990 "host lacks kvm mmu notifiers, -mem-path unsupported");
1991 return NULL;
1994 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1996 * file_ram_alloc() needs to allocate just like
1997 * phys_mem_alloc, but we haven't bothered to provide
1998 * a hook there.
2000 error_setg(errp,
2001 "-mem-path not supported with this accelerator");
2002 return NULL;
2005 size = HOST_PAGE_ALIGN(size);
2006 file_size = get_file_size(fd);
2007 if (file_size > 0 && file_size < size) {
2008 error_setg(errp, "backing store %s size 0x%" PRIx64
2009 " does not match 'size' option 0x" RAM_ADDR_FMT,
2010 mem_path, file_size, size);
2011 return NULL;
2014 new_block = g_malloc0(sizeof(*new_block));
2015 new_block->mr = mr;
2016 new_block->used_length = size;
2017 new_block->max_length = size;
2018 new_block->flags = share ? RAM_SHARED : 0;
2019 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2020 if (!new_block->host) {
2021 g_free(new_block);
2022 return NULL;
2025 ram_block_add(new_block, &local_err);
2026 if (local_err) {
2027 g_free(new_block);
2028 error_propagate(errp, local_err);
2029 return NULL;
2031 return new_block;
2036 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2037 bool share, const char *mem_path,
2038 Error **errp)
2040 int fd;
2041 bool created;
2042 RAMBlock *block;
2044 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2045 if (fd < 0) {
2046 return NULL;
2049 block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
2050 if (!block) {
2051 if (created) {
2052 unlink(mem_path);
2054 close(fd);
2055 return NULL;
2058 return block;
2060 #endif
2062 static
2063 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2064 void (*resized)(const char*,
2065 uint64_t length,
2066 void *host),
2067 void *host, bool resizeable,
2068 MemoryRegion *mr, Error **errp)
2070 RAMBlock *new_block;
2071 Error *local_err = NULL;
2073 size = HOST_PAGE_ALIGN(size);
2074 max_size = HOST_PAGE_ALIGN(max_size);
2075 new_block = g_malloc0(sizeof(*new_block));
2076 new_block->mr = mr;
2077 new_block->resized = resized;
2078 new_block->used_length = size;
2079 new_block->max_length = max_size;
2080 assert(max_size >= size);
2081 new_block->fd = -1;
2082 new_block->page_size = getpagesize();
2083 new_block->host = host;
2084 if (host) {
2085 new_block->flags |= RAM_PREALLOC;
2087 if (resizeable) {
2088 new_block->flags |= RAM_RESIZEABLE;
2090 ram_block_add(new_block, &local_err);
2091 if (local_err) {
2092 g_free(new_block);
2093 error_propagate(errp, local_err);
2094 return NULL;
2096 return new_block;
2099 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2100 MemoryRegion *mr, Error **errp)
2102 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
2105 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
2107 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
2110 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2111 void (*resized)(const char*,
2112 uint64_t length,
2113 void *host),
2114 MemoryRegion *mr, Error **errp)
2116 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
2119 static void reclaim_ramblock(RAMBlock *block)
2121 if (block->flags & RAM_PREALLOC) {
2123 } else if (xen_enabled()) {
2124 xen_invalidate_map_cache_entry(block->host);
2125 #ifndef _WIN32
2126 } else if (block->fd >= 0) {
2127 qemu_ram_munmap(block->host, block->max_length);
2128 close(block->fd);
2129 #endif
2130 } else {
2131 qemu_anon_ram_free(block->host, block->max_length);
2133 g_free(block);
2136 void qemu_ram_free(RAMBlock *block)
2138 if (!block) {
2139 return;
2142 if (block->host) {
2143 ram_block_notify_remove(block->host, block->max_length);
2146 qemu_mutex_lock_ramlist();
2147 QLIST_REMOVE_RCU(block, next);
2148 ram_list.mru_block = NULL;
2149 /* Write list before version */
2150 smp_wmb();
2151 ram_list.version++;
2152 call_rcu(block, reclaim_ramblock, rcu);
2153 qemu_mutex_unlock_ramlist();
2156 #ifndef _WIN32
2157 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2159 RAMBlock *block;
2160 ram_addr_t offset;
2161 int flags;
2162 void *area, *vaddr;
2164 RAMBLOCK_FOREACH(block) {
2165 offset = addr - block->offset;
2166 if (offset < block->max_length) {
2167 vaddr = ramblock_ptr(block, offset);
2168 if (block->flags & RAM_PREALLOC) {
2170 } else if (xen_enabled()) {
2171 abort();
2172 } else {
2173 flags = MAP_FIXED;
2174 if (block->fd >= 0) {
2175 flags |= (block->flags & RAM_SHARED ?
2176 MAP_SHARED : MAP_PRIVATE);
2177 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2178 flags, block->fd, offset);
2179 } else {
2181 * Remap needs to match alloc. Accelerators that
2182 * set phys_mem_alloc never remap. If they did,
2183 * we'd need a remap hook here.
2185 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2187 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2188 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2189 flags, -1, 0);
2191 if (area != vaddr) {
2192 fprintf(stderr, "Could not remap addr: "
2193 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
2194 length, addr);
2195 exit(1);
2197 memory_try_enable_merging(vaddr, length);
2198 qemu_ram_setup_dump(vaddr, length);
2203 #endif /* !_WIN32 */
2205 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2206 * This should not be used for general purpose DMA. Use address_space_map
2207 * or address_space_rw instead. For local memory (e.g. video ram) that the
2208 * device owns, use memory_region_get_ram_ptr.
2210 * Called within RCU critical section.
2212 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2214 RAMBlock *block = ram_block;
2216 if (block == NULL) {
2217 block = qemu_get_ram_block(addr);
2218 addr -= block->offset;
2221 if (xen_enabled() && block->host == NULL) {
2222 /* We need to check if the requested address is in the RAM
2223 * because we don't want to map the entire memory in QEMU.
2224 * In that case just map until the end of the page.
2226 if (block->offset == 0) {
2227 return xen_map_cache(addr, 0, 0, false);
2230 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2232 return ramblock_ptr(block, addr);
2235 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2236 * but takes a size argument.
2238 * Called within RCU critical section.
2240 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2241 hwaddr *size, bool lock)
2243 RAMBlock *block = ram_block;
2244 if (*size == 0) {
2245 return NULL;
2248 if (block == NULL) {
2249 block = qemu_get_ram_block(addr);
2250 addr -= block->offset;
2252 *size = MIN(*size, block->max_length - addr);
2254 if (xen_enabled() && block->host == NULL) {
2255 /* We need to check if the requested address is in the RAM
2256 * because we don't want to map the entire memory in QEMU.
2257 * In that case just map the requested area.
2259 if (block->offset == 0) {
2260 return xen_map_cache(addr, *size, lock, lock);
2263 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2266 return ramblock_ptr(block, addr);
2270 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2271 * in that RAMBlock.
2273 * ptr: Host pointer to look up
2274 * round_offset: If true round the result offset down to a page boundary
2275 * *ram_addr: set to result ram_addr
2276 * *offset: set to result offset within the RAMBlock
2278 * Returns: RAMBlock (or NULL if not found)
2280 * By the time this function returns, the returned pointer is not protected
2281 * by RCU anymore. If the caller is not within an RCU critical section and
2282 * does not hold the iothread lock, it must have other means of protecting the
2283 * pointer, such as a reference to the region that includes the incoming
2284 * ram_addr_t.
2286 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2287 ram_addr_t *offset)
2289 RAMBlock *block;
2290 uint8_t *host = ptr;
2292 if (xen_enabled()) {
2293 ram_addr_t ram_addr;
2294 rcu_read_lock();
2295 ram_addr = xen_ram_addr_from_mapcache(ptr);
2296 block = qemu_get_ram_block(ram_addr);
2297 if (block) {
2298 *offset = ram_addr - block->offset;
2300 rcu_read_unlock();
2301 return block;
2304 rcu_read_lock();
2305 block = atomic_rcu_read(&ram_list.mru_block);
2306 if (block && block->host && host - block->host < block->max_length) {
2307 goto found;
2310 RAMBLOCK_FOREACH(block) {
2311 /* This case append when the block is not mapped. */
2312 if (block->host == NULL) {
2313 continue;
2315 if (host - block->host < block->max_length) {
2316 goto found;
2320 rcu_read_unlock();
2321 return NULL;
2323 found:
2324 *offset = (host - block->host);
2325 if (round_offset) {
2326 *offset &= TARGET_PAGE_MASK;
2328 rcu_read_unlock();
2329 return block;
2333 * Finds the named RAMBlock
2335 * name: The name of RAMBlock to find
2337 * Returns: RAMBlock (or NULL if not found)
2339 RAMBlock *qemu_ram_block_by_name(const char *name)
2341 RAMBlock *block;
2343 RAMBLOCK_FOREACH(block) {
2344 if (!strcmp(name, block->idstr)) {
2345 return block;
2349 return NULL;
2352 /* Some of the softmmu routines need to translate from a host pointer
2353 (typically a TLB entry) back to a ram offset. */
2354 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2356 RAMBlock *block;
2357 ram_addr_t offset;
2359 block = qemu_ram_block_from_host(ptr, false, &offset);
2360 if (!block) {
2361 return RAM_ADDR_INVALID;
2364 return block->offset + offset;
2367 /* Called within RCU critical section. */
2368 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2369 CPUState *cpu,
2370 vaddr mem_vaddr,
2371 ram_addr_t ram_addr,
2372 unsigned size)
2374 ndi->cpu = cpu;
2375 ndi->ram_addr = ram_addr;
2376 ndi->mem_vaddr = mem_vaddr;
2377 ndi->size = size;
2378 ndi->locked = false;
2380 assert(tcg_enabled());
2381 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2382 ndi->locked = true;
2383 tb_lock();
2384 tb_invalidate_phys_page_fast(ram_addr, size);
2388 /* Called within RCU critical section. */
2389 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2391 if (ndi->locked) {
2392 tb_unlock();
2395 /* Set both VGA and migration bits for simplicity and to remove
2396 * the notdirty callback faster.
2398 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2399 DIRTY_CLIENTS_NOCODE);
2400 /* we remove the notdirty callback only if the code has been
2401 flushed */
2402 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2403 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2407 /* Called within RCU critical section. */
2408 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2409 uint64_t val, unsigned size)
2411 NotDirtyInfo ndi;
2413 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2414 ram_addr, size);
2416 switch (size) {
2417 case 1:
2418 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2419 break;
2420 case 2:
2421 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2422 break;
2423 case 4:
2424 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2425 break;
2426 case 8:
2427 stq_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2428 break;
2429 default:
2430 abort();
2432 memory_notdirty_write_complete(&ndi);
2435 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2436 unsigned size, bool is_write)
2438 return is_write;
2441 static const MemoryRegionOps notdirty_mem_ops = {
2442 .write = notdirty_mem_write,
2443 .valid.accepts = notdirty_mem_accepts,
2444 .endianness = DEVICE_NATIVE_ENDIAN,
2445 .valid = {
2446 .min_access_size = 1,
2447 .max_access_size = 8,
2448 .unaligned = false,
2450 .impl = {
2451 .min_access_size = 1,
2452 .max_access_size = 8,
2453 .unaligned = false,
2457 /* Generate a debug exception if a watchpoint has been hit. */
2458 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2460 CPUState *cpu = current_cpu;
2461 CPUClass *cc = CPU_GET_CLASS(cpu);
2462 target_ulong vaddr;
2463 CPUWatchpoint *wp;
2465 assert(tcg_enabled());
2466 if (cpu->watchpoint_hit) {
2467 /* We re-entered the check after replacing the TB. Now raise
2468 * the debug interrupt so that is will trigger after the
2469 * current instruction. */
2470 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2471 return;
2473 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2474 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2475 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2476 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2477 && (wp->flags & flags)) {
2478 if (flags == BP_MEM_READ) {
2479 wp->flags |= BP_WATCHPOINT_HIT_READ;
2480 } else {
2481 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2483 wp->hitaddr = vaddr;
2484 wp->hitattrs = attrs;
2485 if (!cpu->watchpoint_hit) {
2486 if (wp->flags & BP_CPU &&
2487 !cc->debug_check_watchpoint(cpu, wp)) {
2488 wp->flags &= ~BP_WATCHPOINT_HIT;
2489 continue;
2491 cpu->watchpoint_hit = wp;
2493 /* Both tb_lock and iothread_mutex will be reset when
2494 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2495 * back into the cpu_exec main loop.
2497 tb_lock();
2498 tb_check_watchpoint(cpu);
2499 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2500 cpu->exception_index = EXCP_DEBUG;
2501 cpu_loop_exit(cpu);
2502 } else {
2503 /* Force execution of one insn next time. */
2504 cpu->cflags_next_tb = 1 | curr_cflags();
2505 cpu_loop_exit_noexc(cpu);
2508 } else {
2509 wp->flags &= ~BP_WATCHPOINT_HIT;
2514 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2515 so these check for a hit then pass through to the normal out-of-line
2516 phys routines. */
2517 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2518 unsigned size, MemTxAttrs attrs)
2520 MemTxResult res;
2521 uint64_t data;
2522 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2523 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2525 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2526 switch (size) {
2527 case 1:
2528 data = address_space_ldub(as, addr, attrs, &res);
2529 break;
2530 case 2:
2531 data = address_space_lduw(as, addr, attrs, &res);
2532 break;
2533 case 4:
2534 data = address_space_ldl(as, addr, attrs, &res);
2535 break;
2536 case 8:
2537 data = address_space_ldq(as, addr, attrs, &res);
2538 break;
2539 default: abort();
2541 *pdata = data;
2542 return res;
2545 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2546 uint64_t val, unsigned size,
2547 MemTxAttrs attrs)
2549 MemTxResult res;
2550 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2551 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2553 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2554 switch (size) {
2555 case 1:
2556 address_space_stb(as, addr, val, attrs, &res);
2557 break;
2558 case 2:
2559 address_space_stw(as, addr, val, attrs, &res);
2560 break;
2561 case 4:
2562 address_space_stl(as, addr, val, attrs, &res);
2563 break;
2564 case 8:
2565 address_space_stq(as, addr, val, attrs, &res);
2566 break;
2567 default: abort();
2569 return res;
2572 static const MemoryRegionOps watch_mem_ops = {
2573 .read_with_attrs = watch_mem_read,
2574 .write_with_attrs = watch_mem_write,
2575 .endianness = DEVICE_NATIVE_ENDIAN,
2576 .valid = {
2577 .min_access_size = 1,
2578 .max_access_size = 8,
2579 .unaligned = false,
2581 .impl = {
2582 .min_access_size = 1,
2583 .max_access_size = 8,
2584 .unaligned = false,
2588 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2589 const uint8_t *buf, int len);
2590 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
2591 bool is_write);
2593 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2594 unsigned len, MemTxAttrs attrs)
2596 subpage_t *subpage = opaque;
2597 uint8_t buf[8];
2598 MemTxResult res;
2600 #if defined(DEBUG_SUBPAGE)
2601 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2602 subpage, len, addr);
2603 #endif
2604 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2605 if (res) {
2606 return res;
2608 switch (len) {
2609 case 1:
2610 *data = ldub_p(buf);
2611 return MEMTX_OK;
2612 case 2:
2613 *data = lduw_p(buf);
2614 return MEMTX_OK;
2615 case 4:
2616 *data = ldl_p(buf);
2617 return MEMTX_OK;
2618 case 8:
2619 *data = ldq_p(buf);
2620 return MEMTX_OK;
2621 default:
2622 abort();
2626 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2627 uint64_t value, unsigned len, MemTxAttrs attrs)
2629 subpage_t *subpage = opaque;
2630 uint8_t buf[8];
2632 #if defined(DEBUG_SUBPAGE)
2633 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2634 " value %"PRIx64"\n",
2635 __func__, subpage, len, addr, value);
2636 #endif
2637 switch (len) {
2638 case 1:
2639 stb_p(buf, value);
2640 break;
2641 case 2:
2642 stw_p(buf, value);
2643 break;
2644 case 4:
2645 stl_p(buf, value);
2646 break;
2647 case 8:
2648 stq_p(buf, value);
2649 break;
2650 default:
2651 abort();
2653 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2656 static bool subpage_accepts(void *opaque, hwaddr addr,
2657 unsigned len, bool is_write)
2659 subpage_t *subpage = opaque;
2660 #if defined(DEBUG_SUBPAGE)
2661 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2662 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2663 #endif
2665 return flatview_access_valid(subpage->fv, addr + subpage->base,
2666 len, is_write);
2669 static const MemoryRegionOps subpage_ops = {
2670 .read_with_attrs = subpage_read,
2671 .write_with_attrs = subpage_write,
2672 .impl.min_access_size = 1,
2673 .impl.max_access_size = 8,
2674 .valid.min_access_size = 1,
2675 .valid.max_access_size = 8,
2676 .valid.accepts = subpage_accepts,
2677 .endianness = DEVICE_NATIVE_ENDIAN,
2680 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2681 uint16_t section)
2683 int idx, eidx;
2685 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2686 return -1;
2687 idx = SUBPAGE_IDX(start);
2688 eidx = SUBPAGE_IDX(end);
2689 #if defined(DEBUG_SUBPAGE)
2690 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2691 __func__, mmio, start, end, idx, eidx, section);
2692 #endif
2693 for (; idx <= eidx; idx++) {
2694 mmio->sub_section[idx] = section;
2697 return 0;
2700 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2702 subpage_t *mmio;
2704 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2705 mmio->fv = fv;
2706 mmio->base = base;
2707 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2708 NULL, TARGET_PAGE_SIZE);
2709 mmio->iomem.subpage = true;
2710 #if defined(DEBUG_SUBPAGE)
2711 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2712 mmio, base, TARGET_PAGE_SIZE);
2713 #endif
2714 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2716 return mmio;
2719 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2721 assert(fv);
2722 MemoryRegionSection section = {
2723 .fv = fv,
2724 .mr = mr,
2725 .offset_within_address_space = 0,
2726 .offset_within_region = 0,
2727 .size = int128_2_64(),
2730 return phys_section_add(map, &section);
2733 static void readonly_mem_write(void *opaque, hwaddr addr,
2734 uint64_t val, unsigned size)
2736 /* Ignore any write to ROM. */
2739 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
2740 unsigned size, bool is_write)
2742 return is_write;
2745 /* This will only be used for writes, because reads are special cased
2746 * to directly access the underlying host ram.
2748 static const MemoryRegionOps readonly_mem_ops = {
2749 .write = readonly_mem_write,
2750 .valid.accepts = readonly_mem_accepts,
2751 .endianness = DEVICE_NATIVE_ENDIAN,
2752 .valid = {
2753 .min_access_size = 1,
2754 .max_access_size = 8,
2755 .unaligned = false,
2757 .impl = {
2758 .min_access_size = 1,
2759 .max_access_size = 8,
2760 .unaligned = false,
2764 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2766 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2767 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2768 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2769 MemoryRegionSection *sections = d->map.sections;
2771 return sections[index & ~TARGET_PAGE_MASK].mr;
2774 static void io_mem_init(void)
2776 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
2777 NULL, NULL, UINT64_MAX);
2778 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2779 NULL, UINT64_MAX);
2781 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2782 * which can be called without the iothread mutex.
2784 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2785 NULL, UINT64_MAX);
2786 memory_region_clear_global_locking(&io_mem_notdirty);
2788 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2789 NULL, UINT64_MAX);
2792 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2794 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2795 uint16_t n;
2797 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2798 assert(n == PHYS_SECTION_UNASSIGNED);
2799 n = dummy_section(&d->map, fv, &io_mem_notdirty);
2800 assert(n == PHYS_SECTION_NOTDIRTY);
2801 n = dummy_section(&d->map, fv, &io_mem_rom);
2802 assert(n == PHYS_SECTION_ROM);
2803 n = dummy_section(&d->map, fv, &io_mem_watch);
2804 assert(n == PHYS_SECTION_WATCH);
2806 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2808 return d;
2811 void address_space_dispatch_free(AddressSpaceDispatch *d)
2813 phys_sections_free(&d->map);
2814 g_free(d);
2817 static void tcg_commit(MemoryListener *listener)
2819 CPUAddressSpace *cpuas;
2820 AddressSpaceDispatch *d;
2822 /* since each CPU stores ram addresses in its TLB cache, we must
2823 reset the modified entries */
2824 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2825 cpu_reloading_memory_map();
2826 /* The CPU and TLB are protected by the iothread lock.
2827 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2828 * may have split the RCU critical section.
2830 d = address_space_to_dispatch(cpuas->as);
2831 atomic_rcu_set(&cpuas->memory_dispatch, d);
2832 tlb_flush(cpuas->cpu);
2835 static void memory_map_init(void)
2837 system_memory = g_malloc(sizeof(*system_memory));
2839 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2840 address_space_init(&address_space_memory, system_memory, "memory");
2842 system_io = g_malloc(sizeof(*system_io));
2843 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2844 65536);
2845 address_space_init(&address_space_io, system_io, "I/O");
2848 MemoryRegion *get_system_memory(void)
2850 return system_memory;
2853 MemoryRegion *get_system_io(void)
2855 return system_io;
2858 #endif /* !defined(CONFIG_USER_ONLY) */
2860 /* physical memory access (slow version, mainly for debug) */
2861 #if defined(CONFIG_USER_ONLY)
2862 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2863 uint8_t *buf, int len, int is_write)
2865 int l, flags;
2866 target_ulong page;
2867 void * p;
2869 while (len > 0) {
2870 page = addr & TARGET_PAGE_MASK;
2871 l = (page + TARGET_PAGE_SIZE) - addr;
2872 if (l > len)
2873 l = len;
2874 flags = page_get_flags(page);
2875 if (!(flags & PAGE_VALID))
2876 return -1;
2877 if (is_write) {
2878 if (!(flags & PAGE_WRITE))
2879 return -1;
2880 /* XXX: this code should not depend on lock_user */
2881 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2882 return -1;
2883 memcpy(p, buf, l);
2884 unlock_user(p, addr, l);
2885 } else {
2886 if (!(flags & PAGE_READ))
2887 return -1;
2888 /* XXX: this code should not depend on lock_user */
2889 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2890 return -1;
2891 memcpy(buf, p, l);
2892 unlock_user(p, addr, 0);
2894 len -= l;
2895 buf += l;
2896 addr += l;
2898 return 0;
2901 #else
2903 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2904 hwaddr length)
2906 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2907 addr += memory_region_get_ram_addr(mr);
2909 /* No early return if dirty_log_mask is or becomes 0, because
2910 * cpu_physical_memory_set_dirty_range will still call
2911 * xen_modified_memory.
2913 if (dirty_log_mask) {
2914 dirty_log_mask =
2915 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2917 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2918 assert(tcg_enabled());
2919 tb_lock();
2920 tb_invalidate_phys_range(addr, addr + length);
2921 tb_unlock();
2922 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2924 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2927 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2929 unsigned access_size_max = mr->ops->valid.max_access_size;
2931 /* Regions are assumed to support 1-4 byte accesses unless
2932 otherwise specified. */
2933 if (access_size_max == 0) {
2934 access_size_max = 4;
2937 /* Bound the maximum access by the alignment of the address. */
2938 if (!mr->ops->impl.unaligned) {
2939 unsigned align_size_max = addr & -addr;
2940 if (align_size_max != 0 && align_size_max < access_size_max) {
2941 access_size_max = align_size_max;
2945 /* Don't attempt accesses larger than the maximum. */
2946 if (l > access_size_max) {
2947 l = access_size_max;
2949 l = pow2floor(l);
2951 return l;
2954 static bool prepare_mmio_access(MemoryRegion *mr)
2956 bool unlocked = !qemu_mutex_iothread_locked();
2957 bool release_lock = false;
2959 if (unlocked && mr->global_locking) {
2960 qemu_mutex_lock_iothread();
2961 unlocked = false;
2962 release_lock = true;
2964 if (mr->flush_coalesced_mmio) {
2965 if (unlocked) {
2966 qemu_mutex_lock_iothread();
2968 qemu_flush_coalesced_mmio_buffer();
2969 if (unlocked) {
2970 qemu_mutex_unlock_iothread();
2974 return release_lock;
2977 /* Called within RCU critical section. */
2978 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
2979 MemTxAttrs attrs,
2980 const uint8_t *buf,
2981 int len, hwaddr addr1,
2982 hwaddr l, MemoryRegion *mr)
2984 uint8_t *ptr;
2985 uint64_t val;
2986 MemTxResult result = MEMTX_OK;
2987 bool release_lock = false;
2989 for (;;) {
2990 if (!memory_access_is_direct(mr, true)) {
2991 release_lock |= prepare_mmio_access(mr);
2992 l = memory_access_size(mr, l, addr1);
2993 /* XXX: could force current_cpu to NULL to avoid
2994 potential bugs */
2995 switch (l) {
2996 case 8:
2997 /* 64 bit write access */
2998 val = ldq_p(buf);
2999 result |= memory_region_dispatch_write(mr, addr1, val, 8,
3000 attrs);
3001 break;
3002 case 4:
3003 /* 32 bit write access */
3004 val = (uint32_t)ldl_p(buf);
3005 result |= memory_region_dispatch_write(mr, addr1, val, 4,
3006 attrs);
3007 break;
3008 case 2:
3009 /* 16 bit write access */
3010 val = lduw_p(buf);
3011 result |= memory_region_dispatch_write(mr, addr1, val, 2,
3012 attrs);
3013 break;
3014 case 1:
3015 /* 8 bit write access */
3016 val = ldub_p(buf);
3017 result |= memory_region_dispatch_write(mr, addr1, val, 1,
3018 attrs);
3019 break;
3020 default:
3021 abort();
3023 } else {
3024 /* RAM case */
3025 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3026 memcpy(ptr, buf, l);
3027 invalidate_and_set_dirty(mr, addr1, l);
3030 if (release_lock) {
3031 qemu_mutex_unlock_iothread();
3032 release_lock = false;
3035 len -= l;
3036 buf += l;
3037 addr += l;
3039 if (!len) {
3040 break;
3043 l = len;
3044 mr = flatview_translate(fv, addr, &addr1, &l, true);
3047 return result;
3050 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3051 const uint8_t *buf, int len)
3053 hwaddr l;
3054 hwaddr addr1;
3055 MemoryRegion *mr;
3056 MemTxResult result = MEMTX_OK;
3058 if (len > 0) {
3059 rcu_read_lock();
3060 l = len;
3061 mr = flatview_translate(fv, addr, &addr1, &l, true);
3062 result = flatview_write_continue(fv, addr, attrs, buf, len,
3063 addr1, l, mr);
3064 rcu_read_unlock();
3067 return result;
3070 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3071 MemTxAttrs attrs,
3072 const uint8_t *buf, int len)
3074 return flatview_write(address_space_to_flatview(as), addr, attrs, buf, len);
3077 /* Called within RCU critical section. */
3078 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3079 MemTxAttrs attrs, uint8_t *buf,
3080 int len, hwaddr addr1, hwaddr l,
3081 MemoryRegion *mr)
3083 uint8_t *ptr;
3084 uint64_t val;
3085 MemTxResult result = MEMTX_OK;
3086 bool release_lock = false;
3088 for (;;) {
3089 if (!memory_access_is_direct(mr, false)) {
3090 /* I/O case */
3091 release_lock |= prepare_mmio_access(mr);
3092 l = memory_access_size(mr, l, addr1);
3093 switch (l) {
3094 case 8:
3095 /* 64 bit read access */
3096 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
3097 attrs);
3098 stq_p(buf, val);
3099 break;
3100 case 4:
3101 /* 32 bit read access */
3102 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
3103 attrs);
3104 stl_p(buf, val);
3105 break;
3106 case 2:
3107 /* 16 bit read access */
3108 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
3109 attrs);
3110 stw_p(buf, val);
3111 break;
3112 case 1:
3113 /* 8 bit read access */
3114 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
3115 attrs);
3116 stb_p(buf, val);
3117 break;
3118 default:
3119 abort();
3121 } else {
3122 /* RAM case */
3123 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3124 memcpy(buf, ptr, l);
3127 if (release_lock) {
3128 qemu_mutex_unlock_iothread();
3129 release_lock = false;
3132 len -= l;
3133 buf += l;
3134 addr += l;
3136 if (!len) {
3137 break;
3140 l = len;
3141 mr = flatview_translate(fv, addr, &addr1, &l, false);
3144 return result;
3147 MemTxResult flatview_read_full(FlatView *fv, hwaddr addr,
3148 MemTxAttrs attrs, uint8_t *buf, int len)
3150 hwaddr l;
3151 hwaddr addr1;
3152 MemoryRegion *mr;
3153 MemTxResult result = MEMTX_OK;
3155 if (len > 0) {
3156 rcu_read_lock();
3157 l = len;
3158 mr = flatview_translate(fv, addr, &addr1, &l, false);
3159 result = flatview_read_continue(fv, addr, attrs, buf, len,
3160 addr1, l, mr);
3161 rcu_read_unlock();
3164 return result;
3167 static MemTxResult flatview_rw(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3168 uint8_t *buf, int len, bool is_write)
3170 if (is_write) {
3171 return flatview_write(fv, addr, attrs, (uint8_t *)buf, len);
3172 } else {
3173 return flatview_read(fv, addr, attrs, (uint8_t *)buf, len);
3177 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr,
3178 MemTxAttrs attrs, uint8_t *buf,
3179 int len, bool is_write)
3181 return flatview_rw(address_space_to_flatview(as),
3182 addr, attrs, buf, len, is_write);
3185 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3186 int len, int is_write)
3188 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3189 buf, len, is_write);
3192 enum write_rom_type {
3193 WRITE_DATA,
3194 FLUSH_CACHE,
3197 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3198 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3200 hwaddr l;
3201 uint8_t *ptr;
3202 hwaddr addr1;
3203 MemoryRegion *mr;
3205 rcu_read_lock();
3206 while (len > 0) {
3207 l = len;
3208 mr = address_space_translate(as, addr, &addr1, &l, true);
3210 if (!(memory_region_is_ram(mr) ||
3211 memory_region_is_romd(mr))) {
3212 l = memory_access_size(mr, l, addr1);
3213 } else {
3214 /* ROM/RAM case */
3215 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3216 switch (type) {
3217 case WRITE_DATA:
3218 memcpy(ptr, buf, l);
3219 invalidate_and_set_dirty(mr, addr1, l);
3220 break;
3221 case FLUSH_CACHE:
3222 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3223 break;
3226 len -= l;
3227 buf += l;
3228 addr += l;
3230 rcu_read_unlock();
3233 /* used for ROM loading : can write in RAM and ROM */
3234 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3235 const uint8_t *buf, int len)
3237 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3240 void cpu_flush_icache_range(hwaddr start, int len)
3243 * This function should do the same thing as an icache flush that was
3244 * triggered from within the guest. For TCG we are always cache coherent,
3245 * so there is no need to flush anything. For KVM / Xen we need to flush
3246 * the host's instruction cache at least.
3248 if (tcg_enabled()) {
3249 return;
3252 cpu_physical_memory_write_rom_internal(&address_space_memory,
3253 start, NULL, len, FLUSH_CACHE);
3256 typedef struct {
3257 MemoryRegion *mr;
3258 void *buffer;
3259 hwaddr addr;
3260 hwaddr len;
3261 bool in_use;
3262 } BounceBuffer;
3264 static BounceBuffer bounce;
3266 typedef struct MapClient {
3267 QEMUBH *bh;
3268 QLIST_ENTRY(MapClient) link;
3269 } MapClient;
3271 QemuMutex map_client_list_lock;
3272 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3273 = QLIST_HEAD_INITIALIZER(map_client_list);
3275 static void cpu_unregister_map_client_do(MapClient *client)
3277 QLIST_REMOVE(client, link);
3278 g_free(client);
3281 static void cpu_notify_map_clients_locked(void)
3283 MapClient *client;
3285 while (!QLIST_EMPTY(&map_client_list)) {
3286 client = QLIST_FIRST(&map_client_list);
3287 qemu_bh_schedule(client->bh);
3288 cpu_unregister_map_client_do(client);
3292 void cpu_register_map_client(QEMUBH *bh)
3294 MapClient *client = g_malloc(sizeof(*client));
3296 qemu_mutex_lock(&map_client_list_lock);
3297 client->bh = bh;
3298 QLIST_INSERT_HEAD(&map_client_list, client, link);
3299 if (!atomic_read(&bounce.in_use)) {
3300 cpu_notify_map_clients_locked();
3302 qemu_mutex_unlock(&map_client_list_lock);
3305 void cpu_exec_init_all(void)
3307 qemu_mutex_init(&ram_list.mutex);
3308 /* The data structures we set up here depend on knowing the page size,
3309 * so no more changes can be made after this point.
3310 * In an ideal world, nothing we did before we had finished the
3311 * machine setup would care about the target page size, and we could
3312 * do this much later, rather than requiring board models to state
3313 * up front what their requirements are.
3315 finalize_target_page_bits();
3316 io_mem_init();
3317 memory_map_init();
3318 qemu_mutex_init(&map_client_list_lock);
3321 void cpu_unregister_map_client(QEMUBH *bh)
3323 MapClient *client;
3325 qemu_mutex_lock(&map_client_list_lock);
3326 QLIST_FOREACH(client, &map_client_list, link) {
3327 if (client->bh == bh) {
3328 cpu_unregister_map_client_do(client);
3329 break;
3332 qemu_mutex_unlock(&map_client_list_lock);
3335 static void cpu_notify_map_clients(void)
3337 qemu_mutex_lock(&map_client_list_lock);
3338 cpu_notify_map_clients_locked();
3339 qemu_mutex_unlock(&map_client_list_lock);
3342 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
3343 bool is_write)
3345 MemoryRegion *mr;
3346 hwaddr l, xlat;
3348 rcu_read_lock();
3349 while (len > 0) {
3350 l = len;
3351 mr = flatview_translate(fv, addr, &xlat, &l, is_write);
3352 if (!memory_access_is_direct(mr, is_write)) {
3353 l = memory_access_size(mr, l, addr);
3354 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3355 rcu_read_unlock();
3356 return false;
3360 len -= l;
3361 addr += l;
3363 rcu_read_unlock();
3364 return true;
3367 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3368 int len, bool is_write)
3370 return flatview_access_valid(address_space_to_flatview(as),
3371 addr, len, is_write);
3374 static hwaddr
3375 flatview_extend_translation(FlatView *fv, hwaddr addr,
3376 hwaddr target_len,
3377 MemoryRegion *mr, hwaddr base, hwaddr len,
3378 bool is_write)
3380 hwaddr done = 0;
3381 hwaddr xlat;
3382 MemoryRegion *this_mr;
3384 for (;;) {
3385 target_len -= len;
3386 addr += len;
3387 done += len;
3388 if (target_len == 0) {
3389 return done;
3392 len = target_len;
3393 this_mr = flatview_translate(fv, addr, &xlat,
3394 &len, is_write);
3395 if (this_mr != mr || xlat != base + done) {
3396 return done;
3401 /* Map a physical memory region into a host virtual address.
3402 * May map a subset of the requested range, given by and returned in *plen.
3403 * May return NULL if resources needed to perform the mapping are exhausted.
3404 * Use only for reads OR writes - not for read-modify-write operations.
3405 * Use cpu_register_map_client() to know when retrying the map operation is
3406 * likely to succeed.
3408 void *address_space_map(AddressSpace *as,
3409 hwaddr addr,
3410 hwaddr *plen,
3411 bool is_write)
3413 hwaddr len = *plen;
3414 hwaddr l, xlat;
3415 MemoryRegion *mr;
3416 void *ptr;
3417 FlatView *fv = address_space_to_flatview(as);
3419 if (len == 0) {
3420 return NULL;
3423 l = len;
3424 rcu_read_lock();
3425 mr = flatview_translate(fv, addr, &xlat, &l, is_write);
3427 if (!memory_access_is_direct(mr, is_write)) {
3428 if (atomic_xchg(&bounce.in_use, true)) {
3429 rcu_read_unlock();
3430 return NULL;
3432 /* Avoid unbounded allocations */
3433 l = MIN(l, TARGET_PAGE_SIZE);
3434 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3435 bounce.addr = addr;
3436 bounce.len = l;
3438 memory_region_ref(mr);
3439 bounce.mr = mr;
3440 if (!is_write) {
3441 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3442 bounce.buffer, l);
3445 rcu_read_unlock();
3446 *plen = l;
3447 return bounce.buffer;
3451 memory_region_ref(mr);
3452 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3453 l, is_write);
3454 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3455 rcu_read_unlock();
3457 return ptr;
3460 /* Unmaps a memory region previously mapped by address_space_map().
3461 * Will also mark the memory as dirty if is_write == 1. access_len gives
3462 * the amount of memory that was actually read or written by the caller.
3464 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3465 int is_write, hwaddr access_len)
3467 if (buffer != bounce.buffer) {
3468 MemoryRegion *mr;
3469 ram_addr_t addr1;
3471 mr = memory_region_from_host(buffer, &addr1);
3472 assert(mr != NULL);
3473 if (is_write) {
3474 invalidate_and_set_dirty(mr, addr1, access_len);
3476 if (xen_enabled()) {
3477 xen_invalidate_map_cache_entry(buffer);
3479 memory_region_unref(mr);
3480 return;
3482 if (is_write) {
3483 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3484 bounce.buffer, access_len);
3486 qemu_vfree(bounce.buffer);
3487 bounce.buffer = NULL;
3488 memory_region_unref(bounce.mr);
3489 atomic_mb_set(&bounce.in_use, false);
3490 cpu_notify_map_clients();
3493 void *cpu_physical_memory_map(hwaddr addr,
3494 hwaddr *plen,
3495 int is_write)
3497 return address_space_map(&address_space_memory, addr, plen, is_write);
3500 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3501 int is_write, hwaddr access_len)
3503 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3506 #define ARG1_DECL AddressSpace *as
3507 #define ARG1 as
3508 #define SUFFIX
3509 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3510 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3511 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3512 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3513 #define RCU_READ_LOCK(...) rcu_read_lock()
3514 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3515 #include "memory_ldst.inc.c"
3517 int64_t address_space_cache_init(MemoryRegionCache *cache,
3518 AddressSpace *as,
3519 hwaddr addr,
3520 hwaddr len,
3521 bool is_write)
3523 cache->len = len;
3524 cache->as = as;
3525 cache->xlat = addr;
3526 return len;
3529 void address_space_cache_invalidate(MemoryRegionCache *cache,
3530 hwaddr addr,
3531 hwaddr access_len)
3535 void address_space_cache_destroy(MemoryRegionCache *cache)
3537 cache->as = NULL;
3540 #define ARG1_DECL MemoryRegionCache *cache
3541 #define ARG1 cache
3542 #define SUFFIX _cached
3543 #define TRANSLATE(addr, ...) \
3544 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3545 #define IS_DIRECT(mr, is_write) true
3546 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3547 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3548 #define RCU_READ_LOCK() rcu_read_lock()
3549 #define RCU_READ_UNLOCK() rcu_read_unlock()
3550 #include "memory_ldst.inc.c"
3552 /* virtual memory access for debug (includes writing to ROM) */
3553 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3554 uint8_t *buf, int len, int is_write)
3556 int l;
3557 hwaddr phys_addr;
3558 target_ulong page;
3560 cpu_synchronize_state(cpu);
3561 while (len > 0) {
3562 int asidx;
3563 MemTxAttrs attrs;
3565 page = addr & TARGET_PAGE_MASK;
3566 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3567 asidx = cpu_asidx_from_attrs(cpu, attrs);
3568 /* if no physical page mapped, return an error */
3569 if (phys_addr == -1)
3570 return -1;
3571 l = (page + TARGET_PAGE_SIZE) - addr;
3572 if (l > len)
3573 l = len;
3574 phys_addr += (addr & ~TARGET_PAGE_MASK);
3575 if (is_write) {
3576 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3577 phys_addr, buf, l);
3578 } else {
3579 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3580 MEMTXATTRS_UNSPECIFIED,
3581 buf, l, 0);
3583 len -= l;
3584 buf += l;
3585 addr += l;
3587 return 0;
3591 * Allows code that needs to deal with migration bitmaps etc to still be built
3592 * target independent.
3594 size_t qemu_target_page_size(void)
3596 return TARGET_PAGE_SIZE;
3599 int qemu_target_page_bits(void)
3601 return TARGET_PAGE_BITS;
3604 int qemu_target_page_bits_min(void)
3606 return TARGET_PAGE_BITS_MIN;
3608 #endif
3611 * A helper function for the _utterly broken_ virtio device model to find out if
3612 * it's running on a big endian machine. Don't do this at home kids!
3614 bool target_words_bigendian(void);
3615 bool target_words_bigendian(void)
3617 #if defined(TARGET_WORDS_BIGENDIAN)
3618 return true;
3619 #else
3620 return false;
3621 #endif
3624 #ifndef CONFIG_USER_ONLY
3625 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3627 MemoryRegion*mr;
3628 hwaddr l = 1;
3629 bool res;
3631 rcu_read_lock();
3632 mr = address_space_translate(&address_space_memory,
3633 phys_addr, &phys_addr, &l, false);
3635 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3636 rcu_read_unlock();
3637 return res;
3640 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3642 RAMBlock *block;
3643 int ret = 0;
3645 rcu_read_lock();
3646 RAMBLOCK_FOREACH(block) {
3647 ret = func(block->idstr, block->host, block->offset,
3648 block->used_length, opaque);
3649 if (ret) {
3650 break;
3653 rcu_read_unlock();
3654 return ret;
3658 * Unmap pages of memory from start to start+length such that
3659 * they a) read as 0, b) Trigger whatever fault mechanism
3660 * the OS provides for postcopy.
3661 * The pages must be unmapped by the end of the function.
3662 * Returns: 0 on success, none-0 on failure
3665 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3667 int ret = -1;
3669 uint8_t *host_startaddr = rb->host + start;
3671 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3672 error_report("ram_block_discard_range: Unaligned start address: %p",
3673 host_startaddr);
3674 goto err;
3677 if ((start + length) <= rb->used_length) {
3678 uint8_t *host_endaddr = host_startaddr + length;
3679 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3680 error_report("ram_block_discard_range: Unaligned end address: %p",
3681 host_endaddr);
3682 goto err;
3685 errno = ENOTSUP; /* If we are missing MADVISE etc */
3687 if (rb->page_size == qemu_host_page_size) {
3688 #if defined(CONFIG_MADVISE)
3689 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3690 * freeing the page.
3692 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3693 #endif
3694 } else {
3695 /* Huge page case - unfortunately it can't do DONTNEED, but
3696 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3697 * huge page file.
3699 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3700 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3701 start, length);
3702 #endif
3704 if (ret) {
3705 ret = -errno;
3706 error_report("ram_block_discard_range: Failed to discard range "
3707 "%s:%" PRIx64 " +%zx (%d)",
3708 rb->idstr, start, length, ret);
3710 } else {
3711 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3712 "/%zx/" RAM_ADDR_FMT")",
3713 rb->idstr, start, length, rb->used_length);
3716 err:
3717 return ret;
3720 #endif
3722 void page_size_init(void)
3724 /* NOTE: we can always suppose that qemu_host_page_size >=
3725 TARGET_PAGE_SIZE */
3726 if (qemu_host_page_size == 0) {
3727 qemu_host_page_size = qemu_real_host_page_size;
3729 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
3730 qemu_host_page_size = TARGET_PAGE_SIZE;
3732 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
3735 #if !defined(CONFIG_USER_ONLY)
3737 static void mtree_print_phys_entries(fprintf_function mon, void *f,
3738 int start, int end, int skip, int ptr)
3740 if (start == end - 1) {
3741 mon(f, "\t%3d ", start);
3742 } else {
3743 mon(f, "\t%3d..%-3d ", start, end - 1);
3745 mon(f, " skip=%d ", skip);
3746 if (ptr == PHYS_MAP_NODE_NIL) {
3747 mon(f, " ptr=NIL");
3748 } else if (!skip) {
3749 mon(f, " ptr=#%d", ptr);
3750 } else {
3751 mon(f, " ptr=[%d]", ptr);
3753 mon(f, "\n");
3756 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
3757 int128_sub((size), int128_one())) : 0)
3759 void mtree_print_dispatch(fprintf_function mon, void *f,
3760 AddressSpaceDispatch *d, MemoryRegion *root)
3762 int i;
3764 mon(f, " Dispatch\n");
3765 mon(f, " Physical sections\n");
3767 for (i = 0; i < d->map.sections_nb; ++i) {
3768 MemoryRegionSection *s = d->map.sections + i;
3769 const char *names[] = { " [unassigned]", " [not dirty]",
3770 " [ROM]", " [watch]" };
3772 mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s",
3774 s->offset_within_address_space,
3775 s->offset_within_address_space + MR_SIZE(s->mr->size),
3776 s->mr->name ? s->mr->name : "(noname)",
3777 i < ARRAY_SIZE(names) ? names[i] : "",
3778 s->mr == root ? " [ROOT]" : "",
3779 s == d->mru_section ? " [MRU]" : "",
3780 s->mr->is_iommu ? " [iommu]" : "");
3782 if (s->mr->alias) {
3783 mon(f, " alias=%s", s->mr->alias->name ?
3784 s->mr->alias->name : "noname");
3786 mon(f, "\n");
3789 mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
3790 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
3791 for (i = 0; i < d->map.nodes_nb; ++i) {
3792 int j, jprev;
3793 PhysPageEntry prev;
3794 Node *n = d->map.nodes + i;
3796 mon(f, " [%d]\n", i);
3798 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
3799 PhysPageEntry *pe = *n + j;
3801 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
3802 continue;
3805 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
3807 jprev = j;
3808 prev = *pe;
3811 if (jprev != ARRAY_SIZE(*n)) {
3812 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
3817 #endif