hw/ppc/mac_oldworld.c

   1
   2 /*
   3  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   4  *
   5  * Copyright (c) 2004-2007 Fabrice Bellard
   6  * Copyright (c) 2007 Jocelyn Mayer
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "qemu-common.h"
  29 #include "qemu/units.h"
  30 #include "qapi/error.h"
  31 #include "hw/ppc/ppc.h"
  32 #include "hw/qdev-properties.h"
  33 #include "mac.h"
  34 #include "hw/input/adb.h"
  35 #include "sysemu/sysemu.h"
  36 #include "net/net.h"
  37 #include "hw/isa/isa.h"
  38 #include "hw/pci/pci.h"
  39 #include "hw/pci/pci_host.h"
  40 #include "hw/boards.h"
  41 #include "hw/nvram/fw_cfg.h"
  42 #include "hw/char/escc.h"
  43 #include "hw/misc/macio/macio.h"
  44 #include "hw/loader.h"
  45 #include "hw/fw-path-provider.h"
  46 #include "elf.h"
  47 #include "qemu/error-report.h"
  48 #include "sysemu/kvm.h"
  49 #include "sysemu/reset.h"
  50 #include "kvm_ppc.h"
  51 #include "exec/address-spaces.h"
  52
  53 #define MAX_IDE_BUS 2
  54 #define CFG_ADDR 0xf0000510
  55 #define TBFREQ 16600000UL
  56 #define CLOCKFREQ 266000000UL
  57 #define BUSFREQ 66000000UL
  58
  59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
  60
  61 #define GRACKLE_BASE 0xfec00000
  62 #define PROM_BASE 0xffc00000
  63 #define PROM_SIZE (4 * MiB)
  64
  65 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  66                             Error **errp)
  67 {
  68     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  69 }
  70
  71 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
  72 {
  73     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
  74 }
  75
  76 static void ppc_heathrow_reset(void *opaque)
  77 {
  78     PowerPCCPU *cpu = opaque;
  79
  80     cpu_reset(CPU(cpu));
  81 }
  82
  83 static void ppc_heathrow_init(MachineState *machine)
  84 {
  85     ram_addr_t ram_size = machine->ram_size;
  86     const char *boot_device = machine->boot_order;
  87     PowerPCCPU *cpu = NULL;
  88     CPUPPCState *env = NULL;
  89     char *filename;
  90     int i;
  91     MemoryRegion *bios = g_new(MemoryRegion, 1);
  92     uint32_t kernel_base, initrd_base, cmdline_base = 0;
  93     int32_t kernel_size, initrd_size;
  94     PCIBus *pci_bus;
  95     PCIDevice *macio;
  96     MACIOIDEState *macio_ide;
  97     ESCCState *escc;
  98     SysBusDevice *s;
  99     DeviceState *dev, *pic_dev;
 100     BusState *adb_bus;
 101     uint64_t bios_addr;
 102     int bios_size;
 103     unsigned int smp_cpus = machine->smp.cpus;
 104     uint16_t ppc_boot_device;
 105     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 106     void *fw_cfg;
 107     uint64_t tbfreq;
 108
 109     /* init CPUs */
 110     for (i = 0; i < smp_cpus; i++) {
 111         cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 112         env = &cpu->env;
 113
 114         /* Set time-base frequency to 16.6 Mhz */
 115         cpu_ppc_tb_init(env,  TBFREQ);
 116         qemu_register_reset(ppc_heathrow_reset, cpu);
 117     }
 118
 119     /* allocate RAM */
 120     if (ram_size > 2047 * MiB) {
 121         error_report("Too much memory for this machine: %" PRId64 " MB, "
 122                      "maximum 2047 MB", ram_size / MiB);
 123         exit(1);
 124     }
 125
 126     memory_region_add_subregion(get_system_memory(), 0, machine->ram);
 127
 128     /* allocate and load firmware ROM */
 129     memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE,
 130                            &error_fatal);
 131     memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
 132
 133     if (!bios_name) {
 134         bios_name = PROM_FILENAME;
 135     }
 136     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 137     if (filename) {
 138         /* Load OpenBIOS (ELF) */
 139         bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr,
 140                              NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 141         /* Unfortunately, load_elf sign-extends reading elf32 */
 142         bios_addr = (uint32_t)bios_addr;
 143
 144         if (bios_size <= 0) {
 145             /* or if could not load ELF try loading a binary ROM image */
 146             bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
 147             bios_addr = PROM_BASE;
 148         }
 149         g_free(filename);
 150     } else {
 151         bios_size = -1;
 152     }
 153     if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
 154         error_report("could not load PowerPC bios '%s'", bios_name);
 155         exit(1);
 156     }
 157
 158     if (machine->kernel_filename) {
 159         int bswap_needed;
 160
 161 #ifdef BSWAP_NEEDED
 162         bswap_needed = 1;
 163 #else
 164         bswap_needed = 0;
 165 #endif
 166         kernel_base = KERNEL_LOAD_ADDR;
 167         kernel_size = load_elf(machine->kernel_filename, NULL,
 168                                translate_kernel_address, NULL, NULL, NULL,
 169                                NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 170         if (kernel_size < 0)
 171             kernel_size = load_aout(machine->kernel_filename, kernel_base,
 172                                     ram_size - kernel_base, bswap_needed,
 173                                     TARGET_PAGE_SIZE);
 174         if (kernel_size < 0)
 175             kernel_size = load_image_targphys(machine->kernel_filename,
 176                                               kernel_base,
 177                                               ram_size - kernel_base);
 178         if (kernel_size < 0) {
 179             error_report("could not load kernel '%s'",
 180                          machine->kernel_filename);
 181             exit(1);
 182         }
 183         /* load initrd */
 184         if (machine->initrd_filename) {
 185             initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
 186                                             KERNEL_GAP);
 187             initrd_size = load_image_targphys(machine->initrd_filename,
 188                                               initrd_base,
 189                                               ram_size - initrd_base);
 190             if (initrd_size < 0) {
 191                 error_report("could not load initial ram disk '%s'",
 192                              machine->initrd_filename);
 193                 exit(1);
 194             }
 195             cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
 196         } else {
 197             initrd_base = 0;
 198             initrd_size = 0;
 199             cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
 200         }
 201         ppc_boot_device = 'm';
 202     } else {
 203         kernel_base = 0;
 204         kernel_size = 0;
 205         initrd_base = 0;
 206         initrd_size = 0;
 207         ppc_boot_device = '\0';
 208         for (i = 0; boot_device[i] != '\0'; i++) {
 209             /* TOFIX: for now, the second IDE channel is not properly
 210              *        used by OHW. The Mac floppy disk are not emulated.
 211              *        For now, OHW cannot boot from the network.
 212              */
 213 #if 0
 214             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 215                 ppc_boot_device = boot_device[i];
 216                 break;
 217             }
 218 #else
 219             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 220                 ppc_boot_device = boot_device[i];
 221                 break;
 222             }
 223 #endif
 224         }
 225         if (ppc_boot_device == '\0') {
 226             error_report("No valid boot device for G3 Beige machine");
 227             exit(1);
 228         }
 229     }
 230
 231     /* XXX: we register only 1 output pin for heathrow PIC */
 232     pic_dev = qdev_new(TYPE_HEATHROW);
 233     sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal);
 234
 235     /* Connect the heathrow PIC outputs to the 6xx bus */
 236     for (i = 0; i < smp_cpus; i++) {
 237         switch (PPC_INPUT(env)) {
 238         case PPC_FLAGS_INPUT_6xx:
 239             qdev_connect_gpio_out(pic_dev, 0,
 240                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
 241             break;
 242         default:
 243             error_report("Bus model not supported on OldWorld Mac machine");
 244             exit(1);
 245         }
 246     }
 247
 248     /* Timebase Frequency */
 249     if (kvm_enabled()) {
 250         tbfreq = kvmppc_get_tbfreq();
 251     } else {
 252         tbfreq = TBFREQ;
 253     }
 254
 255     /* init basic PC hardware */
 256     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 257         error_report("Only 6xx bus is supported on heathrow machine");
 258         exit(1);
 259     }
 260
 261     /* Grackle PCI host bridge */
 262     dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
 263     qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
 264     s = SYS_BUS_DEVICE(dev);
 265     sysbus_realize_and_unref(s, &error_fatal);
 266
 267     sysbus_mmio_map(s, 0, GRACKLE_BASE);
 268     sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
 269     /* PCI hole */
 270     memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
 271                                 sysbus_mmio_get_region(s, 2));
 272     /* Register 2 MB of ISA IO space */
 273     memory_region_add_subregion(get_system_memory(), 0xfe000000,
 274                                 sysbus_mmio_get_region(s, 3));
 275
 276     for (i = 0; i < 4; i++) {
 277         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x15 + i));
 278     }
 279
 280     pci_bus = PCI_HOST_BRIDGE(dev)->bus;
 281
 282     pci_vga_init(pci_bus);
 283
 284     for (i = 0; i < nb_nics; i++) {
 285         pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 286     }
 287
 288     ide_drive_get(hd, ARRAY_SIZE(hd));
 289
 290     /* MacIO */
 291     macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
 292     dev = DEVICE(macio);
 293     qdev_prop_set_uint64(dev, "frequency", tbfreq);
 294     object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
 295                              &error_abort);
 296
 297     escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
 298     qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
 299     qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
 300
 301     pci_realize_and_unref(macio, pci_bus, &error_fatal);
 302
 303     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
 304                                                         "ide[0]"));
 305     macio_ide_init_drives(macio_ide, hd);
 306
 307     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
 308                                                         "ide[1]"));
 309     macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
 310
 311     dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
 312     adb_bus = qdev_get_child_bus(dev, "adb.0");
 313     dev = qdev_new(TYPE_ADB_KEYBOARD);
 314     qdev_realize_and_unref(dev, adb_bus, &error_fatal);
 315     dev = qdev_new(TYPE_ADB_MOUSE);
 316     qdev_realize_and_unref(dev, adb_bus, &error_fatal);
 317
 318     if (machine_usb(machine)) {
 319         pci_create_simple(pci_bus, -1, "pci-ohci");
 320     }
 321
 322     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 323         graphic_depth = 15;
 324
 325     /* No PCI init: the BIOS will do it */
 326
 327     dev = qdev_new(TYPE_FW_CFG_MEM);
 328     fw_cfg = FW_CFG(dev);
 329     qdev_prop_set_uint32(dev, "data_width", 1);
 330     qdev_prop_set_bit(dev, "dma_enabled", false);
 331     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
 332                               OBJECT(fw_cfg));
 333     s = SYS_BUS_DEVICE(dev);
 334     sysbus_realize_and_unref(s, &error_fatal);
 335     sysbus_mmio_map(s, 0, CFG_ADDR);
 336     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
 337
 338     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 339     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 340     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 341     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 342     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 343     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 344     if (machine->kernel_cmdline) {
 345         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
 346         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 347                          machine->kernel_cmdline);
 348     } else {
 349         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 350     }
 351     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 352     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 353     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 354
 355     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 356     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 357     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 358
 359     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 360     if (kvm_enabled()) {
 361         uint8_t *hypercall;
 362
 363         hypercall = g_malloc(16);
 364         kvmppc_get_hypercall(env, hypercall, 16);
 365         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 366         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 367     }
 368     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
 369     /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
 370     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
 371     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
 372
 373     /* MacOS NDRV VGA driver */
 374     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
 375     if (filename) {
 376         gchar *ndrv_file;
 377         gsize ndrv_size;
 378
 379         if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
 380             fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
 381         }
 382         g_free(filename);
 383     }
 384
 385     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 386 }
 387
 388 /*
 389  * Implementation of an interface to adjust firmware path
 390  * for the bootindex property handling.
 391  */
 392 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
 393                                   DeviceState *dev)
 394 {
 395     PCIDevice *pci;
 396     IDEBus *ide_bus;
 397     IDEState *ide_s;
 398     MACIOIDEState *macio_ide;
 399
 400     if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
 401         pci = PCI_DEVICE(dev);
 402         return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
 403     }
 404
 405     if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
 406         macio_ide = MACIO_IDE(dev);
 407         return g_strdup_printf("ata-3@%x", macio_ide->addr);
 408     }
 409
 410     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
 411         ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
 412         ide_s = idebus_active_if(ide_bus);
 413
 414         if (ide_s->drive_kind == IDE_CD) {
 415             return g_strdup("cdrom");
 416         }
 417
 418         return g_strdup("disk");
 419     }
 420
 421     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
 422         return g_strdup("disk");
 423     }
 424
 425     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
 426         return g_strdup("cdrom");
 427     }
 428
 429     if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
 430         return g_strdup("disk");
 431     }
 432
 433     return NULL;
 434 }
 435
 436 static int heathrow_kvm_type(MachineState *machine, const char *arg)
 437 {
 438     /* Always force PR KVM */
 439     return 2;
 440 }
 441
 442 static void heathrow_class_init(ObjectClass *oc, void *data)
 443 {
 444     MachineClass *mc = MACHINE_CLASS(oc);
 445     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
 446
 447     mc->desc = "Heathrow based PowerMAC";
 448     mc->init = ppc_heathrow_init;
 449     mc->block_default_type = IF_IDE;
 450     mc->max_cpus = MAX_CPUS;
 451 #ifndef TARGET_PPC64
 452     mc->is_default = true;
 453 #endif
 454     /* TOFIX "cad" when Mac floppy is implemented */
 455     mc->default_boot_order = "cd";
 456     mc->kvm_type = heathrow_kvm_type;
 457     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
 458     mc->default_display = "std";
 459     mc->ignore_boot_device_suffixes = true;
 460     mc->default_ram_id = "ppc_heathrow.ram";
 461     fwc->get_dev_path = heathrow_fw_dev_path;
 462 }
 463
 464 static const TypeInfo ppc_heathrow_machine_info = {
 465     .name          = MACHINE_TYPE_NAME("g3beige"),
 466     .parent        = TYPE_MACHINE,
 467     .class_init    = heathrow_class_init,
 468     .interfaces = (InterfaceInfo[]) {
 469         { TYPE_FW_PATH_PROVIDER },
 470         { }
 471     },
 472 };
 473
 474 static void ppc_heathrow_register_types(void)
 475 {
 476     type_register_static(&ppc_heathrow_machine_info);
 477 }
 478
 479 type_init(ppc_heathrow_register_types);