target/mips/cp0_helper.c

   1 /*
   2  *  Helpers for emulation of CP0-related MIPS instructions.
   3  *
   4  *  Copyright (C) 2004-2005  Jocelyn Mayer
   5  *  Copyright (C) 2020  Wave Computing, Inc.
   6  *  Copyright (C) 2020  Aleksandar Markovic <amarkovic@wavecomp.com>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  *
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/main-loop.h"
  25 #include "cpu.h"
  26 #include "internal.h"
  27 #include "qemu/host-utils.h"
  28 #include "exec/helper-proto.h"
  29 #include "exec/exec-all.h"
  30 #include "exec/cpu_ldst.h"
  31 #include "exec/memop.h"
  32 #include "sysemu/kvm.h"
  33
  34
  35 #ifndef CONFIG_USER_ONLY
  36 /* SMP helpers.  */
  37 static bool mips_vpe_is_wfi(MIPSCPU *c)
  38 {
  39     CPUState *cpu = CPU(c);
  40     CPUMIPSState *env = &c->env;
  41
  42     /*
  43      * If the VPE is halted but otherwise active, it means it's waiting for
  44      * an interrupt.\
  45      */
  46     return cpu->halted && mips_vpe_active(env);
  47 }
  48
  49 static bool mips_vp_is_wfi(MIPSCPU *c)
  50 {
  51     CPUState *cpu = CPU(c);
  52     CPUMIPSState *env = &c->env;
  53
  54     return cpu->halted && mips_vp_active(env);
  55 }
  56
  57 static inline void mips_vpe_wake(MIPSCPU *c)
  58 {
  59     /*
  60      * Don't set ->halted = 0 directly, let it be done via cpu_has_work
  61      * because there might be other conditions that state that c should
  62      * be sleeping.
  63      */
  64     qemu_mutex_lock_iothread();
  65     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
  66     qemu_mutex_unlock_iothread();
  67 }
  68
  69 static inline void mips_vpe_sleep(MIPSCPU *cpu)
  70 {
  71     CPUState *cs = CPU(cpu);
  72
  73     /*
  74      * The VPE was shut off, really go to bed.
  75      * Reset any old _WAKE requests.
  76      */
  77     cs->halted = 1;
  78     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
  79 }
  80
  81 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
  82 {
  83     CPUMIPSState *c = &cpu->env;
  84
  85     /* FIXME: TC reschedule.  */
  86     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
  87         mips_vpe_wake(cpu);
  88     }
  89 }
  90
  91 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
  92 {
  93     CPUMIPSState *c = &cpu->env;
  94
  95     /* FIXME: TC reschedule.  */
  96     if (!mips_vpe_active(c)) {
  97         mips_vpe_sleep(cpu);
  98     }
  99 }
 100
 101 /**
 102  * mips_cpu_map_tc:
 103  * @env: CPU from which mapping is performed.
 104  * @tc: Should point to an int with the value of the global TC index.
 105  *
 106  * This function will transform @tc into a local index within the
 107  * returned #CPUMIPSState.
 108  */
 109
 110 /*
 111  * FIXME: This code assumes that all VPEs have the same number of TCs,
 112  *        which depends on runtime setup. Can probably be fixed by
 113  *        walking the list of CPUMIPSStates.
 114  */
 115 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 116 {
 117     MIPSCPU *cpu;
 118     CPUState *cs;
 119     CPUState *other_cs;
 120     int vpe_idx;
 121     int tc_idx = *tc;
 122
 123     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 124         /* Not allowed to address other CPUs.  */
 125         *tc = env->current_tc;
 126         return env;
 127     }
 128
 129     cs = env_cpu(env);
 130     vpe_idx = tc_idx / cs->nr_threads;
 131     *tc = tc_idx % cs->nr_threads;
 132     other_cs = qemu_get_cpu(vpe_idx);
 133     if (other_cs == NULL) {
 134         return env;
 135     }
 136     cpu = MIPS_CPU(other_cs);
 137     return &cpu->env;
 138 }
 139
 140 /*
 141  * The per VPE CP0_Status register shares some fields with the per TC
 142  * CP0_TCStatus registers. These fields are wired to the same registers,
 143  * so changes to either of them should be reflected on both registers.
 144  *
 145  * Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 146  *
 147  * These helper call synchronizes the regs for a given cpu.
 148  */
 149
 150 /*
 151  * Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.
 152  * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 153  *                                   int tc);
 154  */
 155
 156 /* Called for updates to CP0_TCStatus.  */
 157 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 158                              target_ulong v)
 159 {
 160     uint32_t status;
 161     uint32_t tcu, tmx, tasid, tksu;
 162     uint32_t mask = ((1U << CP0St_CU3)
 163                        | (1 << CP0St_CU2)
 164                        | (1 << CP0St_CU1)
 165                        | (1 << CP0St_CU0)
 166                        | (1 << CP0St_MX)
 167                        | (3 << CP0St_KSU));
 168
 169     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 170     tmx = (v >> CP0TCSt_TMX) & 0x1;
 171     tasid = v & cpu->CP0_EntryHi_ASID_mask;
 172     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 173
 174     status = tcu << CP0St_CU0;
 175     status |= tmx << CP0St_MX;
 176     status |= tksu << CP0St_KSU;
 177
 178     cpu->CP0_Status &= ~mask;
 179     cpu->CP0_Status |= status;
 180
 181     /* Sync the TASID with EntryHi.  */
 182     cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
 183     cpu->CP0_EntryHi |= tasid;
 184
 185     compute_hflags(cpu);
 186 }
 187
 188 /* Called for updates to CP0_EntryHi.  */
 189 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 190 {
 191     int32_t *tcst;
 192     uint32_t asid, v = cpu->CP0_EntryHi;
 193
 194     asid = v & cpu->CP0_EntryHi_ASID_mask;
 195
 196     if (tc == cpu->current_tc) {
 197         tcst = &cpu->active_tc.CP0_TCStatus;
 198     } else {
 199         tcst = &cpu->tcs[tc].CP0_TCStatus;
 200     }
 201
 202     *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
 203     *tcst |= asid;
 204 }
 205
 206 /* XXX: do not use a global */
 207 uint32_t cpu_mips_get_random(CPUMIPSState *env)
 208 {
 209     static uint32_t seed = 1;
 210     static uint32_t prev_idx;
 211     uint32_t idx;
 212     uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
 213
 214     if (nb_rand_tlb == 1) {
 215         return env->tlb->nb_tlb - 1;
 216     }
 217
 218     /* Don't return same value twice, so get another value */
 219     do {
 220         /*
 221          * Use a simple algorithm of Linear Congruential Generator
 222          * from ISO/IEC 9899 standard.
 223          */
 224         seed = 1103515245 * seed + 12345;
 225         idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
 226     } while (idx == prev_idx);
 227     prev_idx = idx;
 228     return idx;
 229 }
 230
 231 /* CP0 helpers */
 232 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 233 {
 234     return env->mvp->CP0_MVPControl;
 235 }
 236
 237 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 238 {
 239     return env->mvp->CP0_MVPConf0;
 240 }
 241
 242 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 243 {
 244     return env->mvp->CP0_MVPConf1;
 245 }
 246
 247 target_ulong helper_mfc0_random(CPUMIPSState *env)
 248 {
 249     return (int32_t)cpu_mips_get_random(env);
 250 }
 251
 252 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 253 {
 254     return env->active_tc.CP0_TCStatus;
 255 }
 256
 257 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 258 {
 259     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 260     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 261
 262     if (other_tc == other->current_tc) {
 263         return other->active_tc.CP0_TCStatus;
 264     } else {
 265         return other->tcs[other_tc].CP0_TCStatus;
 266     }
 267 }
 268
 269 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 270 {
 271     return env->active_tc.CP0_TCBind;
 272 }
 273
 274 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 275 {
 276     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 277     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 278
 279     if (other_tc == other->current_tc) {
 280         return other->active_tc.CP0_TCBind;
 281     } else {
 282         return other->tcs[other_tc].CP0_TCBind;
 283     }
 284 }
 285
 286 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 287 {
 288     return env->active_tc.PC;
 289 }
 290
 291 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 292 {
 293     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 294     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 295
 296     if (other_tc == other->current_tc) {
 297         return other->active_tc.PC;
 298     } else {
 299         return other->tcs[other_tc].PC;
 300     }
 301 }
 302
 303 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 304 {
 305     return env->active_tc.CP0_TCHalt;
 306 }
 307
 308 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 309 {
 310     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 311     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 312
 313     if (other_tc == other->current_tc) {
 314         return other->active_tc.CP0_TCHalt;
 315     } else {
 316         return other->tcs[other_tc].CP0_TCHalt;
 317     }
 318 }
 319
 320 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 321 {
 322     return env->active_tc.CP0_TCContext;
 323 }
 324
 325 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 326 {
 327     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 328     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 329
 330     if (other_tc == other->current_tc) {
 331         return other->active_tc.CP0_TCContext;
 332     } else {
 333         return other->tcs[other_tc].CP0_TCContext;
 334     }
 335 }
 336
 337 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 338 {
 339     return env->active_tc.CP0_TCSchedule;
 340 }
 341
 342 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 343 {
 344     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 345     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 346
 347     if (other_tc == other->current_tc) {
 348         return other->active_tc.CP0_TCSchedule;
 349     } else {
 350         return other->tcs[other_tc].CP0_TCSchedule;
 351     }
 352 }
 353
 354 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 355 {
 356     return env->active_tc.CP0_TCScheFBack;
 357 }
 358
 359 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 360 {
 361     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 362     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 363
 364     if (other_tc == other->current_tc) {
 365         return other->active_tc.CP0_TCScheFBack;
 366     } else {
 367         return other->tcs[other_tc].CP0_TCScheFBack;
 368     }
 369 }
 370
 371 target_ulong helper_mfc0_count(CPUMIPSState *env)
 372 {
 373     return (int32_t)cpu_mips_get_count(env);
 374 }
 375
 376 target_ulong helper_mfc0_saar(CPUMIPSState *env)
 377 {
 378     if ((env->CP0_SAARI & 0x3f) < 2) {
 379         return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
 380     }
 381     return 0;
 382 }
 383
 384 target_ulong helper_mfhc0_saar(CPUMIPSState *env)
 385 {
 386     if ((env->CP0_SAARI & 0x3f) < 2) {
 387         return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
 388     }
 389     return 0;
 390 }
 391
 392 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 393 {
 394     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 395     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 396
 397     return other->CP0_EntryHi;
 398 }
 399
 400 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 401 {
 402     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 403     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 404
 405     return other->CP0_Cause;
 406 }
 407
 408 target_ulong helper_mftc0_status(CPUMIPSState *env)
 409 {
 410     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 411     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 412
 413     return other->CP0_Status;
 414 }
 415
 416 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 417 {
 418     return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
 419 }
 420
 421 target_ulong helper_mfc0_maar(CPUMIPSState *env)
 422 {
 423     return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
 424 }
 425
 426 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
 427 {
 428     return env->CP0_MAAR[env->CP0_MAARI] >> 32;
 429 }
 430
 431 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 432 {
 433     return (int32_t)env->CP0_WatchLo[sel];
 434 }
 435
 436 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 437 {
 438     return (int32_t) env->CP0_WatchHi[sel];
 439 }
 440
 441 target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
 442 {
 443     return env->CP0_WatchHi[sel] >> 32;
 444 }
 445
 446 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 447 {
 448     target_ulong t0 = env->CP0_Debug;
 449     if (env->hflags & MIPS_HFLAG_DM) {
 450         t0 |= 1 << CP0DB_DM;
 451     }
 452
 453     return t0;
 454 }
 455
 456 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 457 {
 458     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 459     int32_t tcstatus;
 460     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 461
 462     if (other_tc == other->current_tc) {
 463         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 464     } else {
 465         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 466     }
 467
 468     /* XXX: Might be wrong, check with EJTAG spec. */
 469     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 470             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 471 }
 472
 473 #if defined(TARGET_MIPS64)
 474 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 475 {
 476     return env->active_tc.PC;
 477 }
 478
 479 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 480 {
 481     return env->active_tc.CP0_TCHalt;
 482 }
 483
 484 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 485 {
 486     return env->active_tc.CP0_TCContext;
 487 }
 488
 489 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 490 {
 491     return env->active_tc.CP0_TCSchedule;
 492 }
 493
 494 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 495 {
 496     return env->active_tc.CP0_TCScheFBack;
 497 }
 498
 499 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 500 {
 501     return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
 502 }
 503
 504 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
 505 {
 506     return env->CP0_MAAR[env->CP0_MAARI];
 507 }
 508
 509 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 510 {
 511     return env->CP0_WatchLo[sel];
 512 }
 513
 514 target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 515 {
 516     return env->CP0_WatchHi[sel];
 517 }
 518
 519 target_ulong helper_dmfc0_saar(CPUMIPSState *env)
 520 {
 521     if ((env->CP0_SAARI & 0x3f) < 2) {
 522         return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
 523     }
 524     return 0;
 525 }
 526 #endif /* TARGET_MIPS64 */
 527
 528 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 529 {
 530     uint32_t index_p = env->CP0_Index & 0x80000000;
 531     uint32_t tlb_index = arg1 & 0x7fffffff;
 532     if (tlb_index < env->tlb->nb_tlb) {
 533         if (env->insn_flags & ISA_MIPS32R6) {
 534             index_p |= arg1 & 0x80000000;
 535         }
 536         env->CP0_Index = index_p | tlb_index;
 537     }
 538 }
 539
 540 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 541 {
 542     uint32_t mask = 0;
 543     uint32_t newval;
 544
 545     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
 546         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 547                 (1 << CP0MVPCo_EVP);
 548     }
 549     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
 550         mask |= (1 << CP0MVPCo_STLB);
 551     }
 552     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 553
 554     /* TODO: Enable/disable shared TLB, enable/disable VPEs. */
 555
 556     env->mvp->CP0_MVPControl = newval;
 557 }
 558
 559 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 560 {
 561     uint32_t mask;
 562     uint32_t newval;
 563
 564     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 565            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 566     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 567
 568     /*
 569      * Yield scheduler intercept not implemented.
 570      * Gating storage scheduler intercept not implemented.
 571      */
 572
 573     /* TODO: Enable/disable TCs. */
 574
 575     env->CP0_VPEControl = newval;
 576 }
 577
 578 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 579 {
 580     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 581     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 582     uint32_t mask;
 583     uint32_t newval;
 584
 585     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 586            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 587     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 588
 589     /* TODO: Enable/disable TCs.  */
 590
 591     other->CP0_VPEControl = newval;
 592 }
 593
 594 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
 595 {
 596     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 597     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 598     /* FIXME: Mask away return zero on read bits.  */
 599     return other->CP0_VPEControl;
 600 }
 601
 602 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
 603 {
 604     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 605     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 606
 607     return other->CP0_VPEConf0;
 608 }
 609
 610 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
 611 {
 612     uint32_t mask = 0;
 613     uint32_t newval;
 614
 615     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
 616         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) {
 617             mask |= (0xff << CP0VPEC0_XTC);
 618         }
 619         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 620     }
 621     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
 622
 623     /* TODO: TC exclusive handling due to ERL/EXL. */
 624
 625     env->CP0_VPEConf0 = newval;
 626 }
 627
 628 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
 629 {
 630     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 631     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 632     uint32_t mask = 0;
 633     uint32_t newval;
 634
 635     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 636     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
 637
 638     /* TODO: TC exclusive handling due to ERL/EXL.  */
 639     other->CP0_VPEConf0 = newval;
 640 }
 641
 642 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
 643 {
 644     uint32_t mask = 0;
 645     uint32_t newval;
 646
 647     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 648         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
 649                 (0xff << CP0VPEC1_NCP1);
 650     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
 651
 652     /* UDI not implemented. */
 653     /* CP2 not implemented. */
 654
 655     /* TODO: Handle FPU (CP1) binding. */
 656
 657     env->CP0_VPEConf1 = newval;
 658 }
 659
 660 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
 661 {
 662     /* Yield qualifier inputs not implemented. */
 663     env->CP0_YQMask = 0x00000000;
 664 }
 665
 666 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
 667 {
 668     env->CP0_VPEOpt = arg1 & 0x0000ffff;
 669 }
 670
 671 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
 672
 673 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
 674 {
 675     /* 1k pages not implemented */
 676     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
 677     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
 678                         | (rxi << (CP0EnLo_XI - 30));
 679 }
 680
 681 #if defined(TARGET_MIPS64)
 682 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
 683
 684 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
 685 {
 686     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
 687     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
 688 }
 689 #endif
 690
 691 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
 692 {
 693     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
 694     uint32_t newval;
 695
 696     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
 697
 698     env->active_tc.CP0_TCStatus = newval;
 699     sync_c0_tcstatus(env, env->current_tc, newval);
 700 }
 701
 702 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
 703 {
 704     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 705     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 706
 707     if (other_tc == other->current_tc) {
 708         other->active_tc.CP0_TCStatus = arg1;
 709     } else {
 710         other->tcs[other_tc].CP0_TCStatus = arg1;
 711     }
 712     sync_c0_tcstatus(other, other_tc, arg1);
 713 }
 714
 715 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
 716 {
 717     uint32_t mask = (1 << CP0TCBd_TBE);
 718     uint32_t newval;
 719
 720     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
 721         mask |= (1 << CP0TCBd_CurVPE);
 722     }
 723     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
 724     env->active_tc.CP0_TCBind = newval;
 725 }
 726
 727 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
 728 {
 729     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 730     uint32_t mask = (1 << CP0TCBd_TBE);
 731     uint32_t newval;
 732     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 733
 734     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
 735         mask |= (1 << CP0TCBd_CurVPE);
 736     }
 737     if (other_tc == other->current_tc) {
 738         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
 739         other->active_tc.CP0_TCBind = newval;
 740     } else {
 741         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
 742         other->tcs[other_tc].CP0_TCBind = newval;
 743     }
 744 }
 745
 746 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
 747 {
 748     env->active_tc.PC = arg1;
 749     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
 750     env->CP0_LLAddr = 0;
 751     env->lladdr = 0;
 752     /* MIPS16 not implemented. */
 753 }
 754
 755 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
 756 {
 757     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 758     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 759
 760     if (other_tc == other->current_tc) {
 761         other->active_tc.PC = arg1;
 762         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
 763         other->CP0_LLAddr = 0;
 764         other->lladdr = 0;
 765         /* MIPS16 not implemented. */
 766     } else {
 767         other->tcs[other_tc].PC = arg1;
 768         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
 769         other->CP0_LLAddr = 0;
 770         other->lladdr = 0;
 771         /* MIPS16 not implemented. */
 772     }
 773 }
 774
 775 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
 776 {
 777     MIPSCPU *cpu = env_archcpu(env);
 778
 779     env->active_tc.CP0_TCHalt = arg1 & 0x1;
 780
 781     /* TODO: Halt TC / Restart (if allocated+active) TC. */
 782     if (env->active_tc.CP0_TCHalt & 1) {
 783         mips_tc_sleep(cpu, env->current_tc);
 784     } else {
 785         mips_tc_wake(cpu, env->current_tc);
 786     }
 787 }
 788
 789 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
 790 {
 791     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 792     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 793     MIPSCPU *other_cpu = env_archcpu(other);
 794
 795     /* TODO: Halt TC / Restart (if allocated+active) TC. */
 796
 797     if (other_tc == other->current_tc) {
 798         other->active_tc.CP0_TCHalt = arg1;
 799     } else {
 800         other->tcs[other_tc].CP0_TCHalt = arg1;
 801     }
 802
 803     if (arg1 & 1) {
 804         mips_tc_sleep(other_cpu, other_tc);
 805     } else {
 806         mips_tc_wake(other_cpu, other_tc);
 807     }
 808 }
 809
 810 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
 811 {
 812     env->active_tc.CP0_TCContext = arg1;
 813 }
 814
 815 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
 816 {
 817     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 818     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 819
 820     if (other_tc == other->current_tc) {
 821         other->active_tc.CP0_TCContext = arg1;
 822     } else {
 823         other->tcs[other_tc].CP0_TCContext = arg1;
 824     }
 825 }
 826
 827 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
 828 {
 829     env->active_tc.CP0_TCSchedule = arg1;
 830 }
 831
 832 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
 833 {
 834     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 835     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 836
 837     if (other_tc == other->current_tc) {
 838         other->active_tc.CP0_TCSchedule = arg1;
 839     } else {
 840         other->tcs[other_tc].CP0_TCSchedule = arg1;
 841     }
 842 }
 843
 844 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
 845 {
 846     env->active_tc.CP0_TCScheFBack = arg1;
 847 }
 848
 849 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
 850 {
 851     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 852     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 853
 854     if (other_tc == other->current_tc) {
 855         other->active_tc.CP0_TCScheFBack = arg1;
 856     } else {
 857         other->tcs[other_tc].CP0_TCScheFBack = arg1;
 858     }
 859 }
 860
 861 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
 862 {
 863     /* 1k pages not implemented */
 864     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
 865     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
 866                         | (rxi << (CP0EnLo_XI - 30));
 867 }
 868
 869 #if defined(TARGET_MIPS64)
 870 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
 871 {
 872     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
 873     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
 874 }
 875 #endif
 876
 877 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
 878 {
 879     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
 880 }
 881
 882 void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
 883 {
 884     int32_t old;
 885     old = env->CP0_MemoryMapID;
 886     env->CP0_MemoryMapID = (int32_t) arg1;
 887     /* If the MemoryMapID changes, flush qemu's TLB.  */
 888     if (old != env->CP0_MemoryMapID) {
 889         cpu_mips_tlb_flush(env);
 890     }
 891 }
 892
 893 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
 894 {
 895     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
 896     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
 897         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
 898          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
 899          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
 900         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
 901     }
 902 }
 903
 904 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
 905 {
 906     update_pagemask(env, arg1, &env->CP0_PageMask);
 907 }
 908
 909 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
 910 {
 911     /* SmartMIPS not implemented */
 912     /* 1k pages not implemented */
 913     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
 914                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
 915     compute_hflags(env);
 916     restore_pamask(env);
 917 }
 918
 919 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
 920 {
 921     CPUState *cs = env_cpu(env);
 922
 923     env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
 924     tlb_flush(cs);
 925 }
 926
 927 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
 928 {
 929     CPUState *cs = env_cpu(env);
 930
 931     env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
 932     tlb_flush(cs);
 933 }
 934
 935 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
 936 {
 937     CPUState *cs = env_cpu(env);
 938
 939     env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
 940     tlb_flush(cs);
 941 }
 942
 943 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
 944 {
 945 #if defined(TARGET_MIPS64)
 946     uint64_t mask = 0x3F3FFFFFFFULL;
 947     uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
 948     uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
 949
 950     if ((env->insn_flags & ISA_MIPS32R6)) {
 951         if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
 952             mask &= ~(0x3FULL << CP0PF_BDI);
 953         }
 954         if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
 955             mask &= ~(0x3FULL << CP0PF_GDI);
 956         }
 957         if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
 958             mask &= ~(0x3FULL << CP0PF_UDI);
 959         }
 960         if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
 961             mask &= ~(0x3FULL << CP0PF_MDI);
 962         }
 963         if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
 964             mask &= ~(0x3FULL << CP0PF_PTI);
 965         }
 966     }
 967     env->CP0_PWField = arg1 & mask;
 968
 969     if ((new_ptei >= 32) ||
 970             ((env->insn_flags & ISA_MIPS32R6) &&
 971                     (new_ptei == 0 || new_ptei == 1))) {
 972         env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
 973                 (old_ptei << CP0PF_PTEI);
 974     }
 975 #else
 976     uint32_t mask = 0x3FFFFFFF;
 977     uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
 978     uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
 979
 980     if ((env->insn_flags & ISA_MIPS32R6)) {
 981         if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
 982             mask &= ~(0x3F << CP0PF_GDW);
 983         }
 984         if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
 985             mask &= ~(0x3F << CP0PF_UDW);
 986         }
 987         if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
 988             mask &= ~(0x3F << CP0PF_MDW);
 989         }
 990         if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
 991             mask &= ~(0x3F << CP0PF_PTW);
 992         }
 993     }
 994     env->CP0_PWField = arg1 & mask;
 995
 996     if ((new_ptew >= 32) ||
 997             ((env->insn_flags & ISA_MIPS32R6) &&
 998                     (new_ptew == 0 || new_ptew == 1))) {
 999         env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1000                 (old_ptew << CP0PF_PTEW);
1001     }
1002 #endif
1003 }
1004
1005 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1006 {
1007 #if defined(TARGET_MIPS64)
1008     env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1009 #else
1010     env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1011 #endif
1012 }
1013
1014 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1015 {
1016     if (env->insn_flags & ISA_MIPS32R6) {
1017         if (arg1 < env->tlb->nb_tlb) {
1018             env->CP0_Wired = arg1;
1019         }
1020     } else {
1021         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1022     }
1023 }
1024
1025 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1026 {
1027 #if defined(TARGET_MIPS64)
1028     /* PWEn = 0. Hardware page table walking is not implemented. */
1029     env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1030 #else
1031     env->CP0_PWCtl = (arg1 & 0x800000FF);
1032 #endif
1033 }
1034
1035 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1036 {
1037     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1038 }
1039
1040 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1041 {
1042     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1043 }
1044
1045 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1046 {
1047     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1048 }
1049
1050 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1051 {
1052     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1053 }
1054
1055 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1056 {
1057     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1058 }
1059
1060 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1061 {
1062     uint32_t mask = 0x0000000F;
1063
1064     if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1065         (env->insn_flags & ISA_MIPS32R6)) {
1066         mask |= (1 << 4);
1067     }
1068     if (env->insn_flags & ISA_MIPS32R6) {
1069         mask |= (1 << 5);
1070     }
1071     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1072         mask |= (1 << 29);
1073
1074         if (arg1 & (1 << 29)) {
1075             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1076         } else {
1077             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1078         }
1079     }
1080
1081     env->CP0_HWREna = arg1 & mask;
1082 }
1083
1084 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1085 {
1086     cpu_mips_store_count(env, arg1);
1087 }
1088
1089 void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1090 {
1091     uint32_t target = arg1 & 0x3f;
1092     if (target <= 1) {
1093         env->CP0_SAARI = target;
1094     }
1095 }
1096
1097 void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1098 {
1099     uint32_t target = env->CP0_SAARI & 0x3f;
1100     if (target < 2) {
1101         env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1102         switch (target) {
1103         case 0:
1104             if (env->itu) {
1105                 itc_reconfigure(env->itu);
1106             }
1107             break;
1108         }
1109     }
1110 }
1111
1112 void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1113 {
1114     uint32_t target = env->CP0_SAARI & 0x3f;
1115     if (target < 2) {
1116         env->CP0_SAAR[target] =
1117             (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1118             (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1119         switch (target) {
1120         case 0:
1121             if (env->itu) {
1122                 itc_reconfigure(env->itu);
1123             }
1124             break;
1125         }
1126     }
1127 }
1128
1129 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1130 {
1131     target_ulong old, val, mask;
1132     mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1133     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1134         mask |= 1 << CP0EnHi_EHINV;
1135     }
1136
1137     /* 1k pages not implemented */
1138 #if defined(TARGET_MIPS64)
1139     if (env->insn_flags & ISA_MIPS32R6) {
1140         int entryhi_r = extract64(arg1, 62, 2);
1141         int config0_at = extract32(env->CP0_Config0, 13, 2);
1142         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1143         if ((entryhi_r == 2) ||
1144             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1145             /* skip EntryHi.R field if new value is reserved */
1146             mask &= ~(0x3ull << 62);
1147         }
1148     }
1149     mask &= env->SEGMask;
1150 #endif
1151     old = env->CP0_EntryHi;
1152     val = (arg1 & mask) | (old & ~mask);
1153     env->CP0_EntryHi = val;
1154     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1155         sync_c0_entryhi(env, env->current_tc);
1156     }
1157     /* If the ASID changes, flush qemu's TLB.  */
1158     if ((old & env->CP0_EntryHi_ASID_mask) !=
1159         (val & env->CP0_EntryHi_ASID_mask)) {
1160         tlb_flush(env_cpu(env));
1161     }
1162 }
1163
1164 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1165 {
1166     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1167     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1168
1169     other->CP0_EntryHi = arg1;
1170     sync_c0_entryhi(other, other_tc);
1171 }
1172
1173 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1174 {
1175     cpu_mips_store_compare(env, arg1);
1176 }
1177
1178 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1179 {
1180     uint32_t val, old;
1181
1182     old = env->CP0_Status;
1183     cpu_mips_store_status(env, arg1);
1184     val = env->CP0_Status;
1185
1186     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1187         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1188                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1189                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1190                 env->CP0_Cause);
1191         switch (cpu_mmu_index(env, false)) {
1192         case 3:
1193             qemu_log(", ERL\n");
1194             break;
1195         case MIPS_HFLAG_UM:
1196             qemu_log(", UM\n");
1197             break;
1198         case MIPS_HFLAG_SM:
1199             qemu_log(", SM\n");
1200             break;
1201         case MIPS_HFLAG_KM:
1202             qemu_log("\n");
1203             break;
1204         default:
1205             cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
1206             break;
1207         }
1208     }
1209 }
1210
1211 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1212 {
1213     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1214     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1215     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1216
1217     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1218     sync_c0_status(env, other, other_tc);
1219 }
1220
1221 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1222 {
1223     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1224 }
1225
1226 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1227 {
1228     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1229     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1230 }
1231
1232 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1233 {
1234     cpu_mips_store_cause(env, arg1);
1235 }
1236
1237 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1238 {
1239     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1240     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1241
1242     cpu_mips_store_cause(other, arg1);
1243 }
1244
1245 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1246 {
1247     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1248     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1249
1250     return other->CP0_EPC;
1251 }
1252
1253 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1254 {
1255     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1256     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1257
1258     return other->CP0_EBase;
1259 }
1260
1261 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1262 {
1263     target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1264     if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1265         mask |= ~0x3FFFFFFF;
1266     }
1267     env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1268 }
1269
1270 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1271 {
1272     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1273     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1274     target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1275     if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1276         mask |= ~0x3FFFFFFF;
1277     }
1278     other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1279 }
1280
1281 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1282 {
1283     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1284     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1285
1286     switch (idx) {
1287     case 0: return other->CP0_Config0;
1288     case 1: return other->CP0_Config1;
1289     case 2: return other->CP0_Config2;
1290     case 3: return other->CP0_Config3;
1291     /* 4 and 5 are reserved.  */
1292     case 6: return other->CP0_Config6;
1293     case 7: return other->CP0_Config7;
1294     default:
1295         break;
1296     }
1297     return 0;
1298 }
1299
1300 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1301 {
1302     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1303 }
1304
1305 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1306 {
1307     /* tertiary/secondary caches not implemented */
1308     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1309 }
1310
1311 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1312 {
1313     if (env->insn_flags & ASE_MICROMIPS) {
1314         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1315                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1316     }
1317 }
1318
1319 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1320 {
1321     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1322                        (arg1 & env->CP0_Config4_rw_bitmask);
1323 }
1324
1325 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1326 {
1327     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1328                        (arg1 & env->CP0_Config5_rw_bitmask);
1329     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
1330             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
1331     compute_hflags(env);
1332 }
1333
1334 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1335 {
1336     target_long mask = env->CP0_LLAddr_rw_bitmask;
1337     arg1 = arg1 << env->CP0_LLAddr_shift;
1338     env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1339 }
1340
1341 #define MTC0_MAAR_MASK(env) \
1342         ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1343
1344 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1345 {
1346     env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1347 }
1348
1349 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1350 {
1351     env->CP0_MAAR[env->CP0_MAARI] =
1352         (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1353         (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1354 }
1355
1356 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1357 {
1358     int index = arg1 & 0x3f;
1359     if (index == 0x3f) {
1360         /*
1361          * Software may write all ones to INDEX to determine the
1362          *  maximum value supported.
1363          */
1364         env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1365     } else if (index < MIPS_MAAR_MAX) {
1366         env->CP0_MAARI = index;
1367     }
1368     /*
1369      * Other than the all ones, if the value written is not supported,
1370      * then INDEX is unchanged from its previous value.
1371      */
1372 }
1373
1374 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1375 {
1376     /*
1377      * Watch exceptions for instructions, data loads, data stores
1378      * not implemented.
1379      */
1380     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1381 }
1382
1383 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1384 {
1385     uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1386     if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
1387         mask |= 0xFFFFFFFF00000000ULL; /* MMID */
1388     }
1389     env->CP0_WatchHi[sel] = arg1 & mask;
1390     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1391 }
1392
1393 void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1394 {
1395     env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
1396                             (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
1397 }
1398
1399 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1400 {
1401     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1402     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1403 }
1404
1405 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1406 {
1407     env->CP0_Framemask = arg1; /* XXX */
1408 }
1409
1410 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1411 {
1412     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1413     if (arg1 & (1 << CP0DB_DM)) {
1414         env->hflags |= MIPS_HFLAG_DM;
1415     } else {
1416         env->hflags &= ~MIPS_HFLAG_DM;
1417     }
1418 }
1419
1420 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1421 {
1422     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1423     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1424     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1425
1426     /* XXX: Might be wrong, check with EJTAG spec. */
1427     if (other_tc == other->current_tc) {
1428         other->active_tc.CP0_Debug_tcstatus = val;
1429     } else {
1430         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1431     }
1432     other->CP0_Debug = (other->CP0_Debug &
1433                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1434                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1435 }
1436
1437 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1438 {
1439     env->CP0_Performance0 = arg1 & 0x000007ff;
1440 }
1441
1442 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1443 {
1444     int32_t wst = arg1 & (1 << CP0EC_WST);
1445     int32_t spr = arg1 & (1 << CP0EC_SPR);
1446     int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1447
1448     env->CP0_ErrCtl = wst | spr | itc;
1449
1450     if (itc && !wst && !spr) {
1451         env->hflags |= MIPS_HFLAG_ITC_CACHE;
1452     } else {
1453         env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1454     }
1455 }
1456
1457 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1458 {
1459     if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1460         /*
1461          * If CACHE instruction is configured for ITC tags then make all
1462          * CP0.TagLo bits writable. The actual write to ITC Configuration
1463          * Tag will take care of the read-only bits.
1464          */
1465         env->CP0_TagLo = arg1;
1466     } else {
1467         env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1468     }
1469 }
1470
1471 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1472 {
1473     env->CP0_DataLo = arg1; /* XXX */
1474 }
1475
1476 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1477 {
1478     env->CP0_TagHi = arg1; /* XXX */
1479 }
1480
1481 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1482 {
1483     env->CP0_DataHi = arg1; /* XXX */
1484 }
1485
1486 /* MIPS MT functions */
1487 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1488 {
1489     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1490     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1491
1492     if (other_tc == other->current_tc) {
1493         return other->active_tc.gpr[sel];
1494     } else {
1495         return other->tcs[other_tc].gpr[sel];
1496     }
1497 }
1498
1499 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1500 {
1501     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1502     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1503
1504     if (other_tc == other->current_tc) {
1505         return other->active_tc.LO[sel];
1506     } else {
1507         return other->tcs[other_tc].LO[sel];
1508     }
1509 }
1510
1511 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1512 {
1513     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1514     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1515
1516     if (other_tc == other->current_tc) {
1517         return other->active_tc.HI[sel];
1518     } else {
1519         return other->tcs[other_tc].HI[sel];
1520     }
1521 }
1522
1523 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1524 {
1525     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1526     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1527
1528     if (other_tc == other->current_tc) {
1529         return other->active_tc.ACX[sel];
1530     } else {
1531         return other->tcs[other_tc].ACX[sel];
1532     }
1533 }
1534
1535 target_ulong helper_mftdsp(CPUMIPSState *env)
1536 {
1537     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1538     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1539
1540     if (other_tc == other->current_tc) {
1541         return other->active_tc.DSPControl;
1542     } else {
1543         return other->tcs[other_tc].DSPControl;
1544     }
1545 }
1546
1547 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1548 {
1549     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1550     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1551
1552     if (other_tc == other->current_tc) {
1553         other->active_tc.gpr[sel] = arg1;
1554     } else {
1555         other->tcs[other_tc].gpr[sel] = arg1;
1556     }
1557 }
1558
1559 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1560 {
1561     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1562     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1563
1564     if (other_tc == other->current_tc) {
1565         other->active_tc.LO[sel] = arg1;
1566     } else {
1567         other->tcs[other_tc].LO[sel] = arg1;
1568     }
1569 }
1570
1571 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1572 {
1573     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1574     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1575
1576     if (other_tc == other->current_tc) {
1577         other->active_tc.HI[sel] = arg1;
1578     } else {
1579         other->tcs[other_tc].HI[sel] = arg1;
1580     }
1581 }
1582
1583 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1584 {
1585     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1586     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1587
1588     if (other_tc == other->current_tc) {
1589         other->active_tc.ACX[sel] = arg1;
1590     } else {
1591         other->tcs[other_tc].ACX[sel] = arg1;
1592     }
1593 }
1594
1595 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1596 {
1597     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1598     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1599
1600     if (other_tc == other->current_tc) {
1601         other->active_tc.DSPControl = arg1;
1602     } else {
1603         other->tcs[other_tc].DSPControl = arg1;
1604     }
1605 }
1606
1607 /* MIPS MT functions */
1608 target_ulong helper_dmt(void)
1609 {
1610     /* TODO */
1611     return 0;
1612 }
1613
1614 target_ulong helper_emt(void)
1615 {
1616     /* TODO */
1617     return 0;
1618 }
1619
1620 target_ulong helper_dvpe(CPUMIPSState *env)
1621 {
1622     CPUState *other_cs = first_cpu;
1623     target_ulong prev = env->mvp->CP0_MVPControl;
1624
1625     CPU_FOREACH(other_cs) {
1626         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1627         /* Turn off all VPEs except the one executing the dvpe.  */
1628         if (&other_cpu->env != env) {
1629             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1630             mips_vpe_sleep(other_cpu);
1631         }
1632     }
1633     return prev;
1634 }
1635
1636 target_ulong helper_evpe(CPUMIPSState *env)
1637 {
1638     CPUState *other_cs = first_cpu;
1639     target_ulong prev = env->mvp->CP0_MVPControl;
1640
1641     CPU_FOREACH(other_cs) {
1642         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1643
1644         if (&other_cpu->env != env
1645             /* If the VPE is WFI, don't disturb its sleep.  */
1646             && !mips_vpe_is_wfi(other_cpu)) {
1647             /* Enable the VPE.  */
1648             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1649             mips_vpe_wake(other_cpu); /* And wake it up.  */
1650         }
1651     }
1652     return prev;
1653 }
1654 #endif /* !CONFIG_USER_ONLY */
1655
1656 /* R6 Multi-threading */
1657 #ifndef CONFIG_USER_ONLY
1658 target_ulong helper_dvp(CPUMIPSState *env)
1659 {
1660     CPUState *other_cs = first_cpu;
1661     target_ulong prev = env->CP0_VPControl;
1662
1663     if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1664         CPU_FOREACH(other_cs) {
1665             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1666             /* Turn off all VPs except the one executing the dvp. */
1667             if (&other_cpu->env != env) {
1668                 mips_vpe_sleep(other_cpu);
1669             }
1670         }
1671         env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1672     }
1673     return prev;
1674 }
1675
1676 target_ulong helper_evp(CPUMIPSState *env)
1677 {
1678     CPUState *other_cs = first_cpu;
1679     target_ulong prev = env->CP0_VPControl;
1680
1681     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1682         CPU_FOREACH(other_cs) {
1683             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1684             if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1685                 /*
1686                  * If the VP is WFI, don't disturb its sleep.
1687                  * Otherwise, wake it up.
1688                  */
1689                 mips_vpe_wake(other_cpu);
1690             }
1691         }
1692         env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1693     }
1694     return prev;
1695 }
1696 #endif /* !CONFIG_USER_ONLY */