include/block/nvme.h

   1 #ifndef BLOCK_NVME_H
   2 #define BLOCK_NVME_H
   3
   4 typedef struct QEMU_PACKED NvmeBar {
   5     uint64_t    cap;
   6     uint32_t    vs;
   7     uint32_t    intms;
   8     uint32_t    intmc;
   9     uint32_t    cc;
  10     uint32_t    rsvd1;
  11     uint32_t    csts;
  12     uint32_t    nssrc;
  13     uint32_t    aqa;
  14     uint64_t    asq;
  15     uint64_t    acq;
  16     uint32_t    cmbloc;
  17     uint32_t    cmbsz;
  18     uint32_t    bpinfo;
  19     uint32_t    bprsel;
  20     uint64_t    bpmbl;
  21     uint64_t    cmbmsc;
  22     uint32_t    cmbsts;
  23     uint8_t     rsvd92[3492];
  24     uint32_t    pmrcap;
  25     uint32_t    pmrctl;
  26     uint32_t    pmrsts;
  27     uint32_t    pmrebs;
  28     uint32_t    pmrswtp;
  29     uint64_t    pmrmsc;
  30     uint8_t     css[484];
  31 } NvmeBar;
  32
  33 enum NvmeCapShift {
  34     CAP_MQES_SHIFT     = 0,
  35     CAP_CQR_SHIFT      = 16,
  36     CAP_AMS_SHIFT      = 17,
  37     CAP_TO_SHIFT       = 24,
  38     CAP_DSTRD_SHIFT    = 32,
  39     CAP_NSSRS_SHIFT    = 36,
  40     CAP_CSS_SHIFT      = 37,
  41     CAP_MPSMIN_SHIFT   = 48,
  42     CAP_MPSMAX_SHIFT   = 52,
  43     CAP_PMRS_SHIFT     = 56,
  44     CAP_CMBS_SHIFT     = 57,
  45 };
  46
  47 enum NvmeCapMask {
  48     CAP_MQES_MASK      = 0xffff,
  49     CAP_CQR_MASK       = 0x1,
  50     CAP_AMS_MASK       = 0x3,
  51     CAP_TO_MASK        = 0xff,
  52     CAP_DSTRD_MASK     = 0xf,
  53     CAP_NSSRS_MASK     = 0x1,
  54     CAP_CSS_MASK       = 0xff,
  55     CAP_MPSMIN_MASK    = 0xf,
  56     CAP_MPSMAX_MASK    = 0xf,
  57     CAP_PMRS_MASK      = 0x1,
  58     CAP_CMBS_MASK      = 0x1,
  59 };
  60
  61 #define NVME_CAP_MQES(cap)  (((cap) >> CAP_MQES_SHIFT)   & CAP_MQES_MASK)
  62 #define NVME_CAP_CQR(cap)   (((cap) >> CAP_CQR_SHIFT)    & CAP_CQR_MASK)
  63 #define NVME_CAP_AMS(cap)   (((cap) >> CAP_AMS_SHIFT)    & CAP_AMS_MASK)
  64 #define NVME_CAP_TO(cap)    (((cap) >> CAP_TO_SHIFT)     & CAP_TO_MASK)
  65 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT)  & CAP_DSTRD_MASK)
  66 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT)  & CAP_NSSRS_MASK)
  67 #define NVME_CAP_CSS(cap)   (((cap) >> CAP_CSS_SHIFT)    & CAP_CSS_MASK)
  68 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK)
  69 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK)
  70 #define NVME_CAP_PMRS(cap)  (((cap) >> CAP_PMRS_SHIFT)   & CAP_PMRS_MASK)
  71 #define NVME_CAP_CMBS(cap)  (((cap) >> CAP_CMBS_SHIFT)   & CAP_CMBS_MASK)
  72
  73 #define NVME_CAP_SET_MQES(cap, val)   (cap |= (uint64_t)(val & CAP_MQES_MASK)  \
  74                                                            << CAP_MQES_SHIFT)
  75 #define NVME_CAP_SET_CQR(cap, val)    (cap |= (uint64_t)(val & CAP_CQR_MASK)   \
  76                                                            << CAP_CQR_SHIFT)
  77 #define NVME_CAP_SET_AMS(cap, val)    (cap |= (uint64_t)(val & CAP_AMS_MASK)   \
  78                                                            << CAP_AMS_SHIFT)
  79 #define NVME_CAP_SET_TO(cap, val)     (cap |= (uint64_t)(val & CAP_TO_MASK)    \
  80                                                            << CAP_TO_SHIFT)
  81 #define NVME_CAP_SET_DSTRD(cap, val)  (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \
  82                                                            << CAP_DSTRD_SHIFT)
  83 #define NVME_CAP_SET_NSSRS(cap, val)  (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \
  84                                                            << CAP_NSSRS_SHIFT)
  85 #define NVME_CAP_SET_CSS(cap, val)    (cap |= (uint64_t)(val & CAP_CSS_MASK)   \
  86                                                            << CAP_CSS_SHIFT)
  87 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\
  88                                                            << CAP_MPSMIN_SHIFT)
  89 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
  90                                                            << CAP_MPSMAX_SHIFT)
  91 #define NVME_CAP_SET_PMRS(cap, val)   (cap |= (uint64_t)(val & CAP_PMRS_MASK)  \
  92                                                            << CAP_PMRS_SHIFT)
  93 #define NVME_CAP_SET_CMBS(cap, val)   (cap |= (uint64_t)(val & CAP_CMBS_MASK)  \
  94                                                            << CAP_CMBS_SHIFT)
  95
  96 enum NvmeCapCss {
  97     NVME_CAP_CSS_NVM        = 1 << 0,
  98     NVME_CAP_CSS_CSI_SUPP   = 1 << 6,
  99     NVME_CAP_CSS_ADMIN_ONLY = 1 << 7,
 100 };
 101
 102 enum NvmeCcShift {
 103     CC_EN_SHIFT     = 0,
 104     CC_CSS_SHIFT    = 4,
 105     CC_MPS_SHIFT    = 7,
 106     CC_AMS_SHIFT    = 11,
 107     CC_SHN_SHIFT    = 14,
 108     CC_IOSQES_SHIFT = 16,
 109     CC_IOCQES_SHIFT = 20,
 110 };
 111
 112 enum NvmeCcMask {
 113     CC_EN_MASK      = 0x1,
 114     CC_CSS_MASK     = 0x7,
 115     CC_MPS_MASK     = 0xf,
 116     CC_AMS_MASK     = 0x7,
 117     CC_SHN_MASK     = 0x3,
 118     CC_IOSQES_MASK  = 0xf,
 119     CC_IOCQES_MASK  = 0xf,
 120 };
 121
 122 #define NVME_CC_EN(cc)     ((cc >> CC_EN_SHIFT)     & CC_EN_MASK)
 123 #define NVME_CC_CSS(cc)    ((cc >> CC_CSS_SHIFT)    & CC_CSS_MASK)
 124 #define NVME_CC_MPS(cc)    ((cc >> CC_MPS_SHIFT)    & CC_MPS_MASK)
 125 #define NVME_CC_AMS(cc)    ((cc >> CC_AMS_SHIFT)    & CC_AMS_MASK)
 126 #define NVME_CC_SHN(cc)    ((cc >> CC_SHN_SHIFT)    & CC_SHN_MASK)
 127 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK)
 128 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK)
 129
 130 enum NvmeCcCss {
 131     NVME_CC_CSS_NVM        = 0x0,
 132     NVME_CC_CSS_CSI        = 0x6,
 133     NVME_CC_CSS_ADMIN_ONLY = 0x7,
 134 };
 135
 136 #define NVME_SET_CC_EN(cc, val)     \
 137     (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT)
 138 #define NVME_SET_CC_CSS(cc, val)    \
 139     (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT)
 140 #define NVME_SET_CC_MPS(cc, val)    \
 141     (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT)
 142 #define NVME_SET_CC_AMS(cc, val)    \
 143     (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT)
 144 #define NVME_SET_CC_SHN(cc, val)    \
 145     (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT)
 146 #define NVME_SET_CC_IOSQES(cc, val) \
 147     (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT)
 148 #define NVME_SET_CC_IOCQES(cc, val) \
 149     (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT)
 150
 151 enum NvmeCstsShift {
 152     CSTS_RDY_SHIFT      = 0,
 153     CSTS_CFS_SHIFT      = 1,
 154     CSTS_SHST_SHIFT     = 2,
 155     CSTS_NSSRO_SHIFT    = 4,
 156 };
 157
 158 enum NvmeCstsMask {
 159     CSTS_RDY_MASK   = 0x1,
 160     CSTS_CFS_MASK   = 0x1,
 161     CSTS_SHST_MASK  = 0x3,
 162     CSTS_NSSRO_MASK = 0x1,
 163 };
 164
 165 enum NvmeCsts {
 166     NVME_CSTS_READY         = 1 << CSTS_RDY_SHIFT,
 167     NVME_CSTS_FAILED        = 1 << CSTS_CFS_SHIFT,
 168     NVME_CSTS_SHST_NORMAL   = 0 << CSTS_SHST_SHIFT,
 169     NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT,
 170     NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT,
 171     NVME_CSTS_NSSRO         = 1 << CSTS_NSSRO_SHIFT,
 172 };
 173
 174 #define NVME_CSTS_RDY(csts)     ((csts >> CSTS_RDY_SHIFT)   & CSTS_RDY_MASK)
 175 #define NVME_CSTS_CFS(csts)     ((csts >> CSTS_CFS_SHIFT)   & CSTS_CFS_MASK)
 176 #define NVME_CSTS_SHST(csts)    ((csts >> CSTS_SHST_SHIFT)  & CSTS_SHST_MASK)
 177 #define NVME_CSTS_NSSRO(csts)   ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK)
 178
 179 enum NvmeAqaShift {
 180     AQA_ASQS_SHIFT  = 0,
 181     AQA_ACQS_SHIFT  = 16,
 182 };
 183
 184 enum NvmeAqaMask {
 185     AQA_ASQS_MASK   = 0xfff,
 186     AQA_ACQS_MASK   = 0xfff,
 187 };
 188
 189 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK)
 190 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK)
 191
 192 enum NvmeCmblocShift {
 193     CMBLOC_BIR_SHIFT     = 0,
 194     CMBLOC_CQMMS_SHIFT   = 3,
 195     CMBLOC_CQPDS_SHIFT   = 4,
 196     CMBLOC_CDPMLS_SHIFT  = 5,
 197     CMBLOC_CDPCILS_SHIFT = 6,
 198     CMBLOC_CDMMMS_SHIFT  = 7,
 199     CMBLOC_CQDA_SHIFT    = 8,
 200     CMBLOC_OFST_SHIFT    = 12,
 201 };
 202
 203 enum NvmeCmblocMask {
 204     CMBLOC_BIR_MASK     = 0x7,
 205     CMBLOC_CQMMS_MASK   = 0x1,
 206     CMBLOC_CQPDS_MASK   = 0x1,
 207     CMBLOC_CDPMLS_MASK  = 0x1,
 208     CMBLOC_CDPCILS_MASK = 0x1,
 209     CMBLOC_CDMMMS_MASK  = 0x1,
 210     CMBLOC_CQDA_MASK    = 0x1,
 211     CMBLOC_OFST_MASK    = 0xfffff,
 212 };
 213
 214 #define NVME_CMBLOC_BIR(cmbloc) \
 215     ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK)
 216 #define NVME_CMBLOC_CQMMS(cmbloc) \
 217     ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK)
 218 #define NVME_CMBLOC_CQPDS(cmbloc) \
 219     ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK)
 220 #define NVME_CMBLOC_CDPMLS(cmbloc) \
 221     ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK)
 222 #define NVME_CMBLOC_CDPCILS(cmbloc) \
 223     ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK)
 224 #define NVME_CMBLOC_CDMMMS(cmbloc) \
 225     ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK)
 226 #define NVME_CMBLOC_CQDA(cmbloc) \
 227     ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK)
 228 #define NVME_CMBLOC_OFST(cmbloc) \
 229     ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK)
 230
 231 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \
 232     (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT)
 233 #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \
 234     (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT)
 235 #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \
 236     (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT)
 237 #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \
 238     (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT)
 239 #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \
 240     (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT)
 241 #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \
 242     (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT)
 243 #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \
 244     (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT)
 245 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \
 246     (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT)
 247
 248 #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \
 249     (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT)
 250
 251 enum NvmeCmbszShift {
 252     CMBSZ_SQS_SHIFT   = 0,
 253     CMBSZ_CQS_SHIFT   = 1,
 254     CMBSZ_LISTS_SHIFT = 2,
 255     CMBSZ_RDS_SHIFT   = 3,
 256     CMBSZ_WDS_SHIFT   = 4,
 257     CMBSZ_SZU_SHIFT   = 8,
 258     CMBSZ_SZ_SHIFT    = 12,
 259 };
 260
 261 enum NvmeCmbszMask {
 262     CMBSZ_SQS_MASK   = 0x1,
 263     CMBSZ_CQS_MASK   = 0x1,
 264     CMBSZ_LISTS_MASK = 0x1,
 265     CMBSZ_RDS_MASK   = 0x1,
 266     CMBSZ_WDS_MASK   = 0x1,
 267     CMBSZ_SZU_MASK   = 0xf,
 268     CMBSZ_SZ_MASK    = 0xfffff,
 269 };
 270
 271 #define NVME_CMBSZ_SQS(cmbsz)  ((cmbsz >> CMBSZ_SQS_SHIFT)   & CMBSZ_SQS_MASK)
 272 #define NVME_CMBSZ_CQS(cmbsz)  ((cmbsz >> CMBSZ_CQS_SHIFT)   & CMBSZ_CQS_MASK)
 273 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK)
 274 #define NVME_CMBSZ_RDS(cmbsz)  ((cmbsz >> CMBSZ_RDS_SHIFT)   & CMBSZ_RDS_MASK)
 275 #define NVME_CMBSZ_WDS(cmbsz)  ((cmbsz >> CMBSZ_WDS_SHIFT)   & CMBSZ_WDS_MASK)
 276 #define NVME_CMBSZ_SZU(cmbsz)  ((cmbsz >> CMBSZ_SZU_SHIFT)   & CMBSZ_SZU_MASK)
 277 #define NVME_CMBSZ_SZ(cmbsz)   ((cmbsz >> CMBSZ_SZ_SHIFT)    & CMBSZ_SZ_MASK)
 278
 279 #define NVME_CMBSZ_SET_SQS(cmbsz, val)   \
 280     (cmbsz |= (uint64_t)(val &  CMBSZ_SQS_MASK)  << CMBSZ_SQS_SHIFT)
 281 #define NVME_CMBSZ_SET_CQS(cmbsz, val)   \
 282     (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT)
 283 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \
 284     (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT)
 285 #define NVME_CMBSZ_SET_RDS(cmbsz, val)   \
 286     (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT)
 287 #define NVME_CMBSZ_SET_WDS(cmbsz, val)   \
 288     (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT)
 289 #define NVME_CMBSZ_SET_SZU(cmbsz, val)   \
 290     (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT)
 291 #define NVME_CMBSZ_SET_SZ(cmbsz, val)    \
 292     (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT)
 293
 294 #define NVME_CMBSZ_GETSIZE(cmbsz) \
 295     (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz))))
 296
 297 enum NvmeCmbmscShift {
 298     CMBMSC_CRE_SHIFT  = 0,
 299     CMBMSC_CMSE_SHIFT = 1,
 300     CMBMSC_CBA_SHIFT  = 12,
 301 };
 302
 303 enum NvmeCmbmscMask {
 304     CMBMSC_CRE_MASK  = 0x1,
 305     CMBMSC_CMSE_MASK = 0x1,
 306     CMBMSC_CBA_MASK  = ((1ULL << 52) - 1),
 307 };
 308
 309 #define NVME_CMBMSC_CRE(cmbmsc) \
 310     ((cmbmsc >> CMBMSC_CRE_SHIFT)  & CMBMSC_CRE_MASK)
 311 #define NVME_CMBMSC_CMSE(cmbmsc) \
 312     ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK)
 313 #define NVME_CMBMSC_CBA(cmbmsc) \
 314     ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK)
 315
 316
 317 #define NVME_CMBMSC_SET_CRE(cmbmsc, val)  \
 318     (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT)
 319 #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \
 320     (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT)
 321 #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \
 322     (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT)
 323
 324 enum NvmeCmbstsShift {
 325     CMBSTS_CBAI_SHIFT = 0,
 326 };
 327 enum NvmeCmbstsMask {
 328     CMBSTS_CBAI_MASK = 0x1,
 329 };
 330
 331 #define NVME_CMBSTS_CBAI(cmbsts) \
 332     ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK)
 333
 334 #define NVME_CMBSTS_SET_CBAI(cmbsts, val)  \
 335     (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT)
 336
 337 enum NvmePmrcapShift {
 338     PMRCAP_RDS_SHIFT      = 3,
 339     PMRCAP_WDS_SHIFT      = 4,
 340     PMRCAP_BIR_SHIFT      = 5,
 341     PMRCAP_PMRTU_SHIFT    = 8,
 342     PMRCAP_PMRWBM_SHIFT   = 10,
 343     PMRCAP_PMRTO_SHIFT    = 16,
 344     PMRCAP_CMSS_SHIFT     = 24,
 345 };
 346
 347 enum NvmePmrcapMask {
 348     PMRCAP_RDS_MASK      = 0x1,
 349     PMRCAP_WDS_MASK      = 0x1,
 350     PMRCAP_BIR_MASK      = 0x7,
 351     PMRCAP_PMRTU_MASK    = 0x3,
 352     PMRCAP_PMRWBM_MASK   = 0xf,
 353     PMRCAP_PMRTO_MASK    = 0xff,
 354     PMRCAP_CMSS_MASK     = 0x1,
 355 };
 356
 357 #define NVME_PMRCAP_RDS(pmrcap)    \
 358     ((pmrcap >> PMRCAP_RDS_SHIFT)   & PMRCAP_RDS_MASK)
 359 #define NVME_PMRCAP_WDS(pmrcap)    \
 360     ((pmrcap >> PMRCAP_WDS_SHIFT)   & PMRCAP_WDS_MASK)
 361 #define NVME_PMRCAP_BIR(pmrcap)    \
 362     ((pmrcap >> PMRCAP_BIR_SHIFT)   & PMRCAP_BIR_MASK)
 363 #define NVME_PMRCAP_PMRTU(pmrcap)    \
 364     ((pmrcap >> PMRCAP_PMRTU_SHIFT)   & PMRCAP_PMRTU_MASK)
 365 #define NVME_PMRCAP_PMRWBM(pmrcap)    \
 366     ((pmrcap >> PMRCAP_PMRWBM_SHIFT)   & PMRCAP_PMRWBM_MASK)
 367 #define NVME_PMRCAP_PMRTO(pmrcap)    \
 368     ((pmrcap >> PMRCAP_PMRTO_SHIFT)   & PMRCAP_PMRTO_MASK)
 369 #define NVME_PMRCAP_CMSS(pmrcap)    \
 370     ((pmrcap >> PMRCAP_CMSS_SHIFT)   & PMRCAP_CMSS_MASK)
 371
 372 #define NVME_PMRCAP_SET_RDS(pmrcap, val)   \
 373     (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT)
 374 #define NVME_PMRCAP_SET_WDS(pmrcap, val)   \
 375     (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT)
 376 #define NVME_PMRCAP_SET_BIR(pmrcap, val)   \
 377     (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT)
 378 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val)   \
 379     (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT)
 380 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val)   \
 381     (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT)
 382 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val)   \
 383     (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT)
 384 #define NVME_PMRCAP_SET_CMSS(pmrcap, val)   \
 385     (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT)
 386
 387 enum NvmePmrctlShift {
 388     PMRCTL_EN_SHIFT   = 0,
 389 };
 390
 391 enum NvmePmrctlMask {
 392     PMRCTL_EN_MASK   = 0x1,
 393 };
 394
 395 #define NVME_PMRCTL_EN(pmrctl)  ((pmrctl >> PMRCTL_EN_SHIFT)   & PMRCTL_EN_MASK)
 396
 397 #define NVME_PMRCTL_SET_EN(pmrctl, val)   \
 398     (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT)
 399
 400 enum NvmePmrstsShift {
 401     PMRSTS_ERR_SHIFT    = 0,
 402     PMRSTS_NRDY_SHIFT   = 8,
 403     PMRSTS_HSTS_SHIFT   = 9,
 404     PMRSTS_CBAI_SHIFT   = 12,
 405 };
 406
 407 enum NvmePmrstsMask {
 408     PMRSTS_ERR_MASK    = 0xff,
 409     PMRSTS_NRDY_MASK   = 0x1,
 410     PMRSTS_HSTS_MASK   = 0x7,
 411     PMRSTS_CBAI_MASK   = 0x1,
 412 };
 413
 414 #define NVME_PMRSTS_ERR(pmrsts)     \
 415     ((pmrsts >> PMRSTS_ERR_SHIFT)   & PMRSTS_ERR_MASK)
 416 #define NVME_PMRSTS_NRDY(pmrsts)    \
 417     ((pmrsts >> PMRSTS_NRDY_SHIFT)   & PMRSTS_NRDY_MASK)
 418 #define NVME_PMRSTS_HSTS(pmrsts)    \
 419     ((pmrsts >> PMRSTS_HSTS_SHIFT)   & PMRSTS_HSTS_MASK)
 420 #define NVME_PMRSTS_CBAI(pmrsts)    \
 421     ((pmrsts >> PMRSTS_CBAI_SHIFT)   & PMRSTS_CBAI_MASK)
 422
 423 #define NVME_PMRSTS_SET_ERR(pmrsts, val)   \
 424     (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT)
 425 #define NVME_PMRSTS_SET_NRDY(pmrsts, val)   \
 426     (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT)
 427 #define NVME_PMRSTS_SET_HSTS(pmrsts, val)   \
 428     (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT)
 429 #define NVME_PMRSTS_SET_CBAI(pmrsts, val)   \
 430     (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT)
 431
 432 enum NvmePmrebsShift {
 433     PMREBS_PMRSZU_SHIFT   = 0,
 434     PMREBS_RBB_SHIFT      = 4,
 435     PMREBS_PMRWBZ_SHIFT   = 8,
 436 };
 437
 438 enum NvmePmrebsMask {
 439     PMREBS_PMRSZU_MASK   = 0xf,
 440     PMREBS_RBB_MASK      = 0x1,
 441     PMREBS_PMRWBZ_MASK   = 0xffffff,
 442 };
 443
 444 #define NVME_PMREBS_PMRSZU(pmrebs)  \
 445     ((pmrebs >> PMREBS_PMRSZU_SHIFT)   & PMREBS_PMRSZU_MASK)
 446 #define NVME_PMREBS_RBB(pmrebs)     \
 447     ((pmrebs >> PMREBS_RBB_SHIFT)   & PMREBS_RBB_MASK)
 448 #define NVME_PMREBS_PMRWBZ(pmrebs)  \
 449     ((pmrebs >> PMREBS_PMRWBZ_SHIFT)   & PMREBS_PMRWBZ_MASK)
 450
 451 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val)   \
 452     (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT)
 453 #define NVME_PMREBS_SET_RBB(pmrebs, val)   \
 454     (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT)
 455 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val)   \
 456     (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT)
 457
 458 enum NvmePmrswtpShift {
 459     PMRSWTP_PMRSWTU_SHIFT   = 0,
 460     PMRSWTP_PMRSWTV_SHIFT   = 8,
 461 };
 462
 463 enum NvmePmrswtpMask {
 464     PMRSWTP_PMRSWTU_MASK   = 0xf,
 465     PMRSWTP_PMRSWTV_MASK   = 0xffffff,
 466 };
 467
 468 #define NVME_PMRSWTP_PMRSWTU(pmrswtp)   \
 469     ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT)   & PMRSWTP_PMRSWTU_MASK)
 470 #define NVME_PMRSWTP_PMRSWTV(pmrswtp)   \
 471     ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT)   & PMRSWTP_PMRSWTV_MASK)
 472
 473 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val)   \
 474     (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT)
 475 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val)   \
 476     (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT)
 477
 478 enum NvmePmrmscShift {
 479     PMRMSC_CMSE_SHIFT   = 1,
 480     PMRMSC_CBA_SHIFT    = 12,
 481 };
 482
 483 enum NvmePmrmscMask {
 484     PMRMSC_CMSE_MASK   = 0x1,
 485     PMRMSC_CBA_MASK    = 0xfffffffffffff,
 486 };
 487
 488 #define NVME_PMRMSC_CMSE(pmrmsc)    \
 489     ((pmrmsc >> PMRMSC_CMSE_SHIFT)   & PMRMSC_CMSE_MASK)
 490 #define NVME_PMRMSC_CBA(pmrmsc)     \
 491     ((pmrmsc >> PMRMSC_CBA_SHIFT)   & PMRMSC_CBA_MASK)
 492
 493 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val)   \
 494     (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT)
 495 #define NVME_PMRMSC_SET_CBA(pmrmsc, val)   \
 496     (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT)
 497
 498 enum NvmeSglDescriptorType {
 499     NVME_SGL_DESCR_TYPE_DATA_BLOCK          = 0x0,
 500     NVME_SGL_DESCR_TYPE_BIT_BUCKET          = 0x1,
 501     NVME_SGL_DESCR_TYPE_SEGMENT             = 0x2,
 502     NVME_SGL_DESCR_TYPE_LAST_SEGMENT        = 0x3,
 503     NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK    = 0x4,
 504
 505     NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC     = 0xf,
 506 };
 507
 508 enum NvmeSglDescriptorSubtype {
 509     NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0,
 510 };
 511
 512 typedef struct QEMU_PACKED NvmeSglDescriptor {
 513     uint64_t addr;
 514     uint32_t len;
 515     uint8_t  rsvd[3];
 516     uint8_t  type;
 517 } NvmeSglDescriptor;
 518
 519 #define NVME_SGL_TYPE(type)     ((type >> 4) & 0xf)
 520 #define NVME_SGL_SUBTYPE(type)  (type & 0xf)
 521
 522 typedef union NvmeCmdDptr {
 523     struct {
 524         uint64_t    prp1;
 525         uint64_t    prp2;
 526     };
 527
 528     NvmeSglDescriptor sgl;
 529 } NvmeCmdDptr;
 530
 531 enum NvmePsdt {
 532     NVME_PSDT_PRP                 = 0x0,
 533     NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1,
 534     NVME_PSDT_SGL_MPTR_SGL        = 0x2,
 535 };
 536
 537 typedef struct QEMU_PACKED NvmeCmd {
 538     uint8_t     opcode;
 539     uint8_t     flags;
 540     uint16_t    cid;
 541     uint32_t    nsid;
 542     uint64_t    res1;
 543     uint64_t    mptr;
 544     NvmeCmdDptr dptr;
 545     uint32_t    cdw10;
 546     uint32_t    cdw11;
 547     uint32_t    cdw12;
 548     uint32_t    cdw13;
 549     uint32_t    cdw14;
 550     uint32_t    cdw15;
 551 } NvmeCmd;
 552
 553 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3)
 554 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3)
 555
 556 enum NvmeAdminCommands {
 557     NVME_ADM_CMD_DELETE_SQ      = 0x00,
 558     NVME_ADM_CMD_CREATE_SQ      = 0x01,
 559     NVME_ADM_CMD_GET_LOG_PAGE   = 0x02,
 560     NVME_ADM_CMD_DELETE_CQ      = 0x04,
 561     NVME_ADM_CMD_CREATE_CQ      = 0x05,
 562     NVME_ADM_CMD_IDENTIFY       = 0x06,
 563     NVME_ADM_CMD_ABORT          = 0x08,
 564     NVME_ADM_CMD_SET_FEATURES   = 0x09,
 565     NVME_ADM_CMD_GET_FEATURES   = 0x0a,
 566     NVME_ADM_CMD_ASYNC_EV_REQ   = 0x0c,
 567     NVME_ADM_CMD_ACTIVATE_FW    = 0x10,
 568     NVME_ADM_CMD_DOWNLOAD_FW    = 0x11,
 569     NVME_ADM_CMD_NS_ATTACHMENT  = 0x15,
 570     NVME_ADM_CMD_FORMAT_NVM     = 0x80,
 571     NVME_ADM_CMD_SECURITY_SEND  = 0x81,
 572     NVME_ADM_CMD_SECURITY_RECV  = 0x82,
 573 };
 574
 575 enum NvmeIoCommands {
 576     NVME_CMD_FLUSH              = 0x00,
 577     NVME_CMD_WRITE              = 0x01,
 578     NVME_CMD_READ               = 0x02,
 579     NVME_CMD_WRITE_UNCOR        = 0x04,
 580     NVME_CMD_COMPARE            = 0x05,
 581     NVME_CMD_WRITE_ZEROES       = 0x08,
 582     NVME_CMD_DSM                = 0x09,
 583     NVME_CMD_VERIFY             = 0x0c,
 584     NVME_CMD_COPY               = 0x19,
 585     NVME_CMD_ZONE_MGMT_SEND     = 0x79,
 586     NVME_CMD_ZONE_MGMT_RECV     = 0x7a,
 587     NVME_CMD_ZONE_APPEND        = 0x7d,
 588 };
 589
 590 typedef struct QEMU_PACKED NvmeDeleteQ {
 591     uint8_t     opcode;
 592     uint8_t     flags;
 593     uint16_t    cid;
 594     uint32_t    rsvd1[9];
 595     uint16_t    qid;
 596     uint16_t    rsvd10;
 597     uint32_t    rsvd11[5];
 598 } NvmeDeleteQ;
 599
 600 typedef struct QEMU_PACKED NvmeCreateCq {
 601     uint8_t     opcode;
 602     uint8_t     flags;
 603     uint16_t    cid;
 604     uint32_t    rsvd1[5];
 605     uint64_t    prp1;
 606     uint64_t    rsvd8;
 607     uint16_t    cqid;
 608     uint16_t    qsize;
 609     uint16_t    cq_flags;
 610     uint16_t    irq_vector;
 611     uint32_t    rsvd12[4];
 612 } NvmeCreateCq;
 613
 614 #define NVME_CQ_FLAGS_PC(cq_flags)  (cq_flags & 0x1)
 615 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1)
 616
 617 enum NvmeFlagsCq {
 618     NVME_CQ_PC          = 1,
 619     NVME_CQ_IEN         = 2,
 620 };
 621
 622 typedef struct QEMU_PACKED NvmeCreateSq {
 623     uint8_t     opcode;
 624     uint8_t     flags;
 625     uint16_t    cid;
 626     uint32_t    rsvd1[5];
 627     uint64_t    prp1;
 628     uint64_t    rsvd8;
 629     uint16_t    sqid;
 630     uint16_t    qsize;
 631     uint16_t    sq_flags;
 632     uint16_t    cqid;
 633     uint32_t    rsvd12[4];
 634 } NvmeCreateSq;
 635
 636 #define NVME_SQ_FLAGS_PC(sq_flags)      (sq_flags & 0x1)
 637 #define NVME_SQ_FLAGS_QPRIO(sq_flags)   ((sq_flags >> 1) & 0x3)
 638
 639 enum NvmeFlagsSq {
 640     NVME_SQ_PC          = 1,
 641
 642     NVME_SQ_PRIO_URGENT = 0,
 643     NVME_SQ_PRIO_HIGH   = 1,
 644     NVME_SQ_PRIO_NORMAL = 2,
 645     NVME_SQ_PRIO_LOW    = 3,
 646 };
 647
 648 typedef struct QEMU_PACKED NvmeIdentify {
 649     uint8_t     opcode;
 650     uint8_t     flags;
 651     uint16_t    cid;
 652     uint32_t    nsid;
 653     uint64_t    rsvd2[2];
 654     uint64_t    prp1;
 655     uint64_t    prp2;
 656     uint8_t     cns;
 657     uint8_t     rsvd10;
 658     uint16_t    ctrlid;
 659     uint16_t    nvmsetid;
 660     uint8_t     rsvd11;
 661     uint8_t     csi;
 662     uint32_t    rsvd12[4];
 663 } NvmeIdentify;
 664
 665 typedef struct QEMU_PACKED NvmeRwCmd {
 666     uint8_t     opcode;
 667     uint8_t     flags;
 668     uint16_t    cid;
 669     uint32_t    nsid;
 670     uint64_t    rsvd2;
 671     uint64_t    mptr;
 672     NvmeCmdDptr dptr;
 673     uint64_t    slba;
 674     uint16_t    nlb;
 675     uint16_t    control;
 676     uint32_t    dsmgmt;
 677     uint32_t    reftag;
 678     uint16_t    apptag;
 679     uint16_t    appmask;
 680 } NvmeRwCmd;
 681
 682 enum {
 683     NVME_RW_LR                  = 1 << 15,
 684     NVME_RW_FUA                 = 1 << 14,
 685     NVME_RW_DSM_FREQ_UNSPEC     = 0,
 686     NVME_RW_DSM_FREQ_TYPICAL    = 1,
 687     NVME_RW_DSM_FREQ_RARE       = 2,
 688     NVME_RW_DSM_FREQ_READS      = 3,
 689     NVME_RW_DSM_FREQ_WRITES     = 4,
 690     NVME_RW_DSM_FREQ_RW         = 5,
 691     NVME_RW_DSM_FREQ_ONCE       = 6,
 692     NVME_RW_DSM_FREQ_PREFETCH   = 7,
 693     NVME_RW_DSM_FREQ_TEMP       = 8,
 694     NVME_RW_DSM_LATENCY_NONE    = 0 << 4,
 695     NVME_RW_DSM_LATENCY_IDLE    = 1 << 4,
 696     NVME_RW_DSM_LATENCY_NORM    = 2 << 4,
 697     NVME_RW_DSM_LATENCY_LOW     = 3 << 4,
 698     NVME_RW_DSM_SEQ_REQ         = 1 << 6,
 699     NVME_RW_DSM_COMPRESSED      = 1 << 7,
 700     NVME_RW_PIREMAP             = 1 << 9,
 701     NVME_RW_PRINFO_PRACT        = 1 << 13,
 702     NVME_RW_PRINFO_PRCHK_GUARD  = 1 << 12,
 703     NVME_RW_PRINFO_PRCHK_APP    = 1 << 11,
 704     NVME_RW_PRINFO_PRCHK_REF    = 1 << 10,
 705     NVME_RW_PRINFO_PRCHK_MASK   = 7 << 10,
 706
 707 };
 708
 709 #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf)
 710
 711 typedef struct QEMU_PACKED NvmeDsmCmd {
 712     uint8_t     opcode;
 713     uint8_t     flags;
 714     uint16_t    cid;
 715     uint32_t    nsid;
 716     uint64_t    rsvd2[2];
 717     NvmeCmdDptr dptr;
 718     uint32_t    nr;
 719     uint32_t    attributes;
 720     uint32_t    rsvd12[4];
 721 } NvmeDsmCmd;
 722
 723 enum {
 724     NVME_DSMGMT_IDR = 1 << 0,
 725     NVME_DSMGMT_IDW = 1 << 1,
 726     NVME_DSMGMT_AD  = 1 << 2,
 727 };
 728
 729 typedef struct QEMU_PACKED NvmeDsmRange {
 730     uint32_t    cattr;
 731     uint32_t    nlb;
 732     uint64_t    slba;
 733 } NvmeDsmRange;
 734
 735 enum {
 736     NVME_COPY_FORMAT_0 = 0x0,
 737 };
 738
 739 typedef struct QEMU_PACKED NvmeCopyCmd {
 740     uint8_t     opcode;
 741     uint8_t     flags;
 742     uint16_t    cid;
 743     uint32_t    nsid;
 744     uint32_t    rsvd2[4];
 745     NvmeCmdDptr dptr;
 746     uint64_t    sdlba;
 747     uint8_t     nr;
 748     uint8_t     control[3];
 749     uint16_t    rsvd13;
 750     uint16_t    dspec;
 751     uint32_t    reftag;
 752     uint16_t    apptag;
 753     uint16_t    appmask;
 754 } NvmeCopyCmd;
 755
 756 typedef struct QEMU_PACKED NvmeCopySourceRange {
 757     uint8_t  rsvd0[8];
 758     uint64_t slba;
 759     uint16_t nlb;
 760     uint8_t  rsvd18[6];
 761     uint32_t reftag;
 762     uint16_t apptag;
 763     uint16_t appmask;
 764 } NvmeCopySourceRange;
 765
 766 enum NvmeAsyncEventRequest {
 767     NVME_AER_TYPE_ERROR                     = 0,
 768     NVME_AER_TYPE_SMART                     = 1,
 769     NVME_AER_TYPE_NOTICE                    = 2,
 770     NVME_AER_TYPE_IO_SPECIFIC               = 6,
 771     NVME_AER_TYPE_VENDOR_SPECIFIC           = 7,
 772     NVME_AER_INFO_ERR_INVALID_DB_REGISTER   = 0,
 773     NVME_AER_INFO_ERR_INVALID_DB_VALUE      = 1,
 774     NVME_AER_INFO_ERR_DIAG_FAIL             = 2,
 775     NVME_AER_INFO_ERR_PERS_INTERNAL_ERR     = 3,
 776     NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR    = 4,
 777     NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR       = 5,
 778     NVME_AER_INFO_SMART_RELIABILITY         = 0,
 779     NVME_AER_INFO_SMART_TEMP_THRESH         = 1,
 780     NVME_AER_INFO_SMART_SPARE_THRESH        = 2,
 781     NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED    = 0,
 782 };
 783
 784 typedef struct QEMU_PACKED NvmeAerResult {
 785     uint8_t event_type;
 786     uint8_t event_info;
 787     uint8_t log_page;
 788     uint8_t resv;
 789 } NvmeAerResult;
 790
 791 typedef struct QEMU_PACKED NvmeZonedResult {
 792     uint64_t slba;
 793 } NvmeZonedResult;
 794
 795 typedef struct QEMU_PACKED NvmeCqe {
 796     uint32_t    result;
 797     uint32_t    dw1;
 798     uint16_t    sq_head;
 799     uint16_t    sq_id;
 800     uint16_t    cid;
 801     uint16_t    status;
 802 } NvmeCqe;
 803
 804 enum NvmeStatusCodes {
 805     NVME_SUCCESS                = 0x0000,
 806     NVME_INVALID_OPCODE         = 0x0001,
 807     NVME_INVALID_FIELD          = 0x0002,
 808     NVME_CID_CONFLICT           = 0x0003,
 809     NVME_DATA_TRAS_ERROR        = 0x0004,
 810     NVME_POWER_LOSS_ABORT       = 0x0005,
 811     NVME_INTERNAL_DEV_ERROR     = 0x0006,
 812     NVME_CMD_ABORT_REQ          = 0x0007,
 813     NVME_CMD_ABORT_SQ_DEL       = 0x0008,
 814     NVME_CMD_ABORT_FAILED_FUSE  = 0x0009,
 815     NVME_CMD_ABORT_MISSING_FUSE = 0x000a,
 816     NVME_INVALID_NSID           = 0x000b,
 817     NVME_CMD_SEQ_ERROR          = 0x000c,
 818     NVME_INVALID_SGL_SEG_DESCR  = 0x000d,
 819     NVME_INVALID_NUM_SGL_DESCRS = 0x000e,
 820     NVME_DATA_SGL_LEN_INVALID   = 0x000f,
 821     NVME_MD_SGL_LEN_INVALID     = 0x0010,
 822     NVME_SGL_DESCR_TYPE_INVALID = 0x0011,
 823     NVME_INVALID_USE_OF_CMB     = 0x0012,
 824     NVME_INVALID_PRP_OFFSET     = 0x0013,
 825     NVME_CMD_SET_CMB_REJECTED   = 0x002b,
 826     NVME_INVALID_CMD_SET        = 0x002c,
 827     NVME_LBA_RANGE              = 0x0080,
 828     NVME_CAP_EXCEEDED           = 0x0081,
 829     NVME_NS_NOT_READY           = 0x0082,
 830     NVME_NS_RESV_CONFLICT       = 0x0083,
 831     NVME_FORMAT_IN_PROGRESS     = 0x0084,
 832     NVME_INVALID_CQID           = 0x0100,
 833     NVME_INVALID_QID            = 0x0101,
 834     NVME_MAX_QSIZE_EXCEEDED     = 0x0102,
 835     NVME_ACL_EXCEEDED           = 0x0103,
 836     NVME_RESERVED               = 0x0104,
 837     NVME_AER_LIMIT_EXCEEDED     = 0x0105,
 838     NVME_INVALID_FW_SLOT        = 0x0106,
 839     NVME_INVALID_FW_IMAGE       = 0x0107,
 840     NVME_INVALID_IRQ_VECTOR     = 0x0108,
 841     NVME_INVALID_LOG_ID         = 0x0109,
 842     NVME_INVALID_FORMAT         = 0x010a,
 843     NVME_FW_REQ_RESET           = 0x010b,
 844     NVME_INVALID_QUEUE_DEL      = 0x010c,
 845     NVME_FID_NOT_SAVEABLE       = 0x010d,
 846     NVME_FEAT_NOT_CHANGEABLE    = 0x010e,
 847     NVME_FEAT_NOT_NS_SPEC       = 0x010f,
 848     NVME_FW_REQ_SUSYSTEM_RESET  = 0x0110,
 849     NVME_NS_ALREADY_ATTACHED    = 0x0118,
 850     NVME_NS_NOT_ATTACHED        = 0x011A,
 851     NVME_NS_CTRL_LIST_INVALID   = 0x011C,
 852     NVME_CONFLICTING_ATTRS      = 0x0180,
 853     NVME_INVALID_PROT_INFO      = 0x0181,
 854     NVME_WRITE_TO_RO            = 0x0182,
 855     NVME_CMD_SIZE_LIMIT         = 0x0183,
 856     NVME_ZONE_BOUNDARY_ERROR    = 0x01b8,
 857     NVME_ZONE_FULL              = 0x01b9,
 858     NVME_ZONE_READ_ONLY         = 0x01ba,
 859     NVME_ZONE_OFFLINE           = 0x01bb,
 860     NVME_ZONE_INVALID_WRITE     = 0x01bc,
 861     NVME_ZONE_TOO_MANY_ACTIVE   = 0x01bd,
 862     NVME_ZONE_TOO_MANY_OPEN     = 0x01be,
 863     NVME_ZONE_INVAL_TRANSITION  = 0x01bf,
 864     NVME_WRITE_FAULT            = 0x0280,
 865     NVME_UNRECOVERED_READ       = 0x0281,
 866     NVME_E2E_GUARD_ERROR        = 0x0282,
 867     NVME_E2E_APP_ERROR          = 0x0283,
 868     NVME_E2E_REF_ERROR          = 0x0284,
 869     NVME_CMP_FAILURE            = 0x0285,
 870     NVME_ACCESS_DENIED          = 0x0286,
 871     NVME_DULB                   = 0x0287,
 872     NVME_MORE                   = 0x2000,
 873     NVME_DNR                    = 0x4000,
 874     NVME_NO_COMPLETE            = 0xffff,
 875 };
 876
 877 typedef struct QEMU_PACKED NvmeFwSlotInfoLog {
 878     uint8_t     afi;
 879     uint8_t     reserved1[7];
 880     uint8_t     frs1[8];
 881     uint8_t     frs2[8];
 882     uint8_t     frs3[8];
 883     uint8_t     frs4[8];
 884     uint8_t     frs5[8];
 885     uint8_t     frs6[8];
 886     uint8_t     frs7[8];
 887     uint8_t     reserved2[448];
 888 } NvmeFwSlotInfoLog;
 889
 890 typedef struct QEMU_PACKED NvmeErrorLog {
 891     uint64_t    error_count;
 892     uint16_t    sqid;
 893     uint16_t    cid;
 894     uint16_t    status_field;
 895     uint16_t    param_error_location;
 896     uint64_t    lba;
 897     uint32_t    nsid;
 898     uint8_t     vs;
 899     uint8_t     resv[35];
 900 } NvmeErrorLog;
 901
 902 typedef struct QEMU_PACKED NvmeSmartLog {
 903     uint8_t     critical_warning;
 904     uint16_t    temperature;
 905     uint8_t     available_spare;
 906     uint8_t     available_spare_threshold;
 907     uint8_t     percentage_used;
 908     uint8_t     reserved1[26];
 909     uint64_t    data_units_read[2];
 910     uint64_t    data_units_written[2];
 911     uint64_t    host_read_commands[2];
 912     uint64_t    host_write_commands[2];
 913     uint64_t    controller_busy_time[2];
 914     uint64_t    power_cycles[2];
 915     uint64_t    power_on_hours[2];
 916     uint64_t    unsafe_shutdowns[2];
 917     uint64_t    media_errors[2];
 918     uint64_t    number_of_error_log_entries[2];
 919     uint8_t     reserved2[320];
 920 } NvmeSmartLog;
 921
 922 #define NVME_SMART_WARN_MAX     6
 923 enum NvmeSmartWarn {
 924     NVME_SMART_SPARE                  = 1 << 0,
 925     NVME_SMART_TEMPERATURE            = 1 << 1,
 926     NVME_SMART_RELIABILITY            = 1 << 2,
 927     NVME_SMART_MEDIA_READ_ONLY        = 1 << 3,
 928     NVME_SMART_FAILED_VOLATILE_MEDIA  = 1 << 4,
 929     NVME_SMART_PMR_UNRELIABLE         = 1 << 5,
 930 };
 931
 932 typedef struct NvmeEffectsLog {
 933     uint32_t    acs[256];
 934     uint32_t    iocs[256];
 935     uint8_t     resv[2048];
 936 } NvmeEffectsLog;
 937
 938 enum {
 939     NVME_CMD_EFF_CSUPP      = 1 << 0,
 940     NVME_CMD_EFF_LBCC       = 1 << 1,
 941     NVME_CMD_EFF_NCC        = 1 << 2,
 942     NVME_CMD_EFF_NIC        = 1 << 3,
 943     NVME_CMD_EFF_CCC        = 1 << 4,
 944     NVME_CMD_EFF_CSE_MASK   = 3 << 16,
 945     NVME_CMD_EFF_UUID_SEL   = 1 << 19,
 946 };
 947
 948 enum NvmeLogIdentifier {
 949     NVME_LOG_ERROR_INFO     = 0x01,
 950     NVME_LOG_SMART_INFO     = 0x02,
 951     NVME_LOG_FW_SLOT_INFO   = 0x03,
 952     NVME_LOG_CHANGED_NSLIST = 0x04,
 953     NVME_LOG_CMD_EFFECTS    = 0x05,
 954 };
 955
 956 typedef struct QEMU_PACKED NvmePSD {
 957     uint16_t    mp;
 958     uint16_t    reserved;
 959     uint32_t    enlat;
 960     uint32_t    exlat;
 961     uint8_t     rrt;
 962     uint8_t     rrl;
 963     uint8_t     rwt;
 964     uint8_t     rwl;
 965     uint8_t     resv[16];
 966 } NvmePSD;
 967
 968 #define NVME_CONTROLLER_LIST_SIZE 2048
 969 #define NVME_IDENTIFY_DATA_SIZE 4096
 970
 971 enum NvmeIdCns {
 972     NVME_ID_CNS_NS                    = 0x00,
 973     NVME_ID_CNS_CTRL                  = 0x01,
 974     NVME_ID_CNS_NS_ACTIVE_LIST        = 0x02,
 975     NVME_ID_CNS_NS_DESCR_LIST         = 0x03,
 976     NVME_ID_CNS_CS_NS                 = 0x05,
 977     NVME_ID_CNS_CS_CTRL               = 0x06,
 978     NVME_ID_CNS_CS_NS_ACTIVE_LIST     = 0x07,
 979     NVME_ID_CNS_NS_PRESENT_LIST       = 0x10,
 980     NVME_ID_CNS_NS_PRESENT            = 0x11,
 981     NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12,
 982     NVME_ID_CNS_CS_NS_PRESENT_LIST    = 0x1a,
 983     NVME_ID_CNS_CS_NS_PRESENT         = 0x1b,
 984     NVME_ID_CNS_IO_COMMAND_SET        = 0x1c,
 985 };
 986
 987 typedef struct QEMU_PACKED NvmeIdCtrl {
 988     uint16_t    vid;
 989     uint16_t    ssvid;
 990     uint8_t     sn[20];
 991     uint8_t     mn[40];
 992     uint8_t     fr[8];
 993     uint8_t     rab;
 994     uint8_t     ieee[3];
 995     uint8_t     cmic;
 996     uint8_t     mdts;
 997     uint16_t    cntlid;
 998     uint32_t    ver;
 999     uint32_t    rtd3r;
1000     uint32_t    rtd3e;
1001     uint32_t    oaes;
1002     uint32_t    ctratt;
1003     uint8_t     rsvd100[11];
1004     uint8_t     cntrltype;
1005     uint8_t     fguid[16];
1006     uint8_t     rsvd128[128];
1007     uint16_t    oacs;
1008     uint8_t     acl;
1009     uint8_t     aerl;
1010     uint8_t     frmw;
1011     uint8_t     lpa;
1012     uint8_t     elpe;
1013     uint8_t     npss;
1014     uint8_t     avscc;
1015     uint8_t     apsta;
1016     uint16_t    wctemp;
1017     uint16_t    cctemp;
1018     uint16_t    mtfa;
1019     uint32_t    hmpre;
1020     uint32_t    hmmin;
1021     uint8_t     tnvmcap[16];
1022     uint8_t     unvmcap[16];
1023     uint32_t    rpmbs;
1024     uint16_t    edstt;
1025     uint8_t     dsto;
1026     uint8_t     fwug;
1027     uint16_t    kas;
1028     uint16_t    hctma;
1029     uint16_t    mntmt;
1030     uint16_t    mxtmt;
1031     uint32_t    sanicap;
1032     uint8_t     rsvd332[180];
1033     uint8_t     sqes;
1034     uint8_t     cqes;
1035     uint16_t    maxcmd;
1036     uint32_t    nn;
1037     uint16_t    oncs;
1038     uint16_t    fuses;
1039     uint8_t     fna;
1040     uint8_t     vwc;
1041     uint16_t    awun;
1042     uint16_t    awupf;
1043     uint8_t     nvscc;
1044     uint8_t     rsvd531;
1045     uint16_t    acwu;
1046     uint16_t    ocfs;
1047     uint32_t    sgls;
1048     uint8_t     rsvd540[228];
1049     uint8_t     subnqn[256];
1050     uint8_t     rsvd1024[1024];
1051     NvmePSD     psd[32];
1052     uint8_t     vs[1024];
1053 } NvmeIdCtrl;
1054
1055 typedef struct NvmeIdCtrlZoned {
1056     uint8_t     zasl;
1057     uint8_t     rsvd1[4095];
1058 } NvmeIdCtrlZoned;
1059
1060 typedef struct NvmeIdCtrlNvm {
1061     uint8_t     vsl;
1062     uint8_t     wzsl;
1063     uint8_t     wusl;
1064     uint8_t     dmrl;
1065     uint32_t    dmrsl;
1066     uint64_t    dmsl;
1067     uint8_t     rsvd16[4080];
1068 } NvmeIdCtrlNvm;
1069
1070 enum NvmeIdCtrlOaes {
1071     NVME_OAES_NS_ATTR   = 1 << 8,
1072 };
1073
1074 enum NvmeIdCtrlOacs {
1075     NVME_OACS_SECURITY  = 1 << 0,
1076     NVME_OACS_FORMAT    = 1 << 1,
1077     NVME_OACS_FW        = 1 << 2,
1078     NVME_OACS_NS_MGMT   = 1 << 3,
1079 };
1080
1081 enum NvmeIdCtrlOncs {
1082     NVME_ONCS_COMPARE       = 1 << 0,
1083     NVME_ONCS_WRITE_UNCORR  = 1 << 1,
1084     NVME_ONCS_DSM           = 1 << 2,
1085     NVME_ONCS_WRITE_ZEROES  = 1 << 3,
1086     NVME_ONCS_FEATURES      = 1 << 4,
1087     NVME_ONCS_RESRVATIONS   = 1 << 5,
1088     NVME_ONCS_TIMESTAMP     = 1 << 6,
1089     NVME_ONCS_VERIFY        = 1 << 7,
1090     NVME_ONCS_COPY          = 1 << 8,
1091 };
1092
1093 enum NvmeIdCtrlOcfs {
1094     NVME_OCFS_COPY_FORMAT_0 = 1 << 0,
1095 };
1096
1097 enum NvmeIdctrlVwc {
1098     NVME_VWC_PRESENT                    = 1 << 0,
1099     NVME_VWC_NSID_BROADCAST_NO_SUPPORT  = 0 << 1,
1100     NVME_VWC_NSID_BROADCAST_RESERVED    = 1 << 1,
1101     NVME_VWC_NSID_BROADCAST_CTRL_SPEC   = 2 << 1,
1102     NVME_VWC_NSID_BROADCAST_SUPPORT     = 3 << 1,
1103 };
1104
1105 enum NvmeIdCtrlFrmw {
1106     NVME_FRMW_SLOT1_RO = 1 << 0,
1107 };
1108
1109 enum NvmeIdCtrlLpa {
1110     NVME_LPA_NS_SMART = 1 << 0,
1111     NVME_LPA_CSE      = 1 << 1,
1112     NVME_LPA_EXTENDED = 1 << 2,
1113 };
1114
1115 enum NvmeIdCtrlCmic {
1116     NVME_CMIC_MULTI_CTRL    = 1 << 1,
1117 };
1118
1119 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf)
1120 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf)
1121 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf)
1122 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf)
1123
1124 #define NVME_CTRL_SGLS_SUPPORT_MASK        (0x3 <<  0)
1125 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN    (0x1 <<  0)
1126 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 <<  1)
1127 #define NVME_CTRL_SGLS_KEYED               (0x1 <<  2)
1128 #define NVME_CTRL_SGLS_BITBUCKET           (0x1 << 16)
1129 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS     (0x1 << 17)
1130 #define NVME_CTRL_SGLS_EXCESS_LENGTH       (0x1 << 18)
1131 #define NVME_CTRL_SGLS_MPTR_SGL            (0x1 << 19)
1132 #define NVME_CTRL_SGLS_ADDR_OFFSET         (0x1 << 20)
1133
1134 #define NVME_ARB_AB(arb)    (arb & 0x7)
1135 #define NVME_ARB_AB_NOLIMIT 0x7
1136 #define NVME_ARB_LPW(arb)   ((arb >> 8) & 0xff)
1137 #define NVME_ARB_MPW(arb)   ((arb >> 16) & 0xff)
1138 #define NVME_ARB_HPW(arb)   ((arb >> 24) & 0xff)
1139
1140 #define NVME_INTC_THR(intc)     (intc & 0xff)
1141 #define NVME_INTC_TIME(intc)    ((intc >> 8) & 0xff)
1142
1143 #define NVME_INTVC_NOCOALESCING (0x1 << 16)
1144
1145 #define NVME_TEMP_THSEL(temp)  ((temp >> 20) & 0x3)
1146 #define NVME_TEMP_THSEL_OVER   0x0
1147 #define NVME_TEMP_THSEL_UNDER  0x1
1148
1149 #define NVME_TEMP_TMPSEL(temp)     ((temp >> 16) & 0xf)
1150 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0
1151
1152 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff)
1153
1154 #define NVME_AEC_SMART(aec)         (aec & 0xff)
1155 #define NVME_AEC_NS_ATTR(aec)       ((aec >> 8) & 0x1)
1156 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1)
1157
1158 #define NVME_ERR_REC_TLER(err_rec)  (err_rec & 0xffff)
1159 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000)
1160
1161 enum NvmeFeatureIds {
1162     NVME_ARBITRATION                = 0x1,
1163     NVME_POWER_MANAGEMENT           = 0x2,
1164     NVME_LBA_RANGE_TYPE             = 0x3,
1165     NVME_TEMPERATURE_THRESHOLD      = 0x4,
1166     NVME_ERROR_RECOVERY             = 0x5,
1167     NVME_VOLATILE_WRITE_CACHE       = 0x6,
1168     NVME_NUMBER_OF_QUEUES           = 0x7,
1169     NVME_INTERRUPT_COALESCING       = 0x8,
1170     NVME_INTERRUPT_VECTOR_CONF      = 0x9,
1171     NVME_WRITE_ATOMICITY            = 0xa,
1172     NVME_ASYNCHRONOUS_EVENT_CONF    = 0xb,
1173     NVME_TIMESTAMP                  = 0xe,
1174     NVME_COMMAND_SET_PROFILE        = 0x19,
1175     NVME_SOFTWARE_PROGRESS_MARKER   = 0x80,
1176     NVME_FID_MAX                    = 0x100,
1177 };
1178
1179 typedef enum NvmeFeatureCap {
1180     NVME_FEAT_CAP_SAVE      = 1 << 0,
1181     NVME_FEAT_CAP_NS        = 1 << 1,
1182     NVME_FEAT_CAP_CHANGE    = 1 << 2,
1183 } NvmeFeatureCap;
1184
1185 typedef enum NvmeGetFeatureSelect {
1186     NVME_GETFEAT_SELECT_CURRENT = 0x0,
1187     NVME_GETFEAT_SELECT_DEFAULT = 0x1,
1188     NVME_GETFEAT_SELECT_SAVED   = 0x2,
1189     NVME_GETFEAT_SELECT_CAP     = 0x3,
1190 } NvmeGetFeatureSelect;
1191
1192 #define NVME_GETSETFEAT_FID_MASK 0xff
1193 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK)
1194
1195 #define NVME_GETFEAT_SELECT_SHIFT 8
1196 #define NVME_GETFEAT_SELECT_MASK  0x7
1197 #define NVME_GETFEAT_SELECT(dw10) \
1198     ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK)
1199
1200 #define NVME_SETFEAT_SAVE_SHIFT 31
1201 #define NVME_SETFEAT_SAVE_MASK  0x1
1202 #define NVME_SETFEAT_SAVE(dw10) \
1203     ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK)
1204
1205 typedef struct QEMU_PACKED NvmeRangeType {
1206     uint8_t     type;
1207     uint8_t     attributes;
1208     uint8_t     rsvd2[14];
1209     uint64_t    slba;
1210     uint64_t    nlb;
1211     uint8_t     guid[16];
1212     uint8_t     rsvd48[16];
1213 } NvmeRangeType;
1214
1215 typedef struct QEMU_PACKED NvmeLBAF {
1216     uint16_t    ms;
1217     uint8_t     ds;
1218     uint8_t     rp;
1219 } NvmeLBAF;
1220
1221 typedef struct QEMU_PACKED NvmeLBAFE {
1222     uint64_t    zsze;
1223     uint8_t     zdes;
1224     uint8_t     rsvd9[7];
1225 } NvmeLBAFE;
1226
1227 #define NVME_NSID_BROADCAST 0xffffffff
1228
1229 typedef struct QEMU_PACKED NvmeIdNs {
1230     uint64_t    nsze;
1231     uint64_t    ncap;
1232     uint64_t    nuse;
1233     uint8_t     nsfeat;
1234     uint8_t     nlbaf;
1235     uint8_t     flbas;
1236     uint8_t     mc;
1237     uint8_t     dpc;
1238     uint8_t     dps;
1239     uint8_t     nmic;
1240     uint8_t     rescap;
1241     uint8_t     fpi;
1242     uint8_t     dlfeat;
1243     uint16_t    nawun;
1244     uint16_t    nawupf;
1245     uint16_t    nacwu;
1246     uint16_t    nabsn;
1247     uint16_t    nabo;
1248     uint16_t    nabspf;
1249     uint16_t    noiob;
1250     uint8_t     nvmcap[16];
1251     uint16_t    npwg;
1252     uint16_t    npwa;
1253     uint16_t    npdg;
1254     uint16_t    npda;
1255     uint16_t    nows;
1256     uint16_t    mssrl;
1257     uint32_t    mcl;
1258     uint8_t     msrc;
1259     uint8_t     rsvd81[23];
1260     uint8_t     nguid[16];
1261     uint64_t    eui64;
1262     NvmeLBAF    lbaf[16];
1263     uint8_t     rsvd192[192];
1264     uint8_t     vs[3712];
1265 } NvmeIdNs;
1266
1267 typedef struct QEMU_PACKED NvmeIdNsDescr {
1268     uint8_t nidt;
1269     uint8_t nidl;
1270     uint8_t rsvd2[2];
1271 } NvmeIdNsDescr;
1272
1273 enum NvmeNsIdentifierLength {
1274     NVME_NIDL_EUI64             = 8,
1275     NVME_NIDL_NGUID             = 16,
1276     NVME_NIDL_UUID              = 16,
1277     NVME_NIDL_CSI               = 1,
1278 };
1279
1280 enum NvmeNsIdentifierType {
1281     NVME_NIDT_EUI64             = 0x01,
1282     NVME_NIDT_NGUID             = 0x02,
1283     NVME_NIDT_UUID              = 0x03,
1284     NVME_NIDT_CSI               = 0x04,
1285 };
1286
1287 enum NvmeIdNsNmic {
1288     NVME_NMIC_NS_SHARED         = 1 << 0,
1289 };
1290
1291 enum NvmeCsi {
1292     NVME_CSI_NVM                = 0x00,
1293     NVME_CSI_ZONED              = 0x02,
1294 };
1295
1296 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi)))
1297
1298 typedef struct QEMU_PACKED NvmeIdNsZoned {
1299     uint16_t    zoc;
1300     uint16_t    ozcs;
1301     uint32_t    mar;
1302     uint32_t    mor;
1303     uint32_t    rrl;
1304     uint32_t    frl;
1305     uint8_t     rsvd20[2796];
1306     NvmeLBAFE   lbafe[16];
1307     uint8_t     rsvd3072[768];
1308     uint8_t     vs[256];
1309 } NvmeIdNsZoned;
1310
1311 /*Deallocate Logical Block Features*/
1312 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat)       ((dlfeat) & 0x10)
1313 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat)    ((dlfeat) & 0x08)
1314
1315 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat)     ((dlfeat) & 0x7)
1316 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED   0
1317 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES      1
1318 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES        2
1319
1320
1321 #define NVME_ID_NS_NSFEAT_THIN(nsfeat)      ((nsfeat & 0x1))
1322 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat)     ((nsfeat >> 2) & 0x1)
1323 #define NVME_ID_NS_FLBAS_EXTENDED(flbas)    ((flbas >> 4) & 0x1)
1324 #define NVME_ID_NS_FLBAS_INDEX(flbas)       ((flbas & 0xf))
1325 #define NVME_ID_NS_MC_SEPARATE(mc)          ((mc >> 1) & 0x1)
1326 #define NVME_ID_NS_MC_EXTENDED(mc)          ((mc & 0x1))
1327 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc)      ((dpc >> 4) & 0x1)
1328 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc)     ((dpc >> 3) & 0x1)
1329 #define NVME_ID_NS_DPC_TYPE_3(dpc)          ((dpc >> 2) & 0x1)
1330 #define NVME_ID_NS_DPC_TYPE_2(dpc)          ((dpc >> 1) & 0x1)
1331 #define NVME_ID_NS_DPC_TYPE_1(dpc)          ((dpc & 0x1))
1332 #define NVME_ID_NS_DPC_TYPE_MASK            0x7
1333
1334 enum NvmeIdNsDps {
1335     NVME_ID_NS_DPS_TYPE_NONE   = 0,
1336     NVME_ID_NS_DPS_TYPE_1      = 1,
1337     NVME_ID_NS_DPS_TYPE_2      = 2,
1338     NVME_ID_NS_DPS_TYPE_3      = 3,
1339     NVME_ID_NS_DPS_TYPE_MASK   = 0x7,
1340     NVME_ID_NS_DPS_FIRST_EIGHT = 8,
1341 };
1342
1343 #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK)
1344
1345 typedef struct NvmeDifTuple {
1346     uint16_t guard;
1347     uint16_t apptag;
1348     uint32_t reftag;
1349 } NvmeDifTuple;
1350
1351 enum NvmeZoneAttr {
1352     NVME_ZA_FINISHED_BY_CTLR         = 1 << 0,
1353     NVME_ZA_FINISH_RECOMMENDED       = 1 << 1,
1354     NVME_ZA_RESET_RECOMMENDED        = 1 << 2,
1355     NVME_ZA_ZD_EXT_VALID             = 1 << 7,
1356 };
1357
1358 typedef struct QEMU_PACKED NvmeZoneReportHeader {
1359     uint64_t    nr_zones;
1360     uint8_t     rsvd[56];
1361 } NvmeZoneReportHeader;
1362
1363 enum NvmeZoneReceiveAction {
1364     NVME_ZONE_REPORT                 = 0,
1365     NVME_ZONE_REPORT_EXTENDED        = 1,
1366 };
1367
1368 enum NvmeZoneReportType {
1369     NVME_ZONE_REPORT_ALL             = 0,
1370     NVME_ZONE_REPORT_EMPTY           = 1,
1371     NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2,
1372     NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3,
1373     NVME_ZONE_REPORT_CLOSED          = 4,
1374     NVME_ZONE_REPORT_FULL            = 5,
1375     NVME_ZONE_REPORT_READ_ONLY       = 6,
1376     NVME_ZONE_REPORT_OFFLINE         = 7,
1377 };
1378
1379 enum NvmeZoneType {
1380     NVME_ZONE_TYPE_RESERVED          = 0x00,
1381     NVME_ZONE_TYPE_SEQ_WRITE         = 0x02,
1382 };
1383
1384 enum NvmeZoneSendAction {
1385     NVME_ZONE_ACTION_RSD             = 0x00,
1386     NVME_ZONE_ACTION_CLOSE           = 0x01,
1387     NVME_ZONE_ACTION_FINISH          = 0x02,
1388     NVME_ZONE_ACTION_OPEN            = 0x03,
1389     NVME_ZONE_ACTION_RESET           = 0x04,
1390     NVME_ZONE_ACTION_OFFLINE         = 0x05,
1391     NVME_ZONE_ACTION_SET_ZD_EXT      = 0x10,
1392 };
1393
1394 typedef struct QEMU_PACKED NvmeZoneDescr {
1395     uint8_t     zt;
1396     uint8_t     zs;
1397     uint8_t     za;
1398     uint8_t     rsvd3[5];
1399     uint64_t    zcap;
1400     uint64_t    zslba;
1401     uint64_t    wp;
1402     uint8_t     rsvd32[32];
1403 } NvmeZoneDescr;
1404
1405 typedef enum NvmeZoneState {
1406     NVME_ZONE_STATE_RESERVED         = 0x00,
1407     NVME_ZONE_STATE_EMPTY            = 0x01,
1408     NVME_ZONE_STATE_IMPLICITLY_OPEN  = 0x02,
1409     NVME_ZONE_STATE_EXPLICITLY_OPEN  = 0x03,
1410     NVME_ZONE_STATE_CLOSED           = 0x04,
1411     NVME_ZONE_STATE_READ_ONLY        = 0x0D,
1412     NVME_ZONE_STATE_FULL             = 0x0E,
1413     NVME_ZONE_STATE_OFFLINE          = 0x0F,
1414 } NvmeZoneState;
1415
1416 static inline void _nvme_check_size(void)
1417 {
1418     QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096);
1419     QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4);
1420     QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8);
1421     QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16);
1422     QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16);
1423     QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRange) != 32);
1424     QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64);
1425     QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64);
1426     QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64);
1427     QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64);
1428     QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64);
1429     QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64);
1430     QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64);
1431     QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64);
1432     QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64);
1433     QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64);
1434     QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512);
1435     QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512);
1436     QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096);
1437     QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096);
1438     QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096);
1439     QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096);
1440     QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4);
1441     QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16);
1442     QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096);
1443     QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096);
1444     QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16);
1445     QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
1446     QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64);
1447     QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 8);
1448 }
1449 #endif