hw/ssi/xilinx_spi.c

   1 /*
   2  * QEMU model of the Xilinx SPI Controller
   3  *
   4  * Copyright (C) 2010 Edgar E. Iglesias.
   5  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
   6  * Copyright (C) 2012 PetaLogix
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "sysemu/sysemu.h"
  30 #include "qemu/log.h"
  31 #include "qemu/fifo8.h"
  32
  33 #include "hw/ssi/ssi.h"
  34
  35 #ifdef XILINX_SPI_ERR_DEBUG
  36 #define DB_PRINT(...) do { \
  37     fprintf(stderr,  ": %s: ", __func__); \
  38     fprintf(stderr, ## __VA_ARGS__); \
  39     } while (0)
  40 #else
  41     #define DB_PRINT(...)
  42 #endif
  43
  44 #define R_DGIER     (0x1c / 4)
  45 #define R_DGIER_IE  (1 << 31)
  46
  47 #define R_IPISR     (0x20 / 4)
  48 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
  49 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
  50 #define IRQ_DRR_FULL         (1 << (31 - 27))
  51 #define IRQ_TX_FF_HALF_EMPTY (1 << 6)
  52 #define IRQ_DTR_UNDERRUN     (1 << 3)
  53 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
  54
  55 #define R_IPIER     (0x28 / 4)
  56 #define R_SRR       (0x40 / 4)
  57 #define R_SPICR     (0x60 / 4)
  58 #define R_SPICR_TXFF_RST     (1 << 5)
  59 #define R_SPICR_RXFF_RST     (1 << 6)
  60 #define R_SPICR_MTI          (1 << 8)
  61
  62 #define R_SPISR     (0x64 / 4)
  63 #define SR_TX_FULL    (1 << 3)
  64 #define SR_TX_EMPTY   (1 << 2)
  65 #define SR_RX_FULL    (1 << 1)
  66 #define SR_RX_EMPTY   (1 << 0)
  67
  68 #define R_SPIDTR    (0x68 / 4)
  69 #define R_SPIDRR    (0x6C / 4)
  70 #define R_SPISSR    (0x70 / 4)
  71 #define R_TX_FF_OCY (0x74 / 4)
  72 #define R_RX_FF_OCY (0x78 / 4)
  73 #define R_MAX       (0x7C / 4)
  74
  75 #define FIFO_CAPACITY 256
  76
  77 #define TYPE_XILINX_SPI "xlnx.xps-spi"
  78 #define XILINX_SPI(obj) OBJECT_CHECK(XilinxSPI, (obj), TYPE_XILINX_SPI)
  79
  80 typedef struct XilinxSPI {
  81     SysBusDevice parent_obj;
  82
  83     MemoryRegion mmio;
  84
  85     qemu_irq irq;
  86     int irqline;
  87
  88     uint8_t num_cs;
  89     qemu_irq *cs_lines;
  90
  91     SSIBus *spi;
  92
  93     Fifo8 rx_fifo;
  94     Fifo8 tx_fifo;
  95
  96     uint32_t regs[R_MAX];
  97 } XilinxSPI;
  98
  99 static void txfifo_reset(XilinxSPI *s)
 100 {
 101     fifo8_reset(&s->tx_fifo);
 102
 103     s->regs[R_SPISR] &= ~SR_TX_FULL;
 104     s->regs[R_SPISR] |= SR_TX_EMPTY;
 105 }
 106
 107 static void rxfifo_reset(XilinxSPI *s)
 108 {
 109     fifo8_reset(&s->rx_fifo);
 110
 111     s->regs[R_SPISR] |= SR_RX_EMPTY;
 112     s->regs[R_SPISR] &= ~SR_RX_FULL;
 113 }
 114
 115 static void xlx_spi_update_cs(XilinxSPI *s)
 116 {
 117     int i;
 118
 119     for (i = 0; i < s->num_cs; ++i) {
 120         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
 121     }
 122 }
 123
 124 static void xlx_spi_update_irq(XilinxSPI *s)
 125 {
 126     uint32_t pending;
 127
 128     s->regs[R_IPISR] |=
 129             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
 130             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
 131
 132     pending = s->regs[R_IPISR] & s->regs[R_IPIER];
 133
 134     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
 135     pending = !!pending;
 136
 137     /* This call lies right in the data paths so don't call the
 138        irq chain unless things really changed.  */
 139     if (pending != s->irqline) {
 140         s->irqline = pending;
 141         DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
 142                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);
 143         qemu_set_irq(s->irq, pending);
 144     }
 145
 146 }
 147
 148 static void xlx_spi_do_reset(XilinxSPI *s)
 149 {
 150     memset(s->regs, 0, sizeof s->regs);
 151
 152     rxfifo_reset(s);
 153     txfifo_reset(s);
 154
 155     s->regs[R_SPISSR] = ~0;
 156     xlx_spi_update_irq(s);
 157     xlx_spi_update_cs(s);
 158 }
 159
 160 static void xlx_spi_reset(DeviceState *d)
 161 {
 162     xlx_spi_do_reset(XILINX_SPI(d));
 163 }
 164
 165 static inline int spi_master_enabled(XilinxSPI *s)
 166 {
 167     return !(s->regs[R_SPICR] & R_SPICR_MTI);
 168 }
 169
 170 static void spi_flush_txfifo(XilinxSPI *s)
 171 {
 172     uint32_t tx;
 173     uint32_t rx;
 174
 175     while (!fifo8_is_empty(&s->tx_fifo)) {
 176         tx = (uint32_t)fifo8_pop(&s->tx_fifo);
 177         DB_PRINT("data tx:%x\n", tx);
 178         rx = ssi_transfer(s->spi, tx);
 179         DB_PRINT("data rx:%x\n", rx);
 180         if (fifo8_is_full(&s->rx_fifo)) {
 181             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
 182         } else {
 183             fifo8_push(&s->rx_fifo, (uint8_t)rx);
 184             if (fifo8_is_full(&s->rx_fifo)) {
 185                 s->regs[R_SPISR] |= SR_RX_FULL;
 186                 s->regs[R_IPISR] |= IRQ_DRR_FULL;
 187             }
 188         }
 189
 190         s->regs[R_SPISR] &= ~SR_RX_EMPTY;
 191         s->regs[R_SPISR] &= ~SR_TX_FULL;
 192         s->regs[R_SPISR] |= SR_TX_EMPTY;
 193
 194         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
 195         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
 196     }
 197
 198 }
 199
 200 static uint64_t
 201 spi_read(void *opaque, hwaddr addr, unsigned int size)
 202 {
 203     XilinxSPI *s = opaque;
 204     uint32_t r = 0;
 205
 206     addr >>= 2;
 207     switch (addr) {
 208     case R_SPIDRR:
 209         if (fifo8_is_empty(&s->rx_fifo)) {
 210             DB_PRINT("Read from empty FIFO!\n");
 211             return 0xdeadbeef;
 212         }
 213
 214         s->regs[R_SPISR] &= ~SR_RX_FULL;
 215         r = fifo8_pop(&s->rx_fifo);
 216         if (fifo8_is_empty(&s->rx_fifo)) {
 217             s->regs[R_SPISR] |= SR_RX_EMPTY;
 218         }
 219         break;
 220
 221     case R_SPISR:
 222         r = s->regs[addr];
 223         break;
 224
 225     default:
 226         if (addr < ARRAY_SIZE(s->regs)) {
 227             r = s->regs[addr];
 228         }
 229         break;
 230
 231     }
 232     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
 233     xlx_spi_update_irq(s);
 234     return r;
 235 }
 236
 237 static void
 238 spi_write(void *opaque, hwaddr addr,
 239             uint64_t val64, unsigned int size)
 240 {
 241     XilinxSPI *s = opaque;
 242     uint32_t value = val64;
 243
 244     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
 245     addr >>= 2;
 246     switch (addr) {
 247     case R_SRR:
 248         if (value != 0xa) {
 249             DB_PRINT("Invalid write to SRR %x\n", value);
 250         } else {
 251             xlx_spi_do_reset(s);
 252         }
 253         break;
 254
 255     case R_SPIDTR:
 256         s->regs[R_SPISR] &= ~SR_TX_EMPTY;
 257         fifo8_push(&s->tx_fifo, (uint8_t)value);
 258         if (fifo8_is_full(&s->tx_fifo)) {
 259             s->regs[R_SPISR] |= SR_TX_FULL;
 260         }
 261         if (!spi_master_enabled(s)) {
 262             goto done;
 263         } else {
 264             DB_PRINT("DTR and master enabled\n");
 265         }
 266         spi_flush_txfifo(s);
 267         break;
 268
 269     case R_SPISR:
 270         DB_PRINT("Invalid write to SPISR %x\n", value);
 271         break;
 272
 273     case R_IPISR:
 274         /* Toggle the bits.  */
 275         s->regs[addr] ^= value;
 276         break;
 277
 278     /* Slave Select Register.  */
 279     case R_SPISSR:
 280         s->regs[addr] = value;
 281         xlx_spi_update_cs(s);
 282         break;
 283
 284     case R_SPICR:
 285         /* FIXME: reset irq and sr state to empty queues.  */
 286         if (value & R_SPICR_RXFF_RST) {
 287             rxfifo_reset(s);
 288         }
 289
 290         if (value & R_SPICR_TXFF_RST) {
 291             txfifo_reset(s);
 292         }
 293         value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
 294         s->regs[addr] = value;
 295
 296         if (!(value & R_SPICR_MTI)) {
 297             spi_flush_txfifo(s);
 298         }
 299         break;
 300
 301     default:
 302         if (addr < ARRAY_SIZE(s->regs)) {
 303             s->regs[addr] = value;
 304         }
 305         break;
 306     }
 307
 308 done:
 309     xlx_spi_update_irq(s);
 310 }
 311
 312 static const MemoryRegionOps spi_ops = {
 313     .read = spi_read,
 314     .write = spi_write,
 315     .endianness = DEVICE_NATIVE_ENDIAN,
 316     .valid = {
 317         .min_access_size = 4,
 318         .max_access_size = 4
 319     }
 320 };
 321
 322 static int xilinx_spi_init(SysBusDevice *sbd)
 323 {
 324     DeviceState *dev = DEVICE(sbd);
 325     XilinxSPI *s = XILINX_SPI(dev);
 326     int i;
 327
 328     DB_PRINT("\n");
 329
 330     s->spi = ssi_create_bus(dev, "spi");
 331
 332     sysbus_init_irq(sbd, &s->irq);
 333     s->cs_lines = g_new0(qemu_irq, s->num_cs);
 334     ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
 335     for (i = 0; i < s->num_cs; ++i) {
 336         sysbus_init_irq(sbd, &s->cs_lines[i]);
 337     }
 338
 339     memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
 340                           "xilinx-spi", R_MAX * 4);
 341     sysbus_init_mmio(sbd, &s->mmio);
 342
 343     s->irqline = -1;
 344
 345     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
 346     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
 347
 348     return 0;
 349 }
 350
 351 static const VMStateDescription vmstate_xilinx_spi = {
 352     .name = "xilinx_spi",
 353     .version_id = 1,
 354     .minimum_version_id = 1,
 355     .fields = (VMStateField[]) {
 356         VMSTATE_FIFO8(tx_fifo, XilinxSPI),
 357         VMSTATE_FIFO8(rx_fifo, XilinxSPI),
 358         VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
 359         VMSTATE_END_OF_LIST()
 360     }
 361 };
 362
 363 static Property xilinx_spi_properties[] = {
 364     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
 365     DEFINE_PROP_END_OF_LIST(),
 366 };
 367
 368 static void xilinx_spi_class_init(ObjectClass *klass, void *data)
 369 {
 370     DeviceClass *dc = DEVICE_CLASS(klass);
 371     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 372
 373     k->init = xilinx_spi_init;
 374     dc->reset = xlx_spi_reset;
 375     dc->props = xilinx_spi_properties;
 376     dc->vmsd = &vmstate_xilinx_spi;
 377 }
 378
 379 static const TypeInfo xilinx_spi_info = {
 380     .name           = TYPE_XILINX_SPI,
 381     .parent         = TYPE_SYS_BUS_DEVICE,
 382     .instance_size  = sizeof(XilinxSPI),
 383     .class_init     = xilinx_spi_class_init,
 384 };
 385
 386 static void xilinx_spi_register_types(void)
 387 {
 388     type_register_static(&xilinx_spi_info);
 389 }
 390
 391 type_init(xilinx_spi_register_types)