2 * ARM VFP floating-point operations
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
26 #include "fpu/softfloat.h"
29 /* VFP support. We follow the convention used for VFP instructions:
30 Single precision routines have a "s" suffix, double precision a
35 /* Convert host exception flags to vfp form. */
36 static inline int vfp_exceptbits_from_host(int host_bits
)
40 if (host_bits
& float_flag_invalid
) {
43 if (host_bits
& float_flag_divbyzero
) {
46 if (host_bits
& float_flag_overflow
) {
49 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
)) {
52 if (host_bits
& float_flag_inexact
) {
55 if (host_bits
& float_flag_input_denormal
) {
61 /* Convert vfp exception flags to target form. */
62 static inline int vfp_exceptbits_to_host(int target_bits
)
66 if (target_bits
& 1) {
67 host_bits
|= float_flag_invalid
;
69 if (target_bits
& 2) {
70 host_bits
|= float_flag_divbyzero
;
72 if (target_bits
& 4) {
73 host_bits
|= float_flag_overflow
;
75 if (target_bits
& 8) {
76 host_bits
|= float_flag_underflow
;
78 if (target_bits
& 0x10) {
79 host_bits
|= float_flag_inexact
;
81 if (target_bits
& 0x80) {
82 host_bits
|= float_flag_input_denormal
;
87 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
91 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
92 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
93 /* FZ16 does not generate an input denormal exception. */
94 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
95 & ~float_flag_input_denormal
);
96 i
|= (get_float_exception_flags(&env
->vfp
.standard_fp_status_f16
)
97 & ~float_flag_input_denormal
);
98 return vfp_exceptbits_from_host(i
);
101 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
104 uint32_t changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
107 if (changed
& (3 << 22)) {
110 case FPROUNDING_TIEEVEN
:
111 i
= float_round_nearest_even
;
113 case FPROUNDING_POSINF
:
116 case FPROUNDING_NEGINF
:
117 i
= float_round_down
;
119 case FPROUNDING_ZERO
:
120 i
= float_round_to_zero
;
123 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
124 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
126 if (changed
& FPCR_FZ16
) {
127 bool ftz_enabled
= val
& FPCR_FZ16
;
128 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
129 set_flush_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
130 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
131 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
133 if (changed
& FPCR_FZ
) {
134 bool ftz_enabled
= val
& FPCR_FZ
;
135 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
136 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
138 if (changed
& FPCR_DN
) {
139 bool dnan_enabled
= val
& FPCR_DN
;
140 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
141 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
145 * The exception flags are ORed together when we read fpscr so we
146 * only need to preserve the current state in one of our
147 * float_status values.
149 i
= vfp_exceptbits_to_host(val
);
150 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
151 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
152 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
153 set_float_exception_flags(0, &env
->vfp
.standard_fp_status_f16
);
158 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
163 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
169 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
173 fpscr
= env
->vfp
.xregs
[ARM_VFP_FPSCR
]
174 | (env
->vfp
.vec_len
<< 16)
175 | (env
->vfp
.vec_stride
<< 20);
178 * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
179 * two is not applicable to this CPU will always be zero.
181 fpscr
|= env
->v7m
.ltpsize
<< 16;
183 fpscr
|= vfp_get_fpscr_from_host(env
);
185 i
= env
->vfp
.qc
[0] | env
->vfp
.qc
[1] | env
->vfp
.qc
[2] | env
->vfp
.qc
[3];
186 fpscr
|= i
? FPCR_QC
: 0;
191 uint32_t vfp_get_fpscr(CPUARMState
*env
)
193 return HELPER(vfp_get_fpscr
)(env
);
196 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
198 ARMCPU
*cpu
= env_archcpu(env
);
200 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
201 if (!cpu_isar_feature(any_fp16
, cpu
)) {
205 vfp_set_fpscr_to_host(env
, val
);
207 if (!arm_feature(env
, ARM_FEATURE_M
)) {
209 * Short-vector length and stride; on M-profile these bits
210 * are used for different purposes.
211 * We can't make this conditional be "if MVFR0.FPShVec != 0",
212 * because in v7A no-short-vector-support cores still had to
213 * allow Stride/Len to be written with the only effect that
214 * some insns are required to UNDEF if the guest sets them.
216 env
->vfp
.vec_len
= extract32(val
, 16, 3);
217 env
->vfp
.vec_stride
= extract32(val
, 20, 2);
218 } else if (cpu_isar_feature(aa32_mve
, cpu
)) {
219 env
->v7m
.ltpsize
= extract32(val
, FPCR_LTPSIZE_SHIFT
,
220 FPCR_LTPSIZE_LENGTH
);
223 if (arm_feature(env
, ARM_FEATURE_NEON
) ||
224 cpu_isar_feature(aa32_mve
, cpu
)) {
226 * The bit we set within fpscr_q is arbitrary; the register as a
227 * whole being zero/non-zero is what counts.
228 * TODO: M-profile MVE also has a QC bit.
230 env
->vfp
.qc
[0] = val
& FPCR_QC
;
237 * We don't implement trapped exception handling, so the
238 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
240 * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
241 * fp_status; QC, Len and Stride are stored separately earlier.
242 * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
243 * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
245 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = val
& 0xf7c80000;
248 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
250 HELPER(vfp_set_fpscr
)(env
, val
);
255 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
257 #define VFP_BINOP(name) \
258 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
260 float_status *fpst = fpstp; \
261 return float16_ ## name(a, b, fpst); \
263 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
265 float_status *fpst = fpstp; \
266 return float32_ ## name(a, b, fpst); \
268 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
270 float_status *fpst = fpstp; \
271 return float64_ ## name(a, b, fpst); \
283 dh_ctype_f16
VFP_HELPER(neg
, h
)(dh_ctype_f16 a
)
285 return float16_chs(a
);
288 float32
VFP_HELPER(neg
, s
)(float32 a
)
290 return float32_chs(a
);
293 float64
VFP_HELPER(neg
, d
)(float64 a
)
295 return float64_chs(a
);
298 dh_ctype_f16
VFP_HELPER(abs
, h
)(dh_ctype_f16 a
)
300 return float16_abs(a
);
303 float32
VFP_HELPER(abs
, s
)(float32 a
)
305 return float32_abs(a
);
308 float64
VFP_HELPER(abs
, d
)(float64 a
)
310 return float64_abs(a
);
313 dh_ctype_f16
VFP_HELPER(sqrt
, h
)(dh_ctype_f16 a
, CPUARMState
*env
)
315 return float16_sqrt(a
, &env
->vfp
.fp_status_f16
);
318 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
320 return float32_sqrt(a
, &env
->vfp
.fp_status
);
323 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
325 return float64_sqrt(a
, &env
->vfp
.fp_status
);
328 static void softfloat_to_vfp_compare(CPUARMState
*env
, FloatRelation cmp
)
332 case float_relation_equal
:
335 case float_relation_less
:
338 case float_relation_greater
:
341 case float_relation_unordered
:
345 g_assert_not_reached();
347 env
->vfp
.xregs
[ARM_VFP_FPSCR
] =
348 deposit32(env
->vfp
.xregs
[ARM_VFP_FPSCR
], 28, 4, flags
);
351 /* XXX: check quiet/signaling case */
352 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
353 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
355 softfloat_to_vfp_compare(env, \
356 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
358 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
360 softfloat_to_vfp_compare(env, \
361 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
363 DO_VFP_cmp(h
, float16
, dh_ctype_f16
, fp_status_f16
)
364 DO_VFP_cmp(s
, float32
, float32
, fp_status
)
365 DO_VFP_cmp(d
, float64
, float64
, fp_status
)
368 /* Integer to float and float to integer conversions */
370 #define CONV_ITOF(name, ftype, fsz, sign) \
371 ftype HELPER(name)(uint32_t x, void *fpstp) \
373 float_status *fpst = fpstp; \
374 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
377 #define CONV_FTOI(name, ftype, fsz, sign, round) \
378 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
380 float_status *fpst = fpstp; \
381 if (float##fsz##_is_any_nan(x)) { \
382 float_raise(float_flag_invalid, fpst); \
385 return float##fsz##_to_##sign##int32##round(x, fpst); \
388 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
389 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
390 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
391 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
393 FLOAT_CONVS(si
, h
, uint32_t, 16, )
394 FLOAT_CONVS(si
, s
, float32
, 32, )
395 FLOAT_CONVS(si
, d
, float64
, 64, )
396 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
397 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
398 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
404 /* floating point conversion */
405 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
407 return float32_to_float64(x
, &env
->vfp
.fp_status
);
410 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
412 return float64_to_float32(x
, &env
->vfp
.fp_status
);
415 uint32_t HELPER(bfcvt
)(float32 x
, void *status
)
417 return float32_to_bfloat16(x
, status
);
420 uint32_t HELPER(bfcvt_pair
)(uint64_t pair
, void *status
)
422 bfloat16 lo
= float32_to_bfloat16(extract64(pair
, 0, 32), status
);
423 bfloat16 hi
= float32_to_bfloat16(extract64(pair
, 32, 32), status
);
424 return deposit32(lo
, 16, 16, hi
);
428 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float
429 * must always round-to-nearest; the AArch64 ones honour the FPSCR
430 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to
431 * round-to-nearest so either helper will work.) AArch32 float-to-fix
432 * must round-to-zero.
434 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
435 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
437 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
439 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
440 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
445 float_status *fpst = fpstp; \
446 FloatRoundMode oldmode = fpst->float_rounding_mode; \
447 fpst->float_rounding_mode = float_round_nearest_even; \
448 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
449 fpst->float_rounding_mode = oldmode; \
453 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
454 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
457 if (unlikely(float##fsz##_is_any_nan(x))) { \
458 float_raise(float_flag_invalid, fpst); \
461 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
464 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
465 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
466 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
467 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
468 float_round_to_zero, _round_to_zero) \
469 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
470 get_float_rounding_mode(fpst), )
472 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
473 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
474 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
475 get_float_rounding_mode(fpst), )
477 VFP_CONV_FIX(sh
, d
, 64, float64
, 64, int16
)
478 VFP_CONV_FIX(sl
, d
, 64, float64
, 64, int32
)
479 VFP_CONV_FIX_A64(sq
, d
, 64, float64
, 64, int64
)
480 VFP_CONV_FIX(uh
, d
, 64, float64
, 64, uint16
)
481 VFP_CONV_FIX(ul
, d
, 64, float64
, 64, uint32
)
482 VFP_CONV_FIX_A64(uq
, d
, 64, float64
, 64, uint64
)
483 VFP_CONV_FIX(sh
, s
, 32, float32
, 32, int16
)
484 VFP_CONV_FIX(sl
, s
, 32, float32
, 32, int32
)
485 VFP_CONV_FIX_A64(sq
, s
, 32, float32
, 64, int64
)
486 VFP_CONV_FIX(uh
, s
, 32, float32
, 32, uint16
)
487 VFP_CONV_FIX(ul
, s
, 32, float32
, 32, uint32
)
488 VFP_CONV_FIX_A64(uq
, s
, 32, float32
, 64, uint64
)
489 VFP_CONV_FIX(sh
, h
, 16, dh_ctype_f16
, 32, int16
)
490 VFP_CONV_FIX(sl
, h
, 16, dh_ctype_f16
, 32, int32
)
491 VFP_CONV_FIX_A64(sq
, h
, 16, dh_ctype_f16
, 64, int64
)
492 VFP_CONV_FIX(uh
, h
, 16, dh_ctype_f16
, 32, uint16
)
493 VFP_CONV_FIX(ul
, h
, 16, dh_ctype_f16
, 32, uint32
)
494 VFP_CONV_FIX_A64(uq
, h
, 16, dh_ctype_f16
, 64, uint64
)
497 #undef VFP_CONV_FIX_FLOAT
498 #undef VFP_CONV_FLOAT_FIX_ROUND
499 #undef VFP_CONV_FIX_A64
501 /* Set the current fp rounding mode and return the old one.
502 * The argument is a softfloat float_round_ value.
504 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
506 float_status
*fp_status
= fpstp
;
508 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
509 set_float_rounding_mode(rmode
, fp_status
);
514 /* Half precision conversions. */
515 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
517 /* Squash FZ16 to 0 for the duration of conversion. In this case,
518 * it would affect flushing input denormals.
520 float_status
*fpst
= fpstp
;
521 bool save
= get_flush_inputs_to_zero(fpst
);
522 set_flush_inputs_to_zero(false, fpst
);
523 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
524 set_flush_inputs_to_zero(save
, fpst
);
528 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
530 /* Squash FZ16 to 0 for the duration of conversion. In this case,
531 * it would affect flushing output denormals.
533 float_status
*fpst
= fpstp
;
534 bool save
= get_flush_to_zero(fpst
);
535 set_flush_to_zero(false, fpst
);
536 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
537 set_flush_to_zero(save
, fpst
);
541 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
543 /* Squash FZ16 to 0 for the duration of conversion. In this case,
544 * it would affect flushing input denormals.
546 float_status
*fpst
= fpstp
;
547 bool save
= get_flush_inputs_to_zero(fpst
);
548 set_flush_inputs_to_zero(false, fpst
);
549 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
550 set_flush_inputs_to_zero(save
, fpst
);
554 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
556 /* Squash FZ16 to 0 for the duration of conversion. In this case,
557 * it would affect flushing output denormals.
559 float_status
*fpst
= fpstp
;
560 bool save
= get_flush_to_zero(fpst
);
561 set_flush_to_zero(false, fpst
);
562 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
563 set_flush_to_zero(save
, fpst
);
569 /* Constants 256 and 512 are used in some helpers; we avoid relying on
570 * int->float conversions at run-time. */
571 #define float64_256 make_float64(0x4070000000000000LL)
572 #define float64_512 make_float64(0x4080000000000000LL)
573 #define float16_maxnorm make_float16(0x7bff)
574 #define float32_maxnorm make_float32(0x7f7fffff)
575 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
577 /* Reciprocal functions
579 * The algorithm that must be used to calculate the estimate
580 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
583 /* See RecipEstimate()
585 * input is a 9 bit fixed point number
586 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
587 * result range 256 .. 511 for a number from 1.0 to 511/256.
590 static int recip_estimate(int input
)
593 assert(256 <= input
&& input
< 512);
597 assert(256 <= r
&& r
< 512);
602 * Common wrapper to call recip_estimate
604 * The parameters are exponent and 64 bit fraction (without implicit
605 * bit) where the binary point is nominally at bit 52. Returns a
606 * float64 which can then be rounded to the appropriate size by the
610 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
612 uint32_t scaled
, estimate
;
613 uint64_t result_frac
;
616 /* Handle sub-normals */
618 if (extract64(frac
, 51, 1) == 0) {
626 /* scaled = UInt('1':fraction<51:44>) */
627 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
628 estimate
= recip_estimate(scaled
);
630 result_exp
= exp_off
- *exp
;
631 result_frac
= deposit64(0, 44, 8, estimate
);
632 if (result_exp
== 0) {
633 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
634 } else if (result_exp
== -1) {
635 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
644 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
646 switch (fpst
->float_rounding_mode
) {
647 case float_round_nearest_even
: /* Round to Nearest */
649 case float_round_up
: /* Round to +Inf */
651 case float_round_down
: /* Round to -Inf */
653 case float_round_to_zero
: /* Round to Zero */
656 g_assert_not_reached();
660 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
662 float_status
*fpst
= fpstp
;
663 float16 f16
= float16_squash_input_denormal(input
, fpst
);
664 uint32_t f16_val
= float16_val(f16
);
665 uint32_t f16_sign
= float16_is_neg(f16
);
666 int f16_exp
= extract32(f16_val
, 10, 5);
667 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
670 if (float16_is_any_nan(f16
)) {
672 if (float16_is_signaling_nan(f16
, fpst
)) {
673 float_raise(float_flag_invalid
, fpst
);
674 nan
= float16_silence_nan(f16
, fpst
);
676 if (fpst
->default_nan_mode
) {
677 nan
= float16_default_nan(fpst
);
680 } else if (float16_is_infinity(f16
)) {
681 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
682 } else if (float16_is_zero(f16
)) {
683 float_raise(float_flag_divbyzero
, fpst
);
684 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
685 } else if (float16_abs(f16
) < (1 << 8)) {
686 /* Abs(value) < 2.0^-16 */
687 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
688 if (round_to_inf(fpst
, f16_sign
)) {
689 return float16_set_sign(float16_infinity
, f16_sign
);
691 return float16_set_sign(float16_maxnorm
, f16_sign
);
693 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
694 float_raise(float_flag_underflow
, fpst
);
695 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
698 f64_frac
= call_recip_estimate(&f16_exp
, 29,
699 ((uint64_t) f16_frac
) << (52 - 10));
701 /* result = sign : result_exp<4:0> : fraction<51:42> */
702 f16_val
= deposit32(0, 15, 1, f16_sign
);
703 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
704 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
705 return make_float16(f16_val
);
708 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
710 float_status
*fpst
= fpstp
;
711 float32 f32
= float32_squash_input_denormal(input
, fpst
);
712 uint32_t f32_val
= float32_val(f32
);
713 bool f32_sign
= float32_is_neg(f32
);
714 int f32_exp
= extract32(f32_val
, 23, 8);
715 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
718 if (float32_is_any_nan(f32
)) {
720 if (float32_is_signaling_nan(f32
, fpst
)) {
721 float_raise(float_flag_invalid
, fpst
);
722 nan
= float32_silence_nan(f32
, fpst
);
724 if (fpst
->default_nan_mode
) {
725 nan
= float32_default_nan(fpst
);
728 } else if (float32_is_infinity(f32
)) {
729 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
730 } else if (float32_is_zero(f32
)) {
731 float_raise(float_flag_divbyzero
, fpst
);
732 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
733 } else if (float32_abs(f32
) < (1ULL << 21)) {
734 /* Abs(value) < 2.0^-128 */
735 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
736 if (round_to_inf(fpst
, f32_sign
)) {
737 return float32_set_sign(float32_infinity
, f32_sign
);
739 return float32_set_sign(float32_maxnorm
, f32_sign
);
741 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
742 float_raise(float_flag_underflow
, fpst
);
743 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
746 f64_frac
= call_recip_estimate(&f32_exp
, 253,
747 ((uint64_t) f32_frac
) << (52 - 23));
749 /* result = sign : result_exp<7:0> : fraction<51:29> */
750 f32_val
= deposit32(0, 31, 1, f32_sign
);
751 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
752 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
753 return make_float32(f32_val
);
756 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
758 float_status
*fpst
= fpstp
;
759 float64 f64
= float64_squash_input_denormal(input
, fpst
);
760 uint64_t f64_val
= float64_val(f64
);
761 bool f64_sign
= float64_is_neg(f64
);
762 int f64_exp
= extract64(f64_val
, 52, 11);
763 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
765 /* Deal with any special cases */
766 if (float64_is_any_nan(f64
)) {
768 if (float64_is_signaling_nan(f64
, fpst
)) {
769 float_raise(float_flag_invalid
, fpst
);
770 nan
= float64_silence_nan(f64
, fpst
);
772 if (fpst
->default_nan_mode
) {
773 nan
= float64_default_nan(fpst
);
776 } else if (float64_is_infinity(f64
)) {
777 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
778 } else if (float64_is_zero(f64
)) {
779 float_raise(float_flag_divbyzero
, fpst
);
780 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
781 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
782 /* Abs(value) < 2.0^-1024 */
783 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
784 if (round_to_inf(fpst
, f64_sign
)) {
785 return float64_set_sign(float64_infinity
, f64_sign
);
787 return float64_set_sign(float64_maxnorm
, f64_sign
);
789 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
790 float_raise(float_flag_underflow
, fpst
);
791 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
794 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
796 /* result = sign : result_exp<10:0> : fraction<51:0>; */
797 f64_val
= deposit64(0, 63, 1, f64_sign
);
798 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
799 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
800 return make_float64(f64_val
);
803 /* The algorithm that must be used to calculate the estimate
804 * is specified by the ARM ARM.
807 static int do_recip_sqrt_estimate(int a
)
811 assert(128 <= a
&& a
< 512);
819 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
822 estimate
= (b
+ 1) / 2;
823 assert(256 <= estimate
&& estimate
< 512);
829 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
835 while (extract64(frac
, 51, 1) == 0) {
839 frac
= extract64(frac
, 0, 51) << 1;
843 /* scaled = UInt('01':fraction<51:45>) */
844 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
846 /* scaled = UInt('1':fraction<51:44>) */
847 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
849 estimate
= do_recip_sqrt_estimate(scaled
);
851 *exp
= (exp_off
- *exp
) / 2;
852 return extract64(estimate
, 0, 8) << 44;
855 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
857 float_status
*s
= fpstp
;
858 float16 f16
= float16_squash_input_denormal(input
, s
);
859 uint16_t val
= float16_val(f16
);
860 bool f16_sign
= float16_is_neg(f16
);
861 int f16_exp
= extract32(val
, 10, 5);
862 uint16_t f16_frac
= extract32(val
, 0, 10);
865 if (float16_is_any_nan(f16
)) {
867 if (float16_is_signaling_nan(f16
, s
)) {
868 float_raise(float_flag_invalid
, s
);
869 nan
= float16_silence_nan(f16
, s
);
871 if (s
->default_nan_mode
) {
872 nan
= float16_default_nan(s
);
875 } else if (float16_is_zero(f16
)) {
876 float_raise(float_flag_divbyzero
, s
);
877 return float16_set_sign(float16_infinity
, f16_sign
);
878 } else if (f16_sign
) {
879 float_raise(float_flag_invalid
, s
);
880 return float16_default_nan(s
);
881 } else if (float16_is_infinity(f16
)) {
885 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
886 * preserving the parity of the exponent. */
888 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
890 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
892 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
893 val
= deposit32(0, 15, 1, f16_sign
);
894 val
= deposit32(val
, 10, 5, f16_exp
);
895 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
896 return make_float16(val
);
899 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
901 float_status
*s
= fpstp
;
902 float32 f32
= float32_squash_input_denormal(input
, s
);
903 uint32_t val
= float32_val(f32
);
904 uint32_t f32_sign
= float32_is_neg(f32
);
905 int f32_exp
= extract32(val
, 23, 8);
906 uint32_t f32_frac
= extract32(val
, 0, 23);
909 if (float32_is_any_nan(f32
)) {
911 if (float32_is_signaling_nan(f32
, s
)) {
912 float_raise(float_flag_invalid
, s
);
913 nan
= float32_silence_nan(f32
, s
);
915 if (s
->default_nan_mode
) {
916 nan
= float32_default_nan(s
);
919 } else if (float32_is_zero(f32
)) {
920 float_raise(float_flag_divbyzero
, s
);
921 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
922 } else if (float32_is_neg(f32
)) {
923 float_raise(float_flag_invalid
, s
);
924 return float32_default_nan(s
);
925 } else if (float32_is_infinity(f32
)) {
929 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
930 * preserving the parity of the exponent. */
932 f64_frac
= ((uint64_t) f32_frac
) << 29;
934 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
936 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
937 val
= deposit32(0, 31, 1, f32_sign
);
938 val
= deposit32(val
, 23, 8, f32_exp
);
939 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
940 return make_float32(val
);
943 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
945 float_status
*s
= fpstp
;
946 float64 f64
= float64_squash_input_denormal(input
, s
);
947 uint64_t val
= float64_val(f64
);
948 bool f64_sign
= float64_is_neg(f64
);
949 int f64_exp
= extract64(val
, 52, 11);
950 uint64_t f64_frac
= extract64(val
, 0, 52);
952 if (float64_is_any_nan(f64
)) {
954 if (float64_is_signaling_nan(f64
, s
)) {
955 float_raise(float_flag_invalid
, s
);
956 nan
= float64_silence_nan(f64
, s
);
958 if (s
->default_nan_mode
) {
959 nan
= float64_default_nan(s
);
962 } else if (float64_is_zero(f64
)) {
963 float_raise(float_flag_divbyzero
, s
);
964 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
965 } else if (float64_is_neg(f64
)) {
966 float_raise(float_flag_invalid
, s
);
967 return float64_default_nan(s
);
968 } else if (float64_is_infinity(f64
)) {
972 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
974 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
975 val
= deposit64(0, 61, 1, f64_sign
);
976 val
= deposit64(val
, 52, 11, f64_exp
);
977 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
978 return make_float64(val
);
981 uint32_t HELPER(recpe_u32
)(uint32_t a
)
985 if ((a
& 0x80000000) == 0) {
989 input
= extract32(a
, 23, 9);
990 estimate
= recip_estimate(input
);
992 return deposit32(0, (32 - 9), 9, estimate
);
995 uint32_t HELPER(rsqrte_u32
)(uint32_t a
)
999 if ((a
& 0xc0000000) == 0) {
1003 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
1005 return deposit32(0, 23, 9, estimate
);
1008 /* VFPv4 fused multiply-accumulate */
1009 dh_ctype_f16
VFP_HELPER(muladd
, h
)(dh_ctype_f16 a
, dh_ctype_f16 b
,
1010 dh_ctype_f16 c
, void *fpstp
)
1012 float_status
*fpst
= fpstp
;
1013 return float16_muladd(a
, b
, c
, 0, fpst
);
1016 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
1018 float_status
*fpst
= fpstp
;
1019 return float32_muladd(a
, b
, c
, 0, fpst
);
1022 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
1024 float_status
*fpst
= fpstp
;
1025 return float64_muladd(a
, b
, c
, 0, fpst
);
1028 /* ARMv8 round to integral */
1029 dh_ctype_f16
HELPER(rinth_exact
)(dh_ctype_f16 x
, void *fp_status
)
1031 return float16_round_to_int(x
, fp_status
);
1034 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
1036 return float32_round_to_int(x
, fp_status
);
1039 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
1041 return float64_round_to_int(x
, fp_status
);
1044 dh_ctype_f16
HELPER(rinth
)(dh_ctype_f16 x
, void *fp_status
)
1046 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1049 ret
= float16_round_to_int(x
, fp_status
);
1051 /* Suppress any inexact exceptions the conversion produced */
1052 if (!(old_flags
& float_flag_inexact
)) {
1053 new_flags
= get_float_exception_flags(fp_status
);
1054 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1060 float32
HELPER(rints
)(float32 x
, void *fp_status
)
1062 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1065 ret
= float32_round_to_int(x
, fp_status
);
1067 /* Suppress any inexact exceptions the conversion produced */
1068 if (!(old_flags
& float_flag_inexact
)) {
1069 new_flags
= get_float_exception_flags(fp_status
);
1070 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1076 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
1078 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1081 ret
= float64_round_to_int(x
, fp_status
);
1083 new_flags
= get_float_exception_flags(fp_status
);
1085 /* Suppress any inexact exceptions the conversion produced */
1086 if (!(old_flags
& float_flag_inexact
)) {
1087 new_flags
= get_float_exception_flags(fp_status
);
1088 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1094 /* Convert ARM rounding mode to softfloat */
1095 int arm_rmode_to_sf(int rmode
)
1098 case FPROUNDING_TIEAWAY
:
1099 rmode
= float_round_ties_away
;
1101 case FPROUNDING_ODD
:
1102 /* FIXME: add support for TIEAWAY and ODD */
1103 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
1105 /* fall through for now */
1106 case FPROUNDING_TIEEVEN
:
1108 rmode
= float_round_nearest_even
;
1110 case FPROUNDING_POSINF
:
1111 rmode
= float_round_up
;
1113 case FPROUNDING_NEGINF
:
1114 rmode
= float_round_down
;
1116 case FPROUNDING_ZERO
:
1117 rmode
= float_round_to_zero
;
1124 * Implement float64 to int32_t conversion without saturation;
1125 * the result is supplied modulo 2^32.
1127 uint64_t HELPER(fjcvtzs
)(float64 value
, void *vstatus
)
1129 float_status
*status
= vstatus
;
1132 uint32_t inexact
= 1; /* !Z */
1134 sign
= extract64(value
, 63, 1);
1135 exp
= extract64(value
, 52, 11);
1136 frac
= extract64(value
, 0, 52);
1139 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1142 if (status
->flush_inputs_to_zero
) {
1143 float_raise(float_flag_input_denormal
, status
);
1145 float_raise(float_flag_inexact
, status
);
1150 } else if (exp
== 0x7ff) {
1151 /* This operation raises Invalid for both NaN and overflow (Inf). */
1152 float_raise(float_flag_invalid
, status
);
1155 int true_exp
= exp
- 1023;
1156 int shift
= true_exp
- 52;
1158 /* Restore implicit bit. */
1161 /* Shift the fraction into place. */
1163 /* The number is so large we must shift the fraction left. */
1165 /* The fraction is shifted out entirely. */
1170 } else if (shift
> -64) {
1171 /* Normal case -- shift right and notice if bits shift out. */
1172 inexact
= (frac
<< (64 + shift
)) != 0;
1175 /* The fraction is shifted out entirely. */
1179 /* Notice overflow or inexact exceptions. */
1180 if (true_exp
> 31 || frac
> (sign
? 0x80000000ull
: 0x7fffffff)) {
1181 /* Overflow, for which this operation raises invalid. */
1182 float_raise(float_flag_invalid
, status
);
1184 } else if (inexact
) {
1185 float_raise(float_flag_inexact
, status
);
1188 /* Honor the sign. */
1194 /* Pack the result and the env->ZF representation of Z together. */
1195 return deposit64(frac
, 32, 32, inexact
);
1198 uint32_t HELPER(vjcvt
)(float64 value
, CPUARMState
*env
)
1200 uint64_t pair
= HELPER(fjcvtzs
)(value
, &env
->vfp
.fp_status
);
1201 uint32_t result
= pair
;
1202 uint32_t z
= (pair
>> 32) == 0;
1204 /* Store Z, clear NCV, in FPSCR.NZCV. */
1205 env
->vfp
.xregs
[ARM_VFP_FPSCR
]
1206 = (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & ~CPSR_NZCV
) | (z
* CPSR_Z
);
1211 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1212 static float32
frint_s(float32 f
, float_status
*fpst
, int intsize
)
1214 int old_flags
= get_float_exception_flags(fpst
);
1215 uint32_t exp
= extract32(f
, 23, 8);
1217 if (unlikely(exp
== 0xff)) {
1222 /* Round and re-extract the exponent. */
1223 f
= float32_round_to_int(f
, fpst
);
1224 exp
= extract32(f
, 23, 8);
1226 /* Validate the range of the result. */
1227 if (exp
< 126 + intsize
) {
1228 /* abs(F) <= INT{N}_MAX */
1231 if (exp
== 126 + intsize
) {
1232 uint32_t sign
= extract32(f
, 31, 1);
1233 uint32_t frac
= extract32(f
, 0, 23);
1234 if (sign
&& frac
== 0) {
1235 /* F == INT{N}_MIN */
1242 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1243 * inexact exception float32_round_to_int may have raised.
1245 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1246 return (0x100u
+ 126u + intsize
) << 23;
1249 float32
HELPER(frint32_s
)(float32 f
, void *fpst
)
1251 return frint_s(f
, fpst
, 32);
1254 float32
HELPER(frint64_s
)(float32 f
, void *fpst
)
1256 return frint_s(f
, fpst
, 64);
1259 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1260 static float64
frint_d(float64 f
, float_status
*fpst
, int intsize
)
1262 int old_flags
= get_float_exception_flags(fpst
);
1263 uint32_t exp
= extract64(f
, 52, 11);
1265 if (unlikely(exp
== 0x7ff)) {
1270 /* Round and re-extract the exponent. */
1271 f
= float64_round_to_int(f
, fpst
);
1272 exp
= extract64(f
, 52, 11);
1274 /* Validate the range of the result. */
1275 if (exp
< 1022 + intsize
) {
1276 /* abs(F) <= INT{N}_MAX */
1279 if (exp
== 1022 + intsize
) {
1280 uint64_t sign
= extract64(f
, 63, 1);
1281 uint64_t frac
= extract64(f
, 0, 52);
1282 if (sign
&& frac
== 0) {
1283 /* F == INT{N}_MIN */
1290 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1291 * inexact exception float64_round_to_int may have raised.
1293 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1294 return (uint64_t)(0x800 + 1022 + intsize
) << 52;
1297 float64
HELPER(frint32_d
)(float64 f
, void *fpst
)
1299 return frint_d(f
, fpst
, 32);
1302 float64
HELPER(frint64_d
)(float64 f
, void *fpst
)
1304 return frint_d(f
, fpst
, 64);
1307 void HELPER(check_hcr_el2_trap
)(CPUARMState
*env
, uint32_t rt
, uint32_t reg
)
1315 if (!(arm_hcr_el2_eff(env
) & HCR_TID3
)) {
1320 if (!(arm_hcr_el2_eff(env
) & HCR_TID0
)) {
1325 g_assert_not_reached();
1328 syndrome
= ((EC_FPIDTRAP
<< ARM_EL_EC_SHIFT
)
1330 | (1 << 24) | (0xe << 20) | (7 << 14)
1331 | (reg
<< 10) | (rt
<< 5) | 1);
1333 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);