hw/arm/virt-acpi-build.c

   1 /* Support for generating ACPI tables and passing them to Guests
   2  *
   3  * ARM virt ACPI generation
   4  *
   5  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
   6  * Copyright (C) 2006 Fabrice Bellard
   7  * Copyright (C) 2013 Red Hat Inc
   8  *
   9  * Author: Michael S. Tsirkin <mst@redhat.com>
  10  *
  11  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
  12  *
  13  * Author: Shannon Zhao <zhaoshenglong@huawei.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24
  25  * You should have received a copy of the GNU General Public License along
  26  * with this program; if not, see <http://www.gnu.org/licenses/>.
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "qapi/error.h"
  31 #include "qemu-common.h"
  32 #include "hw/arm/virt-acpi-build.h"
  33 #include "qemu/bitmap.h"
  34 #include "trace.h"
  35 #include "qom/cpu.h"
  36 #include "target-arm/cpu.h"
  37 #include "hw/acpi/acpi-defs.h"
  38 #include "hw/acpi/acpi.h"
  39 #include "hw/nvram/fw_cfg.h"
  40 #include "hw/acpi/bios-linker-loader.h"
  41 #include "hw/loader.h"
  42 #include "hw/hw.h"
  43 #include "hw/acpi/aml-build.h"
  44 #include "hw/pci/pcie_host.h"
  45 #include "hw/pci/pci.h"
  46 #include "sysemu/numa.h"
  47 #include "kvm_arm.h"
  48
  49 #define ARM_SPI_BASE 32
  50 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
  51
  52 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
  53 {
  54     uint16_t i;
  55
  56     for (i = 0; i < smp_cpus; i++) {
  57         Aml *dev = aml_device("C%.03X", i);
  58         aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
  59         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
  60         aml_append(scope, dev);
  61     }
  62 }
  63
  64 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
  65                                            uint32_t uart_irq)
  66 {
  67     Aml *dev = aml_device("COM0");
  68     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
  69     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
  70
  71     Aml *crs = aml_resource_template();
  72     aml_append(crs, aml_memory32_fixed(uart_memmap->base,
  73                                        uart_memmap->size, AML_READ_WRITE));
  74     aml_append(crs,
  75                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  76                              AML_EXCLUSIVE, &uart_irq, 1));
  77     aml_append(dev, aml_name_decl("_CRS", crs));
  78
  79     /* The _ADR entry is used to link this device to the UART described
  80      * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
  81      */
  82     aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
  83
  84     aml_append(scope, dev);
  85 }
  86
  87 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
  88 {
  89     Aml *dev = aml_device("FWCF");
  90     aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
  91     /* device present, functioning, decoding, not shown in UI */
  92     aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
  93
  94     Aml *crs = aml_resource_template();
  95     aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
  96                                        fw_cfg_memmap->size, AML_READ_WRITE));
  97     aml_append(dev, aml_name_decl("_CRS", crs));
  98     aml_append(scope, dev);
  99 }
 100
 101 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
 102 {
 103     Aml *dev, *crs;
 104     hwaddr base = flash_memmap->base;
 105     hwaddr size = flash_memmap->size / 2;
 106
 107     dev = aml_device("FLS0");
 108     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 109     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 110
 111     crs = aml_resource_template();
 112     aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 113     aml_append(dev, aml_name_decl("_CRS", crs));
 114     aml_append(scope, dev);
 115
 116     dev = aml_device("FLS1");
 117     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 118     aml_append(dev, aml_name_decl("_UID", aml_int(1)));
 119     crs = aml_resource_template();
 120     aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
 121     aml_append(dev, aml_name_decl("_CRS", crs));
 122     aml_append(scope, dev);
 123 }
 124
 125 static void acpi_dsdt_add_virtio(Aml *scope,
 126                                  const MemMapEntry *virtio_mmio_memmap,
 127                                  uint32_t mmio_irq, int num)
 128 {
 129     hwaddr base = virtio_mmio_memmap->base;
 130     hwaddr size = virtio_mmio_memmap->size;
 131     int i;
 132
 133     for (i = 0; i < num; i++) {
 134         uint32_t irq = mmio_irq + i;
 135         Aml *dev = aml_device("VR%02u", i);
 136         aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
 137         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
 138
 139         Aml *crs = aml_resource_template();
 140         aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 141         aml_append(crs,
 142                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 143                                  AML_EXCLUSIVE, &irq, 1));
 144         aml_append(dev, aml_name_decl("_CRS", crs));
 145         aml_append(scope, dev);
 146         base += size;
 147     }
 148 }
 149
 150 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
 151                               uint32_t irq, bool use_highmem)
 152 {
 153     Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
 154     int i, bus_no;
 155     hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
 156     hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
 157     hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
 158     hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
 159     hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
 160     hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
 161     int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
 162
 163     Aml *dev = aml_device("%s", "PCI0");
 164     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 165     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 166     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 167     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 168     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 169     aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
 170     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 171     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 172
 173     /* Declare the PCI Routing Table. */
 174     Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
 175     for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
 176         for (i = 0; i < PCI_NUM_PINS; i++) {
 177             int gsi = (i + bus_no) % PCI_NUM_PINS;
 178             Aml *pkg = aml_package(4);
 179             aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
 180             aml_append(pkg, aml_int(i));
 181             aml_append(pkg, aml_name("GSI%d", gsi));
 182             aml_append(pkg, aml_int(0));
 183             aml_append(rt_pkg, pkg);
 184         }
 185     }
 186     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
 187
 188     /* Create GSI link device */
 189     for (i = 0; i < PCI_NUM_PINS; i++) {
 190         uint32_t irqs =  irq + i;
 191         Aml *dev_gsi = aml_device("GSI%d", i);
 192         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
 193         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
 194         crs = aml_resource_template();
 195         aml_append(crs,
 196                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 197                                  AML_EXCLUSIVE, &irqs, 1));
 198         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
 199         crs = aml_resource_template();
 200         aml_append(crs,
 201                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 202                                  AML_EXCLUSIVE, &irqs, 1));
 203         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
 204         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
 205         aml_append(dev_gsi, method);
 206         aml_append(dev, dev_gsi);
 207     }
 208
 209     method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
 210     aml_append(method, aml_return(aml_int(base_ecam)));
 211     aml_append(dev, method);
 212
 213     method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
 214     Aml *rbuf = aml_resource_template();
 215     aml_append(rbuf,
 216         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 217                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 218                             nr_pcie_buses));
 219     aml_append(rbuf,
 220         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 221                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
 222                          base_mmio + size_mmio - 1, 0x0000, size_mmio));
 223     aml_append(rbuf,
 224         aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 225                      AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
 226                      size_pio));
 227
 228     if (use_highmem) {
 229         hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
 230         hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
 231
 232         aml_append(rbuf,
 233             aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 234                              AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 235                              base_mmio_high,
 236                              base_mmio_high + size_mmio_high - 1, 0x0000,
 237                              size_mmio_high));
 238     }
 239
 240     aml_append(method, aml_name_decl("RBUF", rbuf));
 241     aml_append(method, aml_return(rbuf));
 242     aml_append(dev, method);
 243
 244     /* Declare an _OSC (OS Control Handoff) method */
 245     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
 246     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
 247     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
 248     aml_append(method,
 249         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
 250
 251     /* PCI Firmware Specification 3.0
 252      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
 253      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
 254      * identified by the Universal Unique IDentifier (UUID)
 255      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
 256      */
 257     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
 258     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 259     aml_append(ifctx,
 260         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
 261     aml_append(ifctx,
 262         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
 263     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
 264     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
 265     aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
 266                                 aml_name("CTRL")));
 267
 268     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
 269     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
 270                                  aml_name("CDW1")));
 271     aml_append(ifctx, ifctx1);
 272
 273     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
 274     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
 275                                  aml_name("CDW1")));
 276     aml_append(ifctx, ifctx1);
 277
 278     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
 279     aml_append(ifctx, aml_return(aml_arg(3)));
 280     aml_append(method, ifctx);
 281
 282     elsectx = aml_else();
 283     aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
 284                                   aml_name("CDW1")));
 285     aml_append(elsectx, aml_return(aml_arg(3)));
 286     aml_append(method, elsectx);
 287     aml_append(dev, method);
 288
 289     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 290
 291     /* PCI Firmware Specification 3.0
 292      * 4.6.1. _DSM for PCI Express Slot Information
 293      * The UUID in _DSM in this context is
 294      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 295      */
 296     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 297     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 298     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 299     uint8_t byte_list[1] = {1};
 300     buf = aml_buffer(1, byte_list);
 301     aml_append(ifctx1, aml_return(buf));
 302     aml_append(ifctx, ifctx1);
 303     aml_append(method, ifctx);
 304
 305     byte_list[0] = 0;
 306     buf = aml_buffer(1, byte_list);
 307     aml_append(method, aml_return(buf));
 308     aml_append(dev, method);
 309
 310     Aml *dev_rp0 = aml_device("%s", "RP0");
 311     aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
 312     aml_append(dev, dev_rp0);
 313     aml_append(scope, dev);
 314 }
 315
 316 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
 317                                            uint32_t gpio_irq)
 318 {
 319     Aml *dev = aml_device("GPO0");
 320     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
 321     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 322     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 323
 324     Aml *crs = aml_resource_template();
 325     aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
 326                                        AML_READ_WRITE));
 327     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 328                                   AML_EXCLUSIVE, &gpio_irq, 1));
 329     aml_append(dev, aml_name_decl("_CRS", crs));
 330
 331     Aml *aei = aml_resource_template();
 332     /* Pin 3 for power button */
 333     const uint32_t pin_list[1] = {3};
 334     aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
 335                                  AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
 336                                  "GPO0", NULL, 0));
 337     aml_append(dev, aml_name_decl("_AEI", aei));
 338
 339     /* _E03 is handle for power button */
 340     Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
 341     aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
 342                                   aml_int(0x80)));
 343     aml_append(dev, method);
 344     aml_append(scope, dev);
 345 }
 346
 347 static void acpi_dsdt_add_power_button(Aml *scope)
 348 {
 349     Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
 350     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
 351     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 352     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 353     aml_append(scope, dev);
 354 }
 355
 356 /* RSDP */
 357 static GArray *
 358 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
 359 {
 360     AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
 361     unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
 362     unsigned rsdt_pa_offset =
 363         (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
 364
 365     bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
 366                              true /* fseg memory */);
 367
 368     memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
 369     memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
 370     rsdp->length = cpu_to_le32(sizeof(*rsdp));
 371     rsdp->revision = 0x02;
 372
 373     /* Address to be filled by Guest linker */
 374     bios_linker_loader_add_pointer(linker,
 375         ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
 376         ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
 377
 378     /* Checksum to be filled by Guest linker */
 379     bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
 380         (char *)rsdp - rsdp_table->data, sizeof *rsdp,
 381         (char *)&rsdp->checksum - rsdp_table->data);
 382
 383     return rsdp_table;
 384 }
 385
 386 static void
 387 build_spcr(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 388 {
 389     AcpiSerialPortConsoleRedirection *spcr;
 390     const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART];
 391     int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE;
 392
 393     spcr = acpi_data_push(table_data, sizeof(*spcr));
 394
 395     spcr->interface_type = 0x3;    /* ARM PL011 UART */
 396
 397     spcr->base_address.space_id = AML_SYSTEM_MEMORY;
 398     spcr->base_address.bit_width = 8;
 399     spcr->base_address.bit_offset = 0;
 400     spcr->base_address.access_width = 1;
 401     spcr->base_address.address = cpu_to_le64(uart_memmap->base);
 402
 403     spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
 404     spcr->gsi = cpu_to_le32(irq);  /* Global System Interrupt */
 405
 406     spcr->baud = 3;                /* Baud Rate: 3 = 9600 */
 407     spcr->parity = 0;              /* No Parity */
 408     spcr->stopbits = 1;            /* 1 Stop bit */
 409     spcr->flowctrl = (1 << 1);     /* Bit[1] = RTS/CTS hardware flow control */
 410     spcr->term_type = 0;           /* Terminal Type: 0 = VT100 */
 411
 412     spcr->pci_device_id = 0xffff;  /* PCI Device ID: not a PCI device */
 413     spcr->pci_vendor_id = 0xffff;  /* PCI Vendor ID: not a PCI device */
 414
 415     build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2,
 416                  NULL, NULL);
 417 }
 418
 419 static void
 420 build_srat(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 421 {
 422     AcpiSystemResourceAffinityTable *srat;
 423     AcpiSratProcessorGiccAffinity *core;
 424     AcpiSratMemoryAffinity *numamem;
 425     int i, j, srat_start;
 426     uint64_t mem_base;
 427     uint32_t *cpu_node = g_malloc0(guest_info->smp_cpus * sizeof(uint32_t));
 428
 429     for (i = 0; i < guest_info->smp_cpus; i++) {
 430         j = numa_get_node_for_cpu(i);
 431         if (j < nb_numa_nodes) {
 432                 cpu_node[i] = j;
 433         }
 434     }
 435
 436     srat_start = table_data->len;
 437     srat = acpi_data_push(table_data, sizeof(*srat));
 438     srat->reserved1 = cpu_to_le32(1);
 439
 440     for (i = 0; i < guest_info->smp_cpus; ++i) {
 441         core = acpi_data_push(table_data, sizeof(*core));
 442         core->type = ACPI_SRAT_PROCESSOR_GICC;
 443         core->length = sizeof(*core);
 444         core->proximity = cpu_to_le32(cpu_node[i]);
 445         core->acpi_processor_uid = cpu_to_le32(i);
 446         core->flags = cpu_to_le32(1);
 447     }
 448     g_free(cpu_node);
 449
 450     mem_base = guest_info->memmap[VIRT_MEM].base;
 451     for (i = 0; i < nb_numa_nodes; ++i) {
 452         numamem = acpi_data_push(table_data, sizeof(*numamem));
 453         build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
 454                           MEM_AFFINITY_ENABLED);
 455         mem_base += numa_info[i].node_mem;
 456     }
 457
 458     build_header(linker, table_data, (void *)srat, "SRAT",
 459                  table_data->len - srat_start, 3, NULL, NULL);
 460 }
 461
 462 static void
 463 build_mcfg(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 464 {
 465     AcpiTableMcfg *mcfg;
 466     const MemMapEntry *memmap = guest_info->memmap;
 467     int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
 468
 469     mcfg = acpi_data_push(table_data, len);
 470     mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
 471
 472     /* Only a single allocation so no need to play with segments */
 473     mcfg->allocation[0].pci_segment = cpu_to_le16(0);
 474     mcfg->allocation[0].start_bus_number = 0;
 475     mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
 476                                           / PCIE_MMCFG_SIZE_MIN) - 1;
 477
 478     build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL);
 479 }
 480
 481 /* GTDT */
 482 static void
 483 build_gtdt(GArray *table_data, BIOSLinker *linker)
 484 {
 485     int gtdt_start = table_data->len;
 486     AcpiGenericTimerTable *gtdt;
 487
 488     gtdt = acpi_data_push(table_data, sizeof *gtdt);
 489     /* The interrupt values are the same with the device tree when adding 16 */
 490     gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16;
 491     gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
 492
 493     gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16;
 494     gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE | ACPI_GTDT_ALWAYS_ON;
 495
 496     gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16;
 497     gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
 498
 499     gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16;
 500     gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
 501
 502     build_header(linker, table_data,
 503                  (void *)(table_data->data + gtdt_start), "GTDT",
 504                  table_data->len - gtdt_start, 2, NULL, NULL);
 505 }
 506
 507 /* MADT */
 508 static void
 509 build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 510 {
 511     int madt_start = table_data->len;
 512     const MemMapEntry *memmap = guest_info->memmap;
 513     const int *irqmap = guest_info->irqmap;
 514     AcpiMultipleApicTable *madt;
 515     AcpiMadtGenericDistributor *gicd;
 516     AcpiMadtGenericMsiFrame *gic_msi;
 517     int i;
 518
 519     madt = acpi_data_push(table_data, sizeof *madt);
 520
 521     gicd = acpi_data_push(table_data, sizeof *gicd);
 522     gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
 523     gicd->length = sizeof(*gicd);
 524     gicd->base_address = memmap[VIRT_GIC_DIST].base;
 525     gicd->version = guest_info->gic_version;
 526
 527     for (i = 0; i < guest_info->smp_cpus; i++) {
 528         AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
 529                                                      sizeof *gicc);
 530         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
 531
 532         gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
 533         gicc->length = sizeof(*gicc);
 534         if (guest_info->gic_version == 2) {
 535             gicc->base_address = memmap[VIRT_GIC_CPU].base;
 536         }
 537         gicc->cpu_interface_number = i;
 538         gicc->arm_mpidr = armcpu->mp_affinity;
 539         gicc->uid = i;
 540         gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
 541
 542         if (armcpu->has_pmu) {
 543             gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
 544         }
 545     }
 546
 547     if (guest_info->gic_version == 3) {
 548         AcpiMadtGenericTranslator *gic_its;
 549         AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
 550                                                          sizeof *gicr);
 551
 552         gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
 553         gicr->length = sizeof(*gicr);
 554         gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
 555         gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
 556
 557         if (!its_class_name()) {
 558             return;
 559         }
 560
 561         gic_its = acpi_data_push(table_data, sizeof *gic_its);
 562         gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
 563         gic_its->length = sizeof(*gic_its);
 564         gic_its->translation_id = 0;
 565         gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
 566     } else {
 567         gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
 568         gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
 569         gic_msi->length = sizeof(*gic_msi);
 570         gic_msi->gic_msi_frame_id = 0;
 571         gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
 572         gic_msi->flags = cpu_to_le32(1);
 573         gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
 574         gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
 575     }
 576
 577     build_header(linker, table_data,
 578                  (void *)(table_data->data + madt_start), "APIC",
 579                  table_data->len - madt_start, 3, NULL, NULL);
 580 }
 581
 582 /* FADT */
 583 static void
 584 build_fadt(GArray *table_data, BIOSLinker *linker, unsigned dsdt_tbl_offset)
 585 {
 586     AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
 587     unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
 588
 589     /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
 590     fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
 591     fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
 592                                        (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
 593
 594     /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
 595     fadt->minor_revision = 0x1;
 596
 597     /* DSDT address to be filled by Guest linker */
 598     bios_linker_loader_add_pointer(linker,
 599         ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
 600         ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
 601
 602     build_header(linker, table_data,
 603                  (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL);
 604 }
 605
 606 /* DSDT */
 607 static void
 608 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
 609 {
 610     Aml *scope, *dsdt;
 611     const MemMapEntry *memmap = guest_info->memmap;
 612     const int *irqmap = guest_info->irqmap;
 613
 614     dsdt = init_aml_allocator();
 615     /* Reserve space for header */
 616     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
 617
 618     /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
 619      * While UEFI can use libfdt to disable the RTC device node in the DTB that
 620      * it passes to the OS, it cannot modify AML. Therefore, we won't generate
 621      * the RTC ACPI device at all when using UEFI.
 622      */
 623     scope = aml_scope("\\_SB");
 624     acpi_dsdt_add_cpus(scope, guest_info->smp_cpus);
 625     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
 626                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
 627     acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
 628     acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
 629     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
 630                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
 631     acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
 632                       guest_info->use_highmem);
 633     acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
 634                        (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
 635     acpi_dsdt_add_power_button(scope);
 636
 637     aml_append(dsdt, scope);
 638
 639     /* copy AML table into ACPI tables blob and patch header there */
 640     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
 641     build_header(linker, table_data,
 642         (void *)(table_data->data + table_data->len - dsdt->buf->len),
 643         "DSDT", dsdt->buf->len, 2, NULL, NULL);
 644     free_aml_allocator();
 645 }
 646
 647 typedef
 648 struct AcpiBuildState {
 649     /* Copy of table in RAM (for patching). */
 650     MemoryRegion *table_mr;
 651     MemoryRegion *rsdp_mr;
 652     MemoryRegion *linker_mr;
 653     /* Is table patched? */
 654     bool patched;
 655     VirtGuestInfo *guest_info;
 656 } AcpiBuildState;
 657
 658 static
 659 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
 660 {
 661     GArray *table_offsets;
 662     unsigned dsdt, rsdt;
 663     GArray *tables_blob = tables->table_data;
 664
 665     table_offsets = g_array_new(false, true /* clear */,
 666                                         sizeof(uint32_t));
 667
 668     bios_linker_loader_alloc(tables->linker,
 669                              ACPI_BUILD_TABLE_FILE, tables_blob,
 670                              64, false /* high memory */);
 671
 672     /*
 673      * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
 674      * RSDP
 675      * RSDT
 676      * FADT
 677      * GTDT
 678      * MADT
 679      * MCFG
 680      * DSDT
 681      */
 682
 683     /* DSDT is pointed to by FADT */
 684     dsdt = tables_blob->len;
 685     build_dsdt(tables_blob, tables->linker, guest_info);
 686
 687     /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
 688     acpi_add_table(table_offsets, tables_blob);
 689     build_fadt(tables_blob, tables->linker, dsdt);
 690
 691     acpi_add_table(table_offsets, tables_blob);
 692     build_madt(tables_blob, tables->linker, guest_info);
 693
 694     acpi_add_table(table_offsets, tables_blob);
 695     build_gtdt(tables_blob, tables->linker);
 696
 697     acpi_add_table(table_offsets, tables_blob);
 698     build_mcfg(tables_blob, tables->linker, guest_info);
 699
 700     acpi_add_table(table_offsets, tables_blob);
 701     build_spcr(tables_blob, tables->linker, guest_info);
 702
 703     if (nb_numa_nodes > 0) {
 704         acpi_add_table(table_offsets, tables_blob);
 705         build_srat(tables_blob, tables->linker, guest_info);
 706     }
 707
 708     /* RSDT is pointed to by RSDP */
 709     rsdt = tables_blob->len;
 710     build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
 711
 712     /* RSDP is in FSEG memory, so allocate it separately */
 713     build_rsdp(tables->rsdp, tables->linker, rsdt);
 714
 715     /* Cleanup memory that's no longer used. */
 716     g_array_free(table_offsets, true);
 717 }
 718
 719 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
 720 {
 721     uint32_t size = acpi_data_len(data);
 722
 723     /* Make sure RAM size is correct - in case it got changed
 724      * e.g. by migration */
 725     memory_region_ram_resize(mr, size, &error_abort);
 726
 727     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
 728     memory_region_set_dirty(mr, 0, size);
 729 }
 730
 731 static void virt_acpi_build_update(void *build_opaque)
 732 {
 733     AcpiBuildState *build_state = build_opaque;
 734     AcpiBuildTables tables;
 735
 736     /* No state to update or already patched? Nothing to do. */
 737     if (!build_state || build_state->patched) {
 738         return;
 739     }
 740     build_state->patched = true;
 741
 742     acpi_build_tables_init(&tables);
 743
 744     virt_acpi_build(build_state->guest_info, &tables);
 745
 746     acpi_ram_update(build_state->table_mr, tables.table_data);
 747     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
 748     acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
 749
 750
 751     acpi_build_tables_cleanup(&tables, true);
 752 }
 753
 754 static void virt_acpi_build_reset(void *build_opaque)
 755 {
 756     AcpiBuildState *build_state = build_opaque;
 757     build_state->patched = false;
 758 }
 759
 760 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
 761                                        GArray *blob, const char *name,
 762                                        uint64_t max_size)
 763 {
 764     return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
 765                         name, virt_acpi_build_update, build_state);
 766 }
 767
 768 static const VMStateDescription vmstate_virt_acpi_build = {
 769     .name = "virt_acpi_build",
 770     .version_id = 1,
 771     .minimum_version_id = 1,
 772     .fields = (VMStateField[]) {
 773         VMSTATE_BOOL(patched, AcpiBuildState),
 774         VMSTATE_END_OF_LIST()
 775     },
 776 };
 777
 778 void virt_acpi_setup(VirtGuestInfo *guest_info)
 779 {
 780     AcpiBuildTables tables;
 781     AcpiBuildState *build_state;
 782
 783     if (!guest_info->fw_cfg) {
 784         trace_virt_acpi_setup();
 785         return;
 786     }
 787
 788     if (!acpi_enabled) {
 789         trace_virt_acpi_setup();
 790         return;
 791     }
 792
 793     build_state = g_malloc0(sizeof *build_state);
 794     build_state->guest_info = guest_info;
 795
 796     acpi_build_tables_init(&tables);
 797     virt_acpi_build(build_state->guest_info, &tables);
 798
 799     /* Now expose it all to Guest */
 800     build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
 801                                                ACPI_BUILD_TABLE_FILE,
 802                                                ACPI_BUILD_TABLE_MAX_SIZE);
 803     assert(build_state->table_mr != NULL);
 804
 805     build_state->linker_mr =
 806         acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
 807                           "etc/table-loader", 0);
 808
 809     fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
 810                     tables.tcpalog->data, acpi_data_len(tables.tcpalog));
 811
 812     build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
 813                                               ACPI_BUILD_RSDP_FILE, 0);
 814
 815     qemu_register_reset(virt_acpi_build_reset, build_state);
 816     virt_acpi_build_reset(build_state);
 817     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
 818
 819     /* Cleanup tables but don't free the memory: we track it
 820      * in build_state.
 821      */
 822     acpi_build_tables_cleanup(&tables, false);
 823 }