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ivshmem: use error_report
[qemu/ar7.git] / disas / mips.c
blob729782513873d4db0cc3bef882bc786c2f476cf8
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, see <http://www.gnu.org/licenses/>. */
21
22 #include "disas/bfd.h"
23
24 /* mips.h. Mips opcode list for GDB, the GNU debugger.
25 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
26 Free Software Foundation, Inc.
27 Contributed by Ralph Campbell and OSF
28 Commented and modified by Ian Lance Taylor, Cygnus Support
29
30 This file is part of GDB, GAS, and the GNU binutils.
31
32 GDB, GAS, and the GNU binutils are free software; you can redistribute
33 them and/or modify them under the terms of the GNU General Public
34 License as published by the Free Software Foundation; either version
35 1, or (at your option) any later version.
36
37 GDB, GAS, and the GNU binutils are distributed in the hope that they
38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
40 the GNU General Public License for more details.
41
42 You should have received a copy of the GNU General Public License
43 along with this file; see the file COPYING. If not,
44 see <http://www.gnu.org/licenses/>. */
45
46 /* These are bit masks and shift counts to use to access the various
47 fields of an instruction. To retrieve the X field of an
48 instruction, use the expression
49 (i >> OP_SH_X) & OP_MASK_X
50 To set the same field (to j), use
51 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
52
53 Make sure you use fields that are appropriate for the instruction,
54 of course.
55
56 The 'i' format uses OP, RS, RT and IMMEDIATE.
57
58 The 'j' format uses OP and TARGET.
59
60 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
61
62 The 'b' format uses OP, RS, RT and DELTA.
63
64 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
65
66 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
67
68 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
69 breakpoint instruction are not defined; Kane says the breakpoint
70 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
71 only use ten bits). An optional two-operand form of break/sdbbp
72 allows the lower ten bits to be set too, and MIPS32 and later
73 architectures allow 20 bits to be set with a signal operand
74 (using CODE20).
75
76 The syscall instruction uses CODE20.
77
78 The general coprocessor instructions use COPZ. */
79
80 #define OP_MASK_OP 0x3f
81 #define OP_SH_OP 26
82 #define OP_MASK_RS 0x1f
83 #define OP_SH_RS 21
84 #define OP_MASK_FR 0x1f
85 #define OP_SH_FR 21
86 #define OP_MASK_FMT 0x1f
87 #define OP_SH_FMT 21
88 #define OP_MASK_BCC 0x7
89 #define OP_SH_BCC 18
90 #define OP_MASK_CODE 0x3ff
91 #define OP_SH_CODE 16
92 #define OP_MASK_CODE2 0x3ff
93 #define OP_SH_CODE2 6
94 #define OP_MASK_RT 0x1f
95 #define OP_SH_RT 16
96 #define OP_MASK_FT 0x1f
97 #define OP_SH_FT 16
98 #define OP_MASK_CACHE 0x1f
99 #define OP_SH_CACHE 16
100 #define OP_MASK_RD 0x1f
101 #define OP_SH_RD 11
102 #define OP_MASK_FS 0x1f
103 #define OP_SH_FS 11
104 #define OP_MASK_PREFX 0x1f
105 #define OP_SH_PREFX 11
106 #define OP_MASK_CCC 0x7
107 #define OP_SH_CCC 8
108 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
109 #define OP_SH_CODE20 6
110 #define OP_MASK_SHAMT 0x1f
111 #define OP_SH_SHAMT 6
112 #define OP_MASK_FD 0x1f
113 #define OP_SH_FD 6
114 #define OP_MASK_TARGET 0x3ffffff
115 #define OP_SH_TARGET 0
116 #define OP_MASK_COPZ 0x1ffffff
117 #define OP_SH_COPZ 0
118 #define OP_MASK_IMMEDIATE 0xffff
119 #define OP_SH_IMMEDIATE 0
120 #define OP_MASK_DELTA 0xffff
121 #define OP_SH_DELTA 0
122 #define OP_MASK_DELTA_R6 0x1ff
123 #define OP_SH_DELTA_R6 7
124 #define OP_MASK_FUNCT 0x3f
125 #define OP_SH_FUNCT 0
126 #define OP_MASK_SPEC 0x3f
127 #define OP_SH_SPEC 0
128 #define OP_SH_LOCC 8 /* FP condition code. */
129 #define OP_SH_HICC 18 /* FP condition code. */
130 #define OP_MASK_CC 0x7
131 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
132 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
133 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
134 #define OP_MASK_COP1SPEC 0xf
135 #define OP_MASK_COP1SCLR 0x4
136 #define OP_MASK_COP1CMP 0x3
137 #define OP_SH_COP1CMP 4
138 #define OP_SH_FORMAT 21 /* FP short format field. */
139 #define OP_MASK_FORMAT 0x7
140 #define OP_SH_TRUE 16
141 #define OP_MASK_TRUE 0x1
142 #define OP_SH_GE 17
143 #define OP_MASK_GE 0x01
144 #define OP_SH_UNSIGNED 16
145 #define OP_MASK_UNSIGNED 0x1
146 #define OP_SH_HINT 16
147 #define OP_MASK_HINT 0x1f
148 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
149 #define OP_MASK_MMI 0x3f
150 #define OP_SH_MMISUB 6
151 #define OP_MASK_MMISUB 0x1f
152 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
153 #define OP_SH_PERFREG 1
154 #define OP_SH_SEL 0 /* Coprocessor select field. */
155 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
156 #define OP_SH_CODE19 6 /* 19 bit wait code. */
157 #define OP_MASK_CODE19 0x7ffff
158 #define OP_SH_ALN 21
159 #define OP_MASK_ALN 0x7
160 #define OP_SH_VSEL 21
161 #define OP_MASK_VSEL 0x1f
162 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
163 but 0x8-0xf don't select bytes. */
164 #define OP_SH_VECBYTE 22
165 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
166 #define OP_SH_VECALIGN 21
167 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
168 #define OP_SH_INSMSB 11
169 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
170 #define OP_SH_EXTMSBD 11
171
172 #define OP_OP_COP0 0x10
173 #define OP_OP_COP1 0x11
174 #define OP_OP_COP2 0x12
175 #define OP_OP_COP3 0x13
176 #define OP_OP_LWC1 0x31
177 #define OP_OP_LWC2 0x32
178 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
179 #define OP_OP_LDC1 0x35
180 #define OP_OP_LDC2 0x36
181 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
182 #define OP_OP_SWC1 0x39
183 #define OP_OP_SWC2 0x3a
184 #define OP_OP_SWC3 0x3b
185 #define OP_OP_SDC1 0x3d
186 #define OP_OP_SDC2 0x3e
187 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
188
189 /* MIPS DSP ASE */
190 #define OP_SH_DSPACC 11
191 #define OP_MASK_DSPACC 0x3
192 #define OP_SH_DSPACC_S 21
193 #define OP_MASK_DSPACC_S 0x3
194 #define OP_SH_DSPSFT 20
195 #define OP_MASK_DSPSFT 0x3f
196 #define OP_SH_DSPSFT_7 19
197 #define OP_MASK_DSPSFT_7 0x7f
198 #define OP_SH_SA3 21
199 #define OP_MASK_SA3 0x7
200 #define OP_SH_SA4 21
201 #define OP_MASK_SA4 0xf
202 #define OP_SH_IMM8 16
203 #define OP_MASK_IMM8 0xff
204 #define OP_SH_IMM10 16
205 #define OP_MASK_IMM10 0x3ff
206 #define OP_SH_WRDSP 11
207 #define OP_MASK_WRDSP 0x3f
208 #define OP_SH_RDDSP 16
209 #define OP_MASK_RDDSP 0x3f
210 #define OP_SH_BP 11
211 #define OP_MASK_BP 0x3
212
213 /* MIPS MT ASE */
214 #define OP_SH_MT_U 5
215 #define OP_MASK_MT_U 0x1
216 #define OP_SH_MT_H 4
217 #define OP_MASK_MT_H 0x1
218 #define OP_SH_MTACC_T 18
219 #define OP_MASK_MTACC_T 0x3
220 #define OP_SH_MTACC_D 13
221 #define OP_MASK_MTACC_D 0x3
222
223 #define OP_OP_COP0 0x10
224 #define OP_OP_COP1 0x11
225 #define OP_OP_COP2 0x12
226 #define OP_OP_COP3 0x13
227 #define OP_OP_LWC1 0x31
228 #define OP_OP_LWC2 0x32
229 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
230 #define OP_OP_LDC1 0x35
231 #define OP_OP_LDC2 0x36
232 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
233 #define OP_OP_SWC1 0x39
234 #define OP_OP_SWC2 0x3a
235 #define OP_OP_SWC3 0x3b
236 #define OP_OP_SDC1 0x3d
237 #define OP_OP_SDC2 0x3e
238 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
239
240 /* Values in the 'VSEL' field. */
241 #define MDMX_FMTSEL_IMM_QH 0x1d
242 #define MDMX_FMTSEL_IMM_OB 0x1e
243 #define MDMX_FMTSEL_VEC_QH 0x15
244 #define MDMX_FMTSEL_VEC_OB 0x16
245
246 /* UDI */
247 #define OP_SH_UDI1 6
248 #define OP_MASK_UDI1 0x1f
249 #define OP_SH_UDI2 6
250 #define OP_MASK_UDI2 0x3ff
251 #define OP_SH_UDI3 6
252 #define OP_MASK_UDI3 0x7fff
253 #define OP_SH_UDI4 6
254 #define OP_MASK_UDI4 0xfffff
255 /* This structure holds information for a particular instruction. */
256
257 struct mips_opcode
258 {
259 /* The name of the instruction. */
260 const char *name;
261 /* A string describing the arguments for this instruction. */
262 const char *args;
263 /* The basic opcode for the instruction. When assembling, this
264 opcode is modified by the arguments to produce the actual opcode
265 that is used. If pinfo is INSN_MACRO, then this is 0. */
266 unsigned long match;
267 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
268 relevant portions of the opcode when disassembling. If the
269 actual opcode anded with the match field equals the opcode field,
270 then we have found the correct instruction. If pinfo is
271 INSN_MACRO, then this field is the macro identifier. */
272 unsigned long mask;
273 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
274 of bits describing the instruction, notably any relevant hazard
275 information. */
276 unsigned long pinfo;
277 /* A collection of additional bits describing the instruction. */
278 unsigned long pinfo2;
279 /* A collection of bits describing the instruction sets of which this
280 instruction or macro is a member. */
281 unsigned long membership;
282 };
283
284 /* These are the characters which may appear in the args field of an
285 instruction. They appear in the order in which the fields appear
286 when the instruction is used. Commas and parentheses in the args
287 string are ignored when assembling, and written into the output
288 when disassembling.
289
290 Each of these characters corresponds to a mask field defined above.
291
292 "<" 5 bit shift amount (OP_*_SHAMT)
293 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
294 "a" 26 bit target address (OP_*_TARGET)
295 "b" 5 bit base register (OP_*_RS)
296 "c" 10 bit breakpoint code (OP_*_CODE)
297 "d" 5 bit destination register specifier (OP_*_RD)
298 "h" 5 bit prefx hint (OP_*_PREFX)
299 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
300 "j" 16 bit signed immediate (OP_*_DELTA)
301 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
302 Also used for immediate operands in vr5400 vector insns.
303 "o" 16 bit signed offset (OP_*_DELTA)
304 "p" 16 bit PC relative branch target address (OP_*_DELTA)
305 "q" 10 bit extra breakpoint code (OP_*_CODE2)
306 "r" 5 bit same register used as both source and target (OP_*_RS)
307 "s" 5 bit source register specifier (OP_*_RS)
308 "t" 5 bit target register (OP_*_RT)
309 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
310 "v" 5 bit same register used as both source and destination (OP_*_RS)
311 "w" 5 bit same register used as both target and destination (OP_*_RT)
312 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
313 (used by clo and clz)
314 "C" 25 bit coprocessor function code (OP_*_COPZ)
315 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
316 "J" 19 bit wait function code (OP_*_CODE19)
317 "x" accept and ignore register name
318 "z" must be zero register
319 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
320 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
321 LSB (OP_*_SHAMT).
322 Enforces: 0 <= pos < 32.
323 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
324 Requires that "+A" or "+E" occur first to set position.
325 Enforces: 0 < (pos+size) <= 32.
326 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
327 Requires that "+A" or "+E" occur first to set position.
328 Enforces: 0 < (pos+size) <= 32.
329 (Also used by "dext" w/ different limits, but limits for
330 that are checked by the M_DEXT macro.)
331 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
332 Enforces: 32 <= pos < 64.
333 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
334 Requires that "+A" or "+E" occur first to set position.
335 Enforces: 32 < (pos+size) <= 64.
336 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
337 Requires that "+A" or "+E" occur first to set position.
338 Enforces: 32 < (pos+size) <= 64.
339 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
340 Requires that "+A" or "+E" occur first to set position.
341 Enforces: 32 < (pos+size) <= 64.
342
343 Floating point instructions:
344 "D" 5 bit destination register (OP_*_FD)
345 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
346 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
347 "S" 5 bit fs source 1 register (OP_*_FS)
348 "T" 5 bit ft source 2 register (OP_*_FT)
349 "R" 5 bit fr source 3 register (OP_*_FR)
350 "V" 5 bit same register used as floating source and destination (OP_*_FS)
351 "W" 5 bit same register used as floating target and destination (OP_*_FT)
352
353 Coprocessor instructions:
354 "E" 5 bit target register (OP_*_RT)
355 "G" 5 bit destination register (OP_*_RD)
356 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
357 "P" 5 bit performance-monitor register (OP_*_PERFREG)
358 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
359 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
360 see also "k" above
361 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
362 for pretty-printing in disassembly only.
363
364 Macro instructions:
365 "A" General 32 bit expression
366 "I" 32 bit immediate (value placed in imm_expr).
367 "+I" 32 bit immediate (value placed in imm2_expr).
368 "F" 64 bit floating point constant in .rdata
369 "L" 64 bit floating point constant in .lit8
370 "f" 32 bit floating point constant
371 "l" 32 bit floating point constant in .lit4
372
373 MDMX instruction operands (note that while these use the FP register
374 fields, they accept both $fN and $vN names for the registers):
375 "O" MDMX alignment offset (OP_*_ALN)
376 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
377 "X" MDMX destination register (OP_*_FD)
378 "Y" MDMX source register (OP_*_FS)
379 "Z" MDMX source register (OP_*_FT)
380
381 DSP ASE usage:
382 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
383 "3" 3 bit unsigned immediate (OP_*_SA3)
384 "4" 4 bit unsigned immediate (OP_*_SA4)
385 "5" 8 bit unsigned immediate (OP_*_IMM8)
386 "6" 5 bit unsigned immediate (OP_*_RS)
387 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
388 "8" 6 bit unsigned immediate (OP_*_WRDSP)
389 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
390 "0" 6 bit signed immediate (OP_*_DSPSFT)
391 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
392 "'" 6 bit unsigned immediate (OP_*_RDDSP)
393 "@" 10 bit signed immediate (OP_*_IMM10)
394
395 MT ASE usage:
396 "!" 1 bit usermode flag (OP_*_MT_U)
397 "$" 1 bit load high flag (OP_*_MT_H)
398 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
399 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
400 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
401 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
402 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
403
404 UDI immediates:
405 "+1" UDI immediate bits 6-10
406 "+2" UDI immediate bits 6-15
407 "+3" UDI immediate bits 6-20
408 "+4" UDI immediate bits 6-25
409
410 R6 immediates/displacements :
411 (adding suffix to 'o' to avoid adding new characters)
412 "+o" 9 bits immediate/displacement (shift = 7)
413 "+o1" 18 bits immediate/displacement (shift = 0)
414 "+o2" 19 bits immediate/displacement (shift = 0)
415
416 Other:
417 "()" parens surrounding optional value
418 "," separates operands
419 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
420 "+" Start of extension sequence.
421
422 Characters used so far, for quick reference when adding more:
423 "234567890"
424 "%[]<>(),+:'@!$*&"
425 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
426 "abcdefghijklopqrstuvwxz"
427
428 Extension character sequences used so far ("+" followed by the
429 following), for quick reference when adding more:
430 "1234"
431 "ABCDEFGHIT"
432 "t"
433 */
434
435 /* These are the bits which may be set in the pinfo field of an
436 instructions, if it is not equal to INSN_MACRO. */
437
438 /* Modifies the general purpose register in OP_*_RD. */
439 #define INSN_WRITE_GPR_D 0x00000001
440 /* Modifies the general purpose register in OP_*_RT. */
441 #define INSN_WRITE_GPR_T 0x00000002
442 /* Modifies general purpose register 31. */
443 #define INSN_WRITE_GPR_31 0x00000004
444 /* Modifies the floating point register in OP_*_FD. */
445 #define INSN_WRITE_FPR_D 0x00000008
446 /* Modifies the floating point register in OP_*_FS. */
447 #define INSN_WRITE_FPR_S 0x00000010
448 /* Modifies the floating point register in OP_*_FT. */
449 #define INSN_WRITE_FPR_T 0x00000020
450 /* Reads the general purpose register in OP_*_RS. */
451 #define INSN_READ_GPR_S 0x00000040
452 /* Reads the general purpose register in OP_*_RT. */
453 #define INSN_READ_GPR_T 0x00000080
454 /* Reads the floating point register in OP_*_FS. */
455 #define INSN_READ_FPR_S 0x00000100
456 /* Reads the floating point register in OP_*_FT. */
457 #define INSN_READ_FPR_T 0x00000200
458 /* Reads the floating point register in OP_*_FR. */
459 #define INSN_READ_FPR_R 0x00000400
460 /* Modifies coprocessor condition code. */
461 #define INSN_WRITE_COND_CODE 0x00000800
462 /* Reads coprocessor condition code. */
463 #define INSN_READ_COND_CODE 0x00001000
464 /* TLB operation. */
465 #define INSN_TLB 0x00002000
466 /* Reads coprocessor register other than floating point register. */
467 #define INSN_COP 0x00004000
468 /* Instruction loads value from memory, requiring delay. */
469 #define INSN_LOAD_MEMORY_DELAY 0x00008000
470 /* Instruction loads value from coprocessor, requiring delay. */
471 #define INSN_LOAD_COPROC_DELAY 0x00010000
472 /* Instruction has unconditional branch delay slot. */
473 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
474 /* Instruction has conditional branch delay slot. */
475 #define INSN_COND_BRANCH_DELAY 0x00040000
476 /* Conditional branch likely: if branch not taken, insn nullified. */
477 #define INSN_COND_BRANCH_LIKELY 0x00080000
478 /* Moves to coprocessor register, requiring delay. */
479 #define INSN_COPROC_MOVE_DELAY 0x00100000
480 /* Loads coprocessor register from memory, requiring delay. */
481 #define INSN_COPROC_MEMORY_DELAY 0x00200000
482 /* Reads the HI register. */
483 #define INSN_READ_HI 0x00400000
484 /* Reads the LO register. */
485 #define INSN_READ_LO 0x00800000
486 /* Modifies the HI register. */
487 #define INSN_WRITE_HI 0x01000000
488 /* Modifies the LO register. */
489 #define INSN_WRITE_LO 0x02000000
490 /* Takes a trap (easier to keep out of delay slot). */
491 #define INSN_TRAP 0x04000000
492 /* Instruction stores value into memory. */
493 #define INSN_STORE_MEMORY 0x08000000
494 /* Instruction uses single precision floating point. */
495 #define FP_S 0x10000000
496 /* Instruction uses double precision floating point. */
497 #define FP_D 0x20000000
498 /* Instruction is part of the tx39's integer multiply family. */
499 #define INSN_MULT 0x40000000
500 /* Instruction synchronize shared memory. */
501 #define INSN_SYNC 0x80000000
502
503 /* These are the bits which may be set in the pinfo2 field of an
504 instruction. */
505
506 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
507 #define INSN2_ALIAS 0x00000001
508 /* Instruction reads MDMX accumulator. */
509 #define INSN2_READ_MDMX_ACC 0x00000002
510 /* Instruction writes MDMX accumulator. */
511 #define INSN2_WRITE_MDMX_ACC 0x00000004
512
513 /* Instruction is actually a macro. It should be ignored by the
514 disassembler, and requires special treatment by the assembler. */
515 #define INSN_MACRO 0xffffffff
516
517 /* Masks used to mark instructions to indicate which MIPS ISA level
518 they were introduced in. ISAs, as defined below, are logical
519 ORs of these bits, indicating that they support the instructions
520 defined at the given level. */
521
522 #define INSN_ISA_MASK 0x00000fff
523 #define INSN_ISA1 0x00000001
524 #define INSN_ISA2 0x00000002
525 #define INSN_ISA3 0x00000004
526 #define INSN_ISA4 0x00000008
527 #define INSN_ISA5 0x00000010
528 #define INSN_ISA32 0x00000020
529 #define INSN_ISA64 0x00000040
530 #define INSN_ISA32R2 0x00000080
531 #define INSN_ISA64R2 0x00000100
532 #define INSN_ISA32R6 0x00000200
533 #define INSN_ISA64R6 0x00000400
534
535 /* Masks used for MIPS-defined ASEs. */
536 #define INSN_ASE_MASK 0x0000f000
537
538 /* DSP ASE */
539 #define INSN_DSP 0x00001000
540 #define INSN_DSP64 0x00002000
541 /* MIPS 16 ASE */
542 #define INSN_MIPS16 0x00004000
543 /* MIPS-3D ASE */
544 #define INSN_MIPS3D 0x00008000
545
546 /* Chip specific instructions. These are bitmasks. */
547
548 /* MIPS R4650 instruction. */
549 #define INSN_4650 0x00010000
550 /* LSI R4010 instruction. */
551 #define INSN_4010 0x00020000
552 /* NEC VR4100 instruction. */
553 #define INSN_4100 0x00040000
554 /* Toshiba R3900 instruction. */
555 #define INSN_3900 0x00080000
556 /* MIPS R10000 instruction. */
557 #define INSN_10000 0x00100000
558 /* Broadcom SB-1 instruction. */
559 #define INSN_SB1 0x00200000
560 /* NEC VR4111/VR4181 instruction. */
561 #define INSN_4111 0x00400000
562 /* NEC VR4120 instruction. */
563 #define INSN_4120 0x00800000
564 /* NEC VR5400 instruction. */
565 #define INSN_5400 0x01000000
566 /* NEC VR5500 instruction. */
567 #define INSN_5500 0x02000000
568
569 /* MDMX ASE */
570 #define INSN_MDMX 0x04000000
571 /* MT ASE */
572 #define INSN_MT 0x08000000
573 /* SmartMIPS ASE */
574 #define INSN_SMARTMIPS 0x10000000
575 /* DSP R2 ASE */
576 #define INSN_DSPR2 0x20000000
577
578 /* ST Microelectronics Loongson 2E. */
579 #define INSN_LOONGSON_2E 0x40000000
580 /* ST Microelectronics Loongson 2F. */
581 #define INSN_LOONGSON_2F 0x80000000
582
583 /* MIPS ISA defines, use instead of hardcoding ISA level. */
584
585 #define ISA_UNKNOWN 0 /* Gas internal use. */
586 #define ISA_MIPS1 (INSN_ISA1)
587 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
588 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
589 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
590 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
591
592 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
593 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
594
595 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
596 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
597
598 #define ISA_MIPS32R6 (ISA_MIPS32R2 | INSN_ISA32R6)
599 #define ISA_MIPS64R6 (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
600
601 /* CPU defines, use instead of hardcoding processor number. Keep this
602 in sync with bfd/archures.c in order for machine selection to work. */
603 #define CPU_UNKNOWN 0 /* Gas internal use. */
604 #define CPU_R3000 3000
605 #define CPU_R3900 3900
606 #define CPU_R4000 4000
607 #define CPU_R4010 4010
608 #define CPU_VR4100 4100
609 #define CPU_R4111 4111
610 #define CPU_VR4120 4120
611 #define CPU_R4300 4300
612 #define CPU_R4400 4400
613 #define CPU_R4600 4600
614 #define CPU_R4650 4650
615 #define CPU_R5000 5000
616 #define CPU_VR5400 5400
617 #define CPU_VR5500 5500
618 #define CPU_R6000 6000
619 #define CPU_RM7000 7000
620 #define CPU_R8000 8000
621 #define CPU_R10000 10000
622 #define CPU_R12000 12000
623 #define CPU_MIPS16 16
624 #define CPU_MIPS32 32
625 #define CPU_MIPS32R2 33
626 #define CPU_MIPS5 5
627 #define CPU_MIPS64 64
628 #define CPU_MIPS64R2 65
629 #define CPU_SB1 12310201 /* octal 'SB', 01. */
630
631 /* Test for membership in an ISA including chip specific ISAs. INSN
632 is pointer to an element of the opcode table; ISA is the specified
633 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
634 test, or zero if no CPU specific ISA test is desired. */
635
636 #if 0
637 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
638 (((insn)->membership & isa) != 0 \
639 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
640 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
641 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
642 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
643 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
644 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
645 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
646 && ((insn)->membership & INSN_10000) != 0) \
647 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
648 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
649 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
650 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
651 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
652 || 0) /* Please keep this term for easier source merging. */
653 #else
654 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
655 (1 != 0)
656 #endif
657
658 /* This is a list of macro expanded instructions.
659
660 _I appended means immediate
661 _A appended means address
662 _AB appended means address with base register
663 _D appended means 64 bit floating point constant
664 _S appended means 32 bit floating point constant. */
665
666 enum
667 {
668 M_ABS,
669 M_ADD_I,
670 M_ADDU_I,
671 M_AND_I,
672 M_BALIGN,
673 M_BEQ,
674 M_BEQ_I,
675 M_BEQL_I,
676 M_BGE,
677 M_BGEL,
678 M_BGE_I,
679 M_BGEL_I,
680 M_BGEU,
681 M_BGEUL,
682 M_BGEU_I,
683 M_BGEUL_I,
684 M_BGT,
685 M_BGTL,
686 M_BGT_I,
687 M_BGTL_I,
688 M_BGTU,
689 M_BGTUL,
690 M_BGTU_I,
691 M_BGTUL_I,
692 M_BLE,
693 M_BLEL,
694 M_BLE_I,
695 M_BLEL_I,
696 M_BLEU,
697 M_BLEUL,
698 M_BLEU_I,
699 M_BLEUL_I,
700 M_BLT,
701 M_BLTL,
702 M_BLT_I,
703 M_BLTL_I,
704 M_BLTU,
705 M_BLTUL,
706 M_BLTU_I,
707 M_BLTUL_I,
708 M_BNE,
709 M_BNE_I,
710 M_BNEL_I,
711 M_CACHE_AB,
712 M_DABS,
713 M_DADD_I,
714 M_DADDU_I,
715 M_DDIV_3,
716 M_DDIV_3I,
717 M_DDIVU_3,
718 M_DDIVU_3I,
719 M_DEXT,
720 M_DINS,
721 M_DIV_3,
722 M_DIV_3I,
723 M_DIVU_3,
724 M_DIVU_3I,
725 M_DLA_AB,
726 M_DLCA_AB,
727 M_DLI,
728 M_DMUL,
729 M_DMUL_I,
730 M_DMULO,
731 M_DMULO_I,
732 M_DMULOU,
733 M_DMULOU_I,
734 M_DREM_3,
735 M_DREM_3I,
736 M_DREMU_3,
737 M_DREMU_3I,
738 M_DSUB_I,
739 M_DSUBU_I,
740 M_DSUBU_I_2,
741 M_J_A,
742 M_JAL_1,
743 M_JAL_2,
744 M_JAL_A,
745 M_L_DOB,
746 M_L_DAB,
747 M_LA_AB,
748 M_LB_A,
749 M_LB_AB,
750 M_LBU_A,
751 M_LBU_AB,
752 M_LCA_AB,
753 M_LD_A,
754 M_LD_OB,
755 M_LD_AB,
756 M_LDC1_AB,
757 M_LDC2_AB,
758 M_LDC3_AB,
759 M_LDL_AB,
760 M_LDR_AB,
761 M_LH_A,
762 M_LH_AB,
763 M_LHU_A,
764 M_LHU_AB,
765 M_LI,
766 M_LI_D,
767 M_LI_DD,
768 M_LI_S,
769 M_LI_SS,
770 M_LL_AB,
771 M_LLD_AB,
772 M_LS_A,
773 M_LW_A,
774 M_LW_AB,
775 M_LWC0_A,
776 M_LWC0_AB,
777 M_LWC1_A,
778 M_LWC1_AB,
779 M_LWC2_A,
780 M_LWC2_AB,
781 M_LWC3_A,
782 M_LWC3_AB,
783 M_LWL_A,
784 M_LWL_AB,
785 M_LWR_A,
786 M_LWR_AB,
787 M_LWU_AB,
788 M_MOVE,
789 M_MUL,
790 M_MUL_I,
791 M_MULO,
792 M_MULO_I,
793 M_MULOU,
794 M_MULOU_I,
795 M_NOR_I,
796 M_OR_I,
797 M_REM_3,
798 M_REM_3I,
799 M_REMU_3,
800 M_REMU_3I,
801 M_DROL,
802 M_ROL,
803 M_DROL_I,
804 M_ROL_I,
805 M_DROR,
806 M_ROR,
807 M_DROR_I,
808 M_ROR_I,
809 M_S_DA,
810 M_S_DOB,
811 M_S_DAB,
812 M_S_S,
813 M_SC_AB,
814 M_SCD_AB,
815 M_SD_A,
816 M_SD_OB,
817 M_SD_AB,
818 M_SDC1_AB,
819 M_SDC2_AB,
820 M_SDC3_AB,
821 M_SDL_AB,
822 M_SDR_AB,
823 M_SEQ,
824 M_SEQ_I,
825 M_SGE,
826 M_SGE_I,
827 M_SGEU,
828 M_SGEU_I,
829 M_SGT,
830 M_SGT_I,
831 M_SGTU,
832 M_SGTU_I,
833 M_SLE,
834 M_SLE_I,
835 M_SLEU,
836 M_SLEU_I,
837 M_SLT_I,
838 M_SLTU_I,
839 M_SNE,
840 M_SNE_I,
841 M_SB_A,
842 M_SB_AB,
843 M_SH_A,
844 M_SH_AB,
845 M_SW_A,
846 M_SW_AB,
847 M_SWC0_A,
848 M_SWC0_AB,
849 M_SWC1_A,
850 M_SWC1_AB,
851 M_SWC2_A,
852 M_SWC2_AB,
853 M_SWC3_A,
854 M_SWC3_AB,
855 M_SWL_A,
856 M_SWL_AB,
857 M_SWR_A,
858 M_SWR_AB,
859 M_SUB_I,
860 M_SUBU_I,
861 M_SUBU_I_2,
862 M_TEQ_I,
863 M_TGE_I,
864 M_TGEU_I,
865 M_TLT_I,
866 M_TLTU_I,
867 M_TNE_I,
868 M_TRUNCWD,
869 M_TRUNCWS,
870 M_ULD,
871 M_ULD_A,
872 M_ULH,
873 M_ULH_A,
874 M_ULHU,
875 M_ULHU_A,
876 M_ULW,
877 M_ULW_A,
878 M_USH,
879 M_USH_A,
880 M_USW,
881 M_USW_A,
882 M_USD,
883 M_USD_A,
884 M_XOR_I,
885 M_COP0,
886 M_COP1,
887 M_COP2,
888 M_COP3,
889 M_NUM_MACROS
890 };
891
892
893 /* The order of overloaded instructions matters. Label arguments and
894 register arguments look the same. Instructions that can have either
895 for arguments must apear in the correct order in this table for the
896 assembler to pick the right one. In other words, entries with
897 immediate operands must apear after the same instruction with
898 registers.
899
900 Many instructions are short hand for other instructions (i.e., The
901 jal <register> instruction is short for jalr <register>). */
902
903 extern const struct mips_opcode mips_builtin_opcodes[];
904 extern const int bfd_mips_num_builtin_opcodes;
905 extern struct mips_opcode *mips_opcodes;
906 extern int bfd_mips_num_opcodes;
907 #define NUMOPCODES bfd_mips_num_opcodes
908
909 \f
910 /* The rest of this file adds definitions for the mips16 TinyRISC
911 processor. */
912
913 /* These are the bitmasks and shift counts used for the different
914 fields in the instruction formats. Other than OP, no masks are
915 provided for the fixed portions of an instruction, since they are
916 not needed.
917
918 The I format uses IMM11.
919
920 The RI format uses RX and IMM8.
921
922 The RR format uses RX, and RY.
923
924 The RRI format uses RX, RY, and IMM5.
925
926 The RRR format uses RX, RY, and RZ.
927
928 The RRI_A format uses RX, RY, and IMM4.
929
930 The SHIFT format uses RX, RY, and SHAMT.
931
932 The I8 format uses IMM8.
933
934 The I8_MOVR32 format uses RY and REGR32.
935
936 The IR_MOV32R format uses REG32R and MOV32Z.
937
938 The I64 format uses IMM8.
939
940 The RI64 format uses RY and IMM5.
941 */
942
943 #define MIPS16OP_MASK_OP 0x1f
944 #define MIPS16OP_SH_OP 11
945 #define MIPS16OP_MASK_IMM11 0x7ff
946 #define MIPS16OP_SH_IMM11 0
947 #define MIPS16OP_MASK_RX 0x7
948 #define MIPS16OP_SH_RX 8
949 #define MIPS16OP_MASK_IMM8 0xff
950 #define MIPS16OP_SH_IMM8 0
951 #define MIPS16OP_MASK_RY 0x7
952 #define MIPS16OP_SH_RY 5
953 #define MIPS16OP_MASK_IMM5 0x1f
954 #define MIPS16OP_SH_IMM5 0
955 #define MIPS16OP_MASK_RZ 0x7
956 #define MIPS16OP_SH_RZ 2
957 #define MIPS16OP_MASK_IMM4 0xf
958 #define MIPS16OP_SH_IMM4 0
959 #define MIPS16OP_MASK_REGR32 0x1f
960 #define MIPS16OP_SH_REGR32 0
961 #define MIPS16OP_MASK_REG32R 0x1f
962 #define MIPS16OP_SH_REG32R 3
963 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
964 #define MIPS16OP_MASK_MOVE32Z 0x7
965 #define MIPS16OP_SH_MOVE32Z 0
966 #define MIPS16OP_MASK_IMM6 0x3f
967 #define MIPS16OP_SH_IMM6 5
968
969 /* These are the characters which may appears in the args field of an
970 instruction. They appear in the order in which the fields appear
971 when the instruction is used. Commas and parentheses in the args
972 string are ignored when assembling, and written into the output
973 when disassembling.
974
975 "y" 3 bit register (MIPS16OP_*_RY)
976 "x" 3 bit register (MIPS16OP_*_RX)
977 "z" 3 bit register (MIPS16OP_*_RZ)
978 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
979 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
980 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
981 "0" zero register ($0)
982 "S" stack pointer ($sp or $29)
983 "P" program counter
984 "R" return address register ($ra or $31)
985 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
986 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
987 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
988 "a" 26 bit jump address
989 "e" 11 bit extension value
990 "l" register list for entry instruction
991 "L" register list for exit instruction
992
993 The remaining codes may be extended. Except as otherwise noted,
994 the full extended operand is a 16 bit signed value.
995 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
996 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
997 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
998 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
999 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1000 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1001 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1002 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1003 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1004 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1005 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1006 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1007 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1008 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1009 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1010 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1011 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1012 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1013 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1014 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1015 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1016 */
1017
1018 /* Save/restore encoding for the args field when all 4 registers are
1019 either saved as arguments or saved/restored as statics. */
1020 #define MIPS16_ALL_ARGS 0xe
1021 #define MIPS16_ALL_STATICS 0xb
1022
1023 /* For the mips16, we use the same opcode table format and a few of
1024 the same flags. However, most of the flags are different. */
1025
1026 /* Modifies the register in MIPS16OP_*_RX. */
1027 #define MIPS16_INSN_WRITE_X 0x00000001
1028 /* Modifies the register in MIPS16OP_*_RY. */
1029 #define MIPS16_INSN_WRITE_Y 0x00000002
1030 /* Modifies the register in MIPS16OP_*_RZ. */
1031 #define MIPS16_INSN_WRITE_Z 0x00000004
1032 /* Modifies the T ($24) register. */
1033 #define MIPS16_INSN_WRITE_T 0x00000008
1034 /* Modifies the SP ($29) register. */
1035 #define MIPS16_INSN_WRITE_SP 0x00000010
1036 /* Modifies the RA ($31) register. */
1037 #define MIPS16_INSN_WRITE_31 0x00000020
1038 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1039 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1040 /* Reads the register in MIPS16OP_*_RX. */
1041 #define MIPS16_INSN_READ_X 0x00000080
1042 /* Reads the register in MIPS16OP_*_RY. */
1043 #define MIPS16_INSN_READ_Y 0x00000100
1044 /* Reads the register in MIPS16OP_*_MOVE32Z. */
1045 #define MIPS16_INSN_READ_Z 0x00000200
1046 /* Reads the T ($24) register. */
1047 #define MIPS16_INSN_READ_T 0x00000400
1048 /* Reads the SP ($29) register. */
1049 #define MIPS16_INSN_READ_SP 0x00000800
1050 /* Reads the RA ($31) register. */
1051 #define MIPS16_INSN_READ_31 0x00001000
1052 /* Reads the program counter. */
1053 #define MIPS16_INSN_READ_PC 0x00002000
1054 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
1055 #define MIPS16_INSN_READ_GPR_X 0x00004000
1056 /* Is a branch insn. */
1057 #define MIPS16_INSN_BRANCH 0x00010000
1058
1059 /* The following flags have the same value for the mips16 opcode
1060 table:
1061 INSN_UNCOND_BRANCH_DELAY
1062 INSN_COND_BRANCH_DELAY
1063 INSN_COND_BRANCH_LIKELY (never used)
1064 INSN_READ_HI
1065 INSN_READ_LO
1066 INSN_WRITE_HI
1067 INSN_WRITE_LO
1068 INSN_TRAP
1069 INSN_ISA3
1070 */
1071
1072 extern const struct mips_opcode mips16_opcodes[];
1073 extern const int bfd_mips16_num_opcodes;
1074
1075 /* Short hand so the lines aren't too long. */
1076
1077 #define LDD INSN_LOAD_MEMORY_DELAY
1078 #define LCD INSN_LOAD_COPROC_DELAY
1079 #define UBD INSN_UNCOND_BRANCH_DELAY
1080 #define CBD INSN_COND_BRANCH_DELAY
1081 #define COD INSN_COPROC_MOVE_DELAY
1082 #define CLD INSN_COPROC_MEMORY_DELAY
1083 #define CBL INSN_COND_BRANCH_LIKELY
1084 #define TRAP INSN_TRAP
1085 #define SM INSN_STORE_MEMORY
1086
1087 #define WR_d INSN_WRITE_GPR_D
1088 #define WR_t INSN_WRITE_GPR_T
1089 #define WR_31 INSN_WRITE_GPR_31
1090 #define WR_D INSN_WRITE_FPR_D
1091 #define WR_T INSN_WRITE_FPR_T
1092 #define WR_S INSN_WRITE_FPR_S
1093 #define RD_s INSN_READ_GPR_S
1094 #define RD_b INSN_READ_GPR_S
1095 #define RD_t INSN_READ_GPR_T
1096 #define RD_S INSN_READ_FPR_S
1097 #define RD_T INSN_READ_FPR_T
1098 #define RD_R INSN_READ_FPR_R
1099 #define WR_CC INSN_WRITE_COND_CODE
1100 #define RD_CC INSN_READ_COND_CODE
1101 #define RD_C0 INSN_COP
1102 #define RD_C1 INSN_COP
1103 #define RD_C2 INSN_COP
1104 #define RD_C3 INSN_COP
1105 #define WR_C0 INSN_COP
1106 #define WR_C1 INSN_COP
1107 #define WR_C2 INSN_COP
1108 #define WR_C3 INSN_COP
1109
1110 #define WR_HI INSN_WRITE_HI
1111 #define RD_HI INSN_READ_HI
1112 #define MOD_HI WR_HI|RD_HI
1113
1114 #define WR_LO INSN_WRITE_LO
1115 #define RD_LO INSN_READ_LO
1116 #define MOD_LO WR_LO|RD_LO
1117
1118 #define WR_HILO WR_HI|WR_LO
1119 #define RD_HILO RD_HI|RD_LO
1120 #define MOD_HILO WR_HILO|RD_HILO
1121
1122 #define IS_M INSN_MULT
1123
1124 #define WR_MACC INSN2_WRITE_MDMX_ACC
1125 #define RD_MACC INSN2_READ_MDMX_ACC
1126
1127 #define I1 INSN_ISA1
1128 #define I2 INSN_ISA2
1129 #define I3 INSN_ISA3
1130 #define I4 INSN_ISA4
1131 #define I5 INSN_ISA5
1132 #define I32 INSN_ISA32
1133 #define I64 INSN_ISA64
1134 #define I33 INSN_ISA32R2
1135 #define I65 INSN_ISA64R2
1136 #define I32R6 INSN_ISA32R6
1137 #define I64R6 INSN_ISA64R6
1138
1139 /* MIPS64 MIPS-3D ASE support. */
1140 #define I16 INSN_MIPS16
1141
1142 /* MIPS32 SmartMIPS ASE support. */
1143 #define SMT INSN_SMARTMIPS
1144
1145 /* MIPS64 MIPS-3D ASE support. */
1146 #define M3D INSN_MIPS3D
1147
1148 /* MIPS64 MDMX ASE support. */
1149 #define MX INSN_MDMX
1150
1151 #define IL2E (INSN_LOONGSON_2E)
1152 #define IL2F (INSN_LOONGSON_2F)
1153
1154 #define P3 INSN_4650
1155 #define L1 INSN_4010
1156 #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1157 #define T3 INSN_3900
1158 #define M1 INSN_10000
1159 #define SB1 INSN_SB1
1160 #define N411 INSN_4111
1161 #define N412 INSN_4120
1162 #define N5 (INSN_5400 | INSN_5500)
1163 #define N54 INSN_5400
1164 #define N55 INSN_5500
1165
1166 #define G1 (T3 \
1167 )
1168
1169 #define G2 (T3 \
1170 )
1171
1172 #define G3 (I4 \
1173 )
1174
1175 /* MIPS DSP ASE support.
1176 NOTE:
1177 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
1178 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have
1179 the same structure as $ac0 (HI + LO). For DSP instructions that write or
1180 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1181 (RD_HILO) attributes, such that HILO dependencies are maintained
1182 conservatively.
1183
1184 2. For some mul. instructions that use integer registers as destinations
1185 but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1186
1187 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1188 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
1189 certain fields of the DSP control register. For simplicity, we decide not
1190 to track dependencies of these fields.
1191 However, "bposge32" is a branch instruction that depends on the "pos"
1192 field. In order to make sure that GAS does not reorder DSP instructions
1193 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1194 attribute to those instructions that write the "pos" field. */
1195
1196 #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
1197 #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
1198 #define MOD_a WR_a|RD_a
1199 #define DSP_VOLA INSN_TRAP
1200 #define D32 INSN_DSP
1201 #define D33 INSN_DSPR2
1202 #define D64 INSN_DSP64
1203
1204 /* MIPS MT ASE support. */
1205 #define MT32 INSN_MT
1206
1207 /* The order of overloaded instructions matters. Label arguments and
1208 register arguments look the same. Instructions that can have either
1209 for arguments must apear in the correct order in this table for the
1210 assembler to pick the right one. In other words, entries with
1211 immediate operands must apear after the same instruction with
1212 registers.
1213
1214 Because of the lookup algorithm used, entries with the same opcode
1215 name must be contiguous.
1216
1217 Many instructions are short hand for other instructions (i.e., The
1218 jal <register> instruction is short for jalr <register>). */
1219
1220 const struct mips_opcode mips_builtin_opcodes[] =
1221 {
1222 /* These instructions appear first so that the disassembler will find
1223 them first. The assemblers uses a hash table based on the
1224 instruction name anyhow. */
1225 /* name, args, match, mask, pinfo, membership */
1226 {"lwpc", "s,+o2", 0xec080000, 0xfc180000, WR_d, 0, I32R6},
1227 {"lwupc", "s,+o2", 0xec100000, 0xfc180000, WR_d, 0, I64R6},
1228 {"ldpc", "s,+o1", 0xec180000, 0xfc1c0000, WR_d, 0, I64R6},
1229 {"addiupc", "s,+o2", 0xec000000, 0xfc180000, WR_d, 0, I32R6},
1230 {"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_d, 0, I32R6},
1231 {"aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_d, 0, I32R6},
1232 {"daui", "s,t,u", 0x74000000, 0xfc000000, RD_s|WR_t, 0, I64R6},
1233 {"dahi", "s,u", 0x04060000, 0xfc1f0000, RD_s, 0, I64R6},
1234 {"dati", "s,u", 0x041e0000, 0xfc1f0000, RD_s, 0, I64R6},
1235 {"lsa", "d,s,t", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6},
1236 {"dlsa", "d,s,t", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t, 0, I64R6},
1237 {"clz", "U,s", 0x00000050, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
1238 {"clo", "U,s", 0x00000051, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
1239 {"dclz", "U,s", 0x00000052, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
1240 {"dclo", "U,s", 0x00000053, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
1241 {"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I32R6},
1242 {"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1243 {"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1244 {"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1245 {"muhu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1246 {"div", "d,s,t", 0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1247 {"mod", "d,s,t", 0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1248 {"divu", "d,s,t", 0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1249 {"modu", "d,s,t", 0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1250 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1251 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1252 {"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1253 {"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1254 {"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1255 {"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1256 {"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1257 {"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1258 {"ll", "t,o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
1259 {"sc", "t,o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
1260 {"lld", "t,o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
1261 {"scd", "t,o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
1262 {"pref", "h,o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6},
1263 {"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6},
1264 {"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1265 {"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1266 {"maddf.s", "D,S,T", 0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1267 {"maddf.d", "D,S,T", 0x46200018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1268 {"msubf.s", "D,S,T", 0x46000019, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1269 {"msubf.d", "D,S,T", 0x46200019, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1270 {"max.s", "D,S,T", 0x4600001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1271 {"max.d", "D,S,T", 0x4620001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1272 {"maxa.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1273 {"maxa.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1274 {"rint.s", "D,S", 0x4600001a, 0xffff003f, WR_D|RD_S|FP_S, 0, I32R6},
1275 {"rint.d", "D,S", 0x4620001a, 0xffff003f, WR_D|RD_S|FP_D, 0, I32R6},
1276 {"class.s", "D,S", 0x4600001b, 0xffff003f, WR_D|RD_S|FP_S, 0, I32R6},
1277 {"class.d", "D,S", 0x4620001b, 0xffff003f, WR_D|RD_S|FP_D, 0, I32R6},
1278 {"min.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1279 {"min.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1280 {"mina.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1281 {"mina.d", "D,S,T", 0x4620001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1282 {"sel.s", "D,S,T", 0x46000010, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1283 {"sel.d", "D,S,T", 0x46200010, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1284 {"seleqz.s", "D,S,T", 0x46000014, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1285 {"seleqz.d", "D,S,T", 0x46200014, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1286 {"selnez.s", "D,S,T", 0x46000017, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1287 {"selnez.d", "D,S,T", 0x46200017, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1288 {"align", "d,v,t", 0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6},
1289 {"dalign", "d,v,t", 0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t, 0, I64R6},
1290 {"bitswap", "d,w", 0x7c000020, 0xffe007ff, WR_d|RD_t, 0, I32R6},
1291 {"dbitswap","d,w", 0x7c000024, 0xffe007ff, WR_d|RD_t, 0, I64R6},
1292 {"balc", "+p", 0xe8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
1293 {"bc", "+p", 0xc8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
1294 {"jic", "t,o", 0xd8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
1295 {"beqzc", "s,+p", 0xd8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
1296 {"jialc", "t,o", 0xf8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
1297 {"bnezc", "s,+p", 0xf8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
1298 {"beqzalc", "s,t,p", 0x20000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1299 {"bovc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1300 {"beqc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1301 {"bnezalc", "s,t,p", 0x60000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1302 {"bnvc", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1303 {"bnec", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1304 {"blezc", "s,t,p", 0x58000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1305 {"bgezc", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1306 {"bgec", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1307 {"bgtzc", "s,t,p", 0x5c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1308 {"bltzc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1309 {"bltc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1310 {"blezalc", "s,t,p", 0x18000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1311 {"bgezalc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1312 {"bgeuc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1313 {"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1314 {"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1315 {"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1316 {"nal", "p", 0x04100000, 0xffff0000, WR_31, 0, I32R6},
1317 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, 0, I32R6},
1318 {"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
1319 {"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
1320 {"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0, I32R6},
1321 {"bc2nez", "E,p", 0x49a00000, 0xffe00000, CBD|RD_C2, 0, I32R6},
1322 {"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1323 {"cmp.un.s", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1324 {"cmp.eq.s", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1325 {"cmp.ueq.s", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1326 {"cmp.lt.s", "D,S,T", 0x46800004, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1327 {"cmp.ult.s", "D,S,T", 0x46800005, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1328 {"cmp.le.s", "D,S,T", 0x46800006, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1329 {"cmp.ule.s", "D,S,T", 0x46800007, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1330 {"cmp.saf.s", "D,S,T", 0x46800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1331 {"cmp.sun.s", "D,S,T", 0x46800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1332 {"cmp.seq.s", "D,S,T", 0x4680000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1333 {"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1334 {"cmp.slt.s", "D,S,T", 0x4680000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1335 {"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1336 {"cmp.sle.s", "D,S,T", 0x4680000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1337 {"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1338 {"cmp.or.s", "D,S,T", 0x46800011, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1339 {"cmp.une.s", "D,S,T", 0x46800012, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1340 {"cmp.ne.s", "D,S,T", 0x46800013, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1341 {"cmp.sor.s", "D,S,T", 0x46800019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1342 {"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1343 {"cmp.sne.s", "D,S,T", 0x4680001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1344 {"cmp.af.d", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1345 {"cmp.un.d", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1346 {"cmp.eq.d", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1347 {"cmp.ueq.d", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1348 {"cmp.lt.d", "D,S,T", 0x46a00004, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1349 {"cmp.ult.d", "D,S,T", 0x46a00005, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1350 {"cmp.le.d", "D,S,T", 0x46a00006, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1351 {"cmp.ule.d", "D,S,T", 0x46a00007, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1352 {"cmp.saf.d", "D,S,T", 0x46a00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1353 {"cmp.sun.d", "D,S,T", 0x46a00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1354 {"cmp.seq.d", "D,S,T", 0x46a0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1355 {"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1356 {"cmp.slt.d", "D,S,T", 0x46a0000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1357 {"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1358 {"cmp.sle.d", "D,S,T", 0x46a0000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1359 {"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1360 {"cmp.or.d", "D,S,T", 0x46a00011, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1361 {"cmp.une.d", "D,S,T", 0x46a00012, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1362 {"cmp.ne.d", "D,S,T", 0x46a00013, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1363 {"cmp.sor.d", "D,S,T", 0x46a00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1364 {"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1365 {"cmp.sne.d", "D,S,T", 0x46a0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1366 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
1367 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
1368 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
1369 {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
1370 {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
1371 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
1372 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */
1373 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
1374 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
1375 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
1376 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
1377 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
1378 {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
1379 {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
1380 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
1381
1382 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
1383 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1384 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1385 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1386 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1387 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
1388 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1389 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1390 {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1391 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1392 {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1393 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1394 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1395 {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1396 {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1397 {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1398 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1399 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1400 {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1401 {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1402 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
1403 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1404 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
1405 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1406 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
1407 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1408 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1409 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 },
1410 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX },
1411 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1412 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
1413 {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1414 {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1415 {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1416 {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1417 {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1418 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1419 /* b is at the top of the table. */
1420 /* bal is at the top of the table. */
1421 /* bc0[tf]l? are at the bottom of the table. */
1422 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1423 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1424 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1425 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1426 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1427 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1428 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1429 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1430 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1431 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1432 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1433 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1434 /* bc2* are at the bottom of the table. */
1435 /* bc3* are at the bottom of the table. */
1436 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1437 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1438 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1439 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
1440 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1441 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 },
1442 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
1443 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
1444 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 },
1445 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 },
1446 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
1447 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
1448 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 },
1449 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 },
1450 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1451 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1452 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1453 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1454 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
1455 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
1456 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 },
1457 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 },
1458 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
1459 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
1460 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 },
1461 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 },
1462 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1463 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1464 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
1465 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
1466 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 },
1467 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 },
1468 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
1469 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
1470 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 },
1471 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 },
1472 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1473 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1474 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
1475 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
1476 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 },
1477 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 },
1478 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
1479 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
1480 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 },
1481 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 },
1482 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1483 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1484 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1485 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1486 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1487 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1488 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1489 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
1490 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1491 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
1492 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
1493 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
1494 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
1495 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1496 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1497 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1498 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1499 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1500 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1501 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1502 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1503 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1504 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1505 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1506 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1507 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1508 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1509 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1510 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1511 {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1512 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1513 {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1514 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1515 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1516 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1517 {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1518 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1519 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1520 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1521 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1522 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1523 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1524 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1525 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1526 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1527 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1528 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1529 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1530 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1531 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1532 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1533 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1534 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1535 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1536 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1537 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1538 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1539 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1540 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1541 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1542 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1543 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1544 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1545 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1546 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1547 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1548 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1549 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1550 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1551 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1552 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1553 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1554 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1555 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1556 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1557 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1558 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1559 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1560 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1561 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1562 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1563 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1564 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1565 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1566 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1567 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1568 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1569 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1570 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1571 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1572 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1573 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1574 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1575 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1576 {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1577 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1578 {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1579 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1580 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1581 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1582 {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1583 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1584 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1585 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1586 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1587 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1588 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1589 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1590 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1591 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1592 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1593 {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1594 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1595 {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1596 {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1597 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1598 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1599 {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1600 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1601 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1602 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1603 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1604 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1605 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1606 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1607 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1608 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1609 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1610 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1611 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1612 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1613 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1614 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1615 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1616 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1617 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1618 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1619 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1620 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1621 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1622 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1623 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1624 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1625 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1626 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1627 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1628 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1629 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1630 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1631 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1632 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1633 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1634 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1635 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1636 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1637 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1638 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1639 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1640 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1641 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1642 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1643 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1644 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1645 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1646 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1647 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1648 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1649 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1650 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1651 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1652 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1653 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1654 /* CW4010 instructions which are aliases for the cache instruction. */
1655 {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 },
1656 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
1657 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
1658 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
1659 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
1660 {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3},
1661 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1662 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1663 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1664 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1665 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1666 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1667 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1668 /* cfc2 is at the bottom of the table. */
1669 /* cfc3 is at the bottom of the table. */
1670 {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1671 {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1672 {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1673 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1674 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1675 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
1676 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1677 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1678 /* ctc2 is at the bottom of the table. */
1679 /* ctc3 is at the bottom of the table. */
1680 {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1681 {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1682 {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
1683 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1684 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1685 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1686 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1687 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1688 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1689 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1690 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1691 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1692 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1693 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1694 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1695 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1696 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 },
1697 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1698 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
1699 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1700 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
1701 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1702 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1703 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1704 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
1705 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
1706 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1707 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1708 /* dctr and dctw are used on the r5000. */
1709 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
1710 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
1711 {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 },
1712 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
1713 {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
1714 {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
1715 {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 },
1716 /* For ddiv, see the comments about div. */
1717 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1718 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
1719 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
1720 /* For ddivu, see the comments about div. */
1721 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1722 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
1723 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
1724 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
1725 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1726 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
1727 {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
1728 {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
1729 {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 },
1730 /* The MIPS assembler treats the div opcode with two operands as
1731 though the first operand appeared twice (the first operand is both
1732 a source and a destination). To get the div machine instruction,
1733 you must use an explicit destination of $0. */
1734 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1735 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1736 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
1737 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
1738 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1739 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1740 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
1741 /* For divu, see the comments about div. */
1742 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1743 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1744 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
1745 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
1746 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
1747 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
1748 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
1749 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */
1750 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
1751 {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1752 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1753 {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1754 {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1755 {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1756 {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1757 {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1758 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1759 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
1760 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
1761 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1762 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1763 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
1764 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1765 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
1766 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1767 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1768 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1769 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1770 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1771 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1772 /* dmfc2 is at the bottom of the table. */
1773 /* dmtc2 is at the bottom of the table. */
1774 /* dmfc3 is at the bottom of the table. */
1775 /* dmtc3 is at the bottom of the table. */
1776 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
1777 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
1778 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
1779 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
1780 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
1781 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
1782 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1783 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1784 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
1785 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/
1786 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1787 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 },
1788 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
1789 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1790 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
1791 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
1792 {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
1793 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
1794 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
1795 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
1796 {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
1797 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1798 {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 },
1799 {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1800 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
1801 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
1802 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
1803 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
1804 {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 },
1805 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
1806 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
1807 {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 },
1808 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1809 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 },
1810 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
1811 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */
1812 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 },
1813 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1814 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 },
1815 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
1816 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */
1817 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 },
1818 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1819 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 },
1820 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
1821 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */
1822 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 },
1823 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1824 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
1825 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1826 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
1827 {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
1828 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1829 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
1830 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1831 {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
1832 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1833 {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
1834 {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
1835 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1836 {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
1837 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1838 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1839 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1840 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1841 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
1842 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
1843 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
1844 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1845 the same hazard barrier effect. */
1846 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 },
1847 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
1848 /* SVR4 PIC code requires special handling for j, so it must be a
1849 macro. */
1850 {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
1851 /* This form of j is used by the disassembler and internally by the
1852 assembler, but will never match user input (because the line above
1853 will match first). */
1854 {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 },
1855 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 },
1856 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 },
1857 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1858 with the same hazard barrier effect. */
1859 {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 },
1860 {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 },
1861 /* SVR4 PIC code requires special handling for jal, so it must be a
1862 macro. */
1863 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
1864 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
1865 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
1866 /* This form of jal is used by the disassembler and internally by the
1867 assembler, but will never match user input (because the line above
1868 will match first). */
1869 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
1870 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
1871 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
1872 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1873 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
1874 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1875 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
1876 {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
1877 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
1878 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
1879 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
1880 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1881 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1882 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1883 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1884 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
1885 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
1886 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
1887 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1888 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
1889 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1890 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
1891 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1892 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
1893 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1894 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
1895 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1896 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1897 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
1898 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1899 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
1900 /* li is at the start of the table. */
1901 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 },
1902 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 },
1903 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 },
1904 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 },
1905 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 },
1906 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 },
1907 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1908 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
1909 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
1910 {"aui", "s,t,u", 0x3c000000, 0xfc000000, RD_s|WR_t, 0, I32R6},
1911 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55},
1912 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1913 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
1914 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1915 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
1916 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1917 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1918 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1919 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1920 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
1921 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1922 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1923 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
1924 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1925 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
1926 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1927 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
1928 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1929 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */
1930 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1931 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
1932 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1933 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
1934 {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
1935 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1936 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
1937 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1938 {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT },
1939 {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1940 {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1941 {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1942 {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1943 {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1944 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1945 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1946 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1947 {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1948 {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1949 {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1950 {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1951 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1952 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1953 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1954 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1955 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1956 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1957 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1958 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1959 {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1960 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1961 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
1962 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1963 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1964 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1965 {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1966 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1967 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
1968 {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1969 {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1970 {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1971 {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1972 {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1973 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1974 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1975 {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1976 {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1977 {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1978 {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1979 {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1980 {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1981 {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1982 {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1983 {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
1984 {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
1985 {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1986 {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1987 {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1988 {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1989 {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1990 {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1991 {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1992 {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
1993 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1994 {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1995 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1996 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1997 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1998 {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
1999 {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
2000 /* mfc2 is at the bottom of the table. */
2001 /* mfhc2 is at the bottom of the table. */
2002 /* mfc3 is at the bottom of the table. */
2003 {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
2004 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
2005 {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
2006 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
2007 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
2008 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
2009 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2010 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2011 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2012 {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2013 {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2014 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
2015 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2016 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
2017 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
2018 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
2019 {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2020 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2021 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
2022 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
2023 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
2024 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
2025 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
2026 {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2027 {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2028 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
2029 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
2030 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
2031 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
2032 {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2033 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2034 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
2035 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
2036 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
2037 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
2038 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
2039 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2040 {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2041 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
2042 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
2043 {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2044 {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2045 {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2046 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2047 /* move is at the top of the table. */
2048 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2049 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2050 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2051 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2052 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
2053 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
2054 {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2055 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
2056 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
2057 {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2058 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
2059 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
2060 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
2061 {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
2062 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
2063 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
2064 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
2065 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
2066 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
2067 /* mtc2 is at the bottom of the table. */
2068 /* mthc2 is at the bottom of the table. */
2069 /* mtc3 is at the bottom of the table. */
2070 {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
2071 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
2072 {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
2073 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
2074 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
2075 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
2076 {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
2077 {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
2078 {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
2079 {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
2080 {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
2081 {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
2082 {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
2083 {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
2084 {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
2085 {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
2086 {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
2087 {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
2088 {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
2089 {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
2090 {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
2091 {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
2092 {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
2093 {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
2094 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2095 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2096 {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2097 {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2098 {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2099 {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2100 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2101 {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2102 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55},
2103 {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 },
2104 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
2105 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
2106 {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2107 {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2108 {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2109 {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2110 {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2111 {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2112 {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2113 {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2114 {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2115 {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2116 {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2117 {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2118 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
2119 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
2120 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
2121 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
2122 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2123 {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2124 {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2125 {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2126 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2127 {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2128 {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2129 {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2130 {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2131 {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2132 {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2133 {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2134 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2135 {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2136 {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2137 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
2138 {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
2139 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2140 {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
2141 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
2142 {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
2143 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2144 {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2145 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
2146 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
2147 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
2148 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2149 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
2150 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2151 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2152 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2153 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2154 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2155 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2156 /* nop is at the start of the table. */
2157 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2158 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
2159 {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2160 {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2161 {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2162 {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2163 {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2164 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/
2165 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2166 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
2167 {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2168 {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2169 {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2170 {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2171 {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2172 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2173 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2174 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 },
2175 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2176 {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2177 {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2178 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2179 {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2180 {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2181 {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2182 {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2183 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2184 {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2185 {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2186 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2187 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2188 /* pref and prefx are at the start of the table. */
2189 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2190 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2191 {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT },
2192 {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2193 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 },
2194 {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2195 {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2196 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 },
2197 {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2198 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2199 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 },
2200 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2201 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2202 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2203 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2204 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2205 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2206 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2207 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2208 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2209 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2210 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2211 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
2212 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
2213 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2214 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
2215 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
2216 {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 },
2217 {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 },
2218 {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 },
2219 {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2220 {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2221 {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2222 {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2223 {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2224 {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2225 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
2226 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
2227 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
2228 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
2229 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT },
2230 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT },
2231 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT },
2232 {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT },
2233 {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT },
2234 {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT },
2235 {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT },
2236 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2237 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2238 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2239 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2240 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2241 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2242 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2243 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2244 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2245 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2246 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2247 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2248 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2249 {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2250 {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2251 {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
2252 {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2253 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2254 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
2255 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
2256 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
2257 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
2258 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
2259 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2260 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
2261 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
2262 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
2263 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
2264 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
2265 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 },
2266 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
2267 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2268 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2269 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2270 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2271 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
2272 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
2273 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
2274 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
2275 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2276 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
2277 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
2278 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2279 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
2280 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2281 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
2282 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 },
2283 {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
2284 {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
2285 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2286 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2287 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
2288 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
2289 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
2290 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
2291 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
2292 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
2293 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
2294 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
2295 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
2296 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
2297 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2298 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
2299 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2300 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2301 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2302 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2303 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2304 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2305 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2306 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2307 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2308 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2309 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2310 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2311 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2312 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2313 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
2314 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
2315 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
2316 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
2317 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2318 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
2319 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
2320 {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2321 {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2322 {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2323 {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2324 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2325 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
2326 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2327 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2328 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2329 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
2330 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
2331 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
2332 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
2333 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2334 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2335 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2336 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
2337 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
2338 {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2339 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2340 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
2341 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
2342 {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2343 {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2344 {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2345 {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2346 /* ssnop is at the start of the table. */
2347 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 },
2348 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2349 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
2350 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2351 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2352 {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2353 {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2354 {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2355 {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2356 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2357 {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2358 {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2359 {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2360 {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2361 {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2362 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2363 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
2364 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
2365 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55},
2366 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2367 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
2368 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
2369 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
2370 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2371 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2372 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2373 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2374 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
2375 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2376 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
2377 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
2378 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
2379 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
2380 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2381 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
2382 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2383 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */
2384 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2385 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
2386 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2387 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
2388 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 },
2389 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
2390 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
2391 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
2392 {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
2393 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
2394 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
2395 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2396 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2397 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2398 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */
2399 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 },
2400 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2401 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2402 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2403 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */
2404 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 },
2405 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2406 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2407 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2408 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */
2409 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 },
2410 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
2411 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
2412 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
2413 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 },
2414 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2415 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2416 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2417 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */
2418 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 },
2419 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2420 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2421 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2422 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */
2423 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 },
2424 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2425 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2426 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2427 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */
2428 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 },
2429 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2430 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2431 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2432 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2433 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 },
2434 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2435 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2436 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 },
2437 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
2438 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
2439 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
2440 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
2441 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
2442 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
2443 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
2444 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
2445 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
2446 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
2447 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
2448 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
2449 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
2450 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
2451 {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
2452 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
2453 {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
2454 {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2455 {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
2456 {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2457 {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 },
2458 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
2459 {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
2460 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
2461 {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
2462 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2463 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
2464 {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2465 {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2466 {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2467 {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2468 {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2469 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2470 {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
2471 {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
2472
2473 /* User Defined Instruction. */
2474 {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2475 {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2476 {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2477 {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2478 {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2479 {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2480 {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2481 {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2482 {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2483 {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2484 {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2485 {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2486 {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2487 {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2488 {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2489 {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2490 {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2491 {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2492 {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2493 {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2494 {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2495 {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2496 {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2497 {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2498 {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2499 {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2500 {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2501 {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2502 {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2503 {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2504 {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2505 {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2506 {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2507 {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2508 {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2509 {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2510 {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2511 {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2512 {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2513 {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2514 {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2515 {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2516 {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2517 {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2518 {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2519 {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2520 {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2521 {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2522 {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2523 {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2524 {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2525 {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2526 {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2527 {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2528 {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2529 {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2530 {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2531 {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2532 {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2533 {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2534 {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2535 {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2536 {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2537 {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2538
2539 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2540 instructions so they are here for the latters to take precedence. */
2541 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2542 {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
2543 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2544 {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
2545 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2546 {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
2547 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2548 {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
2549 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2550 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2551 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
2552 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
2553 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
2554 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
2555 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2556 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
2557 {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
2558 {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
2559 {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
2560 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
2561 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
2562 {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2563 {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2564 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2565
2566 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2567 instructions, so they are here for the latters to take precedence. */
2568 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2569 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2570 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2571 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2572 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2573 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2574 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
2575 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
2576 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2577 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
2578 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
2579 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
2580
2581 /* No hazard protection on coprocessor instructions--they shouldn't
2582 change the state of the processor and if they do it's up to the
2583 user to put in nops as necessary. These are at the end so that the
2584 disassembler recognizes more specific versions first. */
2585 {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
2586 {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 },
2587 {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
2588 {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
2589 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
2590 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
2591 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
2592 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 },
2593 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
2594 4010 any more, so move this insn out of the way. If the object
2595 format gave us more info, we could do this right. */
2596 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 },
2597 /* MIPS DSP ASE */
2598 {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 },
2599 {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 },
2600 {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 },
2601 {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 },
2602 {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2603 {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2604 {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2605 {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2606 {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2607 {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2608 {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2609 {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2610 {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2611 {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2612 {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2613 {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2614 {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2615 {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2616 {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 },
2617 {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 },
2618 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2619 {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2620 {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2621 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2622 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2623 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2624 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2625 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2626 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2627 {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2628 {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2629 {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2630 {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2631 {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2632 {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2633 {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2634 {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2635 {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2636 {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2637 {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2638 {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2639 {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 },
2640 {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 },
2641 {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2642 {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2643 {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2644 {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2645 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2646 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2647 {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2648 {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2649 {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2650 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2651 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2652 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2653 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2654 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2655 {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2656 {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2657 {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 },
2658 {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2659 {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2660 {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2661 {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2662 {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 },
2663 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2664 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2665 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2666 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2667 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2668 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2669 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2670 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2671 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2672 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2673 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2674 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2675 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2676 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2677 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2678 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2679 {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 },
2680 {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 },
2681 {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 },
2682 {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 },
2683 {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2684 {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2685 {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2686 {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2687 {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2688 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2689 {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2690 {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2691 {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2692 {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2693 {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
2694 {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2695 {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 },
2696 {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2697 {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2698 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2699 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2700 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2701 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2702 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2703 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2704 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2705 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2706 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2707 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2708 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2709 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2710 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2711 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2712 {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2713 {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 },
2714 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2715 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2716 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2717 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2718 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2719 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2720 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2721 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2722 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2723 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2724 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2725 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2726 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2727 {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2728 {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2729 {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2730 {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2731 {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2732 {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2733 {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2734 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 },
2735 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 },
2736 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2737 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 },
2738 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 },
2739 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 },
2740 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 },
2741 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 },
2742 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2743 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 },
2744 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 },
2745 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 },
2746 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2747 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 },
2748 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 },
2749 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 },
2750 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 },
2751 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 },
2752 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2753 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 },
2754 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 },
2755 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 },
2756 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2757 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 },
2758 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2759 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2760 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2761 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2762 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2763 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2764 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2765 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2766 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2767 {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 },
2768 {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 },
2769 {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 },
2770 {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 },
2771 {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 },
2772 {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 },
2773 {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 },
2774 {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 },
2775 {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 },
2776 {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2777 {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2778 {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2779 {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2780 {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2781 {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 },
2782 {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 },
2783 {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 },
2784 {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2785 {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2786 {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 },
2787 {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2788 {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2789 {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2790 {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2791 {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2792 {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2793 {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2794 {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2795 {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2796 {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2797 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2798 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2799 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2800 {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2801 {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2802 {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2803 {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2804 {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2805 {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2806 {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2807 {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2808 {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2809 {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2810 {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2811 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2812 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2813 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2814 {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2815 {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 },
2816 {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 },
2817 {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2818 {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2819 {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2820 {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2821 {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2822 {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2823 {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2824 {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2825 {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2826 {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2827 {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2828 {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2829 {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2830 {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
2831 {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
2832 /* MIPS DSP ASE Rev2 */
2833 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 },
2834 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2835 {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2836 {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2837 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2838 {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2839 {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
2840 {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 },
2841 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2842 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2843 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2844 {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2845 {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2846 {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2847 {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2848 {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2849 {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2850 {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2851 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2852 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2853 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2854 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2855 {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2856 {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 },
2857 {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 },
2858 {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2859 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2860 {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 },
2861 {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2862 {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2863 {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2864 {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2865 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2866 {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2867 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2868 {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2869 {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2870 {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2871 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2872 {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2873 {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2874 {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2875 {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2876 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2877 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2878 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2879 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2880 /* Move bc0* after mftr and mttr to avoid opcode collision. */
2881 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2882 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2883 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2884 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2885 /* ST Microelectronics Loongson-2E and -2F. */
2886 {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2887 {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2888 {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2889 {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2890 {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2891 {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2892 {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2893 {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2894 {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2895 {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2896 {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2897 {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2898 {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2899 {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2900 {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2901 {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2902 {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2903 {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2904 {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2905 {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2906 {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2907 {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2908 {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2909 {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2910 };
2911
2912 #define MIPS_NUM_OPCODES \
2913 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2914 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2915
2916 /* const removed from the following to allow for dynamic extensions to the
2917 * built-in instruction set. */
2918 struct mips_opcode *mips_opcodes =
2919 (struct mips_opcode *) mips_builtin_opcodes;
2920 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2921 #undef MIPS_NUM_OPCODES
2922
2923 /* Mips instructions are at maximum this many bytes long. */
2924 #define INSNLEN 4
2925
2926 \f
2927 /* FIXME: These should be shared with gdb somehow. */
2928
2929 struct mips_cp0sel_name
2930 {
2931 unsigned int cp0reg;
2932 unsigned int sel;
2933 const char * const name;
2934 };
2935
2936 /* The mips16 registers. */
2937 static const unsigned int mips16_to_32_reg_map[] =
2938 {
2939 16, 17, 2, 3, 4, 5, 6, 7
2940 };
2941
2942 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
2943
2944
2945 static const char * const mips_gpr_names_numeric[32] =
2946 {
2947 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2948 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2949 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2950 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2951 };
2952
2953 static const char * const mips_gpr_names_oldabi[32] =
2954 {
2955 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2956 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
2957 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2958 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2959 };
2960
2961 static const char * const mips_gpr_names_newabi[32] =
2962 {
2963 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2964 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
2965 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2966 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2967 };
2968
2969 static const char * const mips_fpr_names_numeric[32] =
2970 {
2971 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
2972 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2973 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2974 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2975 };
2976
2977 static const char * const mips_fpr_names_32[32] =
2978 {
2979 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
2980 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
2981 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
2982 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
2983 };
2984
2985 static const char * const mips_fpr_names_n32[32] =
2986 {
2987 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
2988 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2989 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
2990 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
2991 };
2992
2993 static const char * const mips_fpr_names_64[32] =
2994 {
2995 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
2996 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2997 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
2998 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
2999 };
3000
3001 static const char * const mips_cp0_names_numeric[32] =
3002 {
3003 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
3004 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3005 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3006 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3007 };
3008
3009 static const char * const mips_cp0_names_mips3264[32] =
3010 {
3011 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
3012 "c0_context", "c0_pagemask", "c0_wired", "$7",
3013 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
3014 "c0_status", "c0_cause", "c0_epc", "c0_prid",
3015 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
3016 "c0_xcontext", "$21", "$22", "c0_debug",
3017 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
3018 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
3019 };
3020
3021 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
3022 {
3023 { 4, 1, "c0_contextconfig" },
3024 { 0, 1, "c0_mvpcontrol" },
3025 { 0, 2, "c0_mvpconf0" },
3026 { 0, 3, "c0_mvpconf1" },
3027 { 1, 1, "c0_vpecontrol" },
3028 { 1, 2, "c0_vpeconf0" },
3029 { 1, 3, "c0_vpeconf1" },
3030 { 1, 4, "c0_yqmask" },
3031 { 1, 5, "c0_vpeschedule" },
3032 { 1, 6, "c0_vpeschefback" },
3033 { 2, 1, "c0_tcstatus" },
3034 { 2, 2, "c0_tcbind" },
3035 { 2, 3, "c0_tcrestart" },
3036 { 2, 4, "c0_tchalt" },
3037 { 2, 5, "c0_tccontext" },
3038 { 2, 6, "c0_tcschedule" },
3039 { 2, 7, "c0_tcschefback" },
3040 { 5, 1, "c0_pagegrain" },
3041 { 6, 1, "c0_srsconf0" },
3042 { 6, 2, "c0_srsconf1" },
3043 { 6, 3, "c0_srsconf2" },
3044 { 6, 4, "c0_srsconf3" },
3045 { 6, 5, "c0_srsconf4" },
3046 { 12, 1, "c0_intctl" },
3047 { 12, 2, "c0_srsctl" },
3048 { 12, 3, "c0_srsmap" },
3049 { 15, 1, "c0_ebase" },
3050 { 16, 1, "c0_config1" },
3051 { 16, 2, "c0_config2" },
3052 { 16, 3, "c0_config3" },
3053 { 18, 1, "c0_watchlo,1" },
3054 { 18, 2, "c0_watchlo,2" },
3055 { 18, 3, "c0_watchlo,3" },
3056 { 18, 4, "c0_watchlo,4" },
3057 { 18, 5, "c0_watchlo,5" },
3058 { 18, 6, "c0_watchlo,6" },
3059 { 18, 7, "c0_watchlo,7" },
3060 { 19, 1, "c0_watchhi,1" },
3061 { 19, 2, "c0_watchhi,2" },
3062 { 19, 3, "c0_watchhi,3" },
3063 { 19, 4, "c0_watchhi,4" },
3064 { 19, 5, "c0_watchhi,5" },
3065 { 19, 6, "c0_watchhi,6" },
3066 { 19, 7, "c0_watchhi,7" },
3067 { 23, 1, "c0_tracecontrol" },
3068 { 23, 2, "c0_tracecontrol2" },
3069 { 23, 3, "c0_usertracedata" },
3070 { 23, 4, "c0_tracebpc" },
3071 { 25, 1, "c0_perfcnt,1" },
3072 { 25, 2, "c0_perfcnt,2" },
3073 { 25, 3, "c0_perfcnt,3" },
3074 { 25, 4, "c0_perfcnt,4" },
3075 { 25, 5, "c0_perfcnt,5" },
3076 { 25, 6, "c0_perfcnt,6" },
3077 { 25, 7, "c0_perfcnt,7" },
3078 { 27, 1, "c0_cacheerr,1" },
3079 { 27, 2, "c0_cacheerr,2" },
3080 { 27, 3, "c0_cacheerr,3" },
3081 { 28, 1, "c0_datalo" },
3082 { 28, 2, "c0_taglo1" },
3083 { 28, 3, "c0_datalo1" },
3084 { 28, 4, "c0_taglo2" },
3085 { 28, 5, "c0_datalo2" },
3086 { 28, 6, "c0_taglo3" },
3087 { 28, 7, "c0_datalo3" },
3088 { 29, 1, "c0_datahi" },
3089 { 29, 2, "c0_taghi1" },
3090 { 29, 3, "c0_datahi1" },
3091 { 29, 4, "c0_taghi2" },
3092 { 29, 5, "c0_datahi2" },
3093 { 29, 6, "c0_taghi3" },
3094 { 29, 7, "c0_datahi3" },
3095 };
3096
3097 static const char * const mips_cp0_names_mips3264r2[32] =
3098 {
3099 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
3100 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
3101 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
3102 "c0_status", "c0_cause", "c0_epc", "c0_prid",
3103 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
3104 "c0_xcontext", "$21", "$22", "c0_debug",
3105 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
3106 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
3107 };
3108
3109 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
3110 {
3111 { 4, 1, "c0_contextconfig" },
3112 { 5, 1, "c0_pagegrain" },
3113 { 12, 1, "c0_intctl" },
3114 { 12, 2, "c0_srsctl" },
3115 { 12, 3, "c0_srsmap" },
3116 { 15, 1, "c0_ebase" },
3117 { 16, 1, "c0_config1" },
3118 { 16, 2, "c0_config2" },
3119 { 16, 3, "c0_config3" },
3120 { 18, 1, "c0_watchlo,1" },
3121 { 18, 2, "c0_watchlo,2" },
3122 { 18, 3, "c0_watchlo,3" },
3123 { 18, 4, "c0_watchlo,4" },
3124 { 18, 5, "c0_watchlo,5" },
3125 { 18, 6, "c0_watchlo,6" },
3126 { 18, 7, "c0_watchlo,7" },
3127 { 19, 1, "c0_watchhi,1" },
3128 { 19, 2, "c0_watchhi,2" },
3129 { 19, 3, "c0_watchhi,3" },
3130 { 19, 4, "c0_watchhi,4" },
3131 { 19, 5, "c0_watchhi,5" },
3132 { 19, 6, "c0_watchhi,6" },
3133 { 19, 7, "c0_watchhi,7" },
3134 { 23, 1, "c0_tracecontrol" },
3135 { 23, 2, "c0_tracecontrol2" },
3136 { 23, 3, "c0_usertracedata" },
3137 { 23, 4, "c0_tracebpc" },
3138 { 25, 1, "c0_perfcnt,1" },
3139 { 25, 2, "c0_perfcnt,2" },
3140 { 25, 3, "c0_perfcnt,3" },
3141 { 25, 4, "c0_perfcnt,4" },
3142 { 25, 5, "c0_perfcnt,5" },
3143 { 25, 6, "c0_perfcnt,6" },
3144 { 25, 7, "c0_perfcnt,7" },
3145 { 27, 1, "c0_cacheerr,1" },
3146 { 27, 2, "c0_cacheerr,2" },
3147 { 27, 3, "c0_cacheerr,3" },
3148 { 28, 1, "c0_datalo" },
3149 { 28, 2, "c0_taglo1" },
3150 { 28, 3, "c0_datalo1" },
3151 { 28, 4, "c0_taglo2" },
3152 { 28, 5, "c0_datalo2" },
3153 { 28, 6, "c0_taglo3" },
3154 { 28, 7, "c0_datalo3" },
3155 { 29, 1, "c0_datahi" },
3156 { 29, 2, "c0_taghi1" },
3157 { 29, 3, "c0_datahi1" },
3158 { 29, 4, "c0_taghi2" },
3159 { 29, 5, "c0_datahi2" },
3160 { 29, 6, "c0_taghi3" },
3161 { 29, 7, "c0_datahi3" },
3162 };
3163
3164 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
3165 static const char * const mips_cp0_names_sb1[32] =
3166 {
3167 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
3168 "c0_context", "c0_pagemask", "c0_wired", "$7",
3169 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
3170 "c0_status", "c0_cause", "c0_epc", "c0_prid",
3171 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
3172 "c0_xcontext", "$21", "$22", "c0_debug",
3173 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
3174 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
3175 };
3176
3177 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3178 {
3179 { 16, 1, "c0_config1" },
3180 { 18, 1, "c0_watchlo,1" },
3181 { 19, 1, "c0_watchhi,1" },
3182 { 22, 0, "c0_perftrace" },
3183 { 23, 3, "c0_edebug" },
3184 { 25, 1, "c0_perfcnt,1" },
3185 { 25, 2, "c0_perfcnt,2" },
3186 { 25, 3, "c0_perfcnt,3" },
3187 { 25, 4, "c0_perfcnt,4" },
3188 { 25, 5, "c0_perfcnt,5" },
3189 { 25, 6, "c0_perfcnt,6" },
3190 { 25, 7, "c0_perfcnt,7" },
3191 { 26, 1, "c0_buserr_pa" },
3192 { 27, 1, "c0_cacheerr_d" },
3193 { 27, 3, "c0_cacheerr_d_pa" },
3194 { 28, 1, "c0_datalo_i" },
3195 { 28, 2, "c0_taglo_d" },
3196 { 28, 3, "c0_datalo_d" },
3197 { 29, 1, "c0_datahi_i" },
3198 { 29, 2, "c0_taghi_d" },
3199 { 29, 3, "c0_datahi_d" },
3200 };
3201
3202 static const char * const mips_hwr_names_numeric[32] =
3203 {
3204 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
3205 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3206 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3207 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3208 };
3209
3210 static const char * const mips_hwr_names_mips3264r2[32] =
3211 {
3212 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
3213 "$4", "$5", "$6", "$7",
3214 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3215 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3216 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3217 };
3218
3219 struct mips_abi_choice
3220 {
3221 const char *name;
3222 const char * const *gpr_names;
3223 const char * const *fpr_names;
3224 };
3225
3226 static struct mips_abi_choice mips_abi_choices[] =
3227 {
3228 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3229 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3230 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3231 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3232 };
3233
3234 struct mips_arch_choice
3235 {
3236 const char *name;
3237 int bfd_mach_valid;
3238 unsigned long bfd_mach;
3239 int processor;
3240 int isa;
3241 const char * const *cp0_names;
3242 const struct mips_cp0sel_name *cp0sel_names;
3243 unsigned int cp0sel_names_len;
3244 const char * const *hwr_names;
3245 };
3246
3247 #define bfd_mach_mips3000 3000
3248 #define bfd_mach_mips3900 3900
3249 #define bfd_mach_mips4000 4000
3250 #define bfd_mach_mips4010 4010
3251 #define bfd_mach_mips4100 4100
3252 #define bfd_mach_mips4111 4111
3253 #define bfd_mach_mips4120 4120
3254 #define bfd_mach_mips4300 4300
3255 #define bfd_mach_mips4400 4400
3256 #define bfd_mach_mips4600 4600
3257 #define bfd_mach_mips4650 4650
3258 #define bfd_mach_mips5000 5000
3259 #define bfd_mach_mips5400 5400
3260 #define bfd_mach_mips5500 5500
3261 #define bfd_mach_mips6000 6000
3262 #define bfd_mach_mips7000 7000
3263 #define bfd_mach_mips8000 8000
3264 #define bfd_mach_mips9000 9000
3265 #define bfd_mach_mips10000 10000
3266 #define bfd_mach_mips12000 12000
3267 #define bfd_mach_mips16 16
3268 #define bfd_mach_mips5 5
3269 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
3270 #define bfd_mach_mipsisa32 32
3271 #define bfd_mach_mipsisa32r2 33
3272 #define bfd_mach_mipsisa64 64
3273 #define bfd_mach_mipsisa64r2 65
3274
3275 static const struct mips_arch_choice mips_arch_choices[] =
3276 {
3277 { "numeric", 0, 0, 0, 0,
3278 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3279
3280 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3281 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3282 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3283 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3284 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3285 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3286 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3287 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3288 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3289 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3290 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3291 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3292 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3293 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3294 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3295 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3296 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3297 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3298 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3299 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3300 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3301 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3302 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3303 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3304 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3305 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3306 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3307 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3308 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3309 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3310 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3311 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3312 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3313 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3314 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3315 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3316 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3317 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3318 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3319 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3320 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3321 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3322
3323 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3324 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
3325 _MIPS32 Architecture For Programmers Volume I: Introduction to the
3326 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3327 page 1. */
3328 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
3329 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3330 mips_cp0_names_mips3264,
3331 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3332 mips_hwr_names_numeric },
3333
3334 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3335 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3336 | INSN_MIPS3D | INSN_MT),
3337 mips_cp0_names_mips3264r2,
3338 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3339 mips_hwr_names_mips3264r2 },
3340
3341 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
3342 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
3343 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3344 mips_cp0_names_mips3264,
3345 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3346 mips_hwr_names_numeric },
3347
3348 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3349 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3350 | INSN_DSP64 | INSN_MT | INSN_MDMX),
3351 mips_cp0_names_mips3264r2,
3352 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3353 mips_hwr_names_mips3264r2 },
3354
3355 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
3356 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3357 mips_cp0_names_sb1,
3358 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3359 mips_hwr_names_numeric },
3360
3361 /* This entry, mips16, is here only for ISA/processor selection; do
3362 not print its name. */
3363 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3364 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3365 };
3366
3367 /* ISA and processor type to disassemble for, and register names to use.
3368 set_default_mips_dis_options and parse_mips_dis_options fill in these
3369 values. */
3370 static int mips_processor;
3371 static int mips_isa;
3372 static const char * const *mips_gpr_names;
3373 static const char * const *mips_fpr_names;
3374 static const char * const *mips_cp0_names;
3375 static const struct mips_cp0sel_name *mips_cp0sel_names;
3376 static int mips_cp0sel_names_len;
3377 static const char * const *mips_hwr_names;
3378
3379 /* Other options */
3380 static int no_aliases; /* If set disassemble as most general inst. */
3381 \f
3382 static const struct mips_abi_choice *
3383 choose_abi_by_name (const char *name, unsigned int namelen)
3384 {
3385 const struct mips_abi_choice *c;
3386 unsigned int i;
3387
3388 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3389 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3390 && strlen (mips_abi_choices[i].name) == namelen)
3391 c = &mips_abi_choices[i];
3392
3393 return c;
3394 }
3395
3396 static const struct mips_arch_choice *
3397 choose_arch_by_name (const char *name, unsigned int namelen)
3398 {
3399 const struct mips_arch_choice *c = NULL;
3400 unsigned int i;
3401
3402 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3403 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3404 && strlen (mips_arch_choices[i].name) == namelen)
3405 c = &mips_arch_choices[i];
3406
3407 return c;
3408 }
3409
3410 static const struct mips_arch_choice *
3411 choose_arch_by_number (unsigned long mach)
3412 {
3413 static unsigned long hint_bfd_mach;
3414 static const struct mips_arch_choice *hint_arch_choice;
3415 const struct mips_arch_choice *c;
3416 unsigned int i;
3417
3418 /* We optimize this because even if the user specifies no
3419 flags, this will be done for every instruction! */
3420 if (hint_bfd_mach == mach
3421 && hint_arch_choice != NULL
3422 && hint_arch_choice->bfd_mach == hint_bfd_mach)
3423 return hint_arch_choice;
3424
3425 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3426 {
3427 if (mips_arch_choices[i].bfd_mach_valid
3428 && mips_arch_choices[i].bfd_mach == mach)
3429 {
3430 c = &mips_arch_choices[i];
3431 hint_bfd_mach = mach;
3432 hint_arch_choice = c;
3433 }
3434 }
3435 return c;
3436 }
3437
3438 static void
3439 set_default_mips_dis_options (struct disassemble_info *info)
3440 {
3441 const struct mips_arch_choice *chosen_arch;
3442
3443 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
3444 and numeric FPR, CP0 register, and HWR names. */
3445 mips_isa = ISA_MIPS3;
3446 mips_processor = CPU_R3000;
3447 mips_gpr_names = mips_gpr_names_oldabi;
3448 mips_fpr_names = mips_fpr_names_numeric;
3449 mips_cp0_names = mips_cp0_names_numeric;
3450 mips_cp0sel_names = NULL;
3451 mips_cp0sel_names_len = 0;
3452 mips_hwr_names = mips_hwr_names_numeric;
3453 no_aliases = 0;
3454
3455 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
3456 #if 0
3457 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
3458 {
3459 Elf_Internal_Ehdr *header;
3460
3461 header = elf_elfheader (info->section->owner);
3462 if (is_newabi (header))
3463 mips_gpr_names = mips_gpr_names_newabi;
3464 }
3465 #endif
3466
3467 /* Set ISA, architecture, and cp0 register names as best we can. */
3468 #if !defined(SYMTAB_AVAILABLE) && 0
3469 /* This is running out on a target machine, not in a host tool.
3470 FIXME: Where does mips_target_info come from? */
3471 target_processor = mips_target_info.processor;
3472 mips_isa = mips_target_info.isa;
3473 #else
3474 chosen_arch = choose_arch_by_number (info->mach);
3475 if (chosen_arch != NULL)
3476 {
3477 mips_processor = chosen_arch->processor;
3478 mips_isa = chosen_arch->isa;
3479 mips_cp0_names = chosen_arch->cp0_names;
3480 mips_cp0sel_names = chosen_arch->cp0sel_names;
3481 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3482 mips_hwr_names = chosen_arch->hwr_names;
3483 }
3484 #endif
3485 }
3486
3487 static void
3488 parse_mips_dis_option (const char *option, unsigned int len)
3489 {
3490 unsigned int i, optionlen, vallen;
3491 const char *val;
3492 const struct mips_abi_choice *chosen_abi;
3493 const struct mips_arch_choice *chosen_arch;
3494
3495 /* Look for the = that delimits the end of the option name. */
3496 for (i = 0; i < len; i++)
3497 {
3498 if (option[i] == '=')
3499 break;
3500 }
3501 if (i == 0) /* Invalid option: no name before '='. */
3502 return;
3503 if (i == len) /* Invalid option: no '='. */
3504 return;
3505 if (i == (len - 1)) /* Invalid option: no value after '='. */
3506 return;
3507
3508 optionlen = i;
3509 val = option + (optionlen + 1);
3510 vallen = len - (optionlen + 1);
3511
3512 if (strncmp("gpr-names", option, optionlen) == 0
3513 && strlen("gpr-names") == optionlen)
3514 {
3515 chosen_abi = choose_abi_by_name (val, vallen);
3516 if (chosen_abi != NULL)
3517 mips_gpr_names = chosen_abi->gpr_names;
3518 return;
3519 }
3520
3521 if (strncmp("fpr-names", option, optionlen) == 0
3522 && strlen("fpr-names") == optionlen)
3523 {
3524 chosen_abi = choose_abi_by_name (val, vallen);
3525 if (chosen_abi != NULL)
3526 mips_fpr_names = chosen_abi->fpr_names;
3527 return;
3528 }
3529
3530 if (strncmp("cp0-names", option, optionlen) == 0
3531 && strlen("cp0-names") == optionlen)
3532 {
3533 chosen_arch = choose_arch_by_name (val, vallen);
3534 if (chosen_arch != NULL)
3535 {
3536 mips_cp0_names = chosen_arch->cp0_names;
3537 mips_cp0sel_names = chosen_arch->cp0sel_names;
3538 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3539 }
3540 return;
3541 }
3542
3543 if (strncmp("hwr-names", option, optionlen) == 0
3544 && strlen("hwr-names") == optionlen)
3545 {
3546 chosen_arch = choose_arch_by_name (val, vallen);
3547 if (chosen_arch != NULL)
3548 mips_hwr_names = chosen_arch->hwr_names;
3549 return;
3550 }
3551
3552 if (strncmp("reg-names", option, optionlen) == 0
3553 && strlen("reg-names") == optionlen)
3554 {
3555 /* We check both ABI and ARCH here unconditionally, so
3556 that "numeric" will do the desirable thing: select
3557 numeric register names for all registers. Other than
3558 that, a given name probably won't match both. */
3559 chosen_abi = choose_abi_by_name (val, vallen);
3560 if (chosen_abi != NULL)
3561 {
3562 mips_gpr_names = chosen_abi->gpr_names;
3563 mips_fpr_names = chosen_abi->fpr_names;
3564 }
3565 chosen_arch = choose_arch_by_name (val, vallen);
3566 if (chosen_arch != NULL)
3567 {
3568 mips_cp0_names = chosen_arch->cp0_names;
3569 mips_cp0sel_names = chosen_arch->cp0sel_names;
3570 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3571 mips_hwr_names = chosen_arch->hwr_names;
3572 }
3573 return;
3574 }
3575
3576 /* Invalid option. */
3577 }
3578
3579 static void
3580 parse_mips_dis_options (const char *options)
3581 {
3582 const char *option_end;
3583
3584 if (options == NULL)
3585 return;
3586
3587 while (*options != '\0')
3588 {
3589 /* Skip empty options. */
3590 if (*options == ',')
3591 {
3592 options++;
3593 continue;
3594 }
3595
3596 /* We know that *options is neither NUL or a comma. */
3597 option_end = options + 1;
3598 while (*option_end != ',' && *option_end != '\0')
3599 option_end++;
3600
3601 parse_mips_dis_option (options, option_end - options);
3602
3603 /* Go on to the next one. If option_end points to a comma, it
3604 will be skipped above. */
3605 options = option_end;
3606 }
3607 }
3608
3609 static const struct mips_cp0sel_name *
3610 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
3611 unsigned int len,
3612 unsigned int cp0reg,
3613 unsigned int sel)
3614 {
3615 unsigned int i;
3616
3617 for (i = 0; i < len; i++)
3618 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
3619 return &names[i];
3620 return NULL;
3621 }
3622 \f
3623 /* Print insn arguments for 32/64-bit code. */
3624
3625 static void
3626 print_insn_args (const char *d,
3627 register unsigned long int l,
3628 bfd_vma pc,
3629 struct disassemble_info *info,
3630 const struct mips_opcode *opp)
3631 {
3632 int op, delta;
3633 unsigned int lsb, msb, msbd;
3634
3635 lsb = 0;
3636
3637 for (; *d != '\0'; d++)
3638 {
3639 switch (*d)
3640 {
3641 case ',':
3642 case '(':
3643 case ')':
3644 case '[':
3645 case ']':
3646 (*info->fprintf_func) (info->stream, "%c", *d);
3647 break;
3648
3649 case '+':
3650 /* Extension character; switch for second char. */
3651 d++;
3652 switch (*d)
3653 {
3654 case '\0':
3655 /* xgettext:c-format */
3656 (*info->fprintf_func) (info->stream,
3657 _("# internal error, incomplete extension sequence (+)"));
3658 return;
3659
3660 case 'A':
3661 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
3662 (*info->fprintf_func) (info->stream, "0x%x", lsb);
3663 break;
3664
3665 case 'B':
3666 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
3667 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3668 break;
3669
3670 case '1':
3671 (*info->fprintf_func) (info->stream, "0x%lx",
3672 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
3673 break;
3674
3675 case '2':
3676 (*info->fprintf_func) (info->stream, "0x%lx",
3677 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
3678 break;
3679
3680 case '3':
3681 (*info->fprintf_func) (info->stream, "0x%lx",
3682 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
3683 break;
3684
3685 case '4':
3686 (*info->fprintf_func) (info->stream, "0x%lx",
3687 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
3688 break;
3689
3690 case 'C':
3691 case 'H':
3692 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
3693 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3694 break;
3695
3696 case 'D':
3697 {
3698 const struct mips_cp0sel_name *n;
3699 unsigned int cp0reg, sel;
3700
3701 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
3702 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3703
3704 /* CP0 register including 'sel' code for mtcN (et al.), to be
3705 printed textually if known. If not known, print both
3706 CP0 register name and sel numerically since CP0 register
3707 with sel 0 may have a name unrelated to register being
3708 printed. */
3709 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3710 mips_cp0sel_names_len, cp0reg, sel);
3711 if (n != NULL)
3712 (*info->fprintf_func) (info->stream, "%s", n->name);
3713 else
3714 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3715 break;
3716 }
3717
3718 case 'E':
3719 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
3720 (*info->fprintf_func) (info->stream, "0x%x", lsb);
3721 break;
3722
3723 case 'F':
3724 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
3725 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3726 break;
3727
3728 case 'G':
3729 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
3730 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3731 break;
3732
3733 case 'o':
3734 switch (*(d+1)) {
3735 case '1':
3736 d++;
3737 delta = l & ((1 << 18) - 1);
3738 if (delta & 0x20000) {
3739 delta |= ~0x1ffff;
3740 }
3741 break;
3742 case '2':
3743 d++;
3744 delta = l & ((1 << 19) - 1);
3745 if (delta & 0x40000) {
3746 delta |= ~0x3ffff;
3747 }
3748 break;
3749 default:
3750 delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
3751 if (delta & 0x8000) {
3752 delta |= ~0xffff;
3753 }
3754 }
3755
3756 (*info->fprintf_func) (info->stream, "%d", delta);
3757 break;
3758
3759 case 'p':
3760 /* Sign extend the displacement with 26 bits. */
3761 delta = (l >> OP_SH_DELTA) & OP_MASK_TARGET;
3762 if (delta & 0x2000000) {
3763 delta |= ~0x3FFFFFF;
3764 }
3765 info->target = (delta << 2) + pc + INSNLEN;
3766 (*info->print_address_func) (info->target, info);
3767 break;
3768
3769 case 't': /* Coprocessor 0 reg name */
3770 (*info->fprintf_func) (info->stream, "%s",
3771 mips_cp0_names[(l >> OP_SH_RT) &
3772 OP_MASK_RT]);
3773 break;
3774
3775 case 'T': /* Coprocessor 0 reg name */
3776 {
3777 const struct mips_cp0sel_name *n;
3778 unsigned int cp0reg, sel;
3779
3780 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
3781 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3782
3783 /* CP0 register including 'sel' code for mftc0, to be
3784 printed textually if known. If not known, print both
3785 CP0 register name and sel numerically since CP0 register
3786 with sel 0 may have a name unrelated to register being
3787 printed. */
3788 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3789 mips_cp0sel_names_len, cp0reg, sel);
3790 if (n != NULL)
3791 (*info->fprintf_func) (info->stream, "%s", n->name);
3792 else
3793 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3794 break;
3795 }
3796
3797 default:
3798 /* xgettext:c-format */
3799 (*info->fprintf_func) (info->stream,
3800 _("# internal error, undefined extension sequence (+%c)"),
3801 *d);
3802 return;
3803 }
3804 break;
3805
3806 case '2':
3807 (*info->fprintf_func) (info->stream, "0x%lx",
3808 (l >> OP_SH_BP) & OP_MASK_BP);
3809 break;
3810
3811 case '3':
3812 (*info->fprintf_func) (info->stream, "0x%lx",
3813 (l >> OP_SH_SA3) & OP_MASK_SA3);
3814 break;
3815
3816 case '4':
3817 (*info->fprintf_func) (info->stream, "0x%lx",
3818 (l >> OP_SH_SA4) & OP_MASK_SA4);
3819 break;
3820
3821 case '5':
3822 (*info->fprintf_func) (info->stream, "0x%lx",
3823 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
3824 break;
3825
3826 case '6':
3827 (*info->fprintf_func) (info->stream, "0x%lx",
3828 (l >> OP_SH_RS) & OP_MASK_RS);
3829 break;
3830
3831 case '7':
3832 (*info->fprintf_func) (info->stream, "$ac%ld",
3833 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
3834 break;
3835
3836 case '8':
3837 (*info->fprintf_func) (info->stream, "0x%lx",
3838 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
3839 break;
3840
3841 case '9':
3842 (*info->fprintf_func) (info->stream, "$ac%ld",
3843 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
3844 break;
3845
3846 case '0': /* dsp 6-bit signed immediate in bit 20 */
3847 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
3848 if (delta & 0x20) /* test sign bit */
3849 delta |= ~OP_MASK_DSPSFT;
3850 (*info->fprintf_func) (info->stream, "%d", delta);
3851 break;
3852
3853 case ':': /* dsp 7-bit signed immediate in bit 19 */
3854 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
3855 if (delta & 0x40) /* test sign bit */
3856 delta |= ~OP_MASK_DSPSFT_7;
3857 (*info->fprintf_func) (info->stream, "%d", delta);
3858 break;
3859
3860 case '\'':
3861 (*info->fprintf_func) (info->stream, "0x%lx",
3862 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
3863 break;
3864
3865 case '@': /* dsp 10-bit signed immediate in bit 16 */
3866 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
3867 if (delta & 0x200) /* test sign bit */
3868 delta |= ~OP_MASK_IMM10;
3869 (*info->fprintf_func) (info->stream, "%d", delta);
3870 break;
3871
3872 case '!':
3873 (*info->fprintf_func) (info->stream, "%ld",
3874 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
3875 break;
3876
3877 case '$':
3878 (*info->fprintf_func) (info->stream, "%ld",
3879 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
3880 break;
3881
3882 case '*':
3883 (*info->fprintf_func) (info->stream, "$ac%ld",
3884 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
3885 break;
3886
3887 case '&':
3888 (*info->fprintf_func) (info->stream, "$ac%ld",
3889 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
3890 break;
3891
3892 case 'g':
3893 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
3894 (*info->fprintf_func) (info->stream, "$%ld",
3895 (l >> OP_SH_RD) & OP_MASK_RD);
3896 break;
3897
3898 case 's':
3899 case 'b':
3900 case 'r':
3901 case 'v':
3902 (*info->fprintf_func) (info->stream, "%s",
3903 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
3904 break;
3905
3906 case 't':
3907 case 'w':
3908 (*info->fprintf_func) (info->stream, "%s",
3909 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3910 break;
3911
3912 case 'i':
3913 case 'u':
3914 (*info->fprintf_func) (info->stream, "0x%lx",
3915 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
3916 break;
3917
3918 case 'j': /* Same as i, but sign-extended. */
3919 case 'o':
3920 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3921
3922 if (delta & 0x8000)
3923 delta |= ~0xffff;
3924 (*info->fprintf_func) (info->stream, "%d",
3925 delta);
3926 break;
3927
3928 case 'h':
3929 (*info->fprintf_func) (info->stream, "0x%x",
3930 (unsigned int) ((l >> OP_SH_PREFX)
3931 & OP_MASK_PREFX));
3932 break;
3933
3934 case 'k':
3935 (*info->fprintf_func) (info->stream, "0x%x",
3936 (unsigned int) ((l >> OP_SH_CACHE)
3937 & OP_MASK_CACHE));
3938 break;
3939
3940 case 'a':
3941 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
3942 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
3943 /* For gdb disassembler, force odd address on jalx. */
3944 if (info->flavour == bfd_target_unknown_flavour
3945 && strcmp (opp->name, "jalx") == 0)
3946 info->target |= 1;
3947 (*info->print_address_func) (info->target, info);
3948 break;
3949
3950 case 'p':
3951 /* Sign extend the displacement. */
3952 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3953 if (delta & 0x8000)
3954 delta |= ~0xffff;
3955 info->target = (delta << 2) + pc + INSNLEN;
3956 (*info->print_address_func) (info->target, info);
3957 break;
3958
3959 case 'd':
3960 (*info->fprintf_func) (info->stream, "%s",
3961 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3962 break;
3963
3964 case 'U':
3965 {
3966 /* First check for both rd and rt being equal. */
3967 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
3968 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
3969 (*info->fprintf_func) (info->stream, "%s",
3970 mips_gpr_names[reg]);
3971 else
3972 {
3973 /* If one is zero use the other. */
3974 if (reg == 0)
3975 (*info->fprintf_func) (info->stream, "%s",
3976 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3977 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
3978 (*info->fprintf_func) (info->stream, "%s",
3979 mips_gpr_names[reg]);
3980 else /* Bogus, result depends on processor. */
3981 (*info->fprintf_func) (info->stream, "%s or %s",
3982 mips_gpr_names[reg],
3983 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3984 }
3985 }
3986 break;
3987
3988 case 'z':
3989 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3990 break;
3991
3992 case '<':
3993 (*info->fprintf_func) (info->stream, "0x%lx",
3994 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3995 break;
3996
3997 case 'c':
3998 (*info->fprintf_func) (info->stream, "0x%lx",
3999 (l >> OP_SH_CODE) & OP_MASK_CODE);
4000 break;
4001
4002 case 'q':
4003 (*info->fprintf_func) (info->stream, "0x%lx",
4004 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
4005 break;
4006
4007 case 'C':
4008 (*info->fprintf_func) (info->stream, "0x%lx",
4009 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
4010 break;
4011
4012 case 'B':
4013 (*info->fprintf_func) (info->stream, "0x%lx",
4014
4015 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
4016 break;
4017
4018 case 'J':
4019 (*info->fprintf_func) (info->stream, "0x%lx",
4020 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
4021 break;
4022
4023 case 'S':
4024 case 'V':
4025 (*info->fprintf_func) (info->stream, "%s",
4026 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4027 break;
4028
4029 case 'T':
4030 case 'W':
4031 (*info->fprintf_func) (info->stream, "%s",
4032 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4033 break;
4034
4035 case 'D':
4036 (*info->fprintf_func) (info->stream, "%s",
4037 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4038 break;
4039
4040 case 'R':
4041 (*info->fprintf_func) (info->stream, "%s",
4042 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
4043 break;
4044
4045 case 'E':
4046 /* Coprocessor register for lwcN instructions, et al.
4047
4048 Note that there is no load/store cp0 instructions, and
4049 that FPU (cp1) instructions disassemble this field using
4050 'T' format. Therefore, until we gain understanding of
4051 cp2 register names, we can simply print the register
4052 numbers. */
4053 (*info->fprintf_func) (info->stream, "$%ld",
4054 (l >> OP_SH_RT) & OP_MASK_RT);
4055 break;
4056
4057 case 'G':
4058 /* Coprocessor register for mtcN instructions, et al. Note
4059 that FPU (cp1) instructions disassemble this field using
4060 'S' format. Therefore, we only need to worry about cp0,
4061 cp2, and cp3. */
4062 op = (l >> OP_SH_OP) & OP_MASK_OP;
4063 if (op == OP_OP_COP0)
4064 (*info->fprintf_func) (info->stream, "%s",
4065 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4066 else
4067 (*info->fprintf_func) (info->stream, "$%ld",
4068 (l >> OP_SH_RD) & OP_MASK_RD);
4069 break;
4070
4071 case 'K':
4072 (*info->fprintf_func) (info->stream, "%s",
4073 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4074 break;
4075
4076 case 'N':
4077 (*info->fprintf_func) (info->stream,
4078 ((opp->pinfo & (FP_D | FP_S)) != 0
4079 ? "$fcc%ld" : "$cc%ld"),
4080 (l >> OP_SH_BCC) & OP_MASK_BCC);
4081 break;
4082
4083 case 'M':
4084 (*info->fprintf_func) (info->stream, "$fcc%ld",
4085 (l >> OP_SH_CCC) & OP_MASK_CCC);
4086 break;
4087
4088 case 'P':
4089 (*info->fprintf_func) (info->stream, "%ld",
4090 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
4091 break;
4092
4093 case 'e':
4094 (*info->fprintf_func) (info->stream, "%ld",
4095 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
4096 break;
4097
4098 case '%':
4099 (*info->fprintf_func) (info->stream, "%ld",
4100 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
4101 break;
4102
4103 case 'H':
4104 (*info->fprintf_func) (info->stream, "%ld",
4105 (l >> OP_SH_SEL) & OP_MASK_SEL);
4106 break;
4107
4108 case 'O':
4109 (*info->fprintf_func) (info->stream, "%ld",
4110 (l >> OP_SH_ALN) & OP_MASK_ALN);
4111 break;
4112
4113 case 'Q':
4114 {
4115 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
4116
4117 if ((vsel & 0x10) == 0)
4118 {
4119 int fmt;
4120
4121 vsel &= 0x0f;
4122 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
4123 if ((vsel & 1) == 0)
4124 break;
4125 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
4126 (l >> OP_SH_FT) & OP_MASK_FT,
4127 vsel >> 1);
4128 }
4129 else if ((vsel & 0x08) == 0)
4130 {
4131 (*info->fprintf_func) (info->stream, "$v%ld",
4132 (l >> OP_SH_FT) & OP_MASK_FT);
4133 }
4134 else
4135 {
4136 (*info->fprintf_func) (info->stream, "0x%lx",
4137 (l >> OP_SH_FT) & OP_MASK_FT);
4138 }
4139 }
4140 break;
4141
4142 case 'X':
4143 (*info->fprintf_func) (info->stream, "$v%ld",
4144 (l >> OP_SH_FD) & OP_MASK_FD);
4145 break;
4146
4147 case 'Y':
4148 (*info->fprintf_func) (info->stream, "$v%ld",
4149 (l >> OP_SH_FS) & OP_MASK_FS);
4150 break;
4151
4152 case 'Z':
4153 (*info->fprintf_func) (info->stream, "$v%ld",
4154 (l >> OP_SH_FT) & OP_MASK_FT);
4155 break;
4156
4157 default:
4158 /* xgettext:c-format */
4159 (*info->fprintf_func) (info->stream,
4160 _("# internal error, undefined modifier(%c)"),
4161 *d);
4162 return;
4163 }
4164 }
4165 }
4166 \f
4167 /* Check if the object uses NewABI conventions. */
4168 #if 0
4169 static int
4170 is_newabi (header)
4171 Elf_Internal_Ehdr *header;
4172 {
4173 /* There are no old-style ABIs which use 64-bit ELF. */
4174 if (header->e_ident[EI_CLASS] == ELFCLASS64)
4175 return 1;
4176
4177 /* If a 32-bit ELF file, n32 is a new-style ABI. */
4178 if ((header->e_flags & EF_MIPS_ABI2) != 0)
4179 return 1;
4180
4181 return 0;
4182 }
4183 #endif
4184 \f
4185 /* Print the mips instruction at address MEMADDR in debugged memory,
4186 on using INFO. Returns length of the instruction, in bytes, which is
4187 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
4188 this is little-endian code. */
4189
4190 static int
4191 print_insn_mips (bfd_vma memaddr,
4192 unsigned long int word,
4193 struct disassemble_info *info)
4194 {
4195 const struct mips_opcode *op;
4196 static bfd_boolean init = 0;
4197 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4198
4199 /* Build a hash table to shorten the search time. */
4200 if (! init)
4201 {
4202 unsigned int i;
4203
4204 for (i = 0; i <= OP_MASK_OP; i++)
4205 {
4206 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4207 {
4208 if (op->pinfo == INSN_MACRO
4209 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
4210 continue;
4211 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4212 {
4213 mips_hash[i] = op;
4214 break;
4215 }
4216 }
4217 }
4218
4219 init = 1;
4220 }
4221
4222 info->bytes_per_chunk = INSNLEN;
4223 info->display_endian = info->endian;
4224 info->insn_info_valid = 1;
4225 info->branch_delay_insns = 0;
4226 info->data_size = 0;
4227 info->insn_type = dis_nonbranch;
4228 info->target = 0;
4229 info->target2 = 0;
4230
4231 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4232 if (op != NULL)
4233 {
4234 for (; op < &mips_opcodes[NUMOPCODES]; op++)
4235 {
4236 if (op->pinfo != INSN_MACRO
4237 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4238 && (word & op->mask) == op->match)
4239 {
4240 const char *d;
4241
4242 /* We always allow to disassemble the jalx instruction. */
4243 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4244 && strcmp (op->name, "jalx"))
4245 continue;
4246
4247 if (strcmp(op->name, "bovc") == 0
4248 || strcmp(op->name, "bnvc") == 0) {
4249 if (((word >> OP_SH_RS) & OP_MASK_RS) <
4250 ((word >> OP_SH_RT) & OP_MASK_RT)) {
4251 continue;
4252 }
4253 }
4254 if (strcmp(op->name, "bgezc") == 0
4255 || strcmp(op->name, "bltzc") == 0
4256 || strcmp(op->name, "bgezalc") == 0
4257 || strcmp(op->name, "bltzalc") == 0) {
4258 if (((word >> OP_SH_RS) & OP_MASK_RS) !=
4259 ((word >> OP_SH_RT) & OP_MASK_RT)) {
4260 continue;
4261 }
4262 }
4263
4264 /* Figure out instruction type and branch delay information. */
4265 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4266 {
4267 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4268 info->insn_type = dis_jsr;
4269 else
4270 info->insn_type = dis_branch;
4271 info->branch_delay_insns = 1;
4272 }
4273 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4274 | INSN_COND_BRANCH_LIKELY)) != 0)
4275 {
4276 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4277 info->insn_type = dis_condjsr;
4278 else
4279 info->insn_type = dis_condbranch;
4280 info->branch_delay_insns = 1;
4281 }
4282 else if ((op->pinfo & (INSN_STORE_MEMORY
4283 | INSN_LOAD_MEMORY_DELAY)) != 0)
4284 info->insn_type = dis_dref;
4285
4286 (*info->fprintf_func) (info->stream, "%s", op->name);
4287
4288 d = op->args;
4289 if (d != NULL && *d != '\0')
4290 {
4291 (*info->fprintf_func) (info->stream, "\t");
4292 print_insn_args (d, word, memaddr, info, op);
4293 }
4294
4295 return INSNLEN;
4296 }
4297 }
4298 }
4299
4300 /* Handle undefined instructions. */
4301 info->insn_type = dis_noninsn;
4302 (*info->fprintf_func) (info->stream, "0x%lx", word);
4303 return INSNLEN;
4304 }
4305 \f
4306 /* In an environment where we do not know the symbol type of the
4307 instruction we are forced to assume that the low order bit of the
4308 instructions' address may mark it as a mips16 instruction. If we
4309 are single stepping, or the pc is within the disassembled function,
4310 this works. Otherwise, we need a clue. Sometimes. */
4311
4312 static int
4313 _print_insn_mips (bfd_vma memaddr,
4314 struct disassemble_info *info,
4315 enum bfd_endian endianness)
4316 {
4317 bfd_byte buffer[INSNLEN];
4318 int status;
4319
4320 set_default_mips_dis_options (info);
4321 parse_mips_dis_options (info->disassembler_options);
4322
4323 #if 0
4324 #if 1
4325 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
4326 /* Only a few tools will work this way. */
4327 if (memaddr & 0x01)
4328 return print_insn_mips16 (memaddr, info);
4329 #endif
4330
4331 #if SYMTAB_AVAILABLE
4332 if (info->mach == bfd_mach_mips16
4333 || (info->flavour == bfd_target_elf_flavour
4334 && info->symbols != NULL
4335 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
4336 == STO_MIPS16)))
4337 return print_insn_mips16 (memaddr, info);
4338 #endif
4339 #endif
4340
4341 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
4342 if (status == 0)
4343 {
4344 unsigned long insn;
4345
4346 if (endianness == BFD_ENDIAN_BIG)
4347 insn = (unsigned long) bfd_getb32 (buffer);
4348 else
4349 insn = (unsigned long) bfd_getl32 (buffer);
4350
4351 return print_insn_mips (memaddr, insn, info);
4352 }
4353 else
4354 {
4355 (*info->memory_error_func) (status, memaddr, info);
4356 return -1;
4357 }
4358 }
4359
4360 int
4361 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
4362 {
4363 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
4364 }
4365
4366 int
4367 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
4368 {
4369 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
4370 }
4371 \f
4372 /* Disassemble mips16 instructions. */
4373 #if 0
4374 static int
4375 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
4376 {
4377 int status;
4378 bfd_byte buffer[2];
4379 int length;
4380 int insn;
4381 bfd_boolean use_extend;
4382 int extend = 0;
4383 const struct mips_opcode *op, *opend;
4384
4385 info->bytes_per_chunk = 2;
4386 info->display_endian = info->endian;
4387 info->insn_info_valid = 1;
4388 info->branch_delay_insns = 0;
4389 info->data_size = 0;
4390 info->insn_type = dis_nonbranch;
4391 info->target = 0;
4392 info->target2 = 0;
4393
4394 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4395 if (status != 0)
4396 {
4397 (*info->memory_error_func) (status, memaddr, info);
4398 return -1;
4399 }
4400
4401 length = 2;
4402
4403 if (info->endian == BFD_ENDIAN_BIG)
4404 insn = bfd_getb16 (buffer);
4405 else
4406 insn = bfd_getl16 (buffer);
4407
4408 /* Handle the extend opcode specially. */
4409 use_extend = FALSE;
4410 if ((insn & 0xf800) == 0xf000)
4411 {
4412 use_extend = TRUE;
4413 extend = insn & 0x7ff;
4414
4415 memaddr += 2;
4416
4417 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4418 if (status != 0)
4419 {
4420 (*info->fprintf_func) (info->stream, "extend 0x%x",
4421 (unsigned int) extend);
4422 (*info->memory_error_func) (status, memaddr, info);
4423 return -1;
4424 }
4425
4426 if (info->endian == BFD_ENDIAN_BIG)
4427 insn = bfd_getb16 (buffer);
4428 else
4429 insn = bfd_getl16 (buffer);
4430
4431 /* Check for an extend opcode followed by an extend opcode. */
4432 if ((insn & 0xf800) == 0xf000)
4433 {
4434 (*info->fprintf_func) (info->stream, "extend 0x%x",
4435 (unsigned int) extend);
4436 info->insn_type = dis_noninsn;
4437 return length;
4438 }
4439
4440 length += 2;
4441 }
4442
4443 /* FIXME: Should probably use a hash table on the major opcode here. */
4444
4445 opend = mips16_opcodes + bfd_mips16_num_opcodes;
4446 for (op = mips16_opcodes; op < opend; op++)
4447 {
4448 if (op->pinfo != INSN_MACRO
4449 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4450 && (insn & op->mask) == op->match)
4451 {
4452 const char *s;
4453
4454 if (strchr (op->args, 'a') != NULL)
4455 {
4456 if (use_extend)
4457 {
4458 (*info->fprintf_func) (info->stream, "extend 0x%x",
4459 (unsigned int) extend);
4460 info->insn_type = dis_noninsn;
4461 return length - 2;
4462 }
4463
4464 use_extend = FALSE;
4465
4466 memaddr += 2;
4467
4468 status = (*info->read_memory_func) (memaddr, buffer, 2,
4469 info);
4470 if (status == 0)
4471 {
4472 use_extend = TRUE;
4473 if (info->endian == BFD_ENDIAN_BIG)
4474 extend = bfd_getb16 (buffer);
4475 else
4476 extend = bfd_getl16 (buffer);
4477 length += 2;
4478 }
4479 }
4480
4481 (*info->fprintf_func) (info->stream, "%s", op->name);
4482 if (op->args[0] != '\0')
4483 (*info->fprintf_func) (info->stream, "\t");
4484
4485 for (s = op->args; *s != '\0'; s++)
4486 {
4487 if (*s == ','
4488 && s[1] == 'w'
4489 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
4490 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
4491 {
4492 /* Skip the register and the comma. */
4493 ++s;
4494 continue;
4495 }
4496 if (*s == ','
4497 && s[1] == 'v'
4498 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
4499 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
4500 {
4501 /* Skip the register and the comma. */
4502 ++s;
4503 continue;
4504 }
4505 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
4506 info);
4507 }
4508
4509 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4510 {
4511 info->branch_delay_insns = 1;
4512 if (info->insn_type != dis_jsr)
4513 info->insn_type = dis_branch;
4514 }
4515
4516 return length;
4517 }
4518 }
4519
4520 if (use_extend)
4521 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
4522 (*info->fprintf_func) (info->stream, "0x%x", insn);
4523 info->insn_type = dis_noninsn;
4524
4525 return length;
4526 }
4527
4528 /* Disassemble an operand for a mips16 instruction. */
4529
4530 static void
4531 print_mips16_insn_arg (char type,
4532 const struct mips_opcode *op,
4533 int l,
4534 bfd_boolean use_extend,
4535 int extend,
4536 bfd_vma memaddr,
4537 struct disassemble_info *info)
4538 {
4539 switch (type)
4540 {
4541 case ',':
4542 case '(':
4543 case ')':
4544 (*info->fprintf_func) (info->stream, "%c", type);
4545 break;
4546
4547 case 'y':
4548 case 'w':
4549 (*info->fprintf_func) (info->stream, "%s",
4550 mips16_reg_names(((l >> MIPS16OP_SH_RY)
4551 & MIPS16OP_MASK_RY)));
4552 break;
4553
4554 case 'x':
4555 case 'v':
4556 (*info->fprintf_func) (info->stream, "%s",
4557 mips16_reg_names(((l >> MIPS16OP_SH_RX)
4558 & MIPS16OP_MASK_RX)));
4559 break;
4560
4561 case 'z':
4562 (*info->fprintf_func) (info->stream, "%s",
4563 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
4564 & MIPS16OP_MASK_RZ)));
4565 break;
4566
4567 case 'Z':
4568 (*info->fprintf_func) (info->stream, "%s",
4569 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
4570 & MIPS16OP_MASK_MOVE32Z)));
4571 break;
4572
4573 case '0':
4574 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4575 break;
4576
4577 case 'S':
4578 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
4579 break;
4580
4581 case 'P':
4582 (*info->fprintf_func) (info->stream, "$pc");
4583 break;
4584
4585 case 'R':
4586 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
4587 break;
4588
4589 case 'X':
4590 (*info->fprintf_func) (info->stream, "%s",
4591 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
4592 & MIPS16OP_MASK_REGR32)]);
4593 break;
4594
4595 case 'Y':
4596 (*info->fprintf_func) (info->stream, "%s",
4597 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
4598 break;
4599
4600 case '<':
4601 case '>':
4602 case '[':
4603 case ']':
4604 case '4':
4605 case '5':
4606 case 'H':
4607 case 'W':
4608 case 'D':
4609 case 'j':
4610 case '6':
4611 case '8':
4612 case 'V':
4613 case 'C':
4614 case 'U':
4615 case 'k':
4616 case 'K':
4617 case 'p':
4618 case 'q':
4619 case 'A':
4620 case 'B':
4621 case 'E':
4622 {
4623 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
4624
4625 shift = 0;
4626 signedp = 0;
4627 extbits = 16;
4628 pcrel = 0;
4629 extu = 0;
4630 branch = 0;
4631 switch (type)
4632 {
4633 case '<':
4634 nbits = 3;
4635 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4636 extbits = 5;
4637 extu = 1;
4638 break;
4639 case '>':
4640 nbits = 3;
4641 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4642 extbits = 5;
4643 extu = 1;
4644 break;
4645 case '[':
4646 nbits = 3;
4647 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4648 extbits = 6;
4649 extu = 1;
4650 break;
4651 case ']':
4652 nbits = 3;
4653 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4654 extbits = 6;
4655 extu = 1;
4656 break;
4657 case '4':
4658 nbits = 4;
4659 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
4660 signedp = 1;
4661 extbits = 15;
4662 break;
4663 case '5':
4664 nbits = 5;
4665 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4666 info->insn_type = dis_dref;
4667 info->data_size = 1;
4668 break;
4669 case 'H':
4670 nbits = 5;
4671 shift = 1;
4672 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4673 info->insn_type = dis_dref;
4674 info->data_size = 2;
4675 break;
4676 case 'W':
4677 nbits = 5;
4678 shift = 2;
4679 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4680 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
4681 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
4682 {
4683 info->insn_type = dis_dref;
4684 info->data_size = 4;
4685 }
4686 break;
4687 case 'D':
4688 nbits = 5;
4689 shift = 3;
4690 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4691 info->insn_type = dis_dref;
4692 info->data_size = 8;
4693 break;
4694 case 'j':
4695 nbits = 5;
4696 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4697 signedp = 1;
4698 break;
4699 case '6':
4700 nbits = 6;
4701 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4702 break;
4703 case '8':
4704 nbits = 8;
4705 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4706 break;
4707 case 'V':
4708 nbits = 8;
4709 shift = 2;
4710 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4711 /* FIXME: This might be lw, or it might be addiu to $sp or
4712 $pc. We assume it's load. */
4713 info->insn_type = dis_dref;
4714 info->data_size = 4;
4715 break;
4716 case 'C':
4717 nbits = 8;
4718 shift = 3;
4719 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4720 info->insn_type = dis_dref;
4721 info->data_size = 8;
4722 break;
4723 case 'U':
4724 nbits = 8;
4725 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4726 extu = 1;
4727 break;
4728 case 'k':
4729 nbits = 8;
4730 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4731 signedp = 1;
4732 break;
4733 case 'K':
4734 nbits = 8;
4735 shift = 3;
4736 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4737 signedp = 1;
4738 break;
4739 case 'p':
4740 nbits = 8;
4741 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4742 signedp = 1;
4743 pcrel = 1;
4744 branch = 1;
4745 info->insn_type = dis_condbranch;
4746 break;
4747 case 'q':
4748 nbits = 11;
4749 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
4750 signedp = 1;
4751 pcrel = 1;
4752 branch = 1;
4753 info->insn_type = dis_branch;
4754 break;
4755 case 'A':
4756 nbits = 8;
4757 shift = 2;
4758 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4759 pcrel = 1;
4760 /* FIXME: This can be lw or la. We assume it is lw. */
4761 info->insn_type = dis_dref;
4762 info->data_size = 4;
4763 break;
4764 case 'B':
4765 nbits = 5;
4766 shift = 3;
4767 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4768 pcrel = 1;
4769 info->insn_type = dis_dref;
4770 info->data_size = 8;
4771 break;
4772 case 'E':
4773 nbits = 5;
4774 shift = 2;
4775 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4776 pcrel = 1;
4777 break;
4778 default:
4779 abort ();
4780 }
4781
4782 if (! use_extend)
4783 {
4784 if (signedp && immed >= (1 << (nbits - 1)))
4785 immed -= 1 << nbits;
4786 immed <<= shift;
4787 if ((type == '<' || type == '>' || type == '[' || type == ']')
4788 && immed == 0)
4789 immed = 8;
4790 }
4791 else
4792 {
4793 if (extbits == 16)
4794 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
4795 else if (extbits == 15)
4796 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
4797 else
4798 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
4799 immed &= (1 << extbits) - 1;
4800 if (! extu && immed >= (1 << (extbits - 1)))
4801 immed -= 1 << extbits;
4802 }
4803
4804 if (! pcrel)
4805 (*info->fprintf_func) (info->stream, "%d", immed);
4806 else
4807 {
4808 bfd_vma baseaddr;
4809
4810 if (branch)
4811 {
4812 immed *= 2;
4813 baseaddr = memaddr + 2;
4814 }
4815 else if (use_extend)
4816 baseaddr = memaddr - 2;
4817 else
4818 {
4819 int status;
4820 bfd_byte buffer[2];
4821
4822 baseaddr = memaddr;
4823
4824 /* If this instruction is in the delay slot of a jr
4825 instruction, the base address is the address of the
4826 jr instruction. If it is in the delay slot of jalr
4827 instruction, the base address is the address of the
4828 jalr instruction. This test is unreliable: we have
4829 no way of knowing whether the previous word is
4830 instruction or data. */
4831 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
4832 info);
4833 if (status == 0
4834 && (((info->endian == BFD_ENDIAN_BIG
4835 ? bfd_getb16 (buffer)
4836 : bfd_getl16 (buffer))
4837 & 0xf800) == 0x1800))
4838 baseaddr = memaddr - 4;
4839 else
4840 {
4841 status = (*info->read_memory_func) (memaddr - 2, buffer,
4842 2, info);
4843 if (status == 0
4844 && (((info->endian == BFD_ENDIAN_BIG
4845 ? bfd_getb16 (buffer)
4846 : bfd_getl16 (buffer))
4847 & 0xf81f) == 0xe800))
4848 baseaddr = memaddr - 2;
4849 }
4850 }
4851 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
4852 if (pcrel && branch
4853 && info->flavour == bfd_target_unknown_flavour)
4854 /* For gdb disassembler, maintain odd address. */
4855 info->target |= 1;
4856 (*info->print_address_func) (info->target, info);
4857 }
4858 }
4859 break;
4860
4861 case 'a':
4862 {
4863 int jalx = l & 0x400;
4864
4865 if (! use_extend)
4866 extend = 0;
4867 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4868 if (!jalx && info->flavour == bfd_target_unknown_flavour)
4869 /* For gdb disassembler, maintain odd address. */
4870 l |= 1;
4871 }
4872 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
4873 (*info->print_address_func) (info->target, info);
4874 info->insn_type = dis_jsr;
4875 info->branch_delay_insns = 1;
4876 break;
4877
4878 case 'l':
4879 case 'L':
4880 {
4881 int need_comma, amask, smask;
4882
4883 need_comma = 0;
4884
4885 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4886
4887 amask = (l >> 3) & 7;
4888
4889 if (amask > 0 && amask < 5)
4890 {
4891 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4892 if (amask > 1)
4893 (*info->fprintf_func) (info->stream, "-%s",
4894 mips_gpr_names[amask + 3]);
4895 need_comma = 1;
4896 }
4897
4898 smask = (l >> 1) & 3;
4899 if (smask == 3)
4900 {
4901 (*info->fprintf_func) (info->stream, "%s??",
4902 need_comma ? "," : "");
4903 need_comma = 1;
4904 }
4905 else if (smask > 0)
4906 {
4907 (*info->fprintf_func) (info->stream, "%s%s",
4908 need_comma ? "," : "",
4909 mips_gpr_names[16]);
4910 if (smask > 1)
4911 (*info->fprintf_func) (info->stream, "-%s",
4912 mips_gpr_names[smask + 15]);
4913 need_comma = 1;
4914 }
4915
4916 if (l & 1)
4917 {
4918 (*info->fprintf_func) (info->stream, "%s%s",
4919 need_comma ? "," : "",
4920 mips_gpr_names[31]);
4921 need_comma = 1;
4922 }
4923
4924 if (amask == 5 || amask == 6)
4925 {
4926 (*info->fprintf_func) (info->stream, "%s$f0",
4927 need_comma ? "," : "");
4928 if (amask == 6)
4929 (*info->fprintf_func) (info->stream, "-$f1");
4930 }
4931 }
4932 break;
4933
4934 case 'm':
4935 case 'M':
4936 /* MIPS16e save/restore. */
4937 {
4938 int need_comma = 0;
4939 int amask, args, statics;
4940 int nsreg, smask;
4941 int framesz;
4942 int i, j;
4943
4944 l = l & 0x7f;
4945 if (use_extend)
4946 l |= extend << 16;
4947
4948 amask = (l >> 16) & 0xf;
4949 if (amask == MIPS16_ALL_ARGS)
4950 {
4951 args = 4;
4952 statics = 0;
4953 }
4954 else if (amask == MIPS16_ALL_STATICS)
4955 {
4956 args = 0;
4957 statics = 4;
4958 }
4959 else
4960 {
4961 args = amask >> 2;
4962 statics = amask & 3;
4963 }
4964
4965 if (args > 0) {
4966 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4967 if (args > 1)
4968 (*info->fprintf_func) (info->stream, "-%s",
4969 mips_gpr_names[4 + args - 1]);
4970 need_comma = 1;
4971 }
4972
4973 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
4974 if (framesz == 0 && !use_extend)
4975 framesz = 128;
4976
4977 (*info->fprintf_func) (info->stream, "%s%d",
4978 need_comma ? "," : "",
4979 framesz);
4980
4981 if (l & 0x40) /* $ra */
4982 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
4983
4984 nsreg = (l >> 24) & 0x7;
4985 smask = 0;
4986 if (l & 0x20) /* $s0 */
4987 smask |= 1 << 0;
4988 if (l & 0x10) /* $s1 */
4989 smask |= 1 << 1;
4990 if (nsreg > 0) /* $s2-$s8 */
4991 smask |= ((1 << nsreg) - 1) << 2;
4992
4993 /* Find first set static reg bit. */
4994 for (i = 0; i < 9; i++)
4995 {
4996 if (smask & (1 << i))
4997 {
4998 (*info->fprintf_func) (info->stream, ",%s",
4999 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
5000 /* Skip over string of set bits. */
5001 for (j = i; smask & (2 << j); j++)
5002 continue;
5003 if (j > i)
5004 (*info->fprintf_func) (info->stream, "-%s",
5005 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
5006 i = j + 1;
5007 }
5008 }
5009
5010 /* Statics $ax - $a3. */
5011 if (statics == 1)
5012 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
5013 else if (statics > 0)
5014 (*info->fprintf_func) (info->stream, ",%s-%s",
5015 mips_gpr_names[7 - statics + 1],
5016 mips_gpr_names[7]);
5017 }
5018 break;
5019
5020 default:
5021 /* xgettext:c-format */
5022 (*info->fprintf_func)
5023 (info->stream,
5024 _("# internal disassembler error, unrecognised modifier (%c)"),
5025 type);
5026 abort ();
5027 }
5028 }
5029
5030 void
5031 print_mips_disassembler_options (FILE *stream)
5032 {
5033 unsigned int i;
5034
5035 fprintf (stream, _("\n\
5036 The following MIPS specific disassembler options are supported for use\n\
5037 with the -M switch (multiple options should be separated by commas):\n"));
5038
5039 fprintf (stream, _("\n\
5040 gpr-names=ABI Print GPR names according to specified ABI.\n\
5041 Default: based on binary being disassembled.\n"));
5042
5043 fprintf (stream, _("\n\
5044 fpr-names=ABI Print FPR names according to specified ABI.\n\
5045 Default: numeric.\n"));
5046
5047 fprintf (stream, _("\n\
5048 cp0-names=ARCH Print CP0 register names according to\n\
5049 specified architecture.\n\
5050 Default: based on binary being disassembled.\n"));
5051
5052 fprintf (stream, _("\n\
5053 hwr-names=ARCH Print HWR names according to specified\n\
5054 architecture.\n\
5055 Default: based on binary being disassembled.\n"));
5056
5057 fprintf (stream, _("\n\
5058 reg-names=ABI Print GPR and FPR names according to\n\
5059 specified ABI.\n"));
5060
5061 fprintf (stream, _("\n\
5062 reg-names=ARCH Print CP0 register and HWR names according to\n\
5063 specified architecture.\n"));
5064
5065 fprintf (stream, _("\n\
5066 For the options above, the following values are supported for \"ABI\":\n\
5067 "));
5068 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
5069 fprintf (stream, " %s", mips_abi_choices[i].name);
5070 fprintf (stream, _("\n"));
5071
5072 fprintf (stream, _("\n\
5073 For the options above, The following values are supported for \"ARCH\":\n\
5074 "));
5075 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
5076 if (*mips_arch_choices[i].name != '\0')
5077 fprintf (stream, " %s", mips_arch_choices[i].name);
5078 fprintf (stream, _("\n"));
5079
5080 fprintf (stream, _("\n"));
5081 }
5082 #endif
AR7 emulation for QEMU