2 * AArch64 SVE translation
4 * Copyright (c) 2018 Linaro, Ltd
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
25 #include "tcg/tcg-gvec-desc.h"
28 #include "translate.h"
29 #include "internals.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "translate-a64.h"
34 #include "fpu/softfloat.h"
37 typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t,
38 TCGv_i64
, uint32_t, uint32_t);
40 typedef void gen_helper_gvec_flags_3(TCGv_i32
, TCGv_ptr
, TCGv_ptr
,
42 typedef void gen_helper_gvec_flags_4(TCGv_i32
, TCGv_ptr
, TCGv_ptr
,
43 TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
45 typedef void gen_helper_gvec_mem(TCGv_env
, TCGv_ptr
, TCGv_i64
, TCGv_i32
);
46 typedef void gen_helper_gvec_mem_scatter(TCGv_env
, TCGv_ptr
, TCGv_ptr
,
47 TCGv_ptr
, TCGv_i64
, TCGv_i32
);
50 * Helpers for extracting complex instruction fields.
53 /* See e.g. ASR (immediate, predicated).
54 * Returns -1 for unallocated encoding; diagnose later.
56 static int tszimm_esz(DisasContext
*s
, int x
)
58 x
>>= 3; /* discard imm3 */
62 static int tszimm_shr(DisasContext
*s
, int x
)
64 return (16 << tszimm_esz(s
, x
)) - x
;
67 /* See e.g. LSL (immediate, predicated). */
68 static int tszimm_shl(DisasContext
*s
, int x
)
70 return x
- (8 << tszimm_esz(s
, x
));
73 /* The SH bit is in bit 8. Extract the low 8 and shift. */
74 static inline int expand_imm_sh8s(DisasContext
*s
, int x
)
76 return (int8_t)x
<< (x
& 0x100 ? 8 : 0);
79 static inline int expand_imm_sh8u(DisasContext
*s
, int x
)
81 return (uint8_t)x
<< (x
& 0x100 ? 8 : 0);
84 /* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype)
85 * with unsigned data. C.f. SVE Memory Contiguous Load Group.
87 static inline int msz_dtype(DisasContext
*s
, int msz
)
89 static const uint8_t dtype
[4] = { 0, 5, 10, 15 };
94 * Include the generated decoder.
97 #include "decode-sve.c.inc"
100 * Implement all of the translator functions referenced by the decoder.
103 /* Return the offset info CPUARMState of the predicate vector register Pn.
104 * Note for this purpose, FFR is P16.
106 static inline int pred_full_reg_offset(DisasContext
*s
, int regno
)
108 return offsetof(CPUARMState
, vfp
.pregs
[regno
]);
111 /* Return the byte size of the whole predicate register, VL / 64. */
112 static inline int pred_full_reg_size(DisasContext
*s
)
114 return s
->sve_len
>> 3;
117 /* Round up the size of a register to a size allowed by
118 * the tcg vector infrastructure. Any operation which uses this
119 * size may assume that the bits above pred_full_reg_size are zero,
120 * and must leave them the same way.
122 * Note that this is not needed for the vector registers as they
123 * are always properly sized for tcg vectors.
125 static int size_for_gvec(int size
)
130 return QEMU_ALIGN_UP(size
, 16);
134 static int pred_gvec_reg_size(DisasContext
*s
)
136 return size_for_gvec(pred_full_reg_size(s
));
139 /* Invoke an out-of-line helper on 2 Zregs. */
140 static bool gen_gvec_ool_zz(DisasContext
*s
, gen_helper_gvec_2
*fn
,
141 int rd
, int rn
, int data
)
146 if (sve_access_check(s
)) {
147 unsigned vsz
= vec_full_reg_size(s
);
148 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
149 vec_full_reg_offset(s
, rn
),
155 /* Invoke an out-of-line helper on 3 Zregs. */
156 static bool gen_gvec_ool_zzz(DisasContext
*s
, gen_helper_gvec_3
*fn
,
157 int rd
, int rn
, int rm
, int data
)
162 if (sve_access_check(s
)) {
163 unsigned vsz
= vec_full_reg_size(s
);
164 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
165 vec_full_reg_offset(s
, rn
),
166 vec_full_reg_offset(s
, rm
),
172 static bool gen_gvec_ool_arg_zzz(DisasContext
*s
, gen_helper_gvec_3
*fn
,
173 arg_rrr_esz
*a
, int data
)
175 return gen_gvec_ool_zzz(s
, fn
, a
->rd
, a
->rn
, a
->rm
, data
);
178 /* Invoke an out-of-line helper on 4 Zregs. */
179 static bool gen_gvec_ool_zzzz(DisasContext
*s
, gen_helper_gvec_4
*fn
,
180 int rd
, int rn
, int rm
, int ra
, int data
)
185 if (sve_access_check(s
)) {
186 unsigned vsz
= vec_full_reg_size(s
);
187 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
188 vec_full_reg_offset(s
, rn
),
189 vec_full_reg_offset(s
, rm
),
190 vec_full_reg_offset(s
, ra
),
196 static bool gen_gvec_ool_arg_zzzz(DisasContext
*s
, gen_helper_gvec_4
*fn
,
197 arg_rrrr_esz
*a
, int data
)
199 return gen_gvec_ool_zzzz(s
, fn
, a
->rd
, a
->rn
, a
->rm
, a
->ra
, data
);
202 static bool gen_gvec_ool_arg_zzxz(DisasContext
*s
, gen_helper_gvec_4
*fn
,
205 return gen_gvec_ool_zzzz(s
, fn
, a
->rd
, a
->rn
, a
->rm
, a
->ra
, a
->index
);
208 /* Invoke an out-of-line helper on 2 Zregs and a predicate. */
209 static bool gen_gvec_ool_zzp(DisasContext
*s
, gen_helper_gvec_3
*fn
,
210 int rd
, int rn
, int pg
, int data
)
215 if (sve_access_check(s
)) {
216 unsigned vsz
= vec_full_reg_size(s
);
217 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
218 vec_full_reg_offset(s
, rn
),
219 pred_full_reg_offset(s
, pg
),
225 static bool gen_gvec_ool_arg_zpz(DisasContext
*s
, gen_helper_gvec_3
*fn
,
226 arg_rpr_esz
*a
, int data
)
228 return gen_gvec_ool_zzp(s
, fn
, a
->rd
, a
->rn
, a
->pg
, data
);
231 static bool gen_gvec_ool_arg_zpzi(DisasContext
*s
, gen_helper_gvec_3
*fn
,
234 return gen_gvec_ool_zzp(s
, fn
, a
->rd
, a
->rn
, a
->pg
, a
->imm
);
237 /* Invoke an out-of-line helper on 3 Zregs and a predicate. */
238 static bool gen_gvec_ool_zzzp(DisasContext
*s
, gen_helper_gvec_4
*fn
,
239 int rd
, int rn
, int rm
, int pg
, int data
)
244 if (sve_access_check(s
)) {
245 unsigned vsz
= vec_full_reg_size(s
);
246 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
247 vec_full_reg_offset(s
, rn
),
248 vec_full_reg_offset(s
, rm
),
249 pred_full_reg_offset(s
, pg
),
255 static bool gen_gvec_ool_arg_zpzz(DisasContext
*s
, gen_helper_gvec_4
*fn
,
256 arg_rprr_esz
*a
, int data
)
258 return gen_gvec_ool_zzzp(s
, fn
, a
->rd
, a
->rn
, a
->rm
, a
->pg
, data
);
261 /* Invoke a vector expander on two Zregs and an immediate. */
262 static bool gen_gvec_fn_zzi(DisasContext
*s
, GVecGen2iFn
*gvec_fn
,
263 int esz
, int rd
, int rn
, uint64_t imm
)
265 if (gvec_fn
== NULL
) {
268 if (sve_access_check(s
)) {
269 unsigned vsz
= vec_full_reg_size(s
);
270 gvec_fn(esz
, vec_full_reg_offset(s
, rd
),
271 vec_full_reg_offset(s
, rn
), imm
, vsz
, vsz
);
276 static bool gen_gvec_fn_arg_zzi(DisasContext
*s
, GVecGen2iFn
*gvec_fn
,
280 /* Invalid tsz encoding -- see tszimm_esz. */
283 return gen_gvec_fn_zzi(s
, gvec_fn
, a
->esz
, a
->rd
, a
->rn
, a
->imm
);
286 /* Invoke a vector expander on three Zregs. */
287 static bool gen_gvec_fn_zzz(DisasContext
*s
, GVecGen3Fn
*gvec_fn
,
288 int esz
, int rd
, int rn
, int rm
)
290 if (gvec_fn
== NULL
) {
293 if (sve_access_check(s
)) {
294 unsigned vsz
= vec_full_reg_size(s
);
295 gvec_fn(esz
, vec_full_reg_offset(s
, rd
),
296 vec_full_reg_offset(s
, rn
),
297 vec_full_reg_offset(s
, rm
), vsz
, vsz
);
302 static bool gen_gvec_fn_arg_zzz(DisasContext
*s
, GVecGen3Fn
*fn
,
305 return gen_gvec_fn_zzz(s
, fn
, a
->esz
, a
->rd
, a
->rn
, a
->rm
);
308 /* Invoke a vector expander on four Zregs. */
309 static bool gen_gvec_fn_arg_zzzz(DisasContext
*s
, GVecGen4Fn
*gvec_fn
,
312 if (gvec_fn
== NULL
) {
315 if (sve_access_check(s
)) {
316 unsigned vsz
= vec_full_reg_size(s
);
317 gvec_fn(a
->esz
, vec_full_reg_offset(s
, a
->rd
),
318 vec_full_reg_offset(s
, a
->rn
),
319 vec_full_reg_offset(s
, a
->rm
),
320 vec_full_reg_offset(s
, a
->ra
), vsz
, vsz
);
325 /* Invoke a vector move on two Zregs. */
326 static bool do_mov_z(DisasContext
*s
, int rd
, int rn
)
328 if (sve_access_check(s
)) {
329 unsigned vsz
= vec_full_reg_size(s
);
330 tcg_gen_gvec_mov(MO_8
, vec_full_reg_offset(s
, rd
),
331 vec_full_reg_offset(s
, rn
), vsz
, vsz
);
336 /* Initialize a Zreg with replications of a 64-bit immediate. */
337 static void do_dupi_z(DisasContext
*s
, int rd
, uint64_t word
)
339 unsigned vsz
= vec_full_reg_size(s
);
340 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), vsz
, vsz
, word
);
343 /* Invoke a vector expander on three Pregs. */
344 static void gen_gvec_fn_ppp(DisasContext
*s
, GVecGen3Fn
*gvec_fn
,
345 int rd
, int rn
, int rm
)
347 unsigned psz
= pred_gvec_reg_size(s
);
348 gvec_fn(MO_64
, pred_full_reg_offset(s
, rd
),
349 pred_full_reg_offset(s
, rn
),
350 pred_full_reg_offset(s
, rm
), psz
, psz
);
353 /* Invoke a vector move on two Pregs. */
354 static bool do_mov_p(DisasContext
*s
, int rd
, int rn
)
356 if (sve_access_check(s
)) {
357 unsigned psz
= pred_gvec_reg_size(s
);
358 tcg_gen_gvec_mov(MO_8
, pred_full_reg_offset(s
, rd
),
359 pred_full_reg_offset(s
, rn
), psz
, psz
);
364 /* Set the cpu flags as per a return from an SVE helper. */
365 static void do_pred_flags(TCGv_i32 t
)
367 tcg_gen_mov_i32(cpu_NF
, t
);
368 tcg_gen_andi_i32(cpu_ZF
, t
, 2);
369 tcg_gen_andi_i32(cpu_CF
, t
, 1);
370 tcg_gen_movi_i32(cpu_VF
, 0);
373 /* Subroutines computing the ARM PredTest psuedofunction. */
374 static void do_predtest1(TCGv_i64 d
, TCGv_i64 g
)
376 TCGv_i32 t
= tcg_temp_new_i32();
378 gen_helper_sve_predtest1(t
, d
, g
);
380 tcg_temp_free_i32(t
);
383 static void do_predtest(DisasContext
*s
, int dofs
, int gofs
, int words
)
385 TCGv_ptr dptr
= tcg_temp_new_ptr();
386 TCGv_ptr gptr
= tcg_temp_new_ptr();
387 TCGv_i32 t
= tcg_temp_new_i32();
389 tcg_gen_addi_ptr(dptr
, cpu_env
, dofs
);
390 tcg_gen_addi_ptr(gptr
, cpu_env
, gofs
);
392 gen_helper_sve_predtest(t
, dptr
, gptr
, tcg_constant_i32(words
));
393 tcg_temp_free_ptr(dptr
);
394 tcg_temp_free_ptr(gptr
);
397 tcg_temp_free_i32(t
);
400 /* For each element size, the bits within a predicate word that are active. */
401 const uint64_t pred_esz_masks
[4] = {
402 0xffffffffffffffffull
, 0x5555555555555555ull
,
403 0x1111111111111111ull
, 0x0101010101010101ull
407 *** SVE Logical - Unpredicated Group
410 TRANS_FEAT(AND_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_and
, a
)
411 TRANS_FEAT(ORR_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_or
, a
)
412 TRANS_FEAT(EOR_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_xor
, a
)
413 TRANS_FEAT(BIC_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_andc
, a
)
415 static void gen_xar8_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, int64_t sh
)
417 TCGv_i64 t
= tcg_temp_new_i64();
418 uint64_t mask
= dup_const(MO_8
, 0xff >> sh
);
420 tcg_gen_xor_i64(t
, n
, m
);
421 tcg_gen_shri_i64(d
, t
, sh
);
422 tcg_gen_shli_i64(t
, t
, 8 - sh
);
423 tcg_gen_andi_i64(d
, d
, mask
);
424 tcg_gen_andi_i64(t
, t
, ~mask
);
425 tcg_gen_or_i64(d
, d
, t
);
426 tcg_temp_free_i64(t
);
429 static void gen_xar16_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, int64_t sh
)
431 TCGv_i64 t
= tcg_temp_new_i64();
432 uint64_t mask
= dup_const(MO_16
, 0xffff >> sh
);
434 tcg_gen_xor_i64(t
, n
, m
);
435 tcg_gen_shri_i64(d
, t
, sh
);
436 tcg_gen_shli_i64(t
, t
, 16 - sh
);
437 tcg_gen_andi_i64(d
, d
, mask
);
438 tcg_gen_andi_i64(t
, t
, ~mask
);
439 tcg_gen_or_i64(d
, d
, t
);
440 tcg_temp_free_i64(t
);
443 static void gen_xar_i32(TCGv_i32 d
, TCGv_i32 n
, TCGv_i32 m
, int32_t sh
)
445 tcg_gen_xor_i32(d
, n
, m
);
446 tcg_gen_rotri_i32(d
, d
, sh
);
449 static void gen_xar_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, int64_t sh
)
451 tcg_gen_xor_i64(d
, n
, m
);
452 tcg_gen_rotri_i64(d
, d
, sh
);
455 static void gen_xar_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
,
456 TCGv_vec m
, int64_t sh
)
458 tcg_gen_xor_vec(vece
, d
, n
, m
);
459 tcg_gen_rotri_vec(vece
, d
, d
, sh
);
462 void gen_gvec_xar(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
463 uint32_t rm_ofs
, int64_t shift
,
464 uint32_t opr_sz
, uint32_t max_sz
)
466 static const TCGOpcode vecop
[] = { INDEX_op_rotli_vec
, 0 };
467 static const GVecGen3i ops
[4] = {
468 { .fni8
= gen_xar8_i64
,
470 .fno
= gen_helper_sve2_xar_b
,
473 { .fni8
= gen_xar16_i64
,
475 .fno
= gen_helper_sve2_xar_h
,
478 { .fni4
= gen_xar_i32
,
480 .fno
= gen_helper_sve2_xar_s
,
483 { .fni8
= gen_xar_i64
,
485 .fno
= gen_helper_gvec_xar_d
,
489 int esize
= 8 << vece
;
491 /* The SVE2 range is 1 .. esize; the AdvSIMD range is 0 .. esize-1. */
492 tcg_debug_assert(shift
>= 0);
493 tcg_debug_assert(shift
<= esize
);
497 /* xar with no rotate devolves to xor. */
498 tcg_gen_gvec_xor(vece
, rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
);
500 tcg_gen_gvec_3i(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
,
505 static bool trans_XAR(DisasContext
*s
, arg_rrri_esz
*a
)
507 if (a
->esz
< 0 || !dc_isar_feature(aa64_sve2
, s
)) {
510 if (sve_access_check(s
)) {
511 unsigned vsz
= vec_full_reg_size(s
);
512 gen_gvec_xar(a
->esz
, vec_full_reg_offset(s
, a
->rd
),
513 vec_full_reg_offset(s
, a
->rn
),
514 vec_full_reg_offset(s
, a
->rm
), a
->imm
, vsz
, vsz
);
519 static void gen_eor3_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, TCGv_i64 k
)
521 tcg_gen_xor_i64(d
, n
, m
);
522 tcg_gen_xor_i64(d
, d
, k
);
525 static void gen_eor3_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
,
526 TCGv_vec m
, TCGv_vec k
)
528 tcg_gen_xor_vec(vece
, d
, n
, m
);
529 tcg_gen_xor_vec(vece
, d
, d
, k
);
532 static void gen_eor3(unsigned vece
, uint32_t d
, uint32_t n
, uint32_t m
,
533 uint32_t a
, uint32_t oprsz
, uint32_t maxsz
)
535 static const GVecGen4 op
= {
536 .fni8
= gen_eor3_i64
,
537 .fniv
= gen_eor3_vec
,
538 .fno
= gen_helper_sve2_eor3
,
540 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
542 tcg_gen_gvec_4(d
, n
, m
, a
, oprsz
, maxsz
, &op
);
545 TRANS_FEAT(EOR3
, aa64_sve2
, gen_gvec_fn_arg_zzzz
, gen_eor3
, a
)
547 static void gen_bcax_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, TCGv_i64 k
)
549 tcg_gen_andc_i64(d
, m
, k
);
550 tcg_gen_xor_i64(d
, d
, n
);
553 static void gen_bcax_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
,
554 TCGv_vec m
, TCGv_vec k
)
556 tcg_gen_andc_vec(vece
, d
, m
, k
);
557 tcg_gen_xor_vec(vece
, d
, d
, n
);
560 static void gen_bcax(unsigned vece
, uint32_t d
, uint32_t n
, uint32_t m
,
561 uint32_t a
, uint32_t oprsz
, uint32_t maxsz
)
563 static const GVecGen4 op
= {
564 .fni8
= gen_bcax_i64
,
565 .fniv
= gen_bcax_vec
,
566 .fno
= gen_helper_sve2_bcax
,
568 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
570 tcg_gen_gvec_4(d
, n
, m
, a
, oprsz
, maxsz
, &op
);
573 TRANS_FEAT(BCAX
, aa64_sve2
, gen_gvec_fn_arg_zzzz
, gen_bcax
, a
)
575 static void gen_bsl(unsigned vece
, uint32_t d
, uint32_t n
, uint32_t m
,
576 uint32_t a
, uint32_t oprsz
, uint32_t maxsz
)
578 /* BSL differs from the generic bitsel in argument ordering. */
579 tcg_gen_gvec_bitsel(vece
, d
, a
, n
, m
, oprsz
, maxsz
);
582 TRANS_FEAT(BSL
, aa64_sve2
, gen_gvec_fn_arg_zzzz
, gen_bsl
, a
)
584 static void gen_bsl1n_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, TCGv_i64 k
)
586 tcg_gen_andc_i64(n
, k
, n
);
587 tcg_gen_andc_i64(m
, m
, k
);
588 tcg_gen_or_i64(d
, n
, m
);
591 static void gen_bsl1n_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
,
592 TCGv_vec m
, TCGv_vec k
)
594 if (TCG_TARGET_HAS_bitsel_vec
) {
595 tcg_gen_not_vec(vece
, n
, n
);
596 tcg_gen_bitsel_vec(vece
, d
, k
, n
, m
);
598 tcg_gen_andc_vec(vece
, n
, k
, n
);
599 tcg_gen_andc_vec(vece
, m
, m
, k
);
600 tcg_gen_or_vec(vece
, d
, n
, m
);
604 static void gen_bsl1n(unsigned vece
, uint32_t d
, uint32_t n
, uint32_t m
,
605 uint32_t a
, uint32_t oprsz
, uint32_t maxsz
)
607 static const GVecGen4 op
= {
608 .fni8
= gen_bsl1n_i64
,
609 .fniv
= gen_bsl1n_vec
,
610 .fno
= gen_helper_sve2_bsl1n
,
612 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
614 tcg_gen_gvec_4(d
, n
, m
, a
, oprsz
, maxsz
, &op
);
617 TRANS_FEAT(BSL1N
, aa64_sve2
, gen_gvec_fn_arg_zzzz
, gen_bsl1n
, a
)
619 static void gen_bsl2n_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, TCGv_i64 k
)
622 * Z[dn] = (n & k) | (~m & ~k)
625 tcg_gen_and_i64(n
, n
, k
);
626 if (TCG_TARGET_HAS_orc_i64
) {
627 tcg_gen_or_i64(m
, m
, k
);
628 tcg_gen_orc_i64(d
, n
, m
);
630 tcg_gen_nor_i64(m
, m
, k
);
631 tcg_gen_or_i64(d
, n
, m
);
635 static void gen_bsl2n_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
,
636 TCGv_vec m
, TCGv_vec k
)
638 if (TCG_TARGET_HAS_bitsel_vec
) {
639 tcg_gen_not_vec(vece
, m
, m
);
640 tcg_gen_bitsel_vec(vece
, d
, k
, n
, m
);
642 tcg_gen_and_vec(vece
, n
, n
, k
);
643 tcg_gen_or_vec(vece
, m
, m
, k
);
644 tcg_gen_orc_vec(vece
, d
, n
, m
);
648 static void gen_bsl2n(unsigned vece
, uint32_t d
, uint32_t n
, uint32_t m
,
649 uint32_t a
, uint32_t oprsz
, uint32_t maxsz
)
651 static const GVecGen4 op
= {
652 .fni8
= gen_bsl2n_i64
,
653 .fniv
= gen_bsl2n_vec
,
654 .fno
= gen_helper_sve2_bsl2n
,
656 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
658 tcg_gen_gvec_4(d
, n
, m
, a
, oprsz
, maxsz
, &op
);
661 TRANS_FEAT(BSL2N
, aa64_sve2
, gen_gvec_fn_arg_zzzz
, gen_bsl2n
, a
)
663 static void gen_nbsl_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
, TCGv_i64 k
)
665 tcg_gen_and_i64(n
, n
, k
);
666 tcg_gen_andc_i64(m
, m
, k
);
667 tcg_gen_nor_i64(d
, n
, m
);
670 static void gen_nbsl_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
,
671 TCGv_vec m
, TCGv_vec k
)
673 tcg_gen_bitsel_vec(vece
, d
, k
, n
, m
);
674 tcg_gen_not_vec(vece
, d
, d
);
677 static void gen_nbsl(unsigned vece
, uint32_t d
, uint32_t n
, uint32_t m
,
678 uint32_t a
, uint32_t oprsz
, uint32_t maxsz
)
680 static const GVecGen4 op
= {
681 .fni8
= gen_nbsl_i64
,
682 .fniv
= gen_nbsl_vec
,
683 .fno
= gen_helper_sve2_nbsl
,
685 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
687 tcg_gen_gvec_4(d
, n
, m
, a
, oprsz
, maxsz
, &op
);
690 TRANS_FEAT(NBSL
, aa64_sve2
, gen_gvec_fn_arg_zzzz
, gen_nbsl
, a
)
693 *** SVE Integer Arithmetic - Unpredicated Group
696 TRANS_FEAT(ADD_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_add
, a
)
697 TRANS_FEAT(SUB_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_sub
, a
)
698 TRANS_FEAT(SQADD_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_ssadd
, a
)
699 TRANS_FEAT(SQSUB_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_sssub
, a
)
700 TRANS_FEAT(UQADD_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_usadd
, a
)
701 TRANS_FEAT(UQSUB_zzz
, aa64_sve
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_ussub
, a
)
704 *** SVE Integer Arithmetic - Binary Predicated Group
707 /* Select active elememnts from Zn and inactive elements from Zm,
708 * storing the result in Zd.
710 static bool do_sel_z(DisasContext
*s
, int rd
, int rn
, int rm
, int pg
, int esz
)
712 static gen_helper_gvec_4
* const fns
[4] = {
713 gen_helper_sve_sel_zpzz_b
, gen_helper_sve_sel_zpzz_h
,
714 gen_helper_sve_sel_zpzz_s
, gen_helper_sve_sel_zpzz_d
716 return gen_gvec_ool_zzzp(s
, fns
[esz
], rd
, rn
, rm
, pg
, 0);
719 #define DO_ZPZZ(NAME, FEAT, name) \
720 static gen_helper_gvec_4 * const name##_zpzz_fns[4] = { \
721 gen_helper_##name##_zpzz_b, gen_helper_##name##_zpzz_h, \
722 gen_helper_##name##_zpzz_s, gen_helper_##name##_zpzz_d, \
724 TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \
725 name##_zpzz_fns[a->esz], a, 0)
727 DO_ZPZZ(AND_zpzz
, aa64_sve
, sve_and
)
728 DO_ZPZZ(EOR_zpzz
, aa64_sve
, sve_eor
)
729 DO_ZPZZ(ORR_zpzz
, aa64_sve
, sve_orr
)
730 DO_ZPZZ(BIC_zpzz
, aa64_sve
, sve_bic
)
732 DO_ZPZZ(ADD_zpzz
, aa64_sve
, sve_add
)
733 DO_ZPZZ(SUB_zpzz
, aa64_sve
, sve_sub
)
735 DO_ZPZZ(SMAX_zpzz
, aa64_sve
, sve_smax
)
736 DO_ZPZZ(UMAX_zpzz
, aa64_sve
, sve_umax
)
737 DO_ZPZZ(SMIN_zpzz
, aa64_sve
, sve_smin
)
738 DO_ZPZZ(UMIN_zpzz
, aa64_sve
, sve_umin
)
739 DO_ZPZZ(SABD_zpzz
, aa64_sve
, sve_sabd
)
740 DO_ZPZZ(UABD_zpzz
, aa64_sve
, sve_uabd
)
742 DO_ZPZZ(MUL_zpzz
, aa64_sve
, sve_mul
)
743 DO_ZPZZ(SMULH_zpzz
, aa64_sve
, sve_smulh
)
744 DO_ZPZZ(UMULH_zpzz
, aa64_sve
, sve_umulh
)
746 DO_ZPZZ(ASR_zpzz
, aa64_sve
, sve_asr
)
747 DO_ZPZZ(LSR_zpzz
, aa64_sve
, sve_lsr
)
748 DO_ZPZZ(LSL_zpzz
, aa64_sve
, sve_lsl
)
750 static gen_helper_gvec_4
* const sdiv_fns
[4] = {
751 NULL
, NULL
, gen_helper_sve_sdiv_zpzz_s
, gen_helper_sve_sdiv_zpzz_d
753 TRANS_FEAT(SDIV_zpzz
, aa64_sve
, gen_gvec_ool_arg_zpzz
, sdiv_fns
[a
->esz
], a
, 0)
755 static gen_helper_gvec_4
* const udiv_fns
[4] = {
756 NULL
, NULL
, gen_helper_sve_udiv_zpzz_s
, gen_helper_sve_udiv_zpzz_d
758 TRANS_FEAT(UDIV_zpzz
, aa64_sve
, gen_gvec_ool_arg_zpzz
, udiv_fns
[a
->esz
], a
, 0)
760 static bool trans_SEL_zpzz(DisasContext
*s
, arg_rprr_esz
*a
)
762 return do_sel_z(s
, a
->rd
, a
->rn
, a
->rm
, a
->pg
, a
->esz
);
766 *** SVE Integer Arithmetic - Unary Predicated Group
769 #define DO_ZPZ(NAME, FEAT, name) \
770 static gen_helper_gvec_3 * const name##_fns[4] = { \
771 gen_helper_##name##_b, gen_helper_##name##_h, \
772 gen_helper_##name##_s, gen_helper_##name##_d, \
774 TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0)
776 DO_ZPZ(CLS
, aa64_sve
, sve_cls
)
777 DO_ZPZ(CLZ
, aa64_sve
, sve_clz
)
778 DO_ZPZ(CNT_zpz
, aa64_sve
, sve_cnt_zpz
)
779 DO_ZPZ(CNOT
, aa64_sve
, sve_cnot
)
780 DO_ZPZ(NOT_zpz
, aa64_sve
, sve_not_zpz
)
781 DO_ZPZ(ABS
, aa64_sve
, sve_abs
)
782 DO_ZPZ(NEG
, aa64_sve
, sve_neg
)
783 DO_ZPZ(RBIT
, aa64_sve
, sve_rbit
)
785 static gen_helper_gvec_3
* const fabs_fns
[4] = {
786 NULL
, gen_helper_sve_fabs_h
,
787 gen_helper_sve_fabs_s
, gen_helper_sve_fabs_d
,
789 TRANS_FEAT(FABS
, aa64_sve
, gen_gvec_ool_arg_zpz
, fabs_fns
[a
->esz
], a
, 0)
791 static gen_helper_gvec_3
* const fneg_fns
[4] = {
792 NULL
, gen_helper_sve_fneg_h
,
793 gen_helper_sve_fneg_s
, gen_helper_sve_fneg_d
,
795 TRANS_FEAT(FNEG
, aa64_sve
, gen_gvec_ool_arg_zpz
, fneg_fns
[a
->esz
], a
, 0)
797 static gen_helper_gvec_3
* const sxtb_fns
[4] = {
798 NULL
, gen_helper_sve_sxtb_h
,
799 gen_helper_sve_sxtb_s
, gen_helper_sve_sxtb_d
,
801 TRANS_FEAT(SXTB
, aa64_sve
, gen_gvec_ool_arg_zpz
, sxtb_fns
[a
->esz
], a
, 0)
803 static gen_helper_gvec_3
* const uxtb_fns
[4] = {
804 NULL
, gen_helper_sve_uxtb_h
,
805 gen_helper_sve_uxtb_s
, gen_helper_sve_uxtb_d
,
807 TRANS_FEAT(UXTB
, aa64_sve
, gen_gvec_ool_arg_zpz
, uxtb_fns
[a
->esz
], a
, 0)
809 static gen_helper_gvec_3
* const sxth_fns
[4] = {
810 NULL
, NULL
, gen_helper_sve_sxth_s
, gen_helper_sve_sxth_d
812 TRANS_FEAT(SXTH
, aa64_sve
, gen_gvec_ool_arg_zpz
, sxth_fns
[a
->esz
], a
, 0)
814 static gen_helper_gvec_3
* const uxth_fns
[4] = {
815 NULL
, NULL
, gen_helper_sve_uxth_s
, gen_helper_sve_uxth_d
817 TRANS_FEAT(UXTH
, aa64_sve
, gen_gvec_ool_arg_zpz
, uxth_fns
[a
->esz
], a
, 0)
819 TRANS_FEAT(SXTW
, aa64_sve
, gen_gvec_ool_arg_zpz
,
820 a
->esz
== 3 ? gen_helper_sve_sxtw_d
: NULL
, a
, 0)
821 TRANS_FEAT(UXTW
, aa64_sve
, gen_gvec_ool_arg_zpz
,
822 a
->esz
== 3 ? gen_helper_sve_uxtw_d
: NULL
, a
, 0)
825 *** SVE Integer Reduction Group
828 typedef void gen_helper_gvec_reduc(TCGv_i64
, TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
829 static bool do_vpz_ool(DisasContext
*s
, arg_rpr_esz
*a
,
830 gen_helper_gvec_reduc
*fn
)
832 unsigned vsz
= vec_full_reg_size(s
);
840 if (!sve_access_check(s
)) {
844 desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, 0));
845 temp
= tcg_temp_new_i64();
846 t_zn
= tcg_temp_new_ptr();
847 t_pg
= tcg_temp_new_ptr();
849 tcg_gen_addi_ptr(t_zn
, cpu_env
, vec_full_reg_offset(s
, a
->rn
));
850 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
851 fn(temp
, t_zn
, t_pg
, desc
);
852 tcg_temp_free_ptr(t_zn
);
853 tcg_temp_free_ptr(t_pg
);
855 write_fp_dreg(s
, a
->rd
, temp
);
856 tcg_temp_free_i64(temp
);
860 #define DO_VPZ(NAME, name) \
861 static gen_helper_gvec_reduc * const name##_fns[4] = { \
862 gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
863 gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
865 TRANS_FEAT(NAME, aa64_sve, do_vpz_ool, a, name##_fns[a->esz])
877 static gen_helper_gvec_reduc
* const saddv_fns
[4] = {
878 gen_helper_sve_saddv_b
, gen_helper_sve_saddv_h
,
879 gen_helper_sve_saddv_s
, NULL
881 TRANS_FEAT(SADDV
, aa64_sve
, do_vpz_ool
, a
, saddv_fns
[a
->esz
])
886 *** SVE Shift by Immediate - Predicated Group
890 * Copy Zn into Zd, storing zeros into inactive elements.
891 * If invert, store zeros into the active elements.
893 static bool do_movz_zpz(DisasContext
*s
, int rd
, int rn
, int pg
,
894 int esz
, bool invert
)
896 static gen_helper_gvec_3
* const fns
[4] = {
897 gen_helper_sve_movz_b
, gen_helper_sve_movz_h
,
898 gen_helper_sve_movz_s
, gen_helper_sve_movz_d
,
900 return gen_gvec_ool_zzp(s
, fns
[esz
], rd
, rn
, pg
, invert
);
903 static bool do_shift_zpzi(DisasContext
*s
, arg_rpri_esz
*a
, bool asr
,
904 gen_helper_gvec_3
* const fns
[4])
909 /* Invalid tsz encoding -- see tszimm_esz. */
914 * Shift by element size is architecturally valid.
915 * For arithmetic right-shift, it's the same as by one less.
916 * For logical shifts and ASRD, it is a zeroing operation.
923 return do_movz_zpz(s
, a
->rd
, a
->rd
, a
->pg
, a
->esz
, true);
926 return gen_gvec_ool_arg_zpzi(s
, fns
[a
->esz
], a
);
929 static gen_helper_gvec_3
* const asr_zpzi_fns
[4] = {
930 gen_helper_sve_asr_zpzi_b
, gen_helper_sve_asr_zpzi_h
,
931 gen_helper_sve_asr_zpzi_s
, gen_helper_sve_asr_zpzi_d
,
933 TRANS_FEAT(ASR_zpzi
, aa64_sve
, do_shift_zpzi
, a
, true, asr_zpzi_fns
)
935 static gen_helper_gvec_3
* const lsr_zpzi_fns
[4] = {
936 gen_helper_sve_lsr_zpzi_b
, gen_helper_sve_lsr_zpzi_h
,
937 gen_helper_sve_lsr_zpzi_s
, gen_helper_sve_lsr_zpzi_d
,
939 TRANS_FEAT(LSR_zpzi
, aa64_sve
, do_shift_zpzi
, a
, false, lsr_zpzi_fns
)
941 static gen_helper_gvec_3
* const lsl_zpzi_fns
[4] = {
942 gen_helper_sve_lsl_zpzi_b
, gen_helper_sve_lsl_zpzi_h
,
943 gen_helper_sve_lsl_zpzi_s
, gen_helper_sve_lsl_zpzi_d
,
945 TRANS_FEAT(LSL_zpzi
, aa64_sve
, do_shift_zpzi
, a
, false, lsl_zpzi_fns
)
947 static gen_helper_gvec_3
* const asrd_fns
[4] = {
948 gen_helper_sve_asrd_b
, gen_helper_sve_asrd_h
,
949 gen_helper_sve_asrd_s
, gen_helper_sve_asrd_d
,
951 TRANS_FEAT(ASRD
, aa64_sve
, do_shift_zpzi
, a
, false, asrd_fns
)
953 static gen_helper_gvec_3
* const sqshl_zpzi_fns
[4] = {
954 gen_helper_sve2_sqshl_zpzi_b
, gen_helper_sve2_sqshl_zpzi_h
,
955 gen_helper_sve2_sqshl_zpzi_s
, gen_helper_sve2_sqshl_zpzi_d
,
957 TRANS_FEAT(SQSHL_zpzi
, aa64_sve2
, gen_gvec_ool_arg_zpzi
,
958 a
->esz
< 0 ? NULL
: sqshl_zpzi_fns
[a
->esz
], a
)
960 static gen_helper_gvec_3
* const uqshl_zpzi_fns
[4] = {
961 gen_helper_sve2_uqshl_zpzi_b
, gen_helper_sve2_uqshl_zpzi_h
,
962 gen_helper_sve2_uqshl_zpzi_s
, gen_helper_sve2_uqshl_zpzi_d
,
964 TRANS_FEAT(UQSHL_zpzi
, aa64_sve2
, gen_gvec_ool_arg_zpzi
,
965 a
->esz
< 0 ? NULL
: uqshl_zpzi_fns
[a
->esz
], a
)
967 static gen_helper_gvec_3
* const srshr_fns
[4] = {
968 gen_helper_sve2_srshr_b
, gen_helper_sve2_srshr_h
,
969 gen_helper_sve2_srshr_s
, gen_helper_sve2_srshr_d
,
971 TRANS_FEAT(SRSHR
, aa64_sve2
, gen_gvec_ool_arg_zpzi
,
972 a
->esz
< 0 ? NULL
: srshr_fns
[a
->esz
], a
)
974 static gen_helper_gvec_3
* const urshr_fns
[4] = {
975 gen_helper_sve2_urshr_b
, gen_helper_sve2_urshr_h
,
976 gen_helper_sve2_urshr_s
, gen_helper_sve2_urshr_d
,
978 TRANS_FEAT(URSHR
, aa64_sve2
, gen_gvec_ool_arg_zpzi
,
979 a
->esz
< 0 ? NULL
: urshr_fns
[a
->esz
], a
)
981 static gen_helper_gvec_3
* const sqshlu_fns
[4] = {
982 gen_helper_sve2_sqshlu_b
, gen_helper_sve2_sqshlu_h
,
983 gen_helper_sve2_sqshlu_s
, gen_helper_sve2_sqshlu_d
,
985 TRANS_FEAT(SQSHLU
, aa64_sve2
, gen_gvec_ool_arg_zpzi
,
986 a
->esz
< 0 ? NULL
: sqshlu_fns
[a
->esz
], a
)
989 *** SVE Bitwise Shift - Predicated Group
992 #define DO_ZPZW(NAME, name) \
993 static gen_helper_gvec_4 * const name##_zpzw_fns[4] = { \
994 gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \
995 gen_helper_sve_##name##_zpzw_s, NULL \
997 TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \
998 a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0)
1007 *** SVE Bitwise Shift - Unpredicated Group
1010 static bool do_shift_imm(DisasContext
*s
, arg_rri_esz
*a
, bool asr
,
1011 void (*gvec_fn
)(unsigned, uint32_t, uint32_t,
1012 int64_t, uint32_t, uint32_t))
1015 /* Invalid tsz encoding -- see tszimm_esz. */
1018 if (sve_access_check(s
)) {
1019 unsigned vsz
= vec_full_reg_size(s
);
1020 /* Shift by element size is architecturally valid. For
1021 arithmetic right-shift, it's the same as by one less.
1022 Otherwise it is a zeroing operation. */
1023 if (a
->imm
>= 8 << a
->esz
) {
1025 a
->imm
= (8 << a
->esz
) - 1;
1027 do_dupi_z(s
, a
->rd
, 0);
1031 gvec_fn(a
->esz
, vec_full_reg_offset(s
, a
->rd
),
1032 vec_full_reg_offset(s
, a
->rn
), a
->imm
, vsz
, vsz
);
1037 TRANS_FEAT(ASR_zzi
, aa64_sve
, do_shift_imm
, a
, true, tcg_gen_gvec_sari
)
1038 TRANS_FEAT(LSR_zzi
, aa64_sve
, do_shift_imm
, a
, false, tcg_gen_gvec_shri
)
1039 TRANS_FEAT(LSL_zzi
, aa64_sve
, do_shift_imm
, a
, false, tcg_gen_gvec_shli
)
1041 #define DO_ZZW(NAME, name) \
1042 static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \
1043 gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \
1044 gen_helper_sve_##name##_zzw_s, NULL \
1046 TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \
1047 name##_zzw_fns[a->esz], a, 0)
1049 DO_ZZW(ASR_zzw
, asr
)
1050 DO_ZZW(LSR_zzw
, lsr
)
1051 DO_ZZW(LSL_zzw
, lsl
)
1056 *** SVE Integer Multiply-Add Group
1059 static bool do_zpzzz_ool(DisasContext
*s
, arg_rprrr_esz
*a
,
1060 gen_helper_gvec_5
*fn
)
1062 if (sve_access_check(s
)) {
1063 unsigned vsz
= vec_full_reg_size(s
);
1064 tcg_gen_gvec_5_ool(vec_full_reg_offset(s
, a
->rd
),
1065 vec_full_reg_offset(s
, a
->ra
),
1066 vec_full_reg_offset(s
, a
->rn
),
1067 vec_full_reg_offset(s
, a
->rm
),
1068 pred_full_reg_offset(s
, a
->pg
),
1074 static gen_helper_gvec_5
* const mla_fns
[4] = {
1075 gen_helper_sve_mla_b
, gen_helper_sve_mla_h
,
1076 gen_helper_sve_mla_s
, gen_helper_sve_mla_d
,
1078 TRANS_FEAT(MLA
, aa64_sve
, do_zpzzz_ool
, a
, mla_fns
[a
->esz
])
1080 static gen_helper_gvec_5
* const mls_fns
[4] = {
1081 gen_helper_sve_mls_b
, gen_helper_sve_mls_h
,
1082 gen_helper_sve_mls_s
, gen_helper_sve_mls_d
,
1084 TRANS_FEAT(MLS
, aa64_sve
, do_zpzzz_ool
, a
, mls_fns
[a
->esz
])
1087 *** SVE Index Generation Group
1090 static bool do_index(DisasContext
*s
, int esz
, int rd
,
1091 TCGv_i64 start
, TCGv_i64 incr
)
1097 if (!sve_access_check(s
)) {
1101 vsz
= vec_full_reg_size(s
);
1102 desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, 0));
1103 t_zd
= tcg_temp_new_ptr();
1105 tcg_gen_addi_ptr(t_zd
, cpu_env
, vec_full_reg_offset(s
, rd
));
1107 gen_helper_sve_index_d(t_zd
, start
, incr
, desc
);
1109 typedef void index_fn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
1110 static index_fn
* const fns
[3] = {
1111 gen_helper_sve_index_b
,
1112 gen_helper_sve_index_h
,
1113 gen_helper_sve_index_s
,
1115 TCGv_i32 s32
= tcg_temp_new_i32();
1116 TCGv_i32 i32
= tcg_temp_new_i32();
1118 tcg_gen_extrl_i64_i32(s32
, start
);
1119 tcg_gen_extrl_i64_i32(i32
, incr
);
1120 fns
[esz
](t_zd
, s32
, i32
, desc
);
1122 tcg_temp_free_i32(s32
);
1123 tcg_temp_free_i32(i32
);
1125 tcg_temp_free_ptr(t_zd
);
1129 TRANS_FEAT(INDEX_ii
, aa64_sve
, do_index
, a
->esz
, a
->rd
,
1130 tcg_constant_i64(a
->imm1
), tcg_constant_i64(a
->imm2
))
1131 TRANS_FEAT(INDEX_ir
, aa64_sve
, do_index
, a
->esz
, a
->rd
,
1132 tcg_constant_i64(a
->imm
), cpu_reg(s
, a
->rm
))
1133 TRANS_FEAT(INDEX_ri
, aa64_sve
, do_index
, a
->esz
, a
->rd
,
1134 cpu_reg(s
, a
->rn
), tcg_constant_i64(a
->imm
))
1135 TRANS_FEAT(INDEX_rr
, aa64_sve
, do_index
, a
->esz
, a
->rd
,
1136 cpu_reg(s
, a
->rn
), cpu_reg(s
, a
->rm
))
1139 *** SVE Stack Allocation Group
1142 static bool trans_ADDVL(DisasContext
*s
, arg_ADDVL
*a
)
1144 if (sve_access_check(s
)) {
1145 TCGv_i64 rd
= cpu_reg_sp(s
, a
->rd
);
1146 TCGv_i64 rn
= cpu_reg_sp(s
, a
->rn
);
1147 tcg_gen_addi_i64(rd
, rn
, a
->imm
* vec_full_reg_size(s
));
1152 static bool trans_ADDPL(DisasContext
*s
, arg_ADDPL
*a
)
1154 if (sve_access_check(s
)) {
1155 TCGv_i64 rd
= cpu_reg_sp(s
, a
->rd
);
1156 TCGv_i64 rn
= cpu_reg_sp(s
, a
->rn
);
1157 tcg_gen_addi_i64(rd
, rn
, a
->imm
* pred_full_reg_size(s
));
1162 static bool trans_RDVL(DisasContext
*s
, arg_RDVL
*a
)
1164 if (sve_access_check(s
)) {
1165 TCGv_i64 reg
= cpu_reg(s
, a
->rd
);
1166 tcg_gen_movi_i64(reg
, a
->imm
* vec_full_reg_size(s
));
1172 *** SVE Compute Vector Address Group
1175 static bool do_adr(DisasContext
*s
, arg_rrri
*a
, gen_helper_gvec_3
*fn
)
1177 return gen_gvec_ool_zzz(s
, fn
, a
->rd
, a
->rn
, a
->rm
, a
->imm
);
1180 TRANS_FEAT(ADR_p32
, aa64_sve
, do_adr
, a
, gen_helper_sve_adr_p32
)
1181 TRANS_FEAT(ADR_p64
, aa64_sve
, do_adr
, a
, gen_helper_sve_adr_p64
)
1182 TRANS_FEAT(ADR_s32
, aa64_sve
, do_adr
, a
, gen_helper_sve_adr_s32
)
1183 TRANS_FEAT(ADR_u32
, aa64_sve
, do_adr
, a
, gen_helper_sve_adr_u32
)
1186 *** SVE Integer Misc - Unpredicated Group
1189 static gen_helper_gvec_2
* const fexpa_fns
[4] = {
1190 NULL
, gen_helper_sve_fexpa_h
,
1191 gen_helper_sve_fexpa_s
, gen_helper_sve_fexpa_d
,
1193 TRANS_FEAT(FEXPA
, aa64_sve
, gen_gvec_ool_zz
,
1194 fexpa_fns
[a
->esz
], a
->rd
, a
->rn
, 0)
1196 static gen_helper_gvec_3
* const ftssel_fns
[4] = {
1197 NULL
, gen_helper_sve_ftssel_h
,
1198 gen_helper_sve_ftssel_s
, gen_helper_sve_ftssel_d
,
1200 TRANS_FEAT(FTSSEL
, aa64_sve
, gen_gvec_ool_arg_zzz
, ftssel_fns
[a
->esz
], a
, 0)
1203 *** SVE Predicate Logical Operations Group
1206 static bool do_pppp_flags(DisasContext
*s
, arg_rprr_s
*a
,
1207 const GVecGen4
*gvec_op
)
1209 if (!sve_access_check(s
)) {
1213 unsigned psz
= pred_gvec_reg_size(s
);
1214 int dofs
= pred_full_reg_offset(s
, a
->rd
);
1215 int nofs
= pred_full_reg_offset(s
, a
->rn
);
1216 int mofs
= pred_full_reg_offset(s
, a
->rm
);
1217 int gofs
= pred_full_reg_offset(s
, a
->pg
);
1220 tcg_gen_gvec_4(dofs
, nofs
, mofs
, gofs
, psz
, psz
, gvec_op
);
1225 /* Do the operation and the flags generation in temps. */
1226 TCGv_i64 pd
= tcg_temp_new_i64();
1227 TCGv_i64 pn
= tcg_temp_new_i64();
1228 TCGv_i64 pm
= tcg_temp_new_i64();
1229 TCGv_i64 pg
= tcg_temp_new_i64();
1231 tcg_gen_ld_i64(pn
, cpu_env
, nofs
);
1232 tcg_gen_ld_i64(pm
, cpu_env
, mofs
);
1233 tcg_gen_ld_i64(pg
, cpu_env
, gofs
);
1235 gvec_op
->fni8(pd
, pn
, pm
, pg
);
1236 tcg_gen_st_i64(pd
, cpu_env
, dofs
);
1238 do_predtest1(pd
, pg
);
1240 tcg_temp_free_i64(pd
);
1241 tcg_temp_free_i64(pn
);
1242 tcg_temp_free_i64(pm
);
1243 tcg_temp_free_i64(pg
);
1245 /* The operation and flags generation is large. The computation
1246 * of the flags depends on the original contents of the guarding
1247 * predicate. If the destination overwrites the guarding predicate,
1248 * then the easiest way to get this right is to save a copy.
1251 if (a
->rd
== a
->pg
) {
1252 tofs
= offsetof(CPUARMState
, vfp
.preg_tmp
);
1253 tcg_gen_gvec_mov(0, tofs
, gofs
, psz
, psz
);
1256 tcg_gen_gvec_4(dofs
, nofs
, mofs
, gofs
, psz
, psz
, gvec_op
);
1257 do_predtest(s
, dofs
, tofs
, psz
/ 8);
1262 static void gen_and_pg_i64(TCGv_i64 pd
, TCGv_i64 pn
, TCGv_i64 pm
, TCGv_i64 pg
)
1264 tcg_gen_and_i64(pd
, pn
, pm
);
1265 tcg_gen_and_i64(pd
, pd
, pg
);
1268 static void gen_and_pg_vec(unsigned vece
, TCGv_vec pd
, TCGv_vec pn
,
1269 TCGv_vec pm
, TCGv_vec pg
)
1271 tcg_gen_and_vec(vece
, pd
, pn
, pm
);
1272 tcg_gen_and_vec(vece
, pd
, pd
, pg
);
1275 static bool trans_AND_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1277 static const GVecGen4 op
= {
1278 .fni8
= gen_and_pg_i64
,
1279 .fniv
= gen_and_pg_vec
,
1280 .fno
= gen_helper_sve_and_pppp
,
1281 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
1285 if (!sve_access_check(s
)) {
1288 if (a
->rn
== a
->rm
) {
1289 if (a
->pg
== a
->rn
) {
1290 do_mov_p(s
, a
->rd
, a
->rn
);
1292 gen_gvec_fn_ppp(s
, tcg_gen_gvec_and
, a
->rd
, a
->rn
, a
->pg
);
1295 } else if (a
->pg
== a
->rn
|| a
->pg
== a
->rm
) {
1296 gen_gvec_fn_ppp(s
, tcg_gen_gvec_and
, a
->rd
, a
->rn
, a
->rm
);
1300 return do_pppp_flags(s
, a
, &op
);
1303 static void gen_bic_pg_i64(TCGv_i64 pd
, TCGv_i64 pn
, TCGv_i64 pm
, TCGv_i64 pg
)
1305 tcg_gen_andc_i64(pd
, pn
, pm
);
1306 tcg_gen_and_i64(pd
, pd
, pg
);
1309 static void gen_bic_pg_vec(unsigned vece
, TCGv_vec pd
, TCGv_vec pn
,
1310 TCGv_vec pm
, TCGv_vec pg
)
1312 tcg_gen_andc_vec(vece
, pd
, pn
, pm
);
1313 tcg_gen_and_vec(vece
, pd
, pd
, pg
);
1316 static bool trans_BIC_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1318 static const GVecGen4 op
= {
1319 .fni8
= gen_bic_pg_i64
,
1320 .fniv
= gen_bic_pg_vec
,
1321 .fno
= gen_helper_sve_bic_pppp
,
1322 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
1325 if (!a
->s
&& a
->pg
== a
->rn
) {
1326 if (sve_access_check(s
)) {
1327 gen_gvec_fn_ppp(s
, tcg_gen_gvec_andc
, a
->rd
, a
->rn
, a
->rm
);
1331 return do_pppp_flags(s
, a
, &op
);
1334 static void gen_eor_pg_i64(TCGv_i64 pd
, TCGv_i64 pn
, TCGv_i64 pm
, TCGv_i64 pg
)
1336 tcg_gen_xor_i64(pd
, pn
, pm
);
1337 tcg_gen_and_i64(pd
, pd
, pg
);
1340 static void gen_eor_pg_vec(unsigned vece
, TCGv_vec pd
, TCGv_vec pn
,
1341 TCGv_vec pm
, TCGv_vec pg
)
1343 tcg_gen_xor_vec(vece
, pd
, pn
, pm
);
1344 tcg_gen_and_vec(vece
, pd
, pd
, pg
);
1347 static bool trans_EOR_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1349 static const GVecGen4 op
= {
1350 .fni8
= gen_eor_pg_i64
,
1351 .fniv
= gen_eor_pg_vec
,
1352 .fno
= gen_helper_sve_eor_pppp
,
1353 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
1355 return do_pppp_flags(s
, a
, &op
);
1358 static bool trans_SEL_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1363 if (sve_access_check(s
)) {
1364 unsigned psz
= pred_gvec_reg_size(s
);
1365 tcg_gen_gvec_bitsel(MO_8
, pred_full_reg_offset(s
, a
->rd
),
1366 pred_full_reg_offset(s
, a
->pg
),
1367 pred_full_reg_offset(s
, a
->rn
),
1368 pred_full_reg_offset(s
, a
->rm
), psz
, psz
);
1373 static void gen_orr_pg_i64(TCGv_i64 pd
, TCGv_i64 pn
, TCGv_i64 pm
, TCGv_i64 pg
)
1375 tcg_gen_or_i64(pd
, pn
, pm
);
1376 tcg_gen_and_i64(pd
, pd
, pg
);
1379 static void gen_orr_pg_vec(unsigned vece
, TCGv_vec pd
, TCGv_vec pn
,
1380 TCGv_vec pm
, TCGv_vec pg
)
1382 tcg_gen_or_vec(vece
, pd
, pn
, pm
);
1383 tcg_gen_and_vec(vece
, pd
, pd
, pg
);
1386 static bool trans_ORR_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1388 static const GVecGen4 op
= {
1389 .fni8
= gen_orr_pg_i64
,
1390 .fniv
= gen_orr_pg_vec
,
1391 .fno
= gen_helper_sve_orr_pppp
,
1392 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
1395 if (!a
->s
&& a
->pg
== a
->rn
&& a
->rn
== a
->rm
) {
1396 return do_mov_p(s
, a
->rd
, a
->rn
);
1398 return do_pppp_flags(s
, a
, &op
);
1401 static void gen_orn_pg_i64(TCGv_i64 pd
, TCGv_i64 pn
, TCGv_i64 pm
, TCGv_i64 pg
)
1403 tcg_gen_orc_i64(pd
, pn
, pm
);
1404 tcg_gen_and_i64(pd
, pd
, pg
);
1407 static void gen_orn_pg_vec(unsigned vece
, TCGv_vec pd
, TCGv_vec pn
,
1408 TCGv_vec pm
, TCGv_vec pg
)
1410 tcg_gen_orc_vec(vece
, pd
, pn
, pm
);
1411 tcg_gen_and_vec(vece
, pd
, pd
, pg
);
1414 static bool trans_ORN_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1416 static const GVecGen4 op
= {
1417 .fni8
= gen_orn_pg_i64
,
1418 .fniv
= gen_orn_pg_vec
,
1419 .fno
= gen_helper_sve_orn_pppp
,
1420 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
1422 return do_pppp_flags(s
, a
, &op
);
1425 static void gen_nor_pg_i64(TCGv_i64 pd
, TCGv_i64 pn
, TCGv_i64 pm
, TCGv_i64 pg
)
1427 tcg_gen_or_i64(pd
, pn
, pm
);
1428 tcg_gen_andc_i64(pd
, pg
, pd
);
1431 static void gen_nor_pg_vec(unsigned vece
, TCGv_vec pd
, TCGv_vec pn
,
1432 TCGv_vec pm
, TCGv_vec pg
)
1434 tcg_gen_or_vec(vece
, pd
, pn
, pm
);
1435 tcg_gen_andc_vec(vece
, pd
, pg
, pd
);
1438 static bool trans_NOR_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1440 static const GVecGen4 op
= {
1441 .fni8
= gen_nor_pg_i64
,
1442 .fniv
= gen_nor_pg_vec
,
1443 .fno
= gen_helper_sve_nor_pppp
,
1444 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
1446 return do_pppp_flags(s
, a
, &op
);
1449 static void gen_nand_pg_i64(TCGv_i64 pd
, TCGv_i64 pn
, TCGv_i64 pm
, TCGv_i64 pg
)
1451 tcg_gen_and_i64(pd
, pn
, pm
);
1452 tcg_gen_andc_i64(pd
, pg
, pd
);
1455 static void gen_nand_pg_vec(unsigned vece
, TCGv_vec pd
, TCGv_vec pn
,
1456 TCGv_vec pm
, TCGv_vec pg
)
1458 tcg_gen_and_vec(vece
, pd
, pn
, pm
);
1459 tcg_gen_andc_vec(vece
, pd
, pg
, pd
);
1462 static bool trans_NAND_pppp(DisasContext
*s
, arg_rprr_s
*a
)
1464 static const GVecGen4 op
= {
1465 .fni8
= gen_nand_pg_i64
,
1466 .fniv
= gen_nand_pg_vec
,
1467 .fno
= gen_helper_sve_nand_pppp
,
1468 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
1470 return do_pppp_flags(s
, a
, &op
);
1474 *** SVE Predicate Misc Group
1477 static bool trans_PTEST(DisasContext
*s
, arg_PTEST
*a
)
1479 if (sve_access_check(s
)) {
1480 int nofs
= pred_full_reg_offset(s
, a
->rn
);
1481 int gofs
= pred_full_reg_offset(s
, a
->pg
);
1482 int words
= DIV_ROUND_UP(pred_full_reg_size(s
), 8);
1485 TCGv_i64 pn
= tcg_temp_new_i64();
1486 TCGv_i64 pg
= tcg_temp_new_i64();
1488 tcg_gen_ld_i64(pn
, cpu_env
, nofs
);
1489 tcg_gen_ld_i64(pg
, cpu_env
, gofs
);
1490 do_predtest1(pn
, pg
);
1492 tcg_temp_free_i64(pn
);
1493 tcg_temp_free_i64(pg
);
1495 do_predtest(s
, nofs
, gofs
, words
);
1501 /* See the ARM pseudocode DecodePredCount. */
1502 static unsigned decode_pred_count(unsigned fullsz
, int pattern
, int esz
)
1504 unsigned elements
= fullsz
>> esz
;
1508 case 0x0: /* POW2 */
1509 return pow2floor(elements
);
1520 case 0x9: /* VL16 */
1521 case 0xa: /* VL32 */
1522 case 0xb: /* VL64 */
1523 case 0xc: /* VL128 */
1524 case 0xd: /* VL256 */
1525 bound
= 16 << (pattern
- 9);
1527 case 0x1d: /* MUL4 */
1528 return elements
- elements
% 4;
1529 case 0x1e: /* MUL3 */
1530 return elements
- elements
% 3;
1531 case 0x1f: /* ALL */
1533 default: /* #uimm5 */
1536 return elements
>= bound
? bound
: 0;
1539 /* This handles all of the predicate initialization instructions,
1540 * PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT == 32
1541 * so that decode_pred_count returns 0. For SETFFR, we will have
1542 * set RD == 16 == FFR.
1544 static bool do_predset(DisasContext
*s
, int esz
, int rd
, int pat
, bool setflag
)
1546 if (!sve_access_check(s
)) {
1550 unsigned fullsz
= vec_full_reg_size(s
);
1551 unsigned ofs
= pred_full_reg_offset(s
, rd
);
1552 unsigned numelem
, setsz
, i
;
1553 uint64_t word
, lastword
;
1556 numelem
= decode_pred_count(fullsz
, pat
, esz
);
1558 /* Determine what we must store into each bit, and how many. */
1560 lastword
= word
= 0;
1563 setsz
= numelem
<< esz
;
1564 lastword
= word
= pred_esz_masks
[esz
];
1566 lastword
&= MAKE_64BIT_MASK(0, setsz
% 64);
1570 t
= tcg_temp_new_i64();
1572 tcg_gen_movi_i64(t
, lastword
);
1573 tcg_gen_st_i64(t
, cpu_env
, ofs
);
1577 if (word
== lastword
) {
1578 unsigned maxsz
= size_for_gvec(fullsz
/ 8);
1579 unsigned oprsz
= size_for_gvec(setsz
/ 8);
1581 if (oprsz
* 8 == setsz
) {
1582 tcg_gen_gvec_dup_imm(MO_64
, ofs
, oprsz
, maxsz
, word
);
1590 tcg_gen_movi_i64(t
, word
);
1591 for (i
= 0; i
< QEMU_ALIGN_DOWN(setsz
, 8); i
+= 8) {
1592 tcg_gen_st_i64(t
, cpu_env
, ofs
+ i
);
1594 if (lastword
!= word
) {
1595 tcg_gen_movi_i64(t
, lastword
);
1596 tcg_gen_st_i64(t
, cpu_env
, ofs
+ i
);
1600 tcg_gen_movi_i64(t
, 0);
1601 for (; i
< fullsz
; i
+= 8) {
1602 tcg_gen_st_i64(t
, cpu_env
, ofs
+ i
);
1607 tcg_temp_free_i64(t
);
1611 tcg_gen_movi_i32(cpu_NF
, -(word
!= 0));
1612 tcg_gen_movi_i32(cpu_CF
, word
== 0);
1613 tcg_gen_movi_i32(cpu_VF
, 0);
1614 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
1619 TRANS_FEAT(PTRUE
, aa64_sve
, do_predset
, a
->esz
, a
->rd
, a
->pat
, a
->s
)
1621 /* Note pat == 31 is #all, to set all elements. */
1622 TRANS_FEAT(SETFFR
, aa64_sve
, do_predset
, 0, FFR_PRED_NUM
, 31, false)
1624 /* Note pat == 32 is #unimp, to set no elements. */
1625 TRANS_FEAT(PFALSE
, aa64_sve
, do_predset
, 0, a
->rd
, 32, false)
1627 static bool trans_RDFFR_p(DisasContext
*s
, arg_RDFFR_p
*a
)
1629 /* The path through do_pppp_flags is complicated enough to want to avoid
1630 * duplication. Frob the arguments into the form of a predicated AND.
1632 arg_rprr_s alt_a
= {
1633 .rd
= a
->rd
, .pg
= a
->pg
, .s
= a
->s
,
1634 .rn
= FFR_PRED_NUM
, .rm
= FFR_PRED_NUM
,
1636 return trans_AND_pppp(s
, &alt_a
);
1639 TRANS_FEAT(RDFFR
, aa64_sve
, do_mov_p
, a
->rd
, FFR_PRED_NUM
)
1640 TRANS_FEAT(WRFFR
, aa64_sve
, do_mov_p
, FFR_PRED_NUM
, a
->rn
)
1642 static bool do_pfirst_pnext(DisasContext
*s
, arg_rr_esz
*a
,
1643 void (*gen_fn
)(TCGv_i32
, TCGv_ptr
,
1644 TCGv_ptr
, TCGv_i32
))
1646 if (!sve_access_check(s
)) {
1650 TCGv_ptr t_pd
= tcg_temp_new_ptr();
1651 TCGv_ptr t_pg
= tcg_temp_new_ptr();
1655 desc
= FIELD_DP32(desc
, PREDDESC
, OPRSZ
, pred_full_reg_size(s
));
1656 desc
= FIELD_DP32(desc
, PREDDESC
, ESZ
, a
->esz
);
1658 tcg_gen_addi_ptr(t_pd
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
1659 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, a
->rn
));
1660 t
= tcg_temp_new_i32();
1662 gen_fn(t
, t_pd
, t_pg
, tcg_constant_i32(desc
));
1663 tcg_temp_free_ptr(t_pd
);
1664 tcg_temp_free_ptr(t_pg
);
1667 tcg_temp_free_i32(t
);
1671 TRANS_FEAT(PFIRST
, aa64_sve
, do_pfirst_pnext
, a
, gen_helper_sve_pfirst
)
1672 TRANS_FEAT(PNEXT
, aa64_sve
, do_pfirst_pnext
, a
, gen_helper_sve_pnext
)
1675 *** SVE Element Count Group
1678 /* Perform an inline saturating addition of a 32-bit value within
1679 * a 64-bit register. The second operand is known to be positive,
1680 * which halves the comparisions we must perform to bound the result.
1682 static void do_sat_addsub_32(TCGv_i64 reg
, TCGv_i64 val
, bool u
, bool d
)
1686 /* Use normal 64-bit arithmetic to detect 32-bit overflow. */
1688 tcg_gen_ext32u_i64(reg
, reg
);
1690 tcg_gen_ext32s_i64(reg
, reg
);
1693 tcg_gen_sub_i64(reg
, reg
, val
);
1694 ibound
= (u
? 0 : INT32_MIN
);
1695 tcg_gen_smax_i64(reg
, reg
, tcg_constant_i64(ibound
));
1697 tcg_gen_add_i64(reg
, reg
, val
);
1698 ibound
= (u
? UINT32_MAX
: INT32_MAX
);
1699 tcg_gen_smin_i64(reg
, reg
, tcg_constant_i64(ibound
));
1703 /* Similarly with 64-bit values. */
1704 static void do_sat_addsub_64(TCGv_i64 reg
, TCGv_i64 val
, bool u
, bool d
)
1706 TCGv_i64 t0
= tcg_temp_new_i64();
1711 tcg_gen_sub_i64(t0
, reg
, val
);
1712 t2
= tcg_constant_i64(0);
1713 tcg_gen_movcond_i64(TCG_COND_LTU
, reg
, reg
, val
, t2
, t0
);
1715 tcg_gen_add_i64(t0
, reg
, val
);
1716 t2
= tcg_constant_i64(-1);
1717 tcg_gen_movcond_i64(TCG_COND_LTU
, reg
, t0
, reg
, t2
, t0
);
1720 TCGv_i64 t1
= tcg_temp_new_i64();
1722 /* Detect signed overflow for subtraction. */
1723 tcg_gen_xor_i64(t0
, reg
, val
);
1724 tcg_gen_sub_i64(t1
, reg
, val
);
1725 tcg_gen_xor_i64(reg
, reg
, t1
);
1726 tcg_gen_and_i64(t0
, t0
, reg
);
1728 /* Bound the result. */
1729 tcg_gen_movi_i64(reg
, INT64_MIN
);
1730 t2
= tcg_constant_i64(0);
1731 tcg_gen_movcond_i64(TCG_COND_LT
, reg
, t0
, t2
, reg
, t1
);
1733 /* Detect signed overflow for addition. */
1734 tcg_gen_xor_i64(t0
, reg
, val
);
1735 tcg_gen_add_i64(reg
, reg
, val
);
1736 tcg_gen_xor_i64(t1
, reg
, val
);
1737 tcg_gen_andc_i64(t0
, t1
, t0
);
1739 /* Bound the result. */
1740 tcg_gen_movi_i64(t1
, INT64_MAX
);
1741 t2
= tcg_constant_i64(0);
1742 tcg_gen_movcond_i64(TCG_COND_LT
, reg
, t0
, t2
, t1
, reg
);
1744 tcg_temp_free_i64(t1
);
1746 tcg_temp_free_i64(t0
);
1749 /* Similarly with a vector and a scalar operand. */
1750 static void do_sat_addsub_vec(DisasContext
*s
, int esz
, int rd
, int rn
,
1751 TCGv_i64 val
, bool u
, bool d
)
1753 unsigned vsz
= vec_full_reg_size(s
);
1754 TCGv_ptr dptr
, nptr
;
1758 dptr
= tcg_temp_new_ptr();
1759 nptr
= tcg_temp_new_ptr();
1760 tcg_gen_addi_ptr(dptr
, cpu_env
, vec_full_reg_offset(s
, rd
));
1761 tcg_gen_addi_ptr(nptr
, cpu_env
, vec_full_reg_offset(s
, rn
));
1762 desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, 0));
1766 t32
= tcg_temp_new_i32();
1767 tcg_gen_extrl_i64_i32(t32
, val
);
1769 tcg_gen_neg_i32(t32
, t32
);
1772 gen_helper_sve_uqaddi_b(dptr
, nptr
, t32
, desc
);
1774 gen_helper_sve_sqaddi_b(dptr
, nptr
, t32
, desc
);
1776 tcg_temp_free_i32(t32
);
1780 t32
= tcg_temp_new_i32();
1781 tcg_gen_extrl_i64_i32(t32
, val
);
1783 tcg_gen_neg_i32(t32
, t32
);
1786 gen_helper_sve_uqaddi_h(dptr
, nptr
, t32
, desc
);
1788 gen_helper_sve_sqaddi_h(dptr
, nptr
, t32
, desc
);
1790 tcg_temp_free_i32(t32
);
1794 t64
= tcg_temp_new_i64();
1796 tcg_gen_neg_i64(t64
, val
);
1798 tcg_gen_mov_i64(t64
, val
);
1801 gen_helper_sve_uqaddi_s(dptr
, nptr
, t64
, desc
);
1803 gen_helper_sve_sqaddi_s(dptr
, nptr
, t64
, desc
);
1805 tcg_temp_free_i64(t64
);
1811 gen_helper_sve_uqsubi_d(dptr
, nptr
, val
, desc
);
1813 gen_helper_sve_uqaddi_d(dptr
, nptr
, val
, desc
);
1816 t64
= tcg_temp_new_i64();
1817 tcg_gen_neg_i64(t64
, val
);
1818 gen_helper_sve_sqaddi_d(dptr
, nptr
, t64
, desc
);
1819 tcg_temp_free_i64(t64
);
1821 gen_helper_sve_sqaddi_d(dptr
, nptr
, val
, desc
);
1826 g_assert_not_reached();
1829 tcg_temp_free_ptr(dptr
);
1830 tcg_temp_free_ptr(nptr
);
1833 static bool trans_CNT_r(DisasContext
*s
, arg_CNT_r
*a
)
1835 if (sve_access_check(s
)) {
1836 unsigned fullsz
= vec_full_reg_size(s
);
1837 unsigned numelem
= decode_pred_count(fullsz
, a
->pat
, a
->esz
);
1838 tcg_gen_movi_i64(cpu_reg(s
, a
->rd
), numelem
* a
->imm
);
1843 static bool trans_INCDEC_r(DisasContext
*s
, arg_incdec_cnt
*a
)
1845 if (sve_access_check(s
)) {
1846 unsigned fullsz
= vec_full_reg_size(s
);
1847 unsigned numelem
= decode_pred_count(fullsz
, a
->pat
, a
->esz
);
1848 int inc
= numelem
* a
->imm
* (a
->d
? -1 : 1);
1849 TCGv_i64 reg
= cpu_reg(s
, a
->rd
);
1851 tcg_gen_addi_i64(reg
, reg
, inc
);
1856 static bool trans_SINCDEC_r_32(DisasContext
*s
, arg_incdec_cnt
*a
)
1858 if (!sve_access_check(s
)) {
1862 unsigned fullsz
= vec_full_reg_size(s
);
1863 unsigned numelem
= decode_pred_count(fullsz
, a
->pat
, a
->esz
);
1864 int inc
= numelem
* a
->imm
;
1865 TCGv_i64 reg
= cpu_reg(s
, a
->rd
);
1867 /* Use normal 64-bit arithmetic to detect 32-bit overflow. */
1870 tcg_gen_ext32u_i64(reg
, reg
);
1872 tcg_gen_ext32s_i64(reg
, reg
);
1875 do_sat_addsub_32(reg
, tcg_constant_i64(inc
), a
->u
, a
->d
);
1880 static bool trans_SINCDEC_r_64(DisasContext
*s
, arg_incdec_cnt
*a
)
1882 if (!sve_access_check(s
)) {
1886 unsigned fullsz
= vec_full_reg_size(s
);
1887 unsigned numelem
= decode_pred_count(fullsz
, a
->pat
, a
->esz
);
1888 int inc
= numelem
* a
->imm
;
1889 TCGv_i64 reg
= cpu_reg(s
, a
->rd
);
1892 do_sat_addsub_64(reg
, tcg_constant_i64(inc
), a
->u
, a
->d
);
1897 static bool trans_INCDEC_v(DisasContext
*s
, arg_incdec2_cnt
*a
)
1903 unsigned fullsz
= vec_full_reg_size(s
);
1904 unsigned numelem
= decode_pred_count(fullsz
, a
->pat
, a
->esz
);
1905 int inc
= numelem
* a
->imm
;
1908 if (sve_access_check(s
)) {
1909 tcg_gen_gvec_adds(a
->esz
, vec_full_reg_offset(s
, a
->rd
),
1910 vec_full_reg_offset(s
, a
->rn
),
1911 tcg_constant_i64(a
->d
? -inc
: inc
),
1915 do_mov_z(s
, a
->rd
, a
->rn
);
1920 static bool trans_SINCDEC_v(DisasContext
*s
, arg_incdec2_cnt
*a
)
1926 unsigned fullsz
= vec_full_reg_size(s
);
1927 unsigned numelem
= decode_pred_count(fullsz
, a
->pat
, a
->esz
);
1928 int inc
= numelem
* a
->imm
;
1931 if (sve_access_check(s
)) {
1932 do_sat_addsub_vec(s
, a
->esz
, a
->rd
, a
->rn
,
1933 tcg_constant_i64(inc
), a
->u
, a
->d
);
1936 do_mov_z(s
, a
->rd
, a
->rn
);
1942 *** SVE Bitwise Immediate Group
1945 static bool do_zz_dbm(DisasContext
*s
, arg_rr_dbm
*a
, GVecGen2iFn
*gvec_fn
)
1948 if (!logic_imm_decode_wmask(&imm
, extract32(a
->dbm
, 12, 1),
1949 extract32(a
->dbm
, 0, 6),
1950 extract32(a
->dbm
, 6, 6))) {
1953 return gen_gvec_fn_zzi(s
, gvec_fn
, MO_64
, a
->rd
, a
->rn
, imm
);
1956 TRANS_FEAT(AND_zzi
, aa64_sve
, do_zz_dbm
, a
, tcg_gen_gvec_andi
)
1957 TRANS_FEAT(ORR_zzi
, aa64_sve
, do_zz_dbm
, a
, tcg_gen_gvec_ori
)
1958 TRANS_FEAT(EOR_zzi
, aa64_sve
, do_zz_dbm
, a
, tcg_gen_gvec_xori
)
1960 static bool trans_DUPM(DisasContext
*s
, arg_DUPM
*a
)
1963 if (!logic_imm_decode_wmask(&imm
, extract32(a
->dbm
, 12, 1),
1964 extract32(a
->dbm
, 0, 6),
1965 extract32(a
->dbm
, 6, 6))) {
1968 if (sve_access_check(s
)) {
1969 do_dupi_z(s
, a
->rd
, imm
);
1975 *** SVE Integer Wide Immediate - Predicated Group
1978 /* Implement all merging copies. This is used for CPY (immediate),
1979 * FCPY, CPY (scalar), CPY (SIMD&FP scalar).
1981 static void do_cpy_m(DisasContext
*s
, int esz
, int rd
, int rn
, int pg
,
1984 typedef void gen_cpy(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
, TCGv_i64
, TCGv_i32
);
1985 static gen_cpy
* const fns
[4] = {
1986 gen_helper_sve_cpy_m_b
, gen_helper_sve_cpy_m_h
,
1987 gen_helper_sve_cpy_m_s
, gen_helper_sve_cpy_m_d
,
1989 unsigned vsz
= vec_full_reg_size(s
);
1990 TCGv_i32 desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, 0));
1991 TCGv_ptr t_zd
= tcg_temp_new_ptr();
1992 TCGv_ptr t_zn
= tcg_temp_new_ptr();
1993 TCGv_ptr t_pg
= tcg_temp_new_ptr();
1995 tcg_gen_addi_ptr(t_zd
, cpu_env
, vec_full_reg_offset(s
, rd
));
1996 tcg_gen_addi_ptr(t_zn
, cpu_env
, vec_full_reg_offset(s
, rn
));
1997 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, pg
));
1999 fns
[esz
](t_zd
, t_zn
, t_pg
, val
, desc
);
2001 tcg_temp_free_ptr(t_zd
);
2002 tcg_temp_free_ptr(t_zn
);
2003 tcg_temp_free_ptr(t_pg
);
2006 static bool trans_FCPY(DisasContext
*s
, arg_FCPY
*a
)
2011 if (sve_access_check(s
)) {
2012 /* Decode the VFP immediate. */
2013 uint64_t imm
= vfp_expand_imm(a
->esz
, a
->imm
);
2014 do_cpy_m(s
, a
->esz
, a
->rd
, a
->rn
, a
->pg
, tcg_constant_i64(imm
));
2019 static bool trans_CPY_m_i(DisasContext
*s
, arg_rpri_esz
*a
)
2021 if (a
->esz
== 0 && extract32(s
->insn
, 13, 1)) {
2024 if (sve_access_check(s
)) {
2025 do_cpy_m(s
, a
->esz
, a
->rd
, a
->rn
, a
->pg
, tcg_constant_i64(a
->imm
));
2030 static bool trans_CPY_z_i(DisasContext
*s
, arg_CPY_z_i
*a
)
2032 static gen_helper_gvec_2i
* const fns
[4] = {
2033 gen_helper_sve_cpy_z_b
, gen_helper_sve_cpy_z_h
,
2034 gen_helper_sve_cpy_z_s
, gen_helper_sve_cpy_z_d
,
2037 if (a
->esz
== 0 && extract32(s
->insn
, 13, 1)) {
2040 if (sve_access_check(s
)) {
2041 unsigned vsz
= vec_full_reg_size(s
);
2042 tcg_gen_gvec_2i_ool(vec_full_reg_offset(s
, a
->rd
),
2043 pred_full_reg_offset(s
, a
->pg
),
2044 tcg_constant_i64(a
->imm
),
2045 vsz
, vsz
, 0, fns
[a
->esz
]);
2051 *** SVE Permute Extract Group
2054 static bool do_EXT(DisasContext
*s
, int rd
, int rn
, int rm
, int imm
)
2056 if (!sve_access_check(s
)) {
2060 unsigned vsz
= vec_full_reg_size(s
);
2061 unsigned n_ofs
= imm
>= vsz
? 0 : imm
;
2062 unsigned n_siz
= vsz
- n_ofs
;
2063 unsigned d
= vec_full_reg_offset(s
, rd
);
2064 unsigned n
= vec_full_reg_offset(s
, rn
);
2065 unsigned m
= vec_full_reg_offset(s
, rm
);
2067 /* Use host vector move insns if we have appropriate sizes
2068 * and no unfortunate overlap.
2071 && n_ofs
== size_for_gvec(n_ofs
)
2072 && n_siz
== size_for_gvec(n_siz
)
2073 && (d
!= n
|| n_siz
<= n_ofs
)) {
2074 tcg_gen_gvec_mov(0, d
, n
+ n_ofs
, n_siz
, n_siz
);
2076 tcg_gen_gvec_mov(0, d
+ n_siz
, m
, n_ofs
, n_ofs
);
2079 tcg_gen_gvec_3_ool(d
, n
, m
, vsz
, vsz
, n_ofs
, gen_helper_sve_ext
);
2084 TRANS_FEAT(EXT
, aa64_sve
, do_EXT
, a
->rd
, a
->rn
, a
->rm
, a
->imm
)
2085 TRANS_FEAT(EXT_sve2
, aa64_sve2
, do_EXT
, a
->rd
, a
->rn
, (a
->rn
+ 1) % 32, a
->imm
)
2088 *** SVE Permute - Unpredicated Group
2091 static bool trans_DUP_s(DisasContext
*s
, arg_DUP_s
*a
)
2093 if (sve_access_check(s
)) {
2094 unsigned vsz
= vec_full_reg_size(s
);
2095 tcg_gen_gvec_dup_i64(a
->esz
, vec_full_reg_offset(s
, a
->rd
),
2096 vsz
, vsz
, cpu_reg_sp(s
, a
->rn
));
2101 static bool trans_DUP_x(DisasContext
*s
, arg_DUP_x
*a
)
2103 if ((a
->imm
& 0x1f) == 0) {
2106 if (sve_access_check(s
)) {
2107 unsigned vsz
= vec_full_reg_size(s
);
2108 unsigned dofs
= vec_full_reg_offset(s
, a
->rd
);
2109 unsigned esz
, index
;
2111 esz
= ctz32(a
->imm
);
2112 index
= a
->imm
>> (esz
+ 1);
2114 if ((index
<< esz
) < vsz
) {
2115 unsigned nofs
= vec_reg_offset(s
, a
->rn
, index
, esz
);
2116 tcg_gen_gvec_dup_mem(esz
, dofs
, nofs
, vsz
, vsz
);
2119 * While dup_mem handles 128-bit elements, dup_imm does not.
2120 * Thankfully element size doesn't matter for splatting zero.
2122 tcg_gen_gvec_dup_imm(MO_64
, dofs
, vsz
, vsz
, 0);
2128 static void do_insr_i64(DisasContext
*s
, arg_rrr_esz
*a
, TCGv_i64 val
)
2130 typedef void gen_insr(TCGv_ptr
, TCGv_ptr
, TCGv_i64
, TCGv_i32
);
2131 static gen_insr
* const fns
[4] = {
2132 gen_helper_sve_insr_b
, gen_helper_sve_insr_h
,
2133 gen_helper_sve_insr_s
, gen_helper_sve_insr_d
,
2135 unsigned vsz
= vec_full_reg_size(s
);
2136 TCGv_i32 desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, 0));
2137 TCGv_ptr t_zd
= tcg_temp_new_ptr();
2138 TCGv_ptr t_zn
= tcg_temp_new_ptr();
2140 tcg_gen_addi_ptr(t_zd
, cpu_env
, vec_full_reg_offset(s
, a
->rd
));
2141 tcg_gen_addi_ptr(t_zn
, cpu_env
, vec_full_reg_offset(s
, a
->rn
));
2143 fns
[a
->esz
](t_zd
, t_zn
, val
, desc
);
2145 tcg_temp_free_ptr(t_zd
);
2146 tcg_temp_free_ptr(t_zn
);
2149 static bool trans_INSR_f(DisasContext
*s
, arg_rrr_esz
*a
)
2151 if (sve_access_check(s
)) {
2152 TCGv_i64 t
= tcg_temp_new_i64();
2153 tcg_gen_ld_i64(t
, cpu_env
, vec_reg_offset(s
, a
->rm
, 0, MO_64
));
2154 do_insr_i64(s
, a
, t
);
2155 tcg_temp_free_i64(t
);
2160 static bool trans_INSR_r(DisasContext
*s
, arg_rrr_esz
*a
)
2162 if (sve_access_check(s
)) {
2163 do_insr_i64(s
, a
, cpu_reg(s
, a
->rm
));
2168 static gen_helper_gvec_2
* const rev_fns
[4] = {
2169 gen_helper_sve_rev_b
, gen_helper_sve_rev_h
,
2170 gen_helper_sve_rev_s
, gen_helper_sve_rev_d
2172 TRANS_FEAT(REV_v
, aa64_sve
, gen_gvec_ool_zz
, rev_fns
[a
->esz
], a
->rd
, a
->rn
, 0)
2174 static gen_helper_gvec_3
* const sve_tbl_fns
[4] = {
2175 gen_helper_sve_tbl_b
, gen_helper_sve_tbl_h
,
2176 gen_helper_sve_tbl_s
, gen_helper_sve_tbl_d
2178 TRANS_FEAT(TBL
, aa64_sve
, gen_gvec_ool_arg_zzz
, sve_tbl_fns
[a
->esz
], a
, 0)
2180 static gen_helper_gvec_4
* const sve2_tbl_fns
[4] = {
2181 gen_helper_sve2_tbl_b
, gen_helper_sve2_tbl_h
,
2182 gen_helper_sve2_tbl_s
, gen_helper_sve2_tbl_d
2184 TRANS_FEAT(TBL_sve2
, aa64_sve2
, gen_gvec_ool_zzzz
, sve2_tbl_fns
[a
->esz
],
2185 a
->rd
, a
->rn
, (a
->rn
+ 1) % 32, a
->rm
, 0)
2187 static gen_helper_gvec_3
* const tbx_fns
[4] = {
2188 gen_helper_sve2_tbx_b
, gen_helper_sve2_tbx_h
,
2189 gen_helper_sve2_tbx_s
, gen_helper_sve2_tbx_d
2191 TRANS_FEAT(TBX
, aa64_sve2
, gen_gvec_ool_arg_zzz
, tbx_fns
[a
->esz
], a
, 0)
2193 static bool trans_UNPK(DisasContext
*s
, arg_UNPK
*a
)
2195 static gen_helper_gvec_2
* const fns
[4][2] = {
2197 { gen_helper_sve_sunpk_h
, gen_helper_sve_uunpk_h
},
2198 { gen_helper_sve_sunpk_s
, gen_helper_sve_uunpk_s
},
2199 { gen_helper_sve_sunpk_d
, gen_helper_sve_uunpk_d
},
2205 if (sve_access_check(s
)) {
2206 unsigned vsz
= vec_full_reg_size(s
);
2207 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, a
->rd
),
2208 vec_full_reg_offset(s
, a
->rn
)
2209 + (a
->h
? vsz
/ 2 : 0),
2210 vsz
, vsz
, 0, fns
[a
->esz
][a
->u
]);
2216 *** SVE Permute - Predicates Group
2219 static bool do_perm_pred3(DisasContext
*s
, arg_rrr_esz
*a
, bool high_odd
,
2220 gen_helper_gvec_3
*fn
)
2222 if (!sve_access_check(s
)) {
2226 unsigned vsz
= pred_full_reg_size(s
);
2228 TCGv_ptr t_d
= tcg_temp_new_ptr();
2229 TCGv_ptr t_n
= tcg_temp_new_ptr();
2230 TCGv_ptr t_m
= tcg_temp_new_ptr();
2233 desc
= FIELD_DP32(desc
, PREDDESC
, OPRSZ
, vsz
);
2234 desc
= FIELD_DP32(desc
, PREDDESC
, ESZ
, a
->esz
);
2235 desc
= FIELD_DP32(desc
, PREDDESC
, DATA
, high_odd
);
2237 tcg_gen_addi_ptr(t_d
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
2238 tcg_gen_addi_ptr(t_n
, cpu_env
, pred_full_reg_offset(s
, a
->rn
));
2239 tcg_gen_addi_ptr(t_m
, cpu_env
, pred_full_reg_offset(s
, a
->rm
));
2241 fn(t_d
, t_n
, t_m
, tcg_constant_i32(desc
));
2243 tcg_temp_free_ptr(t_d
);
2244 tcg_temp_free_ptr(t_n
);
2245 tcg_temp_free_ptr(t_m
);
2249 static bool do_perm_pred2(DisasContext
*s
, arg_rr_esz
*a
, bool high_odd
,
2250 gen_helper_gvec_2
*fn
)
2252 if (!sve_access_check(s
)) {
2256 unsigned vsz
= pred_full_reg_size(s
);
2257 TCGv_ptr t_d
= tcg_temp_new_ptr();
2258 TCGv_ptr t_n
= tcg_temp_new_ptr();
2261 tcg_gen_addi_ptr(t_d
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
2262 tcg_gen_addi_ptr(t_n
, cpu_env
, pred_full_reg_offset(s
, a
->rn
));
2264 desc
= FIELD_DP32(desc
, PREDDESC
, OPRSZ
, vsz
);
2265 desc
= FIELD_DP32(desc
, PREDDESC
, ESZ
, a
->esz
);
2266 desc
= FIELD_DP32(desc
, PREDDESC
, DATA
, high_odd
);
2268 fn(t_d
, t_n
, tcg_constant_i32(desc
));
2270 tcg_temp_free_ptr(t_d
);
2271 tcg_temp_free_ptr(t_n
);
2275 TRANS_FEAT(ZIP1_p
, aa64_sve
, do_perm_pred3
, a
, 0, gen_helper_sve_zip_p
)
2276 TRANS_FEAT(ZIP2_p
, aa64_sve
, do_perm_pred3
, a
, 1, gen_helper_sve_zip_p
)
2277 TRANS_FEAT(UZP1_p
, aa64_sve
, do_perm_pred3
, a
, 0, gen_helper_sve_uzp_p
)
2278 TRANS_FEAT(UZP2_p
, aa64_sve
, do_perm_pred3
, a
, 1, gen_helper_sve_uzp_p
)
2279 TRANS_FEAT(TRN1_p
, aa64_sve
, do_perm_pred3
, a
, 0, gen_helper_sve_trn_p
)
2280 TRANS_FEAT(TRN2_p
, aa64_sve
, do_perm_pred3
, a
, 1, gen_helper_sve_trn_p
)
2282 TRANS_FEAT(REV_p
, aa64_sve
, do_perm_pred2
, a
, 0, gen_helper_sve_rev_p
)
2283 TRANS_FEAT(PUNPKLO
, aa64_sve
, do_perm_pred2
, a
, 0, gen_helper_sve_punpk_p
)
2284 TRANS_FEAT(PUNPKHI
, aa64_sve
, do_perm_pred2
, a
, 1, gen_helper_sve_punpk_p
)
2287 *** SVE Permute - Interleaving Group
2290 static gen_helper_gvec_3
* const zip_fns
[4] = {
2291 gen_helper_sve_zip_b
, gen_helper_sve_zip_h
,
2292 gen_helper_sve_zip_s
, gen_helper_sve_zip_d
,
2294 TRANS_FEAT(ZIP1_z
, aa64_sve
, gen_gvec_ool_arg_zzz
,
2295 zip_fns
[a
->esz
], a
, 0)
2296 TRANS_FEAT(ZIP2_z
, aa64_sve
, gen_gvec_ool_arg_zzz
,
2297 zip_fns
[a
->esz
], a
, vec_full_reg_size(s
) / 2)
2299 TRANS_FEAT(ZIP1_q
, aa64_sve_f64mm
, gen_gvec_ool_arg_zzz
,
2300 gen_helper_sve2_zip_q
, a
, 0)
2301 TRANS_FEAT(ZIP2_q
, aa64_sve_f64mm
, gen_gvec_ool_arg_zzz
,
2302 gen_helper_sve2_zip_q
, a
,
2303 QEMU_ALIGN_DOWN(vec_full_reg_size(s
), 32) / 2)
2305 static gen_helper_gvec_3
* const uzp_fns
[4] = {
2306 gen_helper_sve_uzp_b
, gen_helper_sve_uzp_h
,
2307 gen_helper_sve_uzp_s
, gen_helper_sve_uzp_d
,
2310 TRANS_FEAT(UZP1_z
, aa64_sve
, gen_gvec_ool_arg_zzz
,
2311 uzp_fns
[a
->esz
], a
, 0)
2312 TRANS_FEAT(UZP2_z
, aa64_sve
, gen_gvec_ool_arg_zzz
,
2313 uzp_fns
[a
->esz
], a
, 1 << a
->esz
)
2315 TRANS_FEAT(UZP1_q
, aa64_sve_f64mm
, gen_gvec_ool_arg_zzz
,
2316 gen_helper_sve2_uzp_q
, a
, 0)
2317 TRANS_FEAT(UZP2_q
, aa64_sve_f64mm
, gen_gvec_ool_arg_zzz
,
2318 gen_helper_sve2_uzp_q
, a
, 16)
2320 static gen_helper_gvec_3
* const trn_fns
[4] = {
2321 gen_helper_sve_trn_b
, gen_helper_sve_trn_h
,
2322 gen_helper_sve_trn_s
, gen_helper_sve_trn_d
,
2325 TRANS_FEAT(TRN1_z
, aa64_sve
, gen_gvec_ool_arg_zzz
,
2326 trn_fns
[a
->esz
], a
, 0)
2327 TRANS_FEAT(TRN2_z
, aa64_sve
, gen_gvec_ool_arg_zzz
,
2328 trn_fns
[a
->esz
], a
, 1 << a
->esz
)
2330 TRANS_FEAT(TRN1_q
, aa64_sve_f64mm
, gen_gvec_ool_arg_zzz
,
2331 gen_helper_sve2_trn_q
, a
, 0)
2332 TRANS_FEAT(TRN2_q
, aa64_sve_f64mm
, gen_gvec_ool_arg_zzz
,
2333 gen_helper_sve2_trn_q
, a
, 16)
2336 *** SVE Permute Vector - Predicated Group
2339 static gen_helper_gvec_3
* const compact_fns
[4] = {
2340 NULL
, NULL
, gen_helper_sve_compact_s
, gen_helper_sve_compact_d
2342 TRANS_FEAT(COMPACT
, aa64_sve
, gen_gvec_ool_arg_zpz
, compact_fns
[a
->esz
], a
, 0)
2344 /* Call the helper that computes the ARM LastActiveElement pseudocode
2345 * function, scaled by the element size. This includes the not found
2346 * indication; e.g. not found for esz=3 is -8.
2348 static void find_last_active(DisasContext
*s
, TCGv_i32 ret
, int esz
, int pg
)
2350 /* Predicate sizes may be smaller and cannot use simd_desc. We cannot
2351 * round up, as we do elsewhere, because we need the exact size.
2353 TCGv_ptr t_p
= tcg_temp_new_ptr();
2356 desc
= FIELD_DP32(desc
, PREDDESC
, OPRSZ
, pred_full_reg_size(s
));
2357 desc
= FIELD_DP32(desc
, PREDDESC
, ESZ
, esz
);
2359 tcg_gen_addi_ptr(t_p
, cpu_env
, pred_full_reg_offset(s
, pg
));
2361 gen_helper_sve_last_active_element(ret
, t_p
, tcg_constant_i32(desc
));
2363 tcg_temp_free_ptr(t_p
);
2366 /* Increment LAST to the offset of the next element in the vector,
2367 * wrapping around to 0.
2369 static void incr_last_active(DisasContext
*s
, TCGv_i32 last
, int esz
)
2371 unsigned vsz
= vec_full_reg_size(s
);
2373 tcg_gen_addi_i32(last
, last
, 1 << esz
);
2374 if (is_power_of_2(vsz
)) {
2375 tcg_gen_andi_i32(last
, last
, vsz
- 1);
2377 TCGv_i32 max
= tcg_constant_i32(vsz
);
2378 TCGv_i32 zero
= tcg_constant_i32(0);
2379 tcg_gen_movcond_i32(TCG_COND_GEU
, last
, last
, max
, zero
, last
);
2383 /* If LAST < 0, set LAST to the offset of the last element in the vector. */
2384 static void wrap_last_active(DisasContext
*s
, TCGv_i32 last
, int esz
)
2386 unsigned vsz
= vec_full_reg_size(s
);
2388 if (is_power_of_2(vsz
)) {
2389 tcg_gen_andi_i32(last
, last
, vsz
- 1);
2391 TCGv_i32 max
= tcg_constant_i32(vsz
- (1 << esz
));
2392 TCGv_i32 zero
= tcg_constant_i32(0);
2393 tcg_gen_movcond_i32(TCG_COND_LT
, last
, last
, zero
, max
, last
);
2397 /* Load an unsigned element of ESZ from BASE+OFS. */
2398 static TCGv_i64
load_esz(TCGv_ptr base
, int ofs
, int esz
)
2400 TCGv_i64 r
= tcg_temp_new_i64();
2404 tcg_gen_ld8u_i64(r
, base
, ofs
);
2407 tcg_gen_ld16u_i64(r
, base
, ofs
);
2410 tcg_gen_ld32u_i64(r
, base
, ofs
);
2413 tcg_gen_ld_i64(r
, base
, ofs
);
2416 g_assert_not_reached();
2421 /* Load an unsigned element of ESZ from RM[LAST]. */
2422 static TCGv_i64
load_last_active(DisasContext
*s
, TCGv_i32 last
,
2425 TCGv_ptr p
= tcg_temp_new_ptr();
2428 /* Convert offset into vector into offset into ENV.
2429 * The final adjustment for the vector register base
2430 * is added via constant offset to the load.
2433 /* Adjust for element ordering. See vec_reg_offset. */
2435 tcg_gen_xori_i32(last
, last
, 8 - (1 << esz
));
2438 tcg_gen_ext_i32_ptr(p
, last
);
2439 tcg_gen_add_ptr(p
, p
, cpu_env
);
2441 r
= load_esz(p
, vec_full_reg_offset(s
, rm
), esz
);
2442 tcg_temp_free_ptr(p
);
2447 /* Compute CLAST for a Zreg. */
2448 static bool do_clast_vector(DisasContext
*s
, arg_rprr_esz
*a
, bool before
)
2453 unsigned vsz
, esz
= a
->esz
;
2455 if (!sve_access_check(s
)) {
2459 last
= tcg_temp_local_new_i32();
2460 over
= gen_new_label();
2462 find_last_active(s
, last
, esz
, a
->pg
);
2464 /* There is of course no movcond for a 2048-bit vector,
2465 * so we must branch over the actual store.
2467 tcg_gen_brcondi_i32(TCG_COND_LT
, last
, 0, over
);
2470 incr_last_active(s
, last
, esz
);
2473 ele
= load_last_active(s
, last
, a
->rm
, esz
);
2474 tcg_temp_free_i32(last
);
2476 vsz
= vec_full_reg_size(s
);
2477 tcg_gen_gvec_dup_i64(esz
, vec_full_reg_offset(s
, a
->rd
), vsz
, vsz
, ele
);
2478 tcg_temp_free_i64(ele
);
2480 /* If this insn used MOVPRFX, we may need a second move. */
2481 if (a
->rd
!= a
->rn
) {
2482 TCGLabel
*done
= gen_new_label();
2485 gen_set_label(over
);
2486 do_mov_z(s
, a
->rd
, a
->rn
);
2488 gen_set_label(done
);
2490 gen_set_label(over
);
2495 TRANS_FEAT(CLASTA_z
, aa64_sve
, do_clast_vector
, a
, false)
2496 TRANS_FEAT(CLASTB_z
, aa64_sve
, do_clast_vector
, a
, true)
2498 /* Compute CLAST for a scalar. */
2499 static void do_clast_scalar(DisasContext
*s
, int esz
, int pg
, int rm
,
2500 bool before
, TCGv_i64 reg_val
)
2502 TCGv_i32 last
= tcg_temp_new_i32();
2505 find_last_active(s
, last
, esz
, pg
);
2507 /* Extend the original value of last prior to incrementing. */
2508 cmp
= tcg_temp_new_i64();
2509 tcg_gen_ext_i32_i64(cmp
, last
);
2512 incr_last_active(s
, last
, esz
);
2515 /* The conceit here is that while last < 0 indicates not found, after
2516 * adjusting for cpu_env->vfp.zregs[rm], it is still a valid address
2517 * from which we can load garbage. We then discard the garbage with
2518 * a conditional move.
2520 ele
= load_last_active(s
, last
, rm
, esz
);
2521 tcg_temp_free_i32(last
);
2523 tcg_gen_movcond_i64(TCG_COND_GE
, reg_val
, cmp
, tcg_constant_i64(0),
2526 tcg_temp_free_i64(cmp
);
2527 tcg_temp_free_i64(ele
);
2530 /* Compute CLAST for a Vreg. */
2531 static bool do_clast_fp(DisasContext
*s
, arg_rpr_esz
*a
, bool before
)
2533 if (sve_access_check(s
)) {
2535 int ofs
= vec_reg_offset(s
, a
->rd
, 0, esz
);
2536 TCGv_i64 reg
= load_esz(cpu_env
, ofs
, esz
);
2538 do_clast_scalar(s
, esz
, a
->pg
, a
->rn
, before
, reg
);
2539 write_fp_dreg(s
, a
->rd
, reg
);
2540 tcg_temp_free_i64(reg
);
2545 static bool trans_CLASTA_v(DisasContext
*s
, arg_rpr_esz
*a
)
2547 return do_clast_fp(s
, a
, false);
2550 static bool trans_CLASTB_v(DisasContext
*s
, arg_rpr_esz
*a
)
2552 return do_clast_fp(s
, a
, true);
2555 /* Compute CLAST for a Xreg. */
2556 static bool do_clast_general(DisasContext
*s
, arg_rpr_esz
*a
, bool before
)
2560 if (!sve_access_check(s
)) {
2564 reg
= cpu_reg(s
, a
->rd
);
2567 tcg_gen_ext8u_i64(reg
, reg
);
2570 tcg_gen_ext16u_i64(reg
, reg
);
2573 tcg_gen_ext32u_i64(reg
, reg
);
2578 g_assert_not_reached();
2581 do_clast_scalar(s
, a
->esz
, a
->pg
, a
->rn
, before
, reg
);
2585 static bool trans_CLASTA_r(DisasContext
*s
, arg_rpr_esz
*a
)
2587 return do_clast_general(s
, a
, false);
2590 static bool trans_CLASTB_r(DisasContext
*s
, arg_rpr_esz
*a
)
2592 return do_clast_general(s
, a
, true);
2595 /* Compute LAST for a scalar. */
2596 static TCGv_i64
do_last_scalar(DisasContext
*s
, int esz
,
2597 int pg
, int rm
, bool before
)
2599 TCGv_i32 last
= tcg_temp_new_i32();
2602 find_last_active(s
, last
, esz
, pg
);
2604 wrap_last_active(s
, last
, esz
);
2606 incr_last_active(s
, last
, esz
);
2609 ret
= load_last_active(s
, last
, rm
, esz
);
2610 tcg_temp_free_i32(last
);
2614 /* Compute LAST for a Vreg. */
2615 static bool do_last_fp(DisasContext
*s
, arg_rpr_esz
*a
, bool before
)
2617 if (sve_access_check(s
)) {
2618 TCGv_i64 val
= do_last_scalar(s
, a
->esz
, a
->pg
, a
->rn
, before
);
2619 write_fp_dreg(s
, a
->rd
, val
);
2620 tcg_temp_free_i64(val
);
2625 static bool trans_LASTA_v(DisasContext
*s
, arg_rpr_esz
*a
)
2627 return do_last_fp(s
, a
, false);
2630 static bool trans_LASTB_v(DisasContext
*s
, arg_rpr_esz
*a
)
2632 return do_last_fp(s
, a
, true);
2635 /* Compute LAST for a Xreg. */
2636 static bool do_last_general(DisasContext
*s
, arg_rpr_esz
*a
, bool before
)
2638 if (sve_access_check(s
)) {
2639 TCGv_i64 val
= do_last_scalar(s
, a
->esz
, a
->pg
, a
->rn
, before
);
2640 tcg_gen_mov_i64(cpu_reg(s
, a
->rd
), val
);
2641 tcg_temp_free_i64(val
);
2646 static bool trans_LASTA_r(DisasContext
*s
, arg_rpr_esz
*a
)
2648 return do_last_general(s
, a
, false);
2651 static bool trans_LASTB_r(DisasContext
*s
, arg_rpr_esz
*a
)
2653 return do_last_general(s
, a
, true);
2656 static bool trans_CPY_m_r(DisasContext
*s
, arg_rpr_esz
*a
)
2658 if (sve_access_check(s
)) {
2659 do_cpy_m(s
, a
->esz
, a
->rd
, a
->rd
, a
->pg
, cpu_reg_sp(s
, a
->rn
));
2664 static bool trans_CPY_m_v(DisasContext
*s
, arg_rpr_esz
*a
)
2666 if (sve_access_check(s
)) {
2667 int ofs
= vec_reg_offset(s
, a
->rn
, 0, a
->esz
);
2668 TCGv_i64 t
= load_esz(cpu_env
, ofs
, a
->esz
);
2669 do_cpy_m(s
, a
->esz
, a
->rd
, a
->rd
, a
->pg
, t
);
2670 tcg_temp_free_i64(t
);
2675 static gen_helper_gvec_3
* const revb_fns
[4] = {
2676 NULL
, gen_helper_sve_revb_h
,
2677 gen_helper_sve_revb_s
, gen_helper_sve_revb_d
,
2679 TRANS_FEAT(REVB
, aa64_sve
, gen_gvec_ool_arg_zpz
, revb_fns
[a
->esz
], a
, 0)
2681 static gen_helper_gvec_3
* const revh_fns
[4] = {
2682 NULL
, NULL
, gen_helper_sve_revh_s
, gen_helper_sve_revh_d
,
2684 TRANS_FEAT(REVH
, aa64_sve
, gen_gvec_ool_arg_zpz
, revh_fns
[a
->esz
], a
, 0)
2686 TRANS_FEAT(REVW
, aa64_sve
, gen_gvec_ool_arg_zpz
,
2687 a
->esz
== 3 ? gen_helper_sve_revw_d
: NULL
, a
, 0)
2689 static bool trans_SPLICE(DisasContext
*s
, arg_rprr_esz
*a
)
2691 return gen_gvec_ool_zzzp(s
, gen_helper_sve_splice
,
2692 a
->rd
, a
->rn
, a
->rm
, a
->pg
, a
->esz
);
2695 static bool trans_SPLICE_sve2(DisasContext
*s
, arg_rpr_esz
*a
)
2697 if (!dc_isar_feature(aa64_sve2
, s
)) {
2700 return gen_gvec_ool_zzzp(s
, gen_helper_sve_splice
,
2701 a
->rd
, a
->rn
, (a
->rn
+ 1) % 32, a
->pg
, a
->esz
);
2705 *** SVE Integer Compare - Vectors Group
2708 static bool do_ppzz_flags(DisasContext
*s
, arg_rprr_esz
*a
,
2709 gen_helper_gvec_flags_4
*gen_fn
)
2711 TCGv_ptr pd
, zn
, zm
, pg
;
2715 if (gen_fn
== NULL
) {
2718 if (!sve_access_check(s
)) {
2722 vsz
= vec_full_reg_size(s
);
2723 t
= tcg_temp_new_i32();
2724 pd
= tcg_temp_new_ptr();
2725 zn
= tcg_temp_new_ptr();
2726 zm
= tcg_temp_new_ptr();
2727 pg
= tcg_temp_new_ptr();
2729 tcg_gen_addi_ptr(pd
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
2730 tcg_gen_addi_ptr(zn
, cpu_env
, vec_full_reg_offset(s
, a
->rn
));
2731 tcg_gen_addi_ptr(zm
, cpu_env
, vec_full_reg_offset(s
, a
->rm
));
2732 tcg_gen_addi_ptr(pg
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
2734 gen_fn(t
, pd
, zn
, zm
, pg
, tcg_constant_i32(simd_desc(vsz
, vsz
, 0)));
2736 tcg_temp_free_ptr(pd
);
2737 tcg_temp_free_ptr(zn
);
2738 tcg_temp_free_ptr(zm
);
2739 tcg_temp_free_ptr(pg
);
2743 tcg_temp_free_i32(t
);
2747 #define DO_PPZZ(NAME, name) \
2748 static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \
2750 static gen_helper_gvec_flags_4 * const fns[4] = { \
2751 gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
2752 gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
2754 return do_ppzz_flags(s, a, fns[a->esz]); \
2757 DO_PPZZ(CMPEQ
, cmpeq
)
2758 DO_PPZZ(CMPNE
, cmpne
)
2759 DO_PPZZ(CMPGT
, cmpgt
)
2760 DO_PPZZ(CMPGE
, cmpge
)
2761 DO_PPZZ(CMPHI
, cmphi
)
2762 DO_PPZZ(CMPHS
, cmphs
)
2766 #define DO_PPZW(NAME, name) \
2767 static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a) \
2769 static gen_helper_gvec_flags_4 * const fns[4] = { \
2770 gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
2771 gen_helper_sve_##name##_ppzw_s, NULL \
2773 return do_ppzz_flags(s, a, fns[a->esz]); \
2776 DO_PPZW(CMPEQ
, cmpeq
)
2777 DO_PPZW(CMPNE
, cmpne
)
2778 DO_PPZW(CMPGT
, cmpgt
)
2779 DO_PPZW(CMPGE
, cmpge
)
2780 DO_PPZW(CMPHI
, cmphi
)
2781 DO_PPZW(CMPHS
, cmphs
)
2782 DO_PPZW(CMPLT
, cmplt
)
2783 DO_PPZW(CMPLE
, cmple
)
2784 DO_PPZW(CMPLO
, cmplo
)
2785 DO_PPZW(CMPLS
, cmpls
)
2790 *** SVE Integer Compare - Immediate Groups
2793 static bool do_ppzi_flags(DisasContext
*s
, arg_rpri_esz
*a
,
2794 gen_helper_gvec_flags_3
*gen_fn
)
2796 TCGv_ptr pd
, zn
, pg
;
2800 if (gen_fn
== NULL
) {
2803 if (!sve_access_check(s
)) {
2807 vsz
= vec_full_reg_size(s
);
2808 t
= tcg_temp_new_i32();
2809 pd
= tcg_temp_new_ptr();
2810 zn
= tcg_temp_new_ptr();
2811 pg
= tcg_temp_new_ptr();
2813 tcg_gen_addi_ptr(pd
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
2814 tcg_gen_addi_ptr(zn
, cpu_env
, vec_full_reg_offset(s
, a
->rn
));
2815 tcg_gen_addi_ptr(pg
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
2817 gen_fn(t
, pd
, zn
, pg
, tcg_constant_i32(simd_desc(vsz
, vsz
, a
->imm
)));
2819 tcg_temp_free_ptr(pd
);
2820 tcg_temp_free_ptr(zn
);
2821 tcg_temp_free_ptr(pg
);
2825 tcg_temp_free_i32(t
);
2829 #define DO_PPZI(NAME, name) \
2830 static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a) \
2832 static gen_helper_gvec_flags_3 * const fns[4] = { \
2833 gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \
2834 gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \
2836 return do_ppzi_flags(s, a, fns[a->esz]); \
2839 DO_PPZI(CMPEQ
, cmpeq
)
2840 DO_PPZI(CMPNE
, cmpne
)
2841 DO_PPZI(CMPGT
, cmpgt
)
2842 DO_PPZI(CMPGE
, cmpge
)
2843 DO_PPZI(CMPHI
, cmphi
)
2844 DO_PPZI(CMPHS
, cmphs
)
2845 DO_PPZI(CMPLT
, cmplt
)
2846 DO_PPZI(CMPLE
, cmple
)
2847 DO_PPZI(CMPLO
, cmplo
)
2848 DO_PPZI(CMPLS
, cmpls
)
2853 *** SVE Partition Break Group
2856 static bool do_brk3(DisasContext
*s
, arg_rprr_s
*a
,
2857 gen_helper_gvec_4
*fn
, gen_helper_gvec_flags_4
*fn_s
)
2859 if (!sve_access_check(s
)) {
2863 unsigned vsz
= pred_full_reg_size(s
);
2865 /* Predicate sizes may be smaller and cannot use simd_desc. */
2866 TCGv_ptr d
= tcg_temp_new_ptr();
2867 TCGv_ptr n
= tcg_temp_new_ptr();
2868 TCGv_ptr m
= tcg_temp_new_ptr();
2869 TCGv_ptr g
= tcg_temp_new_ptr();
2870 TCGv_i32 desc
= tcg_constant_i32(FIELD_DP32(0, PREDDESC
, OPRSZ
, vsz
));
2872 tcg_gen_addi_ptr(d
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
2873 tcg_gen_addi_ptr(n
, cpu_env
, pred_full_reg_offset(s
, a
->rn
));
2874 tcg_gen_addi_ptr(m
, cpu_env
, pred_full_reg_offset(s
, a
->rm
));
2875 tcg_gen_addi_ptr(g
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
2878 TCGv_i32 t
= tcg_temp_new_i32();
2879 fn_s(t
, d
, n
, m
, g
, desc
);
2881 tcg_temp_free_i32(t
);
2883 fn(d
, n
, m
, g
, desc
);
2885 tcg_temp_free_ptr(d
);
2886 tcg_temp_free_ptr(n
);
2887 tcg_temp_free_ptr(m
);
2888 tcg_temp_free_ptr(g
);
2892 static bool do_brk2(DisasContext
*s
, arg_rpr_s
*a
,
2893 gen_helper_gvec_3
*fn
, gen_helper_gvec_flags_3
*fn_s
)
2895 if (!sve_access_check(s
)) {
2899 unsigned vsz
= pred_full_reg_size(s
);
2901 /* Predicate sizes may be smaller and cannot use simd_desc. */
2902 TCGv_ptr d
= tcg_temp_new_ptr();
2903 TCGv_ptr n
= tcg_temp_new_ptr();
2904 TCGv_ptr g
= tcg_temp_new_ptr();
2905 TCGv_i32 desc
= tcg_constant_i32(FIELD_DP32(0, PREDDESC
, OPRSZ
, vsz
));
2907 tcg_gen_addi_ptr(d
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
2908 tcg_gen_addi_ptr(n
, cpu_env
, pred_full_reg_offset(s
, a
->rn
));
2909 tcg_gen_addi_ptr(g
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
2912 TCGv_i32 t
= tcg_temp_new_i32();
2913 fn_s(t
, d
, n
, g
, desc
);
2915 tcg_temp_free_i32(t
);
2919 tcg_temp_free_ptr(d
);
2920 tcg_temp_free_ptr(n
);
2921 tcg_temp_free_ptr(g
);
2925 static bool trans_BRKPA(DisasContext
*s
, arg_rprr_s
*a
)
2927 return do_brk3(s
, a
, gen_helper_sve_brkpa
, gen_helper_sve_brkpas
);
2930 static bool trans_BRKPB(DisasContext
*s
, arg_rprr_s
*a
)
2932 return do_brk3(s
, a
, gen_helper_sve_brkpb
, gen_helper_sve_brkpbs
);
2935 static bool trans_BRKA_m(DisasContext
*s
, arg_rpr_s
*a
)
2937 return do_brk2(s
, a
, gen_helper_sve_brka_m
, gen_helper_sve_brkas_m
);
2940 static bool trans_BRKB_m(DisasContext
*s
, arg_rpr_s
*a
)
2942 return do_brk2(s
, a
, gen_helper_sve_brkb_m
, gen_helper_sve_brkbs_m
);
2945 static bool trans_BRKA_z(DisasContext
*s
, arg_rpr_s
*a
)
2947 return do_brk2(s
, a
, gen_helper_sve_brka_z
, gen_helper_sve_brkas_z
);
2950 static bool trans_BRKB_z(DisasContext
*s
, arg_rpr_s
*a
)
2952 return do_brk2(s
, a
, gen_helper_sve_brkb_z
, gen_helper_sve_brkbs_z
);
2955 static bool trans_BRKN(DisasContext
*s
, arg_rpr_s
*a
)
2957 return do_brk2(s
, a
, gen_helper_sve_brkn
, gen_helper_sve_brkns
);
2961 *** SVE Predicate Count Group
2964 static void do_cntp(DisasContext
*s
, TCGv_i64 val
, int esz
, int pn
, int pg
)
2966 unsigned psz
= pred_full_reg_size(s
);
2971 tcg_gen_ld_i64(val
, cpu_env
, pred_full_reg_offset(s
, pn
));
2973 TCGv_i64 g
= tcg_temp_new_i64();
2974 tcg_gen_ld_i64(g
, cpu_env
, pred_full_reg_offset(s
, pg
));
2975 tcg_gen_and_i64(val
, val
, g
);
2976 tcg_temp_free_i64(g
);
2979 /* Reduce the pred_esz_masks value simply to reduce the
2980 * size of the code generated here.
2982 psz_mask
= MAKE_64BIT_MASK(0, psz
* 8);
2983 tcg_gen_andi_i64(val
, val
, pred_esz_masks
[esz
] & psz_mask
);
2985 tcg_gen_ctpop_i64(val
, val
);
2987 TCGv_ptr t_pn
= tcg_temp_new_ptr();
2988 TCGv_ptr t_pg
= tcg_temp_new_ptr();
2991 desc
= FIELD_DP32(desc
, PREDDESC
, OPRSZ
, psz
);
2992 desc
= FIELD_DP32(desc
, PREDDESC
, ESZ
, esz
);
2994 tcg_gen_addi_ptr(t_pn
, cpu_env
, pred_full_reg_offset(s
, pn
));
2995 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, pg
));
2997 gen_helper_sve_cntp(val
, t_pn
, t_pg
, tcg_constant_i32(desc
));
2998 tcg_temp_free_ptr(t_pn
);
2999 tcg_temp_free_ptr(t_pg
);
3003 static bool trans_CNTP(DisasContext
*s
, arg_CNTP
*a
)
3005 if (sve_access_check(s
)) {
3006 do_cntp(s
, cpu_reg(s
, a
->rd
), a
->esz
, a
->rn
, a
->pg
);
3011 static bool trans_INCDECP_r(DisasContext
*s
, arg_incdec_pred
*a
)
3013 if (sve_access_check(s
)) {
3014 TCGv_i64 reg
= cpu_reg(s
, a
->rd
);
3015 TCGv_i64 val
= tcg_temp_new_i64();
3017 do_cntp(s
, val
, a
->esz
, a
->pg
, a
->pg
);
3019 tcg_gen_sub_i64(reg
, reg
, val
);
3021 tcg_gen_add_i64(reg
, reg
, val
);
3023 tcg_temp_free_i64(val
);
3028 static bool trans_INCDECP_z(DisasContext
*s
, arg_incdec2_pred
*a
)
3033 if (sve_access_check(s
)) {
3034 unsigned vsz
= vec_full_reg_size(s
);
3035 TCGv_i64 val
= tcg_temp_new_i64();
3036 GVecGen2sFn
*gvec_fn
= a
->d
? tcg_gen_gvec_subs
: tcg_gen_gvec_adds
;
3038 do_cntp(s
, val
, a
->esz
, a
->pg
, a
->pg
);
3039 gvec_fn(a
->esz
, vec_full_reg_offset(s
, a
->rd
),
3040 vec_full_reg_offset(s
, a
->rn
), val
, vsz
, vsz
);
3045 static bool trans_SINCDECP_r_32(DisasContext
*s
, arg_incdec_pred
*a
)
3047 if (sve_access_check(s
)) {
3048 TCGv_i64 reg
= cpu_reg(s
, a
->rd
);
3049 TCGv_i64 val
= tcg_temp_new_i64();
3051 do_cntp(s
, val
, a
->esz
, a
->pg
, a
->pg
);
3052 do_sat_addsub_32(reg
, val
, a
->u
, a
->d
);
3057 static bool trans_SINCDECP_r_64(DisasContext
*s
, arg_incdec_pred
*a
)
3059 if (sve_access_check(s
)) {
3060 TCGv_i64 reg
= cpu_reg(s
, a
->rd
);
3061 TCGv_i64 val
= tcg_temp_new_i64();
3063 do_cntp(s
, val
, a
->esz
, a
->pg
, a
->pg
);
3064 do_sat_addsub_64(reg
, val
, a
->u
, a
->d
);
3069 static bool trans_SINCDECP_z(DisasContext
*s
, arg_incdec2_pred
*a
)
3074 if (sve_access_check(s
)) {
3075 TCGv_i64 val
= tcg_temp_new_i64();
3076 do_cntp(s
, val
, a
->esz
, a
->pg
, a
->pg
);
3077 do_sat_addsub_vec(s
, a
->esz
, a
->rd
, a
->rn
, val
, a
->u
, a
->d
);
3083 *** SVE Integer Compare Scalars Group
3086 static bool trans_CTERM(DisasContext
*s
, arg_CTERM
*a
)
3088 if (!sve_access_check(s
)) {
3092 TCGCond cond
= (a
->ne
? TCG_COND_NE
: TCG_COND_EQ
);
3093 TCGv_i64 rn
= read_cpu_reg(s
, a
->rn
, a
->sf
);
3094 TCGv_i64 rm
= read_cpu_reg(s
, a
->rm
, a
->sf
);
3095 TCGv_i64 cmp
= tcg_temp_new_i64();
3097 tcg_gen_setcond_i64(cond
, cmp
, rn
, rm
);
3098 tcg_gen_extrl_i64_i32(cpu_NF
, cmp
);
3099 tcg_temp_free_i64(cmp
);
3101 /* VF = !NF & !CF. */
3102 tcg_gen_xori_i32(cpu_VF
, cpu_NF
, 1);
3103 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, cpu_CF
);
3105 /* Both NF and VF actually look at bit 31. */
3106 tcg_gen_neg_i32(cpu_NF
, cpu_NF
);
3107 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
3111 static bool trans_WHILE(DisasContext
*s
, arg_WHILE
*a
)
3113 TCGv_i64 op0
, op1
, t0
, t1
, tmax
;
3116 unsigned vsz
= vec_full_reg_size(s
);
3120 /* Note that GE/HS has a->eq == 0 and GT/HI has a->eq == 1. */
3121 bool eq
= a
->eq
== a
->lt
;
3123 /* The greater-than conditions are all SVE2. */
3124 if (!a
->lt
&& !dc_isar_feature(aa64_sve2
, s
)) {
3127 if (!sve_access_check(s
)) {
3131 op0
= read_cpu_reg(s
, a
->rn
, 1);
3132 op1
= read_cpu_reg(s
, a
->rm
, 1);
3136 tcg_gen_ext32u_i64(op0
, op0
);
3137 tcg_gen_ext32u_i64(op1
, op1
);
3139 tcg_gen_ext32s_i64(op0
, op0
);
3140 tcg_gen_ext32s_i64(op1
, op1
);
3144 /* For the helper, compress the different conditions into a computation
3145 * of how many iterations for which the condition is true.
3147 t0
= tcg_temp_new_i64();
3148 t1
= tcg_temp_new_i64();
3151 tcg_gen_sub_i64(t0
, op1
, op0
);
3153 maxval
= a
->sf
? UINT64_MAX
: UINT32_MAX
;
3154 cond
= eq
? TCG_COND_LEU
: TCG_COND_LTU
;
3156 maxval
= a
->sf
? INT64_MAX
: INT32_MAX
;
3157 cond
= eq
? TCG_COND_LE
: TCG_COND_LT
;
3160 tcg_gen_sub_i64(t0
, op0
, op1
);
3163 cond
= eq
? TCG_COND_GEU
: TCG_COND_GTU
;
3165 maxval
= a
->sf
? INT64_MIN
: INT32_MIN
;
3166 cond
= eq
? TCG_COND_GE
: TCG_COND_GT
;
3170 tmax
= tcg_constant_i64(vsz
>> a
->esz
);
3172 /* Equality means one more iteration. */
3173 tcg_gen_addi_i64(t0
, t0
, 1);
3176 * For the less-than while, if op1 is maxval (and the only time
3177 * the addition above could overflow), then we produce an all-true
3178 * predicate by setting the count to the vector length. This is
3179 * because the pseudocode is described as an increment + compare
3180 * loop, and the maximum integer would always compare true.
3181 * Similarly, the greater-than while has the same issue with the
3182 * minimum integer due to the decrement + compare loop.
3184 tcg_gen_movi_i64(t1
, maxval
);
3185 tcg_gen_movcond_i64(TCG_COND_EQ
, t0
, op1
, t1
, tmax
, t0
);
3188 /* Bound to the maximum. */
3189 tcg_gen_umin_i64(t0
, t0
, tmax
);
3191 /* Set the count to zero if the condition is false. */
3192 tcg_gen_movi_i64(t1
, 0);
3193 tcg_gen_movcond_i64(cond
, t0
, op0
, op1
, t0
, t1
);
3194 tcg_temp_free_i64(t1
);
3196 /* Since we're bounded, pass as a 32-bit type. */
3197 t2
= tcg_temp_new_i32();
3198 tcg_gen_extrl_i64_i32(t2
, t0
);
3199 tcg_temp_free_i64(t0
);
3201 /* Scale elements to bits. */
3202 tcg_gen_shli_i32(t2
, t2
, a
->esz
);
3204 desc
= FIELD_DP32(desc
, PREDDESC
, OPRSZ
, vsz
/ 8);
3205 desc
= FIELD_DP32(desc
, PREDDESC
, ESZ
, a
->esz
);
3207 ptr
= tcg_temp_new_ptr();
3208 tcg_gen_addi_ptr(ptr
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
3211 gen_helper_sve_whilel(t2
, ptr
, t2
, tcg_constant_i32(desc
));
3213 gen_helper_sve_whileg(t2
, ptr
, t2
, tcg_constant_i32(desc
));
3217 tcg_temp_free_ptr(ptr
);
3218 tcg_temp_free_i32(t2
);
3222 static bool trans_WHILE_ptr(DisasContext
*s
, arg_WHILE_ptr
*a
)
3224 TCGv_i64 op0
, op1
, diff
, t1
, tmax
;
3227 unsigned vsz
= vec_full_reg_size(s
);
3230 if (!dc_isar_feature(aa64_sve2
, s
)) {
3233 if (!sve_access_check(s
)) {
3237 op0
= read_cpu_reg(s
, a
->rn
, 1);
3238 op1
= read_cpu_reg(s
, a
->rm
, 1);
3240 tmax
= tcg_constant_i64(vsz
);
3241 diff
= tcg_temp_new_i64();
3245 /* diff = abs(op1 - op0), noting that op0/1 are unsigned. */
3246 t1
= tcg_temp_new_i64();
3247 tcg_gen_sub_i64(diff
, op0
, op1
);
3248 tcg_gen_sub_i64(t1
, op1
, op0
);
3249 tcg_gen_movcond_i64(TCG_COND_GEU
, diff
, op0
, op1
, diff
, t1
);
3250 tcg_temp_free_i64(t1
);
3251 /* Round down to a multiple of ESIZE. */
3252 tcg_gen_andi_i64(diff
, diff
, -1 << a
->esz
);
3253 /* If op1 == op0, diff == 0, and the condition is always true. */
3254 tcg_gen_movcond_i64(TCG_COND_EQ
, diff
, op0
, op1
, tmax
, diff
);
3257 tcg_gen_sub_i64(diff
, op1
, op0
);
3258 /* Round down to a multiple of ESIZE. */
3259 tcg_gen_andi_i64(diff
, diff
, -1 << a
->esz
);
3260 /* If op0 >= op1, diff <= 0, the condition is always true. */
3261 tcg_gen_movcond_i64(TCG_COND_GEU
, diff
, op0
, op1
, tmax
, diff
);
3264 /* Bound to the maximum. */
3265 tcg_gen_umin_i64(diff
, diff
, tmax
);
3267 /* Since we're bounded, pass as a 32-bit type. */
3268 t2
= tcg_temp_new_i32();
3269 tcg_gen_extrl_i64_i32(t2
, diff
);
3270 tcg_temp_free_i64(diff
);
3272 desc
= FIELD_DP32(desc
, PREDDESC
, OPRSZ
, vsz
/ 8);
3273 desc
= FIELD_DP32(desc
, PREDDESC
, ESZ
, a
->esz
);
3275 ptr
= tcg_temp_new_ptr();
3276 tcg_gen_addi_ptr(ptr
, cpu_env
, pred_full_reg_offset(s
, a
->rd
));
3278 gen_helper_sve_whilel(t2
, ptr
, t2
, tcg_constant_i32(desc
));
3281 tcg_temp_free_ptr(ptr
);
3282 tcg_temp_free_i32(t2
);
3287 *** SVE Integer Wide Immediate - Unpredicated Group
3290 static bool trans_FDUP(DisasContext
*s
, arg_FDUP
*a
)
3295 if (sve_access_check(s
)) {
3296 unsigned vsz
= vec_full_reg_size(s
);
3297 int dofs
= vec_full_reg_offset(s
, a
->rd
);
3300 /* Decode the VFP immediate. */
3301 imm
= vfp_expand_imm(a
->esz
, a
->imm
);
3302 tcg_gen_gvec_dup_imm(a
->esz
, dofs
, vsz
, vsz
, imm
);
3307 static bool trans_DUP_i(DisasContext
*s
, arg_DUP_i
*a
)
3309 if (a
->esz
== 0 && extract32(s
->insn
, 13, 1)) {
3312 if (sve_access_check(s
)) {
3313 unsigned vsz
= vec_full_reg_size(s
);
3314 int dofs
= vec_full_reg_offset(s
, a
->rd
);
3316 tcg_gen_gvec_dup_imm(a
->esz
, dofs
, vsz
, vsz
, a
->imm
);
3321 static bool trans_ADD_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3323 if (a
->esz
== 0 && extract32(s
->insn
, 13, 1)) {
3326 return gen_gvec_fn_arg_zzi(s
, tcg_gen_gvec_addi
, a
);
3329 static bool trans_SUB_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3332 return trans_ADD_zzi(s
, a
);
3335 static bool trans_SUBR_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3337 static const TCGOpcode vecop_list
[] = { INDEX_op_sub_vec
, 0 };
3338 static const GVecGen2s op
[4] = {
3339 { .fni8
= tcg_gen_vec_sub8_i64
,
3340 .fniv
= tcg_gen_sub_vec
,
3341 .fno
= gen_helper_sve_subri_b
,
3342 .opt_opc
= vecop_list
,
3344 .scalar_first
= true },
3345 { .fni8
= tcg_gen_vec_sub16_i64
,
3346 .fniv
= tcg_gen_sub_vec
,
3347 .fno
= gen_helper_sve_subri_h
,
3348 .opt_opc
= vecop_list
,
3350 .scalar_first
= true },
3351 { .fni4
= tcg_gen_sub_i32
,
3352 .fniv
= tcg_gen_sub_vec
,
3353 .fno
= gen_helper_sve_subri_s
,
3354 .opt_opc
= vecop_list
,
3356 .scalar_first
= true },
3357 { .fni8
= tcg_gen_sub_i64
,
3358 .fniv
= tcg_gen_sub_vec
,
3359 .fno
= gen_helper_sve_subri_d
,
3360 .opt_opc
= vecop_list
,
3361 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3363 .scalar_first
= true }
3366 if (a
->esz
== 0 && extract32(s
->insn
, 13, 1)) {
3369 if (sve_access_check(s
)) {
3370 unsigned vsz
= vec_full_reg_size(s
);
3371 tcg_gen_gvec_2s(vec_full_reg_offset(s
, a
->rd
),
3372 vec_full_reg_offset(s
, a
->rn
),
3373 vsz
, vsz
, tcg_constant_i64(a
->imm
), &op
[a
->esz
]);
3378 static bool trans_MUL_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3380 if (sve_access_check(s
)) {
3381 unsigned vsz
= vec_full_reg_size(s
);
3382 tcg_gen_gvec_muli(a
->esz
, vec_full_reg_offset(s
, a
->rd
),
3383 vec_full_reg_offset(s
, a
->rn
), a
->imm
, vsz
, vsz
);
3388 static bool do_zzi_sat(DisasContext
*s
, arg_rri_esz
*a
, bool u
, bool d
)
3390 if (a
->esz
== 0 && extract32(s
->insn
, 13, 1)) {
3393 if (sve_access_check(s
)) {
3394 do_sat_addsub_vec(s
, a
->esz
, a
->rd
, a
->rn
,
3395 tcg_constant_i64(a
->imm
), u
, d
);
3400 static bool trans_SQADD_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3402 return do_zzi_sat(s
, a
, false, false);
3405 static bool trans_UQADD_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3407 return do_zzi_sat(s
, a
, true, false);
3410 static bool trans_SQSUB_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3412 return do_zzi_sat(s
, a
, false, true);
3415 static bool trans_UQSUB_zzi(DisasContext
*s
, arg_rri_esz
*a
)
3417 return do_zzi_sat(s
, a
, true, true);
3420 static bool do_zzi_ool(DisasContext
*s
, arg_rri_esz
*a
, gen_helper_gvec_2i
*fn
)
3422 if (sve_access_check(s
)) {
3423 unsigned vsz
= vec_full_reg_size(s
);
3424 tcg_gen_gvec_2i_ool(vec_full_reg_offset(s
, a
->rd
),
3425 vec_full_reg_offset(s
, a
->rn
),
3426 tcg_constant_i64(a
->imm
), vsz
, vsz
, 0, fn
);
3431 #define DO_ZZI(NAME, name) \
3432 static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a) \
3434 static gen_helper_gvec_2i * const fns[4] = { \
3435 gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \
3436 gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \
3438 return do_zzi_ool(s, a, fns[a->esz]); \
3448 static gen_helper_gvec_4
* const dot_fns
[2][2] = {
3449 { gen_helper_gvec_sdot_b
, gen_helper_gvec_sdot_h
},
3450 { gen_helper_gvec_udot_b
, gen_helper_gvec_udot_h
}
3452 TRANS_FEAT(DOT_zzzz
, aa64_sve
, gen_gvec_ool_zzzz
,
3453 dot_fns
[a
->u
][a
->sz
], a
->rd
, a
->rn
, a
->rm
, a
->ra
, 0)
3456 * SVE Multiply - Indexed
3459 TRANS_FEAT(SDOT_zzxw_s
, aa64_sve
, gen_gvec_ool_arg_zzxz
,
3460 gen_helper_gvec_sdot_idx_b
, a
)
3461 TRANS_FEAT(SDOT_zzxw_d
, aa64_sve
, gen_gvec_ool_arg_zzxz
,
3462 gen_helper_gvec_sdot_idx_h
, a
)
3463 TRANS_FEAT(UDOT_zzxw_s
, aa64_sve
, gen_gvec_ool_arg_zzxz
,
3464 gen_helper_gvec_udot_idx_b
, a
)
3465 TRANS_FEAT(UDOT_zzxw_d
, aa64_sve
, gen_gvec_ool_arg_zzxz
,
3466 gen_helper_gvec_udot_idx_h
, a
)
3468 TRANS_FEAT(SUDOT_zzxw_s
, aa64_sve_i8mm
, gen_gvec_ool_arg_zzxz
,
3469 gen_helper_gvec_sudot_idx_b
, a
)
3470 TRANS_FEAT(USDOT_zzxw_s
, aa64_sve_i8mm
, gen_gvec_ool_arg_zzxz
,
3471 gen_helper_gvec_usdot_idx_b
, a
)
3473 #define DO_SVE2_RRX(NAME, FUNC) \
3474 TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
3475 a->rd, a->rn, a->rm, a->index)
3477 DO_SVE2_RRX(MUL_zzx_h
, gen_helper_gvec_mul_idx_h
)
3478 DO_SVE2_RRX(MUL_zzx_s
, gen_helper_gvec_mul_idx_s
)
3479 DO_SVE2_RRX(MUL_zzx_d
, gen_helper_gvec_mul_idx_d
)
3481 DO_SVE2_RRX(SQDMULH_zzx_h
, gen_helper_sve2_sqdmulh_idx_h
)
3482 DO_SVE2_RRX(SQDMULH_zzx_s
, gen_helper_sve2_sqdmulh_idx_s
)
3483 DO_SVE2_RRX(SQDMULH_zzx_d
, gen_helper_sve2_sqdmulh_idx_d
)
3485 DO_SVE2_RRX(SQRDMULH_zzx_h
, gen_helper_sve2_sqrdmulh_idx_h
)
3486 DO_SVE2_RRX(SQRDMULH_zzx_s
, gen_helper_sve2_sqrdmulh_idx_s
)
3487 DO_SVE2_RRX(SQRDMULH_zzx_d
, gen_helper_sve2_sqrdmulh_idx_d
)
3491 #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \
3492 TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
3493 a->rd, a->rn, a->rm, (a->index << 1) | TOP)
3495 DO_SVE2_RRX_TB(SQDMULLB_zzx_s
, gen_helper_sve2_sqdmull_idx_s
, false)
3496 DO_SVE2_RRX_TB(SQDMULLB_zzx_d
, gen_helper_sve2_sqdmull_idx_d
, false)
3497 DO_SVE2_RRX_TB(SQDMULLT_zzx_s
, gen_helper_sve2_sqdmull_idx_s
, true)
3498 DO_SVE2_RRX_TB(SQDMULLT_zzx_d
, gen_helper_sve2_sqdmull_idx_d
, true)
3500 DO_SVE2_RRX_TB(SMULLB_zzx_s
, gen_helper_sve2_smull_idx_s
, false)
3501 DO_SVE2_RRX_TB(SMULLB_zzx_d
, gen_helper_sve2_smull_idx_d
, false)
3502 DO_SVE2_RRX_TB(SMULLT_zzx_s
, gen_helper_sve2_smull_idx_s
, true)
3503 DO_SVE2_RRX_TB(SMULLT_zzx_d
, gen_helper_sve2_smull_idx_d
, true)
3505 DO_SVE2_RRX_TB(UMULLB_zzx_s
, gen_helper_sve2_umull_idx_s
, false)
3506 DO_SVE2_RRX_TB(UMULLB_zzx_d
, gen_helper_sve2_umull_idx_d
, false)
3507 DO_SVE2_RRX_TB(UMULLT_zzx_s
, gen_helper_sve2_umull_idx_s
, true)
3508 DO_SVE2_RRX_TB(UMULLT_zzx_d
, gen_helper_sve2_umull_idx_d
, true)
3510 #undef DO_SVE2_RRX_TB
3512 #define DO_SVE2_RRXR(NAME, FUNC) \
3513 TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a)
3515 DO_SVE2_RRXR(MLA_zzxz_h
, gen_helper_gvec_mla_idx_h
)
3516 DO_SVE2_RRXR(MLA_zzxz_s
, gen_helper_gvec_mla_idx_s
)
3517 DO_SVE2_RRXR(MLA_zzxz_d
, gen_helper_gvec_mla_idx_d
)
3519 DO_SVE2_RRXR(MLS_zzxz_h
, gen_helper_gvec_mls_idx_h
)
3520 DO_SVE2_RRXR(MLS_zzxz_s
, gen_helper_gvec_mls_idx_s
)
3521 DO_SVE2_RRXR(MLS_zzxz_d
, gen_helper_gvec_mls_idx_d
)
3523 DO_SVE2_RRXR(SQRDMLAH_zzxz_h
, gen_helper_sve2_sqrdmlah_idx_h
)
3524 DO_SVE2_RRXR(SQRDMLAH_zzxz_s
, gen_helper_sve2_sqrdmlah_idx_s
)
3525 DO_SVE2_RRXR(SQRDMLAH_zzxz_d
, gen_helper_sve2_sqrdmlah_idx_d
)
3527 DO_SVE2_RRXR(SQRDMLSH_zzxz_h
, gen_helper_sve2_sqrdmlsh_idx_h
)
3528 DO_SVE2_RRXR(SQRDMLSH_zzxz_s
, gen_helper_sve2_sqrdmlsh_idx_s
)
3529 DO_SVE2_RRXR(SQRDMLSH_zzxz_d
, gen_helper_sve2_sqrdmlsh_idx_d
)
3533 #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \
3534 TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
3535 a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP)
3537 DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s
, gen_helper_sve2_sqdmlal_idx_s
, false)
3538 DO_SVE2_RRXR_TB(SQDMLALB_zzxw_d
, gen_helper_sve2_sqdmlal_idx_d
, false)
3539 DO_SVE2_RRXR_TB(SQDMLALT_zzxw_s
, gen_helper_sve2_sqdmlal_idx_s
, true)
3540 DO_SVE2_RRXR_TB(SQDMLALT_zzxw_d
, gen_helper_sve2_sqdmlal_idx_d
, true)
3542 DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_s
, gen_helper_sve2_sqdmlsl_idx_s
, false)
3543 DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_d
, gen_helper_sve2_sqdmlsl_idx_d
, false)
3544 DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_s
, gen_helper_sve2_sqdmlsl_idx_s
, true)
3545 DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_d
, gen_helper_sve2_sqdmlsl_idx_d
, true)
3547 DO_SVE2_RRXR_TB(SMLALB_zzxw_s
, gen_helper_sve2_smlal_idx_s
, false)
3548 DO_SVE2_RRXR_TB(SMLALB_zzxw_d
, gen_helper_sve2_smlal_idx_d
, false)
3549 DO_SVE2_RRXR_TB(SMLALT_zzxw_s
, gen_helper_sve2_smlal_idx_s
, true)
3550 DO_SVE2_RRXR_TB(SMLALT_zzxw_d
, gen_helper_sve2_smlal_idx_d
, true)
3552 DO_SVE2_RRXR_TB(UMLALB_zzxw_s
, gen_helper_sve2_umlal_idx_s
, false)
3553 DO_SVE2_RRXR_TB(UMLALB_zzxw_d
, gen_helper_sve2_umlal_idx_d
, false)
3554 DO_SVE2_RRXR_TB(UMLALT_zzxw_s
, gen_helper_sve2_umlal_idx_s
, true)
3555 DO_SVE2_RRXR_TB(UMLALT_zzxw_d
, gen_helper_sve2_umlal_idx_d
, true)
3557 DO_SVE2_RRXR_TB(SMLSLB_zzxw_s
, gen_helper_sve2_smlsl_idx_s
, false)
3558 DO_SVE2_RRXR_TB(SMLSLB_zzxw_d
, gen_helper_sve2_smlsl_idx_d
, false)
3559 DO_SVE2_RRXR_TB(SMLSLT_zzxw_s
, gen_helper_sve2_smlsl_idx_s
, true)
3560 DO_SVE2_RRXR_TB(SMLSLT_zzxw_d
, gen_helper_sve2_smlsl_idx_d
, true)
3562 DO_SVE2_RRXR_TB(UMLSLB_zzxw_s
, gen_helper_sve2_umlsl_idx_s
, false)
3563 DO_SVE2_RRXR_TB(UMLSLB_zzxw_d
, gen_helper_sve2_umlsl_idx_d
, false)
3564 DO_SVE2_RRXR_TB(UMLSLT_zzxw_s
, gen_helper_sve2_umlsl_idx_s
, true)
3565 DO_SVE2_RRXR_TB(UMLSLT_zzxw_d
, gen_helper_sve2_umlsl_idx_d
, true)
3567 #undef DO_SVE2_RRXR_TB
3569 #define DO_SVE2_RRXR_ROT(NAME, FUNC) \
3570 TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
3571 a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot)
3573 DO_SVE2_RRXR_ROT(CMLA_zzxz_h
, gen_helper_sve2_cmla_idx_h
)
3574 DO_SVE2_RRXR_ROT(CMLA_zzxz_s
, gen_helper_sve2_cmla_idx_s
)
3576 DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_h
, gen_helper_sve2_sqrdcmlah_idx_h
)
3577 DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_s
, gen_helper_sve2_sqrdcmlah_idx_s
)
3579 DO_SVE2_RRXR_ROT(CDOT_zzxw_s
, gen_helper_sve2_cdot_idx_s
)
3580 DO_SVE2_RRXR_ROT(CDOT_zzxw_d
, gen_helper_sve2_cdot_idx_d
)
3582 #undef DO_SVE2_RRXR_ROT
3585 *** SVE Floating Point Multiply-Add Indexed Group
3588 static bool do_FMLA_zzxz(DisasContext
*s
, arg_rrxr_esz
*a
, bool sub
)
3590 static gen_helper_gvec_4_ptr
* const fns
[3] = {
3591 gen_helper_gvec_fmla_idx_h
,
3592 gen_helper_gvec_fmla_idx_s
,
3593 gen_helper_gvec_fmla_idx_d
,
3596 if (sve_access_check(s
)) {
3597 unsigned vsz
= vec_full_reg_size(s
);
3598 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3599 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
3600 vec_full_reg_offset(s
, a
->rn
),
3601 vec_full_reg_offset(s
, a
->rm
),
3602 vec_full_reg_offset(s
, a
->ra
),
3603 status
, vsz
, vsz
, (a
->index
<< 1) | sub
,
3605 tcg_temp_free_ptr(status
);
3610 static bool trans_FMLA_zzxz(DisasContext
*s
, arg_FMLA_zzxz
*a
)
3612 return do_FMLA_zzxz(s
, a
, false);
3615 static bool trans_FMLS_zzxz(DisasContext
*s
, arg_FMLA_zzxz
*a
)
3617 return do_FMLA_zzxz(s
, a
, true);
3621 *** SVE Floating Point Multiply Indexed Group
3624 static bool trans_FMUL_zzx(DisasContext
*s
, arg_FMUL_zzx
*a
)
3626 static gen_helper_gvec_3_ptr
* const fns
[3] = {
3627 gen_helper_gvec_fmul_idx_h
,
3628 gen_helper_gvec_fmul_idx_s
,
3629 gen_helper_gvec_fmul_idx_d
,
3632 if (sve_access_check(s
)) {
3633 unsigned vsz
= vec_full_reg_size(s
);
3634 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3635 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, a
->rd
),
3636 vec_full_reg_offset(s
, a
->rn
),
3637 vec_full_reg_offset(s
, a
->rm
),
3638 status
, vsz
, vsz
, a
->index
, fns
[a
->esz
- 1]);
3639 tcg_temp_free_ptr(status
);
3645 *** SVE Floating Point Fast Reduction Group
3648 typedef void gen_helper_fp_reduce(TCGv_i64
, TCGv_ptr
, TCGv_ptr
,
3649 TCGv_ptr
, TCGv_i32
);
3651 static void do_reduce(DisasContext
*s
, arg_rpr_esz
*a
,
3652 gen_helper_fp_reduce
*fn
)
3654 unsigned vsz
= vec_full_reg_size(s
);
3655 unsigned p2vsz
= pow2ceil(vsz
);
3656 TCGv_i32 t_desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, p2vsz
));
3657 TCGv_ptr t_zn
, t_pg
, status
;
3660 temp
= tcg_temp_new_i64();
3661 t_zn
= tcg_temp_new_ptr();
3662 t_pg
= tcg_temp_new_ptr();
3664 tcg_gen_addi_ptr(t_zn
, cpu_env
, vec_full_reg_offset(s
, a
->rn
));
3665 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
3666 status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3668 fn(temp
, t_zn
, t_pg
, status
, t_desc
);
3669 tcg_temp_free_ptr(t_zn
);
3670 tcg_temp_free_ptr(t_pg
);
3671 tcg_temp_free_ptr(status
);
3673 write_fp_dreg(s
, a
->rd
, temp
);
3674 tcg_temp_free_i64(temp
);
3677 #define DO_VPZ(NAME, name) \
3678 static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
3680 static gen_helper_fp_reduce * const fns[3] = { \
3681 gen_helper_sve_##name##_h, \
3682 gen_helper_sve_##name##_s, \
3683 gen_helper_sve_##name##_d, \
3685 if (a->esz == 0) { \
3688 if (sve_access_check(s)) { \
3689 do_reduce(s, a, fns[a->esz - 1]); \
3694 DO_VPZ(FADDV
, faddv
)
3695 DO_VPZ(FMINNMV
, fminnmv
)
3696 DO_VPZ(FMAXNMV
, fmaxnmv
)
3697 DO_VPZ(FMINV
, fminv
)
3698 DO_VPZ(FMAXV
, fmaxv
)
3701 *** SVE Floating Point Unary Operations - Unpredicated Group
3704 static void do_zz_fp(DisasContext
*s
, arg_rr_esz
*a
, gen_helper_gvec_2_ptr
*fn
)
3706 unsigned vsz
= vec_full_reg_size(s
);
3707 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3709 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, a
->rd
),
3710 vec_full_reg_offset(s
, a
->rn
),
3711 status
, vsz
, vsz
, 0, fn
);
3712 tcg_temp_free_ptr(status
);
3715 static bool trans_FRECPE(DisasContext
*s
, arg_rr_esz
*a
)
3717 static gen_helper_gvec_2_ptr
* const fns
[3] = {
3718 gen_helper_gvec_frecpe_h
,
3719 gen_helper_gvec_frecpe_s
,
3720 gen_helper_gvec_frecpe_d
,
3725 if (sve_access_check(s
)) {
3726 do_zz_fp(s
, a
, fns
[a
->esz
- 1]);
3731 static bool trans_FRSQRTE(DisasContext
*s
, arg_rr_esz
*a
)
3733 static gen_helper_gvec_2_ptr
* const fns
[3] = {
3734 gen_helper_gvec_frsqrte_h
,
3735 gen_helper_gvec_frsqrte_s
,
3736 gen_helper_gvec_frsqrte_d
,
3741 if (sve_access_check(s
)) {
3742 do_zz_fp(s
, a
, fns
[a
->esz
- 1]);
3748 *** SVE Floating Point Compare with Zero Group
3751 static void do_ppz_fp(DisasContext
*s
, arg_rpr_esz
*a
,
3752 gen_helper_gvec_3_ptr
*fn
)
3754 unsigned vsz
= vec_full_reg_size(s
);
3755 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3757 tcg_gen_gvec_3_ptr(pred_full_reg_offset(s
, a
->rd
),
3758 vec_full_reg_offset(s
, a
->rn
),
3759 pred_full_reg_offset(s
, a
->pg
),
3760 status
, vsz
, vsz
, 0, fn
);
3761 tcg_temp_free_ptr(status
);
3764 #define DO_PPZ(NAME, name) \
3765 static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
3767 static gen_helper_gvec_3_ptr * const fns[3] = { \
3768 gen_helper_sve_##name##_h, \
3769 gen_helper_sve_##name##_s, \
3770 gen_helper_sve_##name##_d, \
3772 if (a->esz == 0) { \
3775 if (sve_access_check(s)) { \
3776 do_ppz_fp(s, a, fns[a->esz - 1]); \
3781 DO_PPZ(FCMGE_ppz0
, fcmge0
)
3782 DO_PPZ(FCMGT_ppz0
, fcmgt0
)
3783 DO_PPZ(FCMLE_ppz0
, fcmle0
)
3784 DO_PPZ(FCMLT_ppz0
, fcmlt0
)
3785 DO_PPZ(FCMEQ_ppz0
, fcmeq0
)
3786 DO_PPZ(FCMNE_ppz0
, fcmne0
)
3791 *** SVE floating-point trig multiply-add coefficient
3794 static bool trans_FTMAD(DisasContext
*s
, arg_FTMAD
*a
)
3796 static gen_helper_gvec_3_ptr
* const fns
[3] = {
3797 gen_helper_sve_ftmad_h
,
3798 gen_helper_sve_ftmad_s
,
3799 gen_helper_sve_ftmad_d
,
3805 if (sve_access_check(s
)) {
3806 unsigned vsz
= vec_full_reg_size(s
);
3807 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3808 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, a
->rd
),
3809 vec_full_reg_offset(s
, a
->rn
),
3810 vec_full_reg_offset(s
, a
->rm
),
3811 status
, vsz
, vsz
, a
->imm
, fns
[a
->esz
- 1]);
3812 tcg_temp_free_ptr(status
);
3818 *** SVE Floating Point Accumulating Reduction Group
3821 static bool trans_FADDA(DisasContext
*s
, arg_rprr_esz
*a
)
3823 typedef void fadda_fn(TCGv_i64
, TCGv_i64
, TCGv_ptr
,
3824 TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
3825 static fadda_fn
* const fns
[3] = {
3826 gen_helper_sve_fadda_h
,
3827 gen_helper_sve_fadda_s
,
3828 gen_helper_sve_fadda_d
,
3830 unsigned vsz
= vec_full_reg_size(s
);
3831 TCGv_ptr t_rm
, t_pg
, t_fpst
;
3838 if (!sve_access_check(s
)) {
3842 t_val
= load_esz(cpu_env
, vec_reg_offset(s
, a
->rn
, 0, a
->esz
), a
->esz
);
3843 t_rm
= tcg_temp_new_ptr();
3844 t_pg
= tcg_temp_new_ptr();
3845 tcg_gen_addi_ptr(t_rm
, cpu_env
, vec_full_reg_offset(s
, a
->rm
));
3846 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
3847 t_fpst
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3848 t_desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, 0));
3850 fns
[a
->esz
- 1](t_val
, t_val
, t_rm
, t_pg
, t_fpst
, t_desc
);
3852 tcg_temp_free_ptr(t_fpst
);
3853 tcg_temp_free_ptr(t_pg
);
3854 tcg_temp_free_ptr(t_rm
);
3856 write_fp_dreg(s
, a
->rd
, t_val
);
3857 tcg_temp_free_i64(t_val
);
3862 *** SVE Floating Point Arithmetic - Unpredicated Group
3865 static bool do_zzz_fp(DisasContext
*s
, arg_rrr_esz
*a
,
3866 gen_helper_gvec_3_ptr
*fn
)
3871 if (sve_access_check(s
)) {
3872 unsigned vsz
= vec_full_reg_size(s
);
3873 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3874 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, a
->rd
),
3875 vec_full_reg_offset(s
, a
->rn
),
3876 vec_full_reg_offset(s
, a
->rm
),
3877 status
, vsz
, vsz
, 0, fn
);
3878 tcg_temp_free_ptr(status
);
3884 #define DO_FP3(NAME, name) \
3885 static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
3887 static gen_helper_gvec_3_ptr * const fns[4] = { \
3888 NULL, gen_helper_gvec_##name##_h, \
3889 gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \
3891 return do_zzz_fp(s, a, fns[a->esz]); \
3894 DO_FP3(FADD_zzz
, fadd
)
3895 DO_FP3(FSUB_zzz
, fsub
)
3896 DO_FP3(FMUL_zzz
, fmul
)
3897 DO_FP3(FTSMUL
, ftsmul
)
3898 DO_FP3(FRECPS
, recps
)
3899 DO_FP3(FRSQRTS
, rsqrts
)
3904 *** SVE Floating Point Arithmetic - Predicated Group
3907 static bool do_zpzz_fp(DisasContext
*s
, arg_rprr_esz
*a
,
3908 gen_helper_gvec_4_ptr
*fn
)
3913 if (sve_access_check(s
)) {
3914 unsigned vsz
= vec_full_reg_size(s
);
3915 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
3916 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
3917 vec_full_reg_offset(s
, a
->rn
),
3918 vec_full_reg_offset(s
, a
->rm
),
3919 pred_full_reg_offset(s
, a
->pg
),
3920 status
, vsz
, vsz
, 0, fn
);
3921 tcg_temp_free_ptr(status
);
3926 #define DO_FP3(NAME, name) \
3927 static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
3929 static gen_helper_gvec_4_ptr * const fns[4] = { \
3930 NULL, gen_helper_sve_##name##_h, \
3931 gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
3933 return do_zpzz_fp(s, a, fns[a->esz]); \
3936 DO_FP3(FADD_zpzz
, fadd
)
3937 DO_FP3(FSUB_zpzz
, fsub
)
3938 DO_FP3(FMUL_zpzz
, fmul
)
3939 DO_FP3(FMIN_zpzz
, fmin
)
3940 DO_FP3(FMAX_zpzz
, fmax
)
3941 DO_FP3(FMINNM_zpzz
, fminnum
)
3942 DO_FP3(FMAXNM_zpzz
, fmaxnum
)
3944 DO_FP3(FSCALE
, fscalbn
)
3946 DO_FP3(FMULX
, fmulx
)
3950 typedef void gen_helper_sve_fp2scalar(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
,
3951 TCGv_i64
, TCGv_ptr
, TCGv_i32
);
3953 static void do_fp_scalar(DisasContext
*s
, int zd
, int zn
, int pg
, bool is_fp16
,
3954 TCGv_i64 scalar
, gen_helper_sve_fp2scalar
*fn
)
3956 unsigned vsz
= vec_full_reg_size(s
);
3957 TCGv_ptr t_zd
, t_zn
, t_pg
, status
;
3960 t_zd
= tcg_temp_new_ptr();
3961 t_zn
= tcg_temp_new_ptr();
3962 t_pg
= tcg_temp_new_ptr();
3963 tcg_gen_addi_ptr(t_zd
, cpu_env
, vec_full_reg_offset(s
, zd
));
3964 tcg_gen_addi_ptr(t_zn
, cpu_env
, vec_full_reg_offset(s
, zn
));
3965 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, pg
));
3967 status
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
3968 desc
= tcg_constant_i32(simd_desc(vsz
, vsz
, 0));
3969 fn(t_zd
, t_zn
, t_pg
, scalar
, status
, desc
);
3971 tcg_temp_free_ptr(status
);
3972 tcg_temp_free_ptr(t_pg
);
3973 tcg_temp_free_ptr(t_zn
);
3974 tcg_temp_free_ptr(t_zd
);
3977 static void do_fp_imm(DisasContext
*s
, arg_rpri_esz
*a
, uint64_t imm
,
3978 gen_helper_sve_fp2scalar
*fn
)
3980 do_fp_scalar(s
, a
->rd
, a
->rn
, a
->pg
, a
->esz
== MO_16
,
3981 tcg_constant_i64(imm
), fn
);
3984 #define DO_FP_IMM(NAME, name, const0, const1) \
3985 static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a) \
3987 static gen_helper_sve_fp2scalar * const fns[3] = { \
3988 gen_helper_sve_##name##_h, \
3989 gen_helper_sve_##name##_s, \
3990 gen_helper_sve_##name##_d \
3992 static uint64_t const val[3][2] = { \
3993 { float16_##const0, float16_##const1 }, \
3994 { float32_##const0, float32_##const1 }, \
3995 { float64_##const0, float64_##const1 }, \
3997 if (a->esz == 0) { \
4000 if (sve_access_check(s)) { \
4001 do_fp_imm(s, a, val[a->esz - 1][a->imm], fns[a->esz - 1]); \
4006 DO_FP_IMM(FADD
, fadds
, half
, one
)
4007 DO_FP_IMM(FSUB
, fsubs
, half
, one
)
4008 DO_FP_IMM(FMUL
, fmuls
, half
, two
)
4009 DO_FP_IMM(FSUBR
, fsubrs
, half
, one
)
4010 DO_FP_IMM(FMAXNM
, fmaxnms
, zero
, one
)
4011 DO_FP_IMM(FMINNM
, fminnms
, zero
, one
)
4012 DO_FP_IMM(FMAX
, fmaxs
, zero
, one
)
4013 DO_FP_IMM(FMIN
, fmins
, zero
, one
)
4017 static bool do_fp_cmp(DisasContext
*s
, arg_rprr_esz
*a
,
4018 gen_helper_gvec_4_ptr
*fn
)
4023 if (sve_access_check(s
)) {
4024 unsigned vsz
= vec_full_reg_size(s
);
4025 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
4026 tcg_gen_gvec_4_ptr(pred_full_reg_offset(s
, a
->rd
),
4027 vec_full_reg_offset(s
, a
->rn
),
4028 vec_full_reg_offset(s
, a
->rm
),
4029 pred_full_reg_offset(s
, a
->pg
),
4030 status
, vsz
, vsz
, 0, fn
);
4031 tcg_temp_free_ptr(status
);
4036 #define DO_FPCMP(NAME, name) \
4037 static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \
4039 static gen_helper_gvec_4_ptr * const fns[4] = { \
4040 NULL, gen_helper_sve_##name##_h, \
4041 gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
4043 return do_fp_cmp(s, a, fns[a->esz]); \
4046 DO_FPCMP(FCMGE
, fcmge
)
4047 DO_FPCMP(FCMGT
, fcmgt
)
4048 DO_FPCMP(FCMEQ
, fcmeq
)
4049 DO_FPCMP(FCMNE
, fcmne
)
4050 DO_FPCMP(FCMUO
, fcmuo
)
4051 DO_FPCMP(FACGE
, facge
)
4052 DO_FPCMP(FACGT
, facgt
)
4056 static bool trans_FCADD(DisasContext
*s
, arg_FCADD
*a
)
4058 static gen_helper_gvec_4_ptr
* const fns
[3] = {
4059 gen_helper_sve_fcadd_h
,
4060 gen_helper_sve_fcadd_s
,
4061 gen_helper_sve_fcadd_d
4067 if (sve_access_check(s
)) {
4068 unsigned vsz
= vec_full_reg_size(s
);
4069 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
4070 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
4071 vec_full_reg_offset(s
, a
->rn
),
4072 vec_full_reg_offset(s
, a
->rm
),
4073 pred_full_reg_offset(s
, a
->pg
),
4074 status
, vsz
, vsz
, a
->rot
, fns
[a
->esz
- 1]);
4075 tcg_temp_free_ptr(status
);
4080 static bool do_fmla(DisasContext
*s
, arg_rprrr_esz
*a
,
4081 gen_helper_gvec_5_ptr
*fn
)
4086 if (sve_access_check(s
)) {
4087 unsigned vsz
= vec_full_reg_size(s
);
4088 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
4089 tcg_gen_gvec_5_ptr(vec_full_reg_offset(s
, a
->rd
),
4090 vec_full_reg_offset(s
, a
->rn
),
4091 vec_full_reg_offset(s
, a
->rm
),
4092 vec_full_reg_offset(s
, a
->ra
),
4093 pred_full_reg_offset(s
, a
->pg
),
4094 status
, vsz
, vsz
, 0, fn
);
4095 tcg_temp_free_ptr(status
);
4100 #define DO_FMLA(NAME, name) \
4101 static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
4103 static gen_helper_gvec_5_ptr * const fns[4] = { \
4104 NULL, gen_helper_sve_##name##_h, \
4105 gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
4107 return do_fmla(s, a, fns[a->esz]); \
4110 DO_FMLA(FMLA_zpzzz
, fmla_zpzzz
)
4111 DO_FMLA(FMLS_zpzzz
, fmls_zpzzz
)
4112 DO_FMLA(FNMLA_zpzzz
, fnmla_zpzzz
)
4113 DO_FMLA(FNMLS_zpzzz
, fnmls_zpzzz
)
4117 static bool trans_FCMLA_zpzzz(DisasContext
*s
, arg_FCMLA_zpzzz
*a
)
4119 static gen_helper_gvec_5_ptr
* const fns
[4] = {
4121 gen_helper_sve_fcmla_zpzzz_h
,
4122 gen_helper_sve_fcmla_zpzzz_s
,
4123 gen_helper_sve_fcmla_zpzzz_d
,
4129 if (sve_access_check(s
)) {
4130 unsigned vsz
= vec_full_reg_size(s
);
4131 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
4132 tcg_gen_gvec_5_ptr(vec_full_reg_offset(s
, a
->rd
),
4133 vec_full_reg_offset(s
, a
->rn
),
4134 vec_full_reg_offset(s
, a
->rm
),
4135 vec_full_reg_offset(s
, a
->ra
),
4136 pred_full_reg_offset(s
, a
->pg
),
4137 status
, vsz
, vsz
, a
->rot
, fns
[a
->esz
]);
4138 tcg_temp_free_ptr(status
);
4143 static bool trans_FCMLA_zzxz(DisasContext
*s
, arg_FCMLA_zzxz
*a
)
4145 static gen_helper_gvec_4_ptr
* const fns
[2] = {
4146 gen_helper_gvec_fcmlah_idx
,
4147 gen_helper_gvec_fcmlas_idx
,
4150 tcg_debug_assert(a
->esz
== 1 || a
->esz
== 2);
4151 tcg_debug_assert(a
->rd
== a
->ra
);
4152 if (sve_access_check(s
)) {
4153 unsigned vsz
= vec_full_reg_size(s
);
4154 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
4155 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
4156 vec_full_reg_offset(s
, a
->rn
),
4157 vec_full_reg_offset(s
, a
->rm
),
4158 vec_full_reg_offset(s
, a
->ra
),
4160 a
->index
* 4 + a
->rot
,
4162 tcg_temp_free_ptr(status
);
4168 *** SVE Floating Point Unary Operations Predicated Group
4171 static bool do_zpz_ptr(DisasContext
*s
, int rd
, int rn
, int pg
,
4172 bool is_fp16
, gen_helper_gvec_3_ptr
*fn
)
4174 if (sve_access_check(s
)) {
4175 unsigned vsz
= vec_full_reg_size(s
);
4176 TCGv_ptr status
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
4177 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
4178 vec_full_reg_offset(s
, rn
),
4179 pred_full_reg_offset(s
, pg
),
4180 status
, vsz
, vsz
, 0, fn
);
4181 tcg_temp_free_ptr(status
);
4186 static bool trans_FCVT_sh(DisasContext
*s
, arg_rpr_esz
*a
)
4188 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvt_sh
);
4191 static bool trans_FCVT_hs(DisasContext
*s
, arg_rpr_esz
*a
)
4193 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvt_hs
);
4196 static bool trans_BFCVT(DisasContext
*s
, arg_rpr_esz
*a
)
4198 if (!dc_isar_feature(aa64_sve_bf16
, s
)) {
4201 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_bfcvt
);
4204 static bool trans_FCVT_dh(DisasContext
*s
, arg_rpr_esz
*a
)
4206 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvt_dh
);
4209 static bool trans_FCVT_hd(DisasContext
*s
, arg_rpr_esz
*a
)
4211 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvt_hd
);
4214 static bool trans_FCVT_ds(DisasContext
*s
, arg_rpr_esz
*a
)
4216 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvt_ds
);
4219 static bool trans_FCVT_sd(DisasContext
*s
, arg_rpr_esz
*a
)
4221 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvt_sd
);
4224 static bool trans_FCVTZS_hh(DisasContext
*s
, arg_rpr_esz
*a
)
4226 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_fcvtzs_hh
);
4229 static bool trans_FCVTZU_hh(DisasContext
*s
, arg_rpr_esz
*a
)
4231 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_fcvtzu_hh
);
4234 static bool trans_FCVTZS_hs(DisasContext
*s
, arg_rpr_esz
*a
)
4236 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_fcvtzs_hs
);
4239 static bool trans_FCVTZU_hs(DisasContext
*s
, arg_rpr_esz
*a
)
4241 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_fcvtzu_hs
);
4244 static bool trans_FCVTZS_hd(DisasContext
*s
, arg_rpr_esz
*a
)
4246 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_fcvtzs_hd
);
4249 static bool trans_FCVTZU_hd(DisasContext
*s
, arg_rpr_esz
*a
)
4251 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_fcvtzu_hd
);
4254 static bool trans_FCVTZS_ss(DisasContext
*s
, arg_rpr_esz
*a
)
4256 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzs_ss
);
4259 static bool trans_FCVTZU_ss(DisasContext
*s
, arg_rpr_esz
*a
)
4261 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzu_ss
);
4264 static bool trans_FCVTZS_sd(DisasContext
*s
, arg_rpr_esz
*a
)
4266 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzs_sd
);
4269 static bool trans_FCVTZU_sd(DisasContext
*s
, arg_rpr_esz
*a
)
4271 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzu_sd
);
4274 static bool trans_FCVTZS_ds(DisasContext
*s
, arg_rpr_esz
*a
)
4276 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzs_ds
);
4279 static bool trans_FCVTZU_ds(DisasContext
*s
, arg_rpr_esz
*a
)
4281 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzu_ds
);
4284 static bool trans_FCVTZS_dd(DisasContext
*s
, arg_rpr_esz
*a
)
4286 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzs_dd
);
4289 static bool trans_FCVTZU_dd(DisasContext
*s
, arg_rpr_esz
*a
)
4291 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_fcvtzu_dd
);
4294 static gen_helper_gvec_3_ptr
* const frint_fns
[3] = {
4295 gen_helper_sve_frint_h
,
4296 gen_helper_sve_frint_s
,
4297 gen_helper_sve_frint_d
4300 static bool trans_FRINTI(DisasContext
*s
, arg_rpr_esz
*a
)
4305 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, a
->esz
== MO_16
,
4306 frint_fns
[a
->esz
- 1]);
4309 static bool trans_FRINTX(DisasContext
*s
, arg_rpr_esz
*a
)
4311 static gen_helper_gvec_3_ptr
* const fns
[3] = {
4312 gen_helper_sve_frintx_h
,
4313 gen_helper_sve_frintx_s
,
4314 gen_helper_sve_frintx_d
4319 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, a
->esz
== MO_16
, fns
[a
->esz
- 1]);
4322 static bool do_frint_mode(DisasContext
*s
, arg_rpr_esz
*a
,
4323 int mode
, gen_helper_gvec_3_ptr
*fn
)
4325 if (sve_access_check(s
)) {
4326 unsigned vsz
= vec_full_reg_size(s
);
4327 TCGv_i32 tmode
= tcg_const_i32(mode
);
4328 TCGv_ptr status
= fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
4330 gen_helper_set_rmode(tmode
, tmode
, status
);
4332 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, a
->rd
),
4333 vec_full_reg_offset(s
, a
->rn
),
4334 pred_full_reg_offset(s
, a
->pg
),
4335 status
, vsz
, vsz
, 0, fn
);
4337 gen_helper_set_rmode(tmode
, tmode
, status
);
4338 tcg_temp_free_i32(tmode
);
4339 tcg_temp_free_ptr(status
);
4344 static bool trans_FRINTN(DisasContext
*s
, arg_rpr_esz
*a
)
4349 return do_frint_mode(s
, a
, float_round_nearest_even
, frint_fns
[a
->esz
- 1]);
4352 static bool trans_FRINTP(DisasContext
*s
, arg_rpr_esz
*a
)
4357 return do_frint_mode(s
, a
, float_round_up
, frint_fns
[a
->esz
- 1]);
4360 static bool trans_FRINTM(DisasContext
*s
, arg_rpr_esz
*a
)
4365 return do_frint_mode(s
, a
, float_round_down
, frint_fns
[a
->esz
- 1]);
4368 static bool trans_FRINTZ(DisasContext
*s
, arg_rpr_esz
*a
)
4373 return do_frint_mode(s
, a
, float_round_to_zero
, frint_fns
[a
->esz
- 1]);
4376 static bool trans_FRINTA(DisasContext
*s
, arg_rpr_esz
*a
)
4381 return do_frint_mode(s
, a
, float_round_ties_away
, frint_fns
[a
->esz
- 1]);
4384 static bool trans_FRECPX(DisasContext
*s
, arg_rpr_esz
*a
)
4386 static gen_helper_gvec_3_ptr
* const fns
[3] = {
4387 gen_helper_sve_frecpx_h
,
4388 gen_helper_sve_frecpx_s
,
4389 gen_helper_sve_frecpx_d
4394 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, a
->esz
== MO_16
, fns
[a
->esz
- 1]);
4397 static bool trans_FSQRT(DisasContext
*s
, arg_rpr_esz
*a
)
4399 static gen_helper_gvec_3_ptr
* const fns
[3] = {
4400 gen_helper_sve_fsqrt_h
,
4401 gen_helper_sve_fsqrt_s
,
4402 gen_helper_sve_fsqrt_d
4407 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, a
->esz
== MO_16
, fns
[a
->esz
- 1]);
4410 static bool trans_SCVTF_hh(DisasContext
*s
, arg_rpr_esz
*a
)
4412 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_scvt_hh
);
4415 static bool trans_SCVTF_sh(DisasContext
*s
, arg_rpr_esz
*a
)
4417 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_scvt_sh
);
4420 static bool trans_SCVTF_dh(DisasContext
*s
, arg_rpr_esz
*a
)
4422 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_scvt_dh
);
4425 static bool trans_SCVTF_ss(DisasContext
*s
, arg_rpr_esz
*a
)
4427 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_scvt_ss
);
4430 static bool trans_SCVTF_ds(DisasContext
*s
, arg_rpr_esz
*a
)
4432 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_scvt_ds
);
4435 static bool trans_SCVTF_sd(DisasContext
*s
, arg_rpr_esz
*a
)
4437 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_scvt_sd
);
4440 static bool trans_SCVTF_dd(DisasContext
*s
, arg_rpr_esz
*a
)
4442 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_scvt_dd
);
4445 static bool trans_UCVTF_hh(DisasContext
*s
, arg_rpr_esz
*a
)
4447 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_ucvt_hh
);
4450 static bool trans_UCVTF_sh(DisasContext
*s
, arg_rpr_esz
*a
)
4452 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_ucvt_sh
);
4455 static bool trans_UCVTF_dh(DisasContext
*s
, arg_rpr_esz
*a
)
4457 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, true, gen_helper_sve_ucvt_dh
);
4460 static bool trans_UCVTF_ss(DisasContext
*s
, arg_rpr_esz
*a
)
4462 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_ucvt_ss
);
4465 static bool trans_UCVTF_ds(DisasContext
*s
, arg_rpr_esz
*a
)
4467 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_ucvt_ds
);
4470 static bool trans_UCVTF_sd(DisasContext
*s
, arg_rpr_esz
*a
)
4472 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_ucvt_sd
);
4475 static bool trans_UCVTF_dd(DisasContext
*s
, arg_rpr_esz
*a
)
4477 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_ucvt_dd
);
4481 *** SVE Memory - 32-bit Gather and Unsized Contiguous Group
4484 /* Subroutine loading a vector register at VOFS of LEN bytes.
4485 * The load should begin at the address Rn + IMM.
4488 static void do_ldr(DisasContext
*s
, uint32_t vofs
, int len
, int rn
, int imm
)
4490 int len_align
= QEMU_ALIGN_DOWN(len
, 8);
4491 int len_remain
= len
% 8;
4492 int nparts
= len
/ 8 + ctpop8(len_remain
);
4493 int midx
= get_mem_index(s
);
4494 TCGv_i64 dirty_addr
, clean_addr
, t0
, t1
;
4496 dirty_addr
= tcg_temp_new_i64();
4497 tcg_gen_addi_i64(dirty_addr
, cpu_reg_sp(s
, rn
), imm
);
4498 clean_addr
= gen_mte_checkN(s
, dirty_addr
, false, rn
!= 31, len
);
4499 tcg_temp_free_i64(dirty_addr
);
4502 * Note that unpredicated load/store of vector/predicate registers
4503 * are defined as a stream of bytes, which equates to little-endian
4504 * operations on larger quantities.
4505 * Attempt to keep code expansion to a minimum by limiting the
4506 * amount of unrolling done.
4511 t0
= tcg_temp_new_i64();
4512 for (i
= 0; i
< len_align
; i
+= 8) {
4513 tcg_gen_qemu_ld_i64(t0
, clean_addr
, midx
, MO_LEUQ
);
4514 tcg_gen_st_i64(t0
, cpu_env
, vofs
+ i
);
4515 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4517 tcg_temp_free_i64(t0
);
4519 TCGLabel
*loop
= gen_new_label();
4520 TCGv_ptr tp
, i
= tcg_const_local_ptr(0);
4522 /* Copy the clean address into a local temp, live across the loop. */
4524 clean_addr
= new_tmp_a64_local(s
);
4525 tcg_gen_mov_i64(clean_addr
, t0
);
4527 gen_set_label(loop
);
4529 t0
= tcg_temp_new_i64();
4530 tcg_gen_qemu_ld_i64(t0
, clean_addr
, midx
, MO_LEUQ
);
4531 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4533 tp
= tcg_temp_new_ptr();
4534 tcg_gen_add_ptr(tp
, cpu_env
, i
);
4535 tcg_gen_addi_ptr(i
, i
, 8);
4536 tcg_gen_st_i64(t0
, tp
, vofs
);
4537 tcg_temp_free_ptr(tp
);
4538 tcg_temp_free_i64(t0
);
4540 tcg_gen_brcondi_ptr(TCG_COND_LTU
, i
, len_align
, loop
);
4541 tcg_temp_free_ptr(i
);
4545 * Predicate register loads can be any multiple of 2.
4546 * Note that we still store the entire 64-bit unit into cpu_env.
4549 t0
= tcg_temp_new_i64();
4550 switch (len_remain
) {
4554 tcg_gen_qemu_ld_i64(t0
, clean_addr
, midx
,
4555 MO_LE
| ctz32(len_remain
));
4559 t1
= tcg_temp_new_i64();
4560 tcg_gen_qemu_ld_i64(t0
, clean_addr
, midx
, MO_LEUL
);
4561 tcg_gen_addi_i64(clean_addr
, clean_addr
, 4);
4562 tcg_gen_qemu_ld_i64(t1
, clean_addr
, midx
, MO_LEUW
);
4563 tcg_gen_deposit_i64(t0
, t0
, t1
, 32, 32);
4564 tcg_temp_free_i64(t1
);
4568 g_assert_not_reached();
4570 tcg_gen_st_i64(t0
, cpu_env
, vofs
+ len_align
);
4571 tcg_temp_free_i64(t0
);
4575 /* Similarly for stores. */
4576 static void do_str(DisasContext
*s
, uint32_t vofs
, int len
, int rn
, int imm
)
4578 int len_align
= QEMU_ALIGN_DOWN(len
, 8);
4579 int len_remain
= len
% 8;
4580 int nparts
= len
/ 8 + ctpop8(len_remain
);
4581 int midx
= get_mem_index(s
);
4582 TCGv_i64 dirty_addr
, clean_addr
, t0
;
4584 dirty_addr
= tcg_temp_new_i64();
4585 tcg_gen_addi_i64(dirty_addr
, cpu_reg_sp(s
, rn
), imm
);
4586 clean_addr
= gen_mte_checkN(s
, dirty_addr
, false, rn
!= 31, len
);
4587 tcg_temp_free_i64(dirty_addr
);
4589 /* Note that unpredicated load/store of vector/predicate registers
4590 * are defined as a stream of bytes, which equates to little-endian
4591 * operations on larger quantities. There is no nice way to force
4592 * a little-endian store for aarch64_be-linux-user out of line.
4594 * Attempt to keep code expansion to a minimum by limiting the
4595 * amount of unrolling done.
4600 t0
= tcg_temp_new_i64();
4601 for (i
= 0; i
< len_align
; i
+= 8) {
4602 tcg_gen_ld_i64(t0
, cpu_env
, vofs
+ i
);
4603 tcg_gen_qemu_st_i64(t0
, clean_addr
, midx
, MO_LEUQ
);
4604 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4606 tcg_temp_free_i64(t0
);
4608 TCGLabel
*loop
= gen_new_label();
4609 TCGv_ptr tp
, i
= tcg_const_local_ptr(0);
4611 /* Copy the clean address into a local temp, live across the loop. */
4613 clean_addr
= new_tmp_a64_local(s
);
4614 tcg_gen_mov_i64(clean_addr
, t0
);
4616 gen_set_label(loop
);
4618 t0
= tcg_temp_new_i64();
4619 tp
= tcg_temp_new_ptr();
4620 tcg_gen_add_ptr(tp
, cpu_env
, i
);
4621 tcg_gen_ld_i64(t0
, tp
, vofs
);
4622 tcg_gen_addi_ptr(i
, i
, 8);
4623 tcg_temp_free_ptr(tp
);
4625 tcg_gen_qemu_st_i64(t0
, clean_addr
, midx
, MO_LEUQ
);
4626 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4627 tcg_temp_free_i64(t0
);
4629 tcg_gen_brcondi_ptr(TCG_COND_LTU
, i
, len_align
, loop
);
4630 tcg_temp_free_ptr(i
);
4633 /* Predicate register stores can be any multiple of 2. */
4635 t0
= tcg_temp_new_i64();
4636 tcg_gen_ld_i64(t0
, cpu_env
, vofs
+ len_align
);
4638 switch (len_remain
) {
4642 tcg_gen_qemu_st_i64(t0
, clean_addr
, midx
,
4643 MO_LE
| ctz32(len_remain
));
4647 tcg_gen_qemu_st_i64(t0
, clean_addr
, midx
, MO_LEUL
);
4648 tcg_gen_addi_i64(clean_addr
, clean_addr
, 4);
4649 tcg_gen_shri_i64(t0
, t0
, 32);
4650 tcg_gen_qemu_st_i64(t0
, clean_addr
, midx
, MO_LEUW
);
4654 g_assert_not_reached();
4656 tcg_temp_free_i64(t0
);
4660 static bool trans_LDR_zri(DisasContext
*s
, arg_rri
*a
)
4662 if (sve_access_check(s
)) {
4663 int size
= vec_full_reg_size(s
);
4664 int off
= vec_full_reg_offset(s
, a
->rd
);
4665 do_ldr(s
, off
, size
, a
->rn
, a
->imm
* size
);
4670 static bool trans_LDR_pri(DisasContext
*s
, arg_rri
*a
)
4672 if (sve_access_check(s
)) {
4673 int size
= pred_full_reg_size(s
);
4674 int off
= pred_full_reg_offset(s
, a
->rd
);
4675 do_ldr(s
, off
, size
, a
->rn
, a
->imm
* size
);
4680 static bool trans_STR_zri(DisasContext
*s
, arg_rri
*a
)
4682 if (sve_access_check(s
)) {
4683 int size
= vec_full_reg_size(s
);
4684 int off
= vec_full_reg_offset(s
, a
->rd
);
4685 do_str(s
, off
, size
, a
->rn
, a
->imm
* size
);
4690 static bool trans_STR_pri(DisasContext
*s
, arg_rri
*a
)
4692 if (sve_access_check(s
)) {
4693 int size
= pred_full_reg_size(s
);
4694 int off
= pred_full_reg_offset(s
, a
->rd
);
4695 do_str(s
, off
, size
, a
->rn
, a
->imm
* size
);
4701 *** SVE Memory - Contiguous Load Group
4704 /* The memory mode of the dtype. */
4705 static const MemOp dtype_mop
[16] = {
4706 MO_UB
, MO_UB
, MO_UB
, MO_UB
,
4707 MO_SL
, MO_UW
, MO_UW
, MO_UW
,
4708 MO_SW
, MO_SW
, MO_UL
, MO_UL
,
4709 MO_SB
, MO_SB
, MO_SB
, MO_UQ
4712 #define dtype_msz(x) (dtype_mop[x] & MO_SIZE)
4714 /* The vector element size of dtype. */
4715 static const uint8_t dtype_esz
[16] = {
4722 static void do_mem_zpa(DisasContext
*s
, int zt
, int pg
, TCGv_i64 addr
,
4723 int dtype
, uint32_t mte_n
, bool is_write
,
4724 gen_helper_gvec_mem
*fn
)
4726 unsigned vsz
= vec_full_reg_size(s
);
4731 * For e.g. LD4, there are not enough arguments to pass all 4
4732 * registers as pointers, so encode the regno into the data field.
4733 * For consistency, do this even for LD1.
4735 if (s
->mte_active
[0]) {
4736 int msz
= dtype_msz(dtype
);
4738 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
4739 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
4740 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
4741 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
4742 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (mte_n
<< msz
) - 1);
4743 desc
<<= SVE_MTEDESC_SHIFT
;
4745 addr
= clean_data_tbi(s
, addr
);
4748 desc
= simd_desc(vsz
, vsz
, zt
| desc
);
4749 t_pg
= tcg_temp_new_ptr();
4751 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, pg
));
4752 fn(cpu_env
, t_pg
, addr
, tcg_constant_i32(desc
));
4754 tcg_temp_free_ptr(t_pg
);
4757 /* Indexed by [mte][be][dtype][nreg] */
4758 static gen_helper_gvec_mem
* const ldr_fns
[2][2][16][4] = {
4759 { /* mte inactive, little-endian */
4760 { { gen_helper_sve_ld1bb_r
, gen_helper_sve_ld2bb_r
,
4761 gen_helper_sve_ld3bb_r
, gen_helper_sve_ld4bb_r
},
4762 { gen_helper_sve_ld1bhu_r
, NULL
, NULL
, NULL
},
4763 { gen_helper_sve_ld1bsu_r
, NULL
, NULL
, NULL
},
4764 { gen_helper_sve_ld1bdu_r
, NULL
, NULL
, NULL
},
4766 { gen_helper_sve_ld1sds_le_r
, NULL
, NULL
, NULL
},
4767 { gen_helper_sve_ld1hh_le_r
, gen_helper_sve_ld2hh_le_r
,
4768 gen_helper_sve_ld3hh_le_r
, gen_helper_sve_ld4hh_le_r
},
4769 { gen_helper_sve_ld1hsu_le_r
, NULL
, NULL
, NULL
},
4770 { gen_helper_sve_ld1hdu_le_r
, NULL
, NULL
, NULL
},
4772 { gen_helper_sve_ld1hds_le_r
, NULL
, NULL
, NULL
},
4773 { gen_helper_sve_ld1hss_le_r
, NULL
, NULL
, NULL
},
4774 { gen_helper_sve_ld1ss_le_r
, gen_helper_sve_ld2ss_le_r
,
4775 gen_helper_sve_ld3ss_le_r
, gen_helper_sve_ld4ss_le_r
},
4776 { gen_helper_sve_ld1sdu_le_r
, NULL
, NULL
, NULL
},
4778 { gen_helper_sve_ld1bds_r
, NULL
, NULL
, NULL
},
4779 { gen_helper_sve_ld1bss_r
, NULL
, NULL
, NULL
},
4780 { gen_helper_sve_ld1bhs_r
, NULL
, NULL
, NULL
},
4781 { gen_helper_sve_ld1dd_le_r
, gen_helper_sve_ld2dd_le_r
,
4782 gen_helper_sve_ld3dd_le_r
, gen_helper_sve_ld4dd_le_r
} },
4784 /* mte inactive, big-endian */
4785 { { gen_helper_sve_ld1bb_r
, gen_helper_sve_ld2bb_r
,
4786 gen_helper_sve_ld3bb_r
, gen_helper_sve_ld4bb_r
},
4787 { gen_helper_sve_ld1bhu_r
, NULL
, NULL
, NULL
},
4788 { gen_helper_sve_ld1bsu_r
, NULL
, NULL
, NULL
},
4789 { gen_helper_sve_ld1bdu_r
, NULL
, NULL
, NULL
},
4791 { gen_helper_sve_ld1sds_be_r
, NULL
, NULL
, NULL
},
4792 { gen_helper_sve_ld1hh_be_r
, gen_helper_sve_ld2hh_be_r
,
4793 gen_helper_sve_ld3hh_be_r
, gen_helper_sve_ld4hh_be_r
},
4794 { gen_helper_sve_ld1hsu_be_r
, NULL
, NULL
, NULL
},
4795 { gen_helper_sve_ld1hdu_be_r
, NULL
, NULL
, NULL
},
4797 { gen_helper_sve_ld1hds_be_r
, NULL
, NULL
, NULL
},
4798 { gen_helper_sve_ld1hss_be_r
, NULL
, NULL
, NULL
},
4799 { gen_helper_sve_ld1ss_be_r
, gen_helper_sve_ld2ss_be_r
,
4800 gen_helper_sve_ld3ss_be_r
, gen_helper_sve_ld4ss_be_r
},
4801 { gen_helper_sve_ld1sdu_be_r
, NULL
, NULL
, NULL
},
4803 { gen_helper_sve_ld1bds_r
, NULL
, NULL
, NULL
},
4804 { gen_helper_sve_ld1bss_r
, NULL
, NULL
, NULL
},
4805 { gen_helper_sve_ld1bhs_r
, NULL
, NULL
, NULL
},
4806 { gen_helper_sve_ld1dd_be_r
, gen_helper_sve_ld2dd_be_r
,
4807 gen_helper_sve_ld3dd_be_r
, gen_helper_sve_ld4dd_be_r
} } },
4809 { /* mte active, little-endian */
4810 { { gen_helper_sve_ld1bb_r_mte
,
4811 gen_helper_sve_ld2bb_r_mte
,
4812 gen_helper_sve_ld3bb_r_mte
,
4813 gen_helper_sve_ld4bb_r_mte
},
4814 { gen_helper_sve_ld1bhu_r_mte
, NULL
, NULL
, NULL
},
4815 { gen_helper_sve_ld1bsu_r_mte
, NULL
, NULL
, NULL
},
4816 { gen_helper_sve_ld1bdu_r_mte
, NULL
, NULL
, NULL
},
4818 { gen_helper_sve_ld1sds_le_r_mte
, NULL
, NULL
, NULL
},
4819 { gen_helper_sve_ld1hh_le_r_mte
,
4820 gen_helper_sve_ld2hh_le_r_mte
,
4821 gen_helper_sve_ld3hh_le_r_mte
,
4822 gen_helper_sve_ld4hh_le_r_mte
},
4823 { gen_helper_sve_ld1hsu_le_r_mte
, NULL
, NULL
, NULL
},
4824 { gen_helper_sve_ld1hdu_le_r_mte
, NULL
, NULL
, NULL
},
4826 { gen_helper_sve_ld1hds_le_r_mte
, NULL
, NULL
, NULL
},
4827 { gen_helper_sve_ld1hss_le_r_mte
, NULL
, NULL
, NULL
},
4828 { gen_helper_sve_ld1ss_le_r_mte
,
4829 gen_helper_sve_ld2ss_le_r_mte
,
4830 gen_helper_sve_ld3ss_le_r_mte
,
4831 gen_helper_sve_ld4ss_le_r_mte
},
4832 { gen_helper_sve_ld1sdu_le_r_mte
, NULL
, NULL
, NULL
},
4834 { gen_helper_sve_ld1bds_r_mte
, NULL
, NULL
, NULL
},
4835 { gen_helper_sve_ld1bss_r_mte
, NULL
, NULL
, NULL
},
4836 { gen_helper_sve_ld1bhs_r_mte
, NULL
, NULL
, NULL
},
4837 { gen_helper_sve_ld1dd_le_r_mte
,
4838 gen_helper_sve_ld2dd_le_r_mte
,
4839 gen_helper_sve_ld3dd_le_r_mte
,
4840 gen_helper_sve_ld4dd_le_r_mte
} },
4842 /* mte active, big-endian */
4843 { { gen_helper_sve_ld1bb_r_mte
,
4844 gen_helper_sve_ld2bb_r_mte
,
4845 gen_helper_sve_ld3bb_r_mte
,
4846 gen_helper_sve_ld4bb_r_mte
},
4847 { gen_helper_sve_ld1bhu_r_mte
, NULL
, NULL
, NULL
},
4848 { gen_helper_sve_ld1bsu_r_mte
, NULL
, NULL
, NULL
},
4849 { gen_helper_sve_ld1bdu_r_mte
, NULL
, NULL
, NULL
},
4851 { gen_helper_sve_ld1sds_be_r_mte
, NULL
, NULL
, NULL
},
4852 { gen_helper_sve_ld1hh_be_r_mte
,
4853 gen_helper_sve_ld2hh_be_r_mte
,
4854 gen_helper_sve_ld3hh_be_r_mte
,
4855 gen_helper_sve_ld4hh_be_r_mte
},
4856 { gen_helper_sve_ld1hsu_be_r_mte
, NULL
, NULL
, NULL
},
4857 { gen_helper_sve_ld1hdu_be_r_mte
, NULL
, NULL
, NULL
},
4859 { gen_helper_sve_ld1hds_be_r_mte
, NULL
, NULL
, NULL
},
4860 { gen_helper_sve_ld1hss_be_r_mte
, NULL
, NULL
, NULL
},
4861 { gen_helper_sve_ld1ss_be_r_mte
,
4862 gen_helper_sve_ld2ss_be_r_mte
,
4863 gen_helper_sve_ld3ss_be_r_mte
,
4864 gen_helper_sve_ld4ss_be_r_mte
},
4865 { gen_helper_sve_ld1sdu_be_r_mte
, NULL
, NULL
, NULL
},
4867 { gen_helper_sve_ld1bds_r_mte
, NULL
, NULL
, NULL
},
4868 { gen_helper_sve_ld1bss_r_mte
, NULL
, NULL
, NULL
},
4869 { gen_helper_sve_ld1bhs_r_mte
, NULL
, NULL
, NULL
},
4870 { gen_helper_sve_ld1dd_be_r_mte
,
4871 gen_helper_sve_ld2dd_be_r_mte
,
4872 gen_helper_sve_ld3dd_be_r_mte
,
4873 gen_helper_sve_ld4dd_be_r_mte
} } },
4876 static void do_ld_zpa(DisasContext
*s
, int zt
, int pg
,
4877 TCGv_i64 addr
, int dtype
, int nreg
)
4879 gen_helper_gvec_mem
*fn
4880 = ldr_fns
[s
->mte_active
[0]][s
->be_data
== MO_BE
][dtype
][nreg
];
4883 * While there are holes in the table, they are not
4884 * accessible via the instruction encoding.
4887 do_mem_zpa(s
, zt
, pg
, addr
, dtype
, nreg
, false, fn
);
4890 static bool trans_LD_zprr(DisasContext
*s
, arg_rprr_load
*a
)
4895 if (sve_access_check(s
)) {
4896 TCGv_i64 addr
= new_tmp_a64(s
);
4897 tcg_gen_shli_i64(addr
, cpu_reg(s
, a
->rm
), dtype_msz(a
->dtype
));
4898 tcg_gen_add_i64(addr
, addr
, cpu_reg_sp(s
, a
->rn
));
4899 do_ld_zpa(s
, a
->rd
, a
->pg
, addr
, a
->dtype
, a
->nreg
);
4904 static bool trans_LD_zpri(DisasContext
*s
, arg_rpri_load
*a
)
4906 if (sve_access_check(s
)) {
4907 int vsz
= vec_full_reg_size(s
);
4908 int elements
= vsz
>> dtype_esz
[a
->dtype
];
4909 TCGv_i64 addr
= new_tmp_a64(s
);
4911 tcg_gen_addi_i64(addr
, cpu_reg_sp(s
, a
->rn
),
4912 (a
->imm
* elements
* (a
->nreg
+ 1))
4913 << dtype_msz(a
->dtype
));
4914 do_ld_zpa(s
, a
->rd
, a
->pg
, addr
, a
->dtype
, a
->nreg
);
4919 static bool trans_LDFF1_zprr(DisasContext
*s
, arg_rprr_load
*a
)
4921 static gen_helper_gvec_mem
* const fns
[2][2][16] = {
4922 { /* mte inactive, little-endian */
4923 { gen_helper_sve_ldff1bb_r
,
4924 gen_helper_sve_ldff1bhu_r
,
4925 gen_helper_sve_ldff1bsu_r
,
4926 gen_helper_sve_ldff1bdu_r
,
4928 gen_helper_sve_ldff1sds_le_r
,
4929 gen_helper_sve_ldff1hh_le_r
,
4930 gen_helper_sve_ldff1hsu_le_r
,
4931 gen_helper_sve_ldff1hdu_le_r
,
4933 gen_helper_sve_ldff1hds_le_r
,
4934 gen_helper_sve_ldff1hss_le_r
,
4935 gen_helper_sve_ldff1ss_le_r
,
4936 gen_helper_sve_ldff1sdu_le_r
,
4938 gen_helper_sve_ldff1bds_r
,
4939 gen_helper_sve_ldff1bss_r
,
4940 gen_helper_sve_ldff1bhs_r
,
4941 gen_helper_sve_ldff1dd_le_r
},
4943 /* mte inactive, big-endian */
4944 { gen_helper_sve_ldff1bb_r
,
4945 gen_helper_sve_ldff1bhu_r
,
4946 gen_helper_sve_ldff1bsu_r
,
4947 gen_helper_sve_ldff1bdu_r
,
4949 gen_helper_sve_ldff1sds_be_r
,
4950 gen_helper_sve_ldff1hh_be_r
,
4951 gen_helper_sve_ldff1hsu_be_r
,
4952 gen_helper_sve_ldff1hdu_be_r
,
4954 gen_helper_sve_ldff1hds_be_r
,
4955 gen_helper_sve_ldff1hss_be_r
,
4956 gen_helper_sve_ldff1ss_be_r
,
4957 gen_helper_sve_ldff1sdu_be_r
,
4959 gen_helper_sve_ldff1bds_r
,
4960 gen_helper_sve_ldff1bss_r
,
4961 gen_helper_sve_ldff1bhs_r
,
4962 gen_helper_sve_ldff1dd_be_r
} },
4964 { /* mte active, little-endian */
4965 { gen_helper_sve_ldff1bb_r_mte
,
4966 gen_helper_sve_ldff1bhu_r_mte
,
4967 gen_helper_sve_ldff1bsu_r_mte
,
4968 gen_helper_sve_ldff1bdu_r_mte
,
4970 gen_helper_sve_ldff1sds_le_r_mte
,
4971 gen_helper_sve_ldff1hh_le_r_mte
,
4972 gen_helper_sve_ldff1hsu_le_r_mte
,
4973 gen_helper_sve_ldff1hdu_le_r_mte
,
4975 gen_helper_sve_ldff1hds_le_r_mte
,
4976 gen_helper_sve_ldff1hss_le_r_mte
,
4977 gen_helper_sve_ldff1ss_le_r_mte
,
4978 gen_helper_sve_ldff1sdu_le_r_mte
,
4980 gen_helper_sve_ldff1bds_r_mte
,
4981 gen_helper_sve_ldff1bss_r_mte
,
4982 gen_helper_sve_ldff1bhs_r_mte
,
4983 gen_helper_sve_ldff1dd_le_r_mte
},
4985 /* mte active, big-endian */
4986 { gen_helper_sve_ldff1bb_r_mte
,
4987 gen_helper_sve_ldff1bhu_r_mte
,
4988 gen_helper_sve_ldff1bsu_r_mte
,
4989 gen_helper_sve_ldff1bdu_r_mte
,
4991 gen_helper_sve_ldff1sds_be_r_mte
,
4992 gen_helper_sve_ldff1hh_be_r_mte
,
4993 gen_helper_sve_ldff1hsu_be_r_mte
,
4994 gen_helper_sve_ldff1hdu_be_r_mte
,
4996 gen_helper_sve_ldff1hds_be_r_mte
,
4997 gen_helper_sve_ldff1hss_be_r_mte
,
4998 gen_helper_sve_ldff1ss_be_r_mte
,
4999 gen_helper_sve_ldff1sdu_be_r_mte
,
5001 gen_helper_sve_ldff1bds_r_mte
,
5002 gen_helper_sve_ldff1bss_r_mte
,
5003 gen_helper_sve_ldff1bhs_r_mte
,
5004 gen_helper_sve_ldff1dd_be_r_mte
} },
5007 if (sve_access_check(s
)) {
5008 TCGv_i64 addr
= new_tmp_a64(s
);
5009 tcg_gen_shli_i64(addr
, cpu_reg(s
, a
->rm
), dtype_msz(a
->dtype
));
5010 tcg_gen_add_i64(addr
, addr
, cpu_reg_sp(s
, a
->rn
));
5011 do_mem_zpa(s
, a
->rd
, a
->pg
, addr
, a
->dtype
, 1, false,
5012 fns
[s
->mte_active
[0]][s
->be_data
== MO_BE
][a
->dtype
]);
5017 static bool trans_LDNF1_zpri(DisasContext
*s
, arg_rpri_load
*a
)
5019 static gen_helper_gvec_mem
* const fns
[2][2][16] = {
5020 { /* mte inactive, little-endian */
5021 { gen_helper_sve_ldnf1bb_r
,
5022 gen_helper_sve_ldnf1bhu_r
,
5023 gen_helper_sve_ldnf1bsu_r
,
5024 gen_helper_sve_ldnf1bdu_r
,
5026 gen_helper_sve_ldnf1sds_le_r
,
5027 gen_helper_sve_ldnf1hh_le_r
,
5028 gen_helper_sve_ldnf1hsu_le_r
,
5029 gen_helper_sve_ldnf1hdu_le_r
,
5031 gen_helper_sve_ldnf1hds_le_r
,
5032 gen_helper_sve_ldnf1hss_le_r
,
5033 gen_helper_sve_ldnf1ss_le_r
,
5034 gen_helper_sve_ldnf1sdu_le_r
,
5036 gen_helper_sve_ldnf1bds_r
,
5037 gen_helper_sve_ldnf1bss_r
,
5038 gen_helper_sve_ldnf1bhs_r
,
5039 gen_helper_sve_ldnf1dd_le_r
},
5041 /* mte inactive, big-endian */
5042 { gen_helper_sve_ldnf1bb_r
,
5043 gen_helper_sve_ldnf1bhu_r
,
5044 gen_helper_sve_ldnf1bsu_r
,
5045 gen_helper_sve_ldnf1bdu_r
,
5047 gen_helper_sve_ldnf1sds_be_r
,
5048 gen_helper_sve_ldnf1hh_be_r
,
5049 gen_helper_sve_ldnf1hsu_be_r
,
5050 gen_helper_sve_ldnf1hdu_be_r
,
5052 gen_helper_sve_ldnf1hds_be_r
,
5053 gen_helper_sve_ldnf1hss_be_r
,
5054 gen_helper_sve_ldnf1ss_be_r
,
5055 gen_helper_sve_ldnf1sdu_be_r
,
5057 gen_helper_sve_ldnf1bds_r
,
5058 gen_helper_sve_ldnf1bss_r
,
5059 gen_helper_sve_ldnf1bhs_r
,
5060 gen_helper_sve_ldnf1dd_be_r
} },
5062 { /* mte inactive, little-endian */
5063 { gen_helper_sve_ldnf1bb_r_mte
,
5064 gen_helper_sve_ldnf1bhu_r_mte
,
5065 gen_helper_sve_ldnf1bsu_r_mte
,
5066 gen_helper_sve_ldnf1bdu_r_mte
,
5068 gen_helper_sve_ldnf1sds_le_r_mte
,
5069 gen_helper_sve_ldnf1hh_le_r_mte
,
5070 gen_helper_sve_ldnf1hsu_le_r_mte
,
5071 gen_helper_sve_ldnf1hdu_le_r_mte
,
5073 gen_helper_sve_ldnf1hds_le_r_mte
,
5074 gen_helper_sve_ldnf1hss_le_r_mte
,
5075 gen_helper_sve_ldnf1ss_le_r_mte
,
5076 gen_helper_sve_ldnf1sdu_le_r_mte
,
5078 gen_helper_sve_ldnf1bds_r_mte
,
5079 gen_helper_sve_ldnf1bss_r_mte
,
5080 gen_helper_sve_ldnf1bhs_r_mte
,
5081 gen_helper_sve_ldnf1dd_le_r_mte
},
5083 /* mte inactive, big-endian */
5084 { gen_helper_sve_ldnf1bb_r_mte
,
5085 gen_helper_sve_ldnf1bhu_r_mte
,
5086 gen_helper_sve_ldnf1bsu_r_mte
,
5087 gen_helper_sve_ldnf1bdu_r_mte
,
5089 gen_helper_sve_ldnf1sds_be_r_mte
,
5090 gen_helper_sve_ldnf1hh_be_r_mte
,
5091 gen_helper_sve_ldnf1hsu_be_r_mte
,
5092 gen_helper_sve_ldnf1hdu_be_r_mte
,
5094 gen_helper_sve_ldnf1hds_be_r_mte
,
5095 gen_helper_sve_ldnf1hss_be_r_mte
,
5096 gen_helper_sve_ldnf1ss_be_r_mte
,
5097 gen_helper_sve_ldnf1sdu_be_r_mte
,
5099 gen_helper_sve_ldnf1bds_r_mte
,
5100 gen_helper_sve_ldnf1bss_r_mte
,
5101 gen_helper_sve_ldnf1bhs_r_mte
,
5102 gen_helper_sve_ldnf1dd_be_r_mte
} },
5105 if (sve_access_check(s
)) {
5106 int vsz
= vec_full_reg_size(s
);
5107 int elements
= vsz
>> dtype_esz
[a
->dtype
];
5108 int off
= (a
->imm
* elements
) << dtype_msz(a
->dtype
);
5109 TCGv_i64 addr
= new_tmp_a64(s
);
5111 tcg_gen_addi_i64(addr
, cpu_reg_sp(s
, a
->rn
), off
);
5112 do_mem_zpa(s
, a
->rd
, a
->pg
, addr
, a
->dtype
, 1, false,
5113 fns
[s
->mte_active
[0]][s
->be_data
== MO_BE
][a
->dtype
]);
5118 static void do_ldrq(DisasContext
*s
, int zt
, int pg
, TCGv_i64 addr
, int dtype
)
5120 unsigned vsz
= vec_full_reg_size(s
);
5124 /* Load the first quadword using the normal predicated load helpers. */
5125 poff
= pred_full_reg_offset(s
, pg
);
5128 * Zero-extend the first 16 bits of the predicate into a temporary.
5129 * This avoids triggering an assert making sure we don't have bits
5130 * set within a predicate beyond VQ, but we have lowered VQ to 1
5131 * for this load operation.
5133 TCGv_i64 tmp
= tcg_temp_new_i64();
5137 tcg_gen_ld16u_i64(tmp
, cpu_env
, poff
);
5139 poff
= offsetof(CPUARMState
, vfp
.preg_tmp
);
5140 tcg_gen_st_i64(tmp
, cpu_env
, poff
);
5141 tcg_temp_free_i64(tmp
);
5144 t_pg
= tcg_temp_new_ptr();
5145 tcg_gen_addi_ptr(t_pg
, cpu_env
, poff
);
5147 gen_helper_gvec_mem
*fn
5148 = ldr_fns
[s
->mte_active
[0]][s
->be_data
== MO_BE
][dtype
][0];
5149 fn(cpu_env
, t_pg
, addr
, tcg_constant_i32(simd_desc(16, 16, zt
)));
5151 tcg_temp_free_ptr(t_pg
);
5153 /* Replicate that first quadword. */
5155 int doff
= vec_full_reg_offset(s
, zt
);
5156 tcg_gen_gvec_dup_mem(4, doff
+ 16, doff
, vsz
- 16, vsz
- 16);
5160 static bool trans_LD1RQ_zprr(DisasContext
*s
, arg_rprr_load
*a
)
5165 if (sve_access_check(s
)) {
5166 int msz
= dtype_msz(a
->dtype
);
5167 TCGv_i64 addr
= new_tmp_a64(s
);
5168 tcg_gen_shli_i64(addr
, cpu_reg(s
, a
->rm
), msz
);
5169 tcg_gen_add_i64(addr
, addr
, cpu_reg_sp(s
, a
->rn
));
5170 do_ldrq(s
, a
->rd
, a
->pg
, addr
, a
->dtype
);
5175 static bool trans_LD1RQ_zpri(DisasContext
*s
, arg_rpri_load
*a
)
5177 if (sve_access_check(s
)) {
5178 TCGv_i64 addr
= new_tmp_a64(s
);
5179 tcg_gen_addi_i64(addr
, cpu_reg_sp(s
, a
->rn
), a
->imm
* 16);
5180 do_ldrq(s
, a
->rd
, a
->pg
, addr
, a
->dtype
);
5185 static void do_ldro(DisasContext
*s
, int zt
, int pg
, TCGv_i64 addr
, int dtype
)
5187 unsigned vsz
= vec_full_reg_size(s
);
5194 * Note that this UNDEFINED check comes after CheckSVEEnabled()
5195 * in the ARM pseudocode, which is the sve_access_check() done
5196 * in our caller. We should not now return false from the caller.
5198 unallocated_encoding(s
);
5202 /* Load the first octaword using the normal predicated load helpers. */
5204 poff
= pred_full_reg_offset(s
, pg
);
5207 * Zero-extend the first 32 bits of the predicate into a temporary.
5208 * This avoids triggering an assert making sure we don't have bits
5209 * set within a predicate beyond VQ, but we have lowered VQ to 2
5210 * for this load operation.
5212 TCGv_i64 tmp
= tcg_temp_new_i64();
5216 tcg_gen_ld32u_i64(tmp
, cpu_env
, poff
);
5218 poff
= offsetof(CPUARMState
, vfp
.preg_tmp
);
5219 tcg_gen_st_i64(tmp
, cpu_env
, poff
);
5220 tcg_temp_free_i64(tmp
);
5223 t_pg
= tcg_temp_new_ptr();
5224 tcg_gen_addi_ptr(t_pg
, cpu_env
, poff
);
5226 gen_helper_gvec_mem
*fn
5227 = ldr_fns
[s
->mte_active
[0]][s
->be_data
== MO_BE
][dtype
][0];
5228 fn(cpu_env
, t_pg
, addr
, tcg_constant_i32(simd_desc(32, 32, zt
)));
5230 tcg_temp_free_ptr(t_pg
);
5233 * Replicate that first octaword.
5234 * The replication happens in units of 32; if the full vector size
5235 * is not a multiple of 32, the final bits are zeroed.
5237 doff
= vec_full_reg_offset(s
, zt
);
5238 vsz_r32
= QEMU_ALIGN_DOWN(vsz
, 32);
5240 tcg_gen_gvec_dup_mem(5, doff
+ 32, doff
, vsz_r32
- 32, vsz_r32
- 32);
5244 tcg_gen_gvec_dup_imm(MO_64
, doff
+ vsz_r32
, vsz
, vsz
, 0);
5248 static bool trans_LD1RO_zprr(DisasContext
*s
, arg_rprr_load
*a
)
5250 if (!dc_isar_feature(aa64_sve_f64mm
, s
)) {
5256 if (sve_access_check(s
)) {
5257 TCGv_i64 addr
= new_tmp_a64(s
);
5258 tcg_gen_shli_i64(addr
, cpu_reg(s
, a
->rm
), dtype_msz(a
->dtype
));
5259 tcg_gen_add_i64(addr
, addr
, cpu_reg_sp(s
, a
->rn
));
5260 do_ldro(s
, a
->rd
, a
->pg
, addr
, a
->dtype
);
5265 static bool trans_LD1RO_zpri(DisasContext
*s
, arg_rpri_load
*a
)
5267 if (!dc_isar_feature(aa64_sve_f64mm
, s
)) {
5270 if (sve_access_check(s
)) {
5271 TCGv_i64 addr
= new_tmp_a64(s
);
5272 tcg_gen_addi_i64(addr
, cpu_reg_sp(s
, a
->rn
), a
->imm
* 32);
5273 do_ldro(s
, a
->rd
, a
->pg
, addr
, a
->dtype
);
5278 /* Load and broadcast element. */
5279 static bool trans_LD1R_zpri(DisasContext
*s
, arg_rpri_load
*a
)
5281 unsigned vsz
= vec_full_reg_size(s
);
5282 unsigned psz
= pred_full_reg_size(s
);
5283 unsigned esz
= dtype_esz
[a
->dtype
];
5284 unsigned msz
= dtype_msz(a
->dtype
);
5286 TCGv_i64 temp
, clean_addr
;
5288 if (!sve_access_check(s
)) {
5292 over
= gen_new_label();
5294 /* If the guarding predicate has no bits set, no load occurs. */
5296 /* Reduce the pred_esz_masks value simply to reduce the
5297 * size of the code generated here.
5299 uint64_t psz_mask
= MAKE_64BIT_MASK(0, psz
* 8);
5300 temp
= tcg_temp_new_i64();
5301 tcg_gen_ld_i64(temp
, cpu_env
, pred_full_reg_offset(s
, a
->pg
));
5302 tcg_gen_andi_i64(temp
, temp
, pred_esz_masks
[esz
] & psz_mask
);
5303 tcg_gen_brcondi_i64(TCG_COND_EQ
, temp
, 0, over
);
5304 tcg_temp_free_i64(temp
);
5306 TCGv_i32 t32
= tcg_temp_new_i32();
5307 find_last_active(s
, t32
, esz
, a
->pg
);
5308 tcg_gen_brcondi_i32(TCG_COND_LT
, t32
, 0, over
);
5309 tcg_temp_free_i32(t32
);
5312 /* Load the data. */
5313 temp
= tcg_temp_new_i64();
5314 tcg_gen_addi_i64(temp
, cpu_reg_sp(s
, a
->rn
), a
->imm
<< msz
);
5315 clean_addr
= gen_mte_check1(s
, temp
, false, true, msz
);
5317 tcg_gen_qemu_ld_i64(temp
, clean_addr
, get_mem_index(s
),
5318 finalize_memop(s
, dtype_mop
[a
->dtype
]));
5320 /* Broadcast to *all* elements. */
5321 tcg_gen_gvec_dup_i64(esz
, vec_full_reg_offset(s
, a
->rd
),
5323 tcg_temp_free_i64(temp
);
5325 /* Zero the inactive elements. */
5326 gen_set_label(over
);
5327 return do_movz_zpz(s
, a
->rd
, a
->rd
, a
->pg
, esz
, false);
5330 static void do_st_zpa(DisasContext
*s
, int zt
, int pg
, TCGv_i64 addr
,
5331 int msz
, int esz
, int nreg
)
5333 static gen_helper_gvec_mem
* const fn_single
[2][2][4][4] = {
5334 { { { gen_helper_sve_st1bb_r
,
5335 gen_helper_sve_st1bh_r
,
5336 gen_helper_sve_st1bs_r
,
5337 gen_helper_sve_st1bd_r
},
5339 gen_helper_sve_st1hh_le_r
,
5340 gen_helper_sve_st1hs_le_r
,
5341 gen_helper_sve_st1hd_le_r
},
5343 gen_helper_sve_st1ss_le_r
,
5344 gen_helper_sve_st1sd_le_r
},
5346 gen_helper_sve_st1dd_le_r
} },
5347 { { gen_helper_sve_st1bb_r
,
5348 gen_helper_sve_st1bh_r
,
5349 gen_helper_sve_st1bs_r
,
5350 gen_helper_sve_st1bd_r
},
5352 gen_helper_sve_st1hh_be_r
,
5353 gen_helper_sve_st1hs_be_r
,
5354 gen_helper_sve_st1hd_be_r
},
5356 gen_helper_sve_st1ss_be_r
,
5357 gen_helper_sve_st1sd_be_r
},
5359 gen_helper_sve_st1dd_be_r
} } },
5361 { { { gen_helper_sve_st1bb_r_mte
,
5362 gen_helper_sve_st1bh_r_mte
,
5363 gen_helper_sve_st1bs_r_mte
,
5364 gen_helper_sve_st1bd_r_mte
},
5366 gen_helper_sve_st1hh_le_r_mte
,
5367 gen_helper_sve_st1hs_le_r_mte
,
5368 gen_helper_sve_st1hd_le_r_mte
},
5370 gen_helper_sve_st1ss_le_r_mte
,
5371 gen_helper_sve_st1sd_le_r_mte
},
5373 gen_helper_sve_st1dd_le_r_mte
} },
5374 { { gen_helper_sve_st1bb_r_mte
,
5375 gen_helper_sve_st1bh_r_mte
,
5376 gen_helper_sve_st1bs_r_mte
,
5377 gen_helper_sve_st1bd_r_mte
},
5379 gen_helper_sve_st1hh_be_r_mte
,
5380 gen_helper_sve_st1hs_be_r_mte
,
5381 gen_helper_sve_st1hd_be_r_mte
},
5383 gen_helper_sve_st1ss_be_r_mte
,
5384 gen_helper_sve_st1sd_be_r_mte
},
5386 gen_helper_sve_st1dd_be_r_mte
} } },
5388 static gen_helper_gvec_mem
* const fn_multiple
[2][2][3][4] = {
5389 { { { gen_helper_sve_st2bb_r
,
5390 gen_helper_sve_st2hh_le_r
,
5391 gen_helper_sve_st2ss_le_r
,
5392 gen_helper_sve_st2dd_le_r
},
5393 { gen_helper_sve_st3bb_r
,
5394 gen_helper_sve_st3hh_le_r
,
5395 gen_helper_sve_st3ss_le_r
,
5396 gen_helper_sve_st3dd_le_r
},
5397 { gen_helper_sve_st4bb_r
,
5398 gen_helper_sve_st4hh_le_r
,
5399 gen_helper_sve_st4ss_le_r
,
5400 gen_helper_sve_st4dd_le_r
} },
5401 { { gen_helper_sve_st2bb_r
,
5402 gen_helper_sve_st2hh_be_r
,
5403 gen_helper_sve_st2ss_be_r
,
5404 gen_helper_sve_st2dd_be_r
},
5405 { gen_helper_sve_st3bb_r
,
5406 gen_helper_sve_st3hh_be_r
,
5407 gen_helper_sve_st3ss_be_r
,
5408 gen_helper_sve_st3dd_be_r
},
5409 { gen_helper_sve_st4bb_r
,
5410 gen_helper_sve_st4hh_be_r
,
5411 gen_helper_sve_st4ss_be_r
,
5412 gen_helper_sve_st4dd_be_r
} } },
5413 { { { gen_helper_sve_st2bb_r_mte
,
5414 gen_helper_sve_st2hh_le_r_mte
,
5415 gen_helper_sve_st2ss_le_r_mte
,
5416 gen_helper_sve_st2dd_le_r_mte
},
5417 { gen_helper_sve_st3bb_r_mte
,
5418 gen_helper_sve_st3hh_le_r_mte
,
5419 gen_helper_sve_st3ss_le_r_mte
,
5420 gen_helper_sve_st3dd_le_r_mte
},
5421 { gen_helper_sve_st4bb_r_mte
,
5422 gen_helper_sve_st4hh_le_r_mte
,
5423 gen_helper_sve_st4ss_le_r_mte
,
5424 gen_helper_sve_st4dd_le_r_mte
} },
5425 { { gen_helper_sve_st2bb_r_mte
,
5426 gen_helper_sve_st2hh_be_r_mte
,
5427 gen_helper_sve_st2ss_be_r_mte
,
5428 gen_helper_sve_st2dd_be_r_mte
},
5429 { gen_helper_sve_st3bb_r_mte
,
5430 gen_helper_sve_st3hh_be_r_mte
,
5431 gen_helper_sve_st3ss_be_r_mte
,
5432 gen_helper_sve_st3dd_be_r_mte
},
5433 { gen_helper_sve_st4bb_r_mte
,
5434 gen_helper_sve_st4hh_be_r_mte
,
5435 gen_helper_sve_st4ss_be_r_mte
,
5436 gen_helper_sve_st4dd_be_r_mte
} } },
5438 gen_helper_gvec_mem
*fn
;
5439 int be
= s
->be_data
== MO_BE
;
5443 fn
= fn_single
[s
->mte_active
[0]][be
][msz
][esz
];
5446 /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
5448 fn
= fn_multiple
[s
->mte_active
[0]][be
][nreg
- 1][msz
];
5451 do_mem_zpa(s
, zt
, pg
, addr
, msz_dtype(s
, msz
), nreg
, true, fn
);
5454 static bool trans_ST_zprr(DisasContext
*s
, arg_rprr_store
*a
)
5456 if (a
->rm
== 31 || a
->msz
> a
->esz
) {
5459 if (sve_access_check(s
)) {
5460 TCGv_i64 addr
= new_tmp_a64(s
);
5461 tcg_gen_shli_i64(addr
, cpu_reg(s
, a
->rm
), a
->msz
);
5462 tcg_gen_add_i64(addr
, addr
, cpu_reg_sp(s
, a
->rn
));
5463 do_st_zpa(s
, a
->rd
, a
->pg
, addr
, a
->msz
, a
->esz
, a
->nreg
);
5468 static bool trans_ST_zpri(DisasContext
*s
, arg_rpri_store
*a
)
5470 if (a
->msz
> a
->esz
) {
5473 if (sve_access_check(s
)) {
5474 int vsz
= vec_full_reg_size(s
);
5475 int elements
= vsz
>> a
->esz
;
5476 TCGv_i64 addr
= new_tmp_a64(s
);
5478 tcg_gen_addi_i64(addr
, cpu_reg_sp(s
, a
->rn
),
5479 (a
->imm
* elements
* (a
->nreg
+ 1)) << a
->msz
);
5480 do_st_zpa(s
, a
->rd
, a
->pg
, addr
, a
->msz
, a
->esz
, a
->nreg
);
5486 *** SVE gather loads / scatter stores
5489 static void do_mem_zpz(DisasContext
*s
, int zt
, int pg
, int zm
,
5490 int scale
, TCGv_i64 scalar
, int msz
, bool is_write
,
5491 gen_helper_gvec_mem_scatter
*fn
)
5493 unsigned vsz
= vec_full_reg_size(s
);
5494 TCGv_ptr t_zm
= tcg_temp_new_ptr();
5495 TCGv_ptr t_pg
= tcg_temp_new_ptr();
5496 TCGv_ptr t_zt
= tcg_temp_new_ptr();
5499 if (s
->mte_active
[0]) {
5500 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
5501 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
5502 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
5503 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
5504 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << msz
) - 1);
5505 desc
<<= SVE_MTEDESC_SHIFT
;
5507 desc
= simd_desc(vsz
, vsz
, desc
| scale
);
5509 tcg_gen_addi_ptr(t_pg
, cpu_env
, pred_full_reg_offset(s
, pg
));
5510 tcg_gen_addi_ptr(t_zm
, cpu_env
, vec_full_reg_offset(s
, zm
));
5511 tcg_gen_addi_ptr(t_zt
, cpu_env
, vec_full_reg_offset(s
, zt
));
5512 fn(cpu_env
, t_zt
, t_pg
, t_zm
, scalar
, tcg_constant_i32(desc
));
5514 tcg_temp_free_ptr(t_zt
);
5515 tcg_temp_free_ptr(t_zm
);
5516 tcg_temp_free_ptr(t_pg
);
5519 /* Indexed by [mte][be][ff][xs][u][msz]. */
5520 static gen_helper_gvec_mem_scatter
* const
5521 gather_load_fn32
[2][2][2][2][2][3] = {
5522 { /* MTE Inactive */
5523 { /* Little-endian */
5524 { { { gen_helper_sve_ldbss_zsu
,
5525 gen_helper_sve_ldhss_le_zsu
,
5527 { gen_helper_sve_ldbsu_zsu
,
5528 gen_helper_sve_ldhsu_le_zsu
,
5529 gen_helper_sve_ldss_le_zsu
, } },
5530 { { gen_helper_sve_ldbss_zss
,
5531 gen_helper_sve_ldhss_le_zss
,
5533 { gen_helper_sve_ldbsu_zss
,
5534 gen_helper_sve_ldhsu_le_zss
,
5535 gen_helper_sve_ldss_le_zss
, } } },
5538 { { { gen_helper_sve_ldffbss_zsu
,
5539 gen_helper_sve_ldffhss_le_zsu
,
5541 { gen_helper_sve_ldffbsu_zsu
,
5542 gen_helper_sve_ldffhsu_le_zsu
,
5543 gen_helper_sve_ldffss_le_zsu
, } },
5544 { { gen_helper_sve_ldffbss_zss
,
5545 gen_helper_sve_ldffhss_le_zss
,
5547 { gen_helper_sve_ldffbsu_zss
,
5548 gen_helper_sve_ldffhsu_le_zss
,
5549 gen_helper_sve_ldffss_le_zss
, } } } },
5552 { { { gen_helper_sve_ldbss_zsu
,
5553 gen_helper_sve_ldhss_be_zsu
,
5555 { gen_helper_sve_ldbsu_zsu
,
5556 gen_helper_sve_ldhsu_be_zsu
,
5557 gen_helper_sve_ldss_be_zsu
, } },
5558 { { gen_helper_sve_ldbss_zss
,
5559 gen_helper_sve_ldhss_be_zss
,
5561 { gen_helper_sve_ldbsu_zss
,
5562 gen_helper_sve_ldhsu_be_zss
,
5563 gen_helper_sve_ldss_be_zss
, } } },
5566 { { { gen_helper_sve_ldffbss_zsu
,
5567 gen_helper_sve_ldffhss_be_zsu
,
5569 { gen_helper_sve_ldffbsu_zsu
,
5570 gen_helper_sve_ldffhsu_be_zsu
,
5571 gen_helper_sve_ldffss_be_zsu
, } },
5572 { { gen_helper_sve_ldffbss_zss
,
5573 gen_helper_sve_ldffhss_be_zss
,
5575 { gen_helper_sve_ldffbsu_zss
,
5576 gen_helper_sve_ldffhsu_be_zss
,
5577 gen_helper_sve_ldffss_be_zss
, } } } } },
5579 { /* Little-endian */
5580 { { { gen_helper_sve_ldbss_zsu_mte
,
5581 gen_helper_sve_ldhss_le_zsu_mte
,
5583 { gen_helper_sve_ldbsu_zsu_mte
,
5584 gen_helper_sve_ldhsu_le_zsu_mte
,
5585 gen_helper_sve_ldss_le_zsu_mte
, } },
5586 { { gen_helper_sve_ldbss_zss_mte
,
5587 gen_helper_sve_ldhss_le_zss_mte
,
5589 { gen_helper_sve_ldbsu_zss_mte
,
5590 gen_helper_sve_ldhsu_le_zss_mte
,
5591 gen_helper_sve_ldss_le_zss_mte
, } } },
5594 { { { gen_helper_sve_ldffbss_zsu_mte
,
5595 gen_helper_sve_ldffhss_le_zsu_mte
,
5597 { gen_helper_sve_ldffbsu_zsu_mte
,
5598 gen_helper_sve_ldffhsu_le_zsu_mte
,
5599 gen_helper_sve_ldffss_le_zsu_mte
, } },
5600 { { gen_helper_sve_ldffbss_zss_mte
,
5601 gen_helper_sve_ldffhss_le_zss_mte
,
5603 { gen_helper_sve_ldffbsu_zss_mte
,
5604 gen_helper_sve_ldffhsu_le_zss_mte
,
5605 gen_helper_sve_ldffss_le_zss_mte
, } } } },
5608 { { { gen_helper_sve_ldbss_zsu_mte
,
5609 gen_helper_sve_ldhss_be_zsu_mte
,
5611 { gen_helper_sve_ldbsu_zsu_mte
,
5612 gen_helper_sve_ldhsu_be_zsu_mte
,
5613 gen_helper_sve_ldss_be_zsu_mte
, } },
5614 { { gen_helper_sve_ldbss_zss_mte
,
5615 gen_helper_sve_ldhss_be_zss_mte
,
5617 { gen_helper_sve_ldbsu_zss_mte
,
5618 gen_helper_sve_ldhsu_be_zss_mte
,
5619 gen_helper_sve_ldss_be_zss_mte
, } } },
5622 { { { gen_helper_sve_ldffbss_zsu_mte
,
5623 gen_helper_sve_ldffhss_be_zsu_mte
,
5625 { gen_helper_sve_ldffbsu_zsu_mte
,
5626 gen_helper_sve_ldffhsu_be_zsu_mte
,
5627 gen_helper_sve_ldffss_be_zsu_mte
, } },
5628 { { gen_helper_sve_ldffbss_zss_mte
,
5629 gen_helper_sve_ldffhss_be_zss_mte
,
5631 { gen_helper_sve_ldffbsu_zss_mte
,
5632 gen_helper_sve_ldffhsu_be_zss_mte
,
5633 gen_helper_sve_ldffss_be_zss_mte
, } } } } },
5636 /* Note that we overload xs=2 to indicate 64-bit offset. */
5637 static gen_helper_gvec_mem_scatter
* const
5638 gather_load_fn64
[2][2][2][3][2][4] = {
5639 { /* MTE Inactive */
5640 { /* Little-endian */
5641 { { { gen_helper_sve_ldbds_zsu
,
5642 gen_helper_sve_ldhds_le_zsu
,
5643 gen_helper_sve_ldsds_le_zsu
,
5645 { gen_helper_sve_ldbdu_zsu
,
5646 gen_helper_sve_ldhdu_le_zsu
,
5647 gen_helper_sve_ldsdu_le_zsu
,
5648 gen_helper_sve_lddd_le_zsu
, } },
5649 { { gen_helper_sve_ldbds_zss
,
5650 gen_helper_sve_ldhds_le_zss
,
5651 gen_helper_sve_ldsds_le_zss
,
5653 { gen_helper_sve_ldbdu_zss
,
5654 gen_helper_sve_ldhdu_le_zss
,
5655 gen_helper_sve_ldsdu_le_zss
,
5656 gen_helper_sve_lddd_le_zss
, } },
5657 { { gen_helper_sve_ldbds_zd
,
5658 gen_helper_sve_ldhds_le_zd
,
5659 gen_helper_sve_ldsds_le_zd
,
5661 { gen_helper_sve_ldbdu_zd
,
5662 gen_helper_sve_ldhdu_le_zd
,
5663 gen_helper_sve_ldsdu_le_zd
,
5664 gen_helper_sve_lddd_le_zd
, } } },
5667 { { { gen_helper_sve_ldffbds_zsu
,
5668 gen_helper_sve_ldffhds_le_zsu
,
5669 gen_helper_sve_ldffsds_le_zsu
,
5671 { gen_helper_sve_ldffbdu_zsu
,
5672 gen_helper_sve_ldffhdu_le_zsu
,
5673 gen_helper_sve_ldffsdu_le_zsu
,
5674 gen_helper_sve_ldffdd_le_zsu
, } },
5675 { { gen_helper_sve_ldffbds_zss
,
5676 gen_helper_sve_ldffhds_le_zss
,
5677 gen_helper_sve_ldffsds_le_zss
,
5679 { gen_helper_sve_ldffbdu_zss
,
5680 gen_helper_sve_ldffhdu_le_zss
,
5681 gen_helper_sve_ldffsdu_le_zss
,
5682 gen_helper_sve_ldffdd_le_zss
, } },
5683 { { gen_helper_sve_ldffbds_zd
,
5684 gen_helper_sve_ldffhds_le_zd
,
5685 gen_helper_sve_ldffsds_le_zd
,
5687 { gen_helper_sve_ldffbdu_zd
,
5688 gen_helper_sve_ldffhdu_le_zd
,
5689 gen_helper_sve_ldffsdu_le_zd
,
5690 gen_helper_sve_ldffdd_le_zd
, } } } },
5692 { { { gen_helper_sve_ldbds_zsu
,
5693 gen_helper_sve_ldhds_be_zsu
,
5694 gen_helper_sve_ldsds_be_zsu
,
5696 { gen_helper_sve_ldbdu_zsu
,
5697 gen_helper_sve_ldhdu_be_zsu
,
5698 gen_helper_sve_ldsdu_be_zsu
,
5699 gen_helper_sve_lddd_be_zsu
, } },
5700 { { gen_helper_sve_ldbds_zss
,
5701 gen_helper_sve_ldhds_be_zss
,
5702 gen_helper_sve_ldsds_be_zss
,
5704 { gen_helper_sve_ldbdu_zss
,
5705 gen_helper_sve_ldhdu_be_zss
,
5706 gen_helper_sve_ldsdu_be_zss
,
5707 gen_helper_sve_lddd_be_zss
, } },
5708 { { gen_helper_sve_ldbds_zd
,
5709 gen_helper_sve_ldhds_be_zd
,
5710 gen_helper_sve_ldsds_be_zd
,
5712 { gen_helper_sve_ldbdu_zd
,
5713 gen_helper_sve_ldhdu_be_zd
,
5714 gen_helper_sve_ldsdu_be_zd
,
5715 gen_helper_sve_lddd_be_zd
, } } },
5718 { { { gen_helper_sve_ldffbds_zsu
,
5719 gen_helper_sve_ldffhds_be_zsu
,
5720 gen_helper_sve_ldffsds_be_zsu
,
5722 { gen_helper_sve_ldffbdu_zsu
,
5723 gen_helper_sve_ldffhdu_be_zsu
,
5724 gen_helper_sve_ldffsdu_be_zsu
,
5725 gen_helper_sve_ldffdd_be_zsu
, } },
5726 { { gen_helper_sve_ldffbds_zss
,
5727 gen_helper_sve_ldffhds_be_zss
,
5728 gen_helper_sve_ldffsds_be_zss
,
5730 { gen_helper_sve_ldffbdu_zss
,
5731 gen_helper_sve_ldffhdu_be_zss
,
5732 gen_helper_sve_ldffsdu_be_zss
,
5733 gen_helper_sve_ldffdd_be_zss
, } },
5734 { { gen_helper_sve_ldffbds_zd
,
5735 gen_helper_sve_ldffhds_be_zd
,
5736 gen_helper_sve_ldffsds_be_zd
,
5738 { gen_helper_sve_ldffbdu_zd
,
5739 gen_helper_sve_ldffhdu_be_zd
,
5740 gen_helper_sve_ldffsdu_be_zd
,
5741 gen_helper_sve_ldffdd_be_zd
, } } } } },
5743 { /* Little-endian */
5744 { { { gen_helper_sve_ldbds_zsu_mte
,
5745 gen_helper_sve_ldhds_le_zsu_mte
,
5746 gen_helper_sve_ldsds_le_zsu_mte
,
5748 { gen_helper_sve_ldbdu_zsu_mte
,
5749 gen_helper_sve_ldhdu_le_zsu_mte
,
5750 gen_helper_sve_ldsdu_le_zsu_mte
,
5751 gen_helper_sve_lddd_le_zsu_mte
, } },
5752 { { gen_helper_sve_ldbds_zss_mte
,
5753 gen_helper_sve_ldhds_le_zss_mte
,
5754 gen_helper_sve_ldsds_le_zss_mte
,
5756 { gen_helper_sve_ldbdu_zss_mte
,
5757 gen_helper_sve_ldhdu_le_zss_mte
,
5758 gen_helper_sve_ldsdu_le_zss_mte
,
5759 gen_helper_sve_lddd_le_zss_mte
, } },
5760 { { gen_helper_sve_ldbds_zd_mte
,
5761 gen_helper_sve_ldhds_le_zd_mte
,
5762 gen_helper_sve_ldsds_le_zd_mte
,
5764 { gen_helper_sve_ldbdu_zd_mte
,
5765 gen_helper_sve_ldhdu_le_zd_mte
,
5766 gen_helper_sve_ldsdu_le_zd_mte
,
5767 gen_helper_sve_lddd_le_zd_mte
, } } },
5770 { { { gen_helper_sve_ldffbds_zsu_mte
,
5771 gen_helper_sve_ldffhds_le_zsu_mte
,
5772 gen_helper_sve_ldffsds_le_zsu_mte
,
5774 { gen_helper_sve_ldffbdu_zsu_mte
,
5775 gen_helper_sve_ldffhdu_le_zsu_mte
,
5776 gen_helper_sve_ldffsdu_le_zsu_mte
,
5777 gen_helper_sve_ldffdd_le_zsu_mte
, } },
5778 { { gen_helper_sve_ldffbds_zss_mte
,
5779 gen_helper_sve_ldffhds_le_zss_mte
,
5780 gen_helper_sve_ldffsds_le_zss_mte
,
5782 { gen_helper_sve_ldffbdu_zss_mte
,
5783 gen_helper_sve_ldffhdu_le_zss_mte
,
5784 gen_helper_sve_ldffsdu_le_zss_mte
,
5785 gen_helper_sve_ldffdd_le_zss_mte
, } },
5786 { { gen_helper_sve_ldffbds_zd_mte
,
5787 gen_helper_sve_ldffhds_le_zd_mte
,
5788 gen_helper_sve_ldffsds_le_zd_mte
,
5790 { gen_helper_sve_ldffbdu_zd_mte
,
5791 gen_helper_sve_ldffhdu_le_zd_mte
,
5792 gen_helper_sve_ldffsdu_le_zd_mte
,
5793 gen_helper_sve_ldffdd_le_zd_mte
, } } } },
5795 { { { gen_helper_sve_ldbds_zsu_mte
,
5796 gen_helper_sve_ldhds_be_zsu_mte
,
5797 gen_helper_sve_ldsds_be_zsu_mte
,
5799 { gen_helper_sve_ldbdu_zsu_mte
,
5800 gen_helper_sve_ldhdu_be_zsu_mte
,
5801 gen_helper_sve_ldsdu_be_zsu_mte
,
5802 gen_helper_sve_lddd_be_zsu_mte
, } },
5803 { { gen_helper_sve_ldbds_zss_mte
,
5804 gen_helper_sve_ldhds_be_zss_mte
,
5805 gen_helper_sve_ldsds_be_zss_mte
,
5807 { gen_helper_sve_ldbdu_zss_mte
,
5808 gen_helper_sve_ldhdu_be_zss_mte
,
5809 gen_helper_sve_ldsdu_be_zss_mte
,
5810 gen_helper_sve_lddd_be_zss_mte
, } },
5811 { { gen_helper_sve_ldbds_zd_mte
,
5812 gen_helper_sve_ldhds_be_zd_mte
,
5813 gen_helper_sve_ldsds_be_zd_mte
,
5815 { gen_helper_sve_ldbdu_zd_mte
,
5816 gen_helper_sve_ldhdu_be_zd_mte
,
5817 gen_helper_sve_ldsdu_be_zd_mte
,
5818 gen_helper_sve_lddd_be_zd_mte
, } } },
5821 { { { gen_helper_sve_ldffbds_zsu_mte
,
5822 gen_helper_sve_ldffhds_be_zsu_mte
,
5823 gen_helper_sve_ldffsds_be_zsu_mte
,
5825 { gen_helper_sve_ldffbdu_zsu_mte
,
5826 gen_helper_sve_ldffhdu_be_zsu_mte
,
5827 gen_helper_sve_ldffsdu_be_zsu_mte
,
5828 gen_helper_sve_ldffdd_be_zsu_mte
, } },
5829 { { gen_helper_sve_ldffbds_zss_mte
,
5830 gen_helper_sve_ldffhds_be_zss_mte
,
5831 gen_helper_sve_ldffsds_be_zss_mte
,
5833 { gen_helper_sve_ldffbdu_zss_mte
,
5834 gen_helper_sve_ldffhdu_be_zss_mte
,
5835 gen_helper_sve_ldffsdu_be_zss_mte
,
5836 gen_helper_sve_ldffdd_be_zss_mte
, } },
5837 { { gen_helper_sve_ldffbds_zd_mte
,
5838 gen_helper_sve_ldffhds_be_zd_mte
,
5839 gen_helper_sve_ldffsds_be_zd_mte
,
5841 { gen_helper_sve_ldffbdu_zd_mte
,
5842 gen_helper_sve_ldffhdu_be_zd_mte
,
5843 gen_helper_sve_ldffsdu_be_zd_mte
,
5844 gen_helper_sve_ldffdd_be_zd_mte
, } } } } },
5847 static bool trans_LD1_zprz(DisasContext
*s
, arg_LD1_zprz
*a
)
5849 gen_helper_gvec_mem_scatter
*fn
= NULL
;
5850 bool be
= s
->be_data
== MO_BE
;
5851 bool mte
= s
->mte_active
[0];
5853 if (!sve_access_check(s
)) {
5859 fn
= gather_load_fn32
[mte
][be
][a
->ff
][a
->xs
][a
->u
][a
->msz
];
5862 fn
= gather_load_fn64
[mte
][be
][a
->ff
][a
->xs
][a
->u
][a
->msz
];
5867 do_mem_zpz(s
, a
->rd
, a
->pg
, a
->rm
, a
->scale
* a
->msz
,
5868 cpu_reg_sp(s
, a
->rn
), a
->msz
, false, fn
);
5872 static bool trans_LD1_zpiz(DisasContext
*s
, arg_LD1_zpiz
*a
)
5874 gen_helper_gvec_mem_scatter
*fn
= NULL
;
5875 bool be
= s
->be_data
== MO_BE
;
5876 bool mte
= s
->mte_active
[0];
5878 if (a
->esz
< a
->msz
|| (a
->esz
== a
->msz
&& !a
->u
)) {
5881 if (!sve_access_check(s
)) {
5887 fn
= gather_load_fn32
[mte
][be
][a
->ff
][0][a
->u
][a
->msz
];
5890 fn
= gather_load_fn64
[mte
][be
][a
->ff
][2][a
->u
][a
->msz
];
5895 /* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x])
5896 * by loading the immediate into the scalar parameter.
5898 do_mem_zpz(s
, a
->rd
, a
->pg
, a
->rn
, 0,
5899 tcg_constant_i64(a
->imm
<< a
->msz
), a
->msz
, false, fn
);
5903 static bool trans_LDNT1_zprz(DisasContext
*s
, arg_LD1_zprz
*a
)
5905 gen_helper_gvec_mem_scatter
*fn
= NULL
;
5906 bool be
= s
->be_data
== MO_BE
;
5907 bool mte
= s
->mte_active
[0];
5909 if (a
->esz
< a
->msz
+ !a
->u
) {
5912 if (!dc_isar_feature(aa64_sve2
, s
)) {
5915 if (!sve_access_check(s
)) {
5921 fn
= gather_load_fn32
[mte
][be
][0][0][a
->u
][a
->msz
];
5924 fn
= gather_load_fn64
[mte
][be
][0][2][a
->u
][a
->msz
];
5929 do_mem_zpz(s
, a
->rd
, a
->pg
, a
->rn
, 0,
5930 cpu_reg(s
, a
->rm
), a
->msz
, false, fn
);
5934 /* Indexed by [mte][be][xs][msz]. */
5935 static gen_helper_gvec_mem_scatter
* const scatter_store_fn32
[2][2][2][3] = {
5936 { /* MTE Inactive */
5937 { /* Little-endian */
5938 { gen_helper_sve_stbs_zsu
,
5939 gen_helper_sve_sths_le_zsu
,
5940 gen_helper_sve_stss_le_zsu
, },
5941 { gen_helper_sve_stbs_zss
,
5942 gen_helper_sve_sths_le_zss
,
5943 gen_helper_sve_stss_le_zss
, } },
5945 { gen_helper_sve_stbs_zsu
,
5946 gen_helper_sve_sths_be_zsu
,
5947 gen_helper_sve_stss_be_zsu
, },
5948 { gen_helper_sve_stbs_zss
,
5949 gen_helper_sve_sths_be_zss
,
5950 gen_helper_sve_stss_be_zss
, } } },
5952 { /* Little-endian */
5953 { gen_helper_sve_stbs_zsu_mte
,
5954 gen_helper_sve_sths_le_zsu_mte
,
5955 gen_helper_sve_stss_le_zsu_mte
, },
5956 { gen_helper_sve_stbs_zss_mte
,
5957 gen_helper_sve_sths_le_zss_mte
,
5958 gen_helper_sve_stss_le_zss_mte
, } },
5960 { gen_helper_sve_stbs_zsu_mte
,
5961 gen_helper_sve_sths_be_zsu_mte
,
5962 gen_helper_sve_stss_be_zsu_mte
, },
5963 { gen_helper_sve_stbs_zss_mte
,
5964 gen_helper_sve_sths_be_zss_mte
,
5965 gen_helper_sve_stss_be_zss_mte
, } } },
5968 /* Note that we overload xs=2 to indicate 64-bit offset. */
5969 static gen_helper_gvec_mem_scatter
* const scatter_store_fn64
[2][2][3][4] = {
5970 { /* MTE Inactive */
5971 { /* Little-endian */
5972 { gen_helper_sve_stbd_zsu
,
5973 gen_helper_sve_sthd_le_zsu
,
5974 gen_helper_sve_stsd_le_zsu
,
5975 gen_helper_sve_stdd_le_zsu
, },
5976 { gen_helper_sve_stbd_zss
,
5977 gen_helper_sve_sthd_le_zss
,
5978 gen_helper_sve_stsd_le_zss
,
5979 gen_helper_sve_stdd_le_zss
, },
5980 { gen_helper_sve_stbd_zd
,
5981 gen_helper_sve_sthd_le_zd
,
5982 gen_helper_sve_stsd_le_zd
,
5983 gen_helper_sve_stdd_le_zd
, } },
5985 { gen_helper_sve_stbd_zsu
,
5986 gen_helper_sve_sthd_be_zsu
,
5987 gen_helper_sve_stsd_be_zsu
,
5988 gen_helper_sve_stdd_be_zsu
, },
5989 { gen_helper_sve_stbd_zss
,
5990 gen_helper_sve_sthd_be_zss
,
5991 gen_helper_sve_stsd_be_zss
,
5992 gen_helper_sve_stdd_be_zss
, },
5993 { gen_helper_sve_stbd_zd
,
5994 gen_helper_sve_sthd_be_zd
,
5995 gen_helper_sve_stsd_be_zd
,
5996 gen_helper_sve_stdd_be_zd
, } } },
5997 { /* MTE Inactive */
5998 { /* Little-endian */
5999 { gen_helper_sve_stbd_zsu_mte
,
6000 gen_helper_sve_sthd_le_zsu_mte
,
6001 gen_helper_sve_stsd_le_zsu_mte
,
6002 gen_helper_sve_stdd_le_zsu_mte
, },
6003 { gen_helper_sve_stbd_zss_mte
,
6004 gen_helper_sve_sthd_le_zss_mte
,
6005 gen_helper_sve_stsd_le_zss_mte
,
6006 gen_helper_sve_stdd_le_zss_mte
, },
6007 { gen_helper_sve_stbd_zd_mte
,
6008 gen_helper_sve_sthd_le_zd_mte
,
6009 gen_helper_sve_stsd_le_zd_mte
,
6010 gen_helper_sve_stdd_le_zd_mte
, } },
6012 { gen_helper_sve_stbd_zsu_mte
,
6013 gen_helper_sve_sthd_be_zsu_mte
,
6014 gen_helper_sve_stsd_be_zsu_mte
,
6015 gen_helper_sve_stdd_be_zsu_mte
, },
6016 { gen_helper_sve_stbd_zss_mte
,
6017 gen_helper_sve_sthd_be_zss_mte
,
6018 gen_helper_sve_stsd_be_zss_mte
,
6019 gen_helper_sve_stdd_be_zss_mte
, },
6020 { gen_helper_sve_stbd_zd_mte
,
6021 gen_helper_sve_sthd_be_zd_mte
,
6022 gen_helper_sve_stsd_be_zd_mte
,
6023 gen_helper_sve_stdd_be_zd_mte
, } } },
6026 static bool trans_ST1_zprz(DisasContext
*s
, arg_ST1_zprz
*a
)
6028 gen_helper_gvec_mem_scatter
*fn
;
6029 bool be
= s
->be_data
== MO_BE
;
6030 bool mte
= s
->mte_active
[0];
6032 if (a
->esz
< a
->msz
|| (a
->msz
== 0 && a
->scale
)) {
6035 if (!sve_access_check(s
)) {
6040 fn
= scatter_store_fn32
[mte
][be
][a
->xs
][a
->msz
];
6043 fn
= scatter_store_fn64
[mte
][be
][a
->xs
][a
->msz
];
6046 g_assert_not_reached();
6048 do_mem_zpz(s
, a
->rd
, a
->pg
, a
->rm
, a
->scale
* a
->msz
,
6049 cpu_reg_sp(s
, a
->rn
), a
->msz
, true, fn
);
6053 static bool trans_ST1_zpiz(DisasContext
*s
, arg_ST1_zpiz
*a
)
6055 gen_helper_gvec_mem_scatter
*fn
= NULL
;
6056 bool be
= s
->be_data
== MO_BE
;
6057 bool mte
= s
->mte_active
[0];
6059 if (a
->esz
< a
->msz
) {
6062 if (!sve_access_check(s
)) {
6068 fn
= scatter_store_fn32
[mte
][be
][0][a
->msz
];
6071 fn
= scatter_store_fn64
[mte
][be
][2][a
->msz
];
6076 /* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x])
6077 * by loading the immediate into the scalar parameter.
6079 do_mem_zpz(s
, a
->rd
, a
->pg
, a
->rn
, 0,
6080 tcg_constant_i64(a
->imm
<< a
->msz
), a
->msz
, true, fn
);
6084 static bool trans_STNT1_zprz(DisasContext
*s
, arg_ST1_zprz
*a
)
6086 gen_helper_gvec_mem_scatter
*fn
;
6087 bool be
= s
->be_data
== MO_BE
;
6088 bool mte
= s
->mte_active
[0];
6090 if (a
->esz
< a
->msz
) {
6093 if (!dc_isar_feature(aa64_sve2
, s
)) {
6096 if (!sve_access_check(s
)) {
6102 fn
= scatter_store_fn32
[mte
][be
][0][a
->msz
];
6105 fn
= scatter_store_fn64
[mte
][be
][2][a
->msz
];
6108 g_assert_not_reached();
6111 do_mem_zpz(s
, a
->rd
, a
->pg
, a
->rn
, 0,
6112 cpu_reg(s
, a
->rm
), a
->msz
, true, fn
);
6120 static bool trans_PRF(DisasContext
*s
, arg_PRF
*a
)
6122 /* Prefetch is a nop within QEMU. */
6123 (void)sve_access_check(s
);
6127 static bool trans_PRF_rr(DisasContext
*s
, arg_PRF_rr
*a
)
6132 /* Prefetch is a nop within QEMU. */
6133 (void)sve_access_check(s
);
6140 * TODO: The implementation so far could handle predicated merging movprfx.
6141 * The helper functions as written take an extra source register to
6142 * use in the operation, but the result is only written when predication
6143 * succeeds. For unpredicated movprfx, we need to rearrange the helpers
6144 * to allow the final write back to the destination to be unconditional.
6145 * For predicated zeroing movprfx, we need to rearrange the helpers to
6146 * allow the final write back to zero inactives.
6148 * In the meantime, just emit the moves.
6151 static bool trans_MOVPRFX(DisasContext
*s
, arg_MOVPRFX
*a
)
6153 return do_mov_z(s
, a
->rd
, a
->rn
);
6156 static bool trans_MOVPRFX_m(DisasContext
*s
, arg_rpr_esz
*a
)
6158 return do_sel_z(s
, a
->rd
, a
->rn
, a
->rd
, a
->pg
, a
->esz
);
6161 static bool trans_MOVPRFX_z(DisasContext
*s
, arg_rpr_esz
*a
)
6163 return do_movz_zpz(s
, a
->rd
, a
->rn
, a
->pg
, a
->esz
, false);
6167 * SVE2 Integer Multiply - Unpredicated
6170 TRANS_FEAT(MUL_zzz
, aa64_sve2
, gen_gvec_fn_arg_zzz
, tcg_gen_gvec_mul
, a
)
6172 static gen_helper_gvec_3
* const smulh_zzz_fns
[4] = {
6173 gen_helper_gvec_smulh_b
, gen_helper_gvec_smulh_h
,
6174 gen_helper_gvec_smulh_s
, gen_helper_gvec_smulh_d
,
6176 TRANS_FEAT(SMULH_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6177 smulh_zzz_fns
[a
->esz
], a
, 0)
6179 static gen_helper_gvec_3
* const umulh_zzz_fns
[4] = {
6180 gen_helper_gvec_umulh_b
, gen_helper_gvec_umulh_h
,
6181 gen_helper_gvec_umulh_s
, gen_helper_gvec_umulh_d
,
6183 TRANS_FEAT(UMULH_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6184 umulh_zzz_fns
[a
->esz
], a
, 0)
6186 TRANS_FEAT(PMUL_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6187 gen_helper_gvec_pmul_b
, a
, 0)
6189 static gen_helper_gvec_3
* const sqdmulh_zzz_fns
[4] = {
6190 gen_helper_sve2_sqdmulh_b
, gen_helper_sve2_sqdmulh_h
,
6191 gen_helper_sve2_sqdmulh_s
, gen_helper_sve2_sqdmulh_d
,
6193 TRANS_FEAT(SQDMULH_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6194 sqdmulh_zzz_fns
[a
->esz
], a
, 0)
6196 static gen_helper_gvec_3
* const sqrdmulh_zzz_fns
[4] = {
6197 gen_helper_sve2_sqrdmulh_b
, gen_helper_sve2_sqrdmulh_h
,
6198 gen_helper_sve2_sqrdmulh_s
, gen_helper_sve2_sqrdmulh_d
,
6200 TRANS_FEAT(SQRDMULH_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6201 sqrdmulh_zzz_fns
[a
->esz
], a
, 0)
6204 * SVE2 Integer - Predicated
6207 static gen_helper_gvec_4
* const sadlp_fns
[4] = {
6208 NULL
, gen_helper_sve2_sadalp_zpzz_h
,
6209 gen_helper_sve2_sadalp_zpzz_s
, gen_helper_sve2_sadalp_zpzz_d
,
6211 TRANS_FEAT(SADALP_zpzz
, aa64_sve2
, gen_gvec_ool_arg_zpzz
,
6212 sadlp_fns
[a
->esz
], a
, 0)
6214 static gen_helper_gvec_4
* const uadlp_fns
[4] = {
6215 NULL
, gen_helper_sve2_uadalp_zpzz_h
,
6216 gen_helper_sve2_uadalp_zpzz_s
, gen_helper_sve2_uadalp_zpzz_d
,
6218 TRANS_FEAT(UADALP_zpzz
, aa64_sve2
, gen_gvec_ool_arg_zpzz
,
6219 uadlp_fns
[a
->esz
], a
, 0)
6222 * SVE2 integer unary operations (predicated)
6225 TRANS_FEAT(URECPE
, aa64_sve2
, gen_gvec_ool_arg_zpz
,
6226 a
->esz
== 2 ? gen_helper_sve2_urecpe_s
: NULL
, a
, 0)
6228 TRANS_FEAT(URSQRTE
, aa64_sve2
, gen_gvec_ool_arg_zpz
,
6229 a
->esz
== 2 ? gen_helper_sve2_ursqrte_s
: NULL
, a
, 0)
6231 static gen_helper_gvec_3
* const sqabs_fns
[4] = {
6232 gen_helper_sve2_sqabs_b
, gen_helper_sve2_sqabs_h
,
6233 gen_helper_sve2_sqabs_s
, gen_helper_sve2_sqabs_d
,
6235 TRANS_FEAT(SQABS
, aa64_sve2
, gen_gvec_ool_arg_zpz
, sqabs_fns
[a
->esz
], a
, 0)
6237 static gen_helper_gvec_3
* const sqneg_fns
[4] = {
6238 gen_helper_sve2_sqneg_b
, gen_helper_sve2_sqneg_h
,
6239 gen_helper_sve2_sqneg_s
, gen_helper_sve2_sqneg_d
,
6241 TRANS_FEAT(SQNEG
, aa64_sve2
, gen_gvec_ool_arg_zpz
, sqneg_fns
[a
->esz
], a
, 0)
6243 DO_ZPZZ(SQSHL
, aa64_sve2
, sve2_sqshl
)
6244 DO_ZPZZ(SQRSHL
, aa64_sve2
, sve2_sqrshl
)
6245 DO_ZPZZ(SRSHL
, aa64_sve2
, sve2_srshl
)
6247 DO_ZPZZ(UQSHL
, aa64_sve2
, sve2_uqshl
)
6248 DO_ZPZZ(UQRSHL
, aa64_sve2
, sve2_uqrshl
)
6249 DO_ZPZZ(URSHL
, aa64_sve2
, sve2_urshl
)
6251 DO_ZPZZ(SHADD
, aa64_sve2
, sve2_shadd
)
6252 DO_ZPZZ(SRHADD
, aa64_sve2
, sve2_srhadd
)
6253 DO_ZPZZ(SHSUB
, aa64_sve2
, sve2_shsub
)
6255 DO_ZPZZ(UHADD
, aa64_sve2
, sve2_uhadd
)
6256 DO_ZPZZ(URHADD
, aa64_sve2
, sve2_urhadd
)
6257 DO_ZPZZ(UHSUB
, aa64_sve2
, sve2_uhsub
)
6259 DO_ZPZZ(ADDP
, aa64_sve2
, sve2_addp
)
6260 DO_ZPZZ(SMAXP
, aa64_sve2
, sve2_smaxp
)
6261 DO_ZPZZ(UMAXP
, aa64_sve2
, sve2_umaxp
)
6262 DO_ZPZZ(SMINP
, aa64_sve2
, sve2_sminp
)
6263 DO_ZPZZ(UMINP
, aa64_sve2
, sve2_uminp
)
6265 DO_ZPZZ(SQADD_zpzz
, aa64_sve2
, sve2_sqadd
)
6266 DO_ZPZZ(UQADD_zpzz
, aa64_sve2
, sve2_uqadd
)
6267 DO_ZPZZ(SQSUB_zpzz
, aa64_sve2
, sve2_sqsub
)
6268 DO_ZPZZ(UQSUB_zpzz
, aa64_sve2
, sve2_uqsub
)
6269 DO_ZPZZ(SUQADD
, aa64_sve2
, sve2_suqadd
)
6270 DO_ZPZZ(USQADD
, aa64_sve2
, sve2_usqadd
)
6273 * SVE2 Widening Integer Arithmetic
6276 static gen_helper_gvec_3
* const saddl_fns
[4] = {
6277 NULL
, gen_helper_sve2_saddl_h
,
6278 gen_helper_sve2_saddl_s
, gen_helper_sve2_saddl_d
,
6280 TRANS_FEAT(SADDLB
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6281 saddl_fns
[a
->esz
], a
, 0)
6282 TRANS_FEAT(SADDLT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6283 saddl_fns
[a
->esz
], a
, 3)
6284 TRANS_FEAT(SADDLBT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6285 saddl_fns
[a
->esz
], a
, 2)
6287 static gen_helper_gvec_3
* const ssubl_fns
[4] = {
6288 NULL
, gen_helper_sve2_ssubl_h
,
6289 gen_helper_sve2_ssubl_s
, gen_helper_sve2_ssubl_d
,
6291 TRANS_FEAT(SSUBLB
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6292 ssubl_fns
[a
->esz
], a
, 0)
6293 TRANS_FEAT(SSUBLT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6294 ssubl_fns
[a
->esz
], a
, 3)
6295 TRANS_FEAT(SSUBLBT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6296 ssubl_fns
[a
->esz
], a
, 2)
6297 TRANS_FEAT(SSUBLTB
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6298 ssubl_fns
[a
->esz
], a
, 1)
6300 static gen_helper_gvec_3
* const sabdl_fns
[4] = {
6301 NULL
, gen_helper_sve2_sabdl_h
,
6302 gen_helper_sve2_sabdl_s
, gen_helper_sve2_sabdl_d
,
6304 TRANS_FEAT(SABDLB
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6305 sabdl_fns
[a
->esz
], a
, 0)
6306 TRANS_FEAT(SABDLT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6307 sabdl_fns
[a
->esz
], a
, 3)
6309 static gen_helper_gvec_3
* const uaddl_fns
[4] = {
6310 NULL
, gen_helper_sve2_uaddl_h
,
6311 gen_helper_sve2_uaddl_s
, gen_helper_sve2_uaddl_d
,
6313 TRANS_FEAT(UADDLB
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6314 uaddl_fns
[a
->esz
], a
, 0)
6315 TRANS_FEAT(UADDLT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6316 uaddl_fns
[a
->esz
], a
, 3)
6318 static gen_helper_gvec_3
* const usubl_fns
[4] = {
6319 NULL
, gen_helper_sve2_usubl_h
,
6320 gen_helper_sve2_usubl_s
, gen_helper_sve2_usubl_d
,
6322 TRANS_FEAT(USUBLB
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6323 usubl_fns
[a
->esz
], a
, 0)
6324 TRANS_FEAT(USUBLT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6325 usubl_fns
[a
->esz
], a
, 3)
6327 static gen_helper_gvec_3
* const uabdl_fns
[4] = {
6328 NULL
, gen_helper_sve2_uabdl_h
,
6329 gen_helper_sve2_uabdl_s
, gen_helper_sve2_uabdl_d
,
6331 TRANS_FEAT(UABDLB
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6332 uabdl_fns
[a
->esz
], a
, 0)
6333 TRANS_FEAT(UABDLT
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6334 uabdl_fns
[a
->esz
], a
, 3)
6336 static gen_helper_gvec_3
* const sqdmull_fns
[4] = {
6337 NULL
, gen_helper_sve2_sqdmull_zzz_h
,
6338 gen_helper_sve2_sqdmull_zzz_s
, gen_helper_sve2_sqdmull_zzz_d
,
6340 TRANS_FEAT(SQDMULLB_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6341 sqdmull_fns
[a
->esz
], a
, 0)
6342 TRANS_FEAT(SQDMULLT_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6343 sqdmull_fns
[a
->esz
], a
, 3)
6345 static gen_helper_gvec_3
* const smull_fns
[4] = {
6346 NULL
, gen_helper_sve2_smull_zzz_h
,
6347 gen_helper_sve2_smull_zzz_s
, gen_helper_sve2_smull_zzz_d
,
6349 TRANS_FEAT(SMULLB_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6350 smull_fns
[a
->esz
], a
, 0)
6351 TRANS_FEAT(SMULLT_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6352 smull_fns
[a
->esz
], a
, 3)
6354 static gen_helper_gvec_3
* const umull_fns
[4] = {
6355 NULL
, gen_helper_sve2_umull_zzz_h
,
6356 gen_helper_sve2_umull_zzz_s
, gen_helper_sve2_umull_zzz_d
,
6358 TRANS_FEAT(UMULLB_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6359 umull_fns
[a
->esz
], a
, 0)
6360 TRANS_FEAT(UMULLT_zzz
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6361 umull_fns
[a
->esz
], a
, 3)
6363 static gen_helper_gvec_3
* const eoril_fns
[4] = {
6364 gen_helper_sve2_eoril_b
, gen_helper_sve2_eoril_h
,
6365 gen_helper_sve2_eoril_s
, gen_helper_sve2_eoril_d
,
6367 TRANS_FEAT(EORBT
, aa64_sve2
, gen_gvec_ool_arg_zzz
, eoril_fns
[a
->esz
], a
, 2)
6368 TRANS_FEAT(EORTB
, aa64_sve2
, gen_gvec_ool_arg_zzz
, eoril_fns
[a
->esz
], a
, 1)
6370 static bool do_trans_pmull(DisasContext
*s
, arg_rrr_esz
*a
, bool sel
)
6372 static gen_helper_gvec_3
* const fns
[4] = {
6373 gen_helper_gvec_pmull_q
, gen_helper_sve2_pmull_h
,
6374 NULL
, gen_helper_sve2_pmull_d
,
6376 if (a
->esz
== 0 && !dc_isar_feature(aa64_sve2_pmull128
, s
)) {
6379 return gen_gvec_ool_arg_zzz(s
, fns
[a
->esz
], a
, sel
);
6382 TRANS_FEAT(PMULLB
, aa64_sve2
, do_trans_pmull
, a
, false)
6383 TRANS_FEAT(PMULLT
, aa64_sve2
, do_trans_pmull
, a
, true)
6385 static gen_helper_gvec_3
* const saddw_fns
[4] = {
6386 NULL
, gen_helper_sve2_saddw_h
,
6387 gen_helper_sve2_saddw_s
, gen_helper_sve2_saddw_d
,
6389 TRANS_FEAT(SADDWB
, aa64_sve2
, gen_gvec_ool_arg_zzz
, saddw_fns
[a
->esz
], a
, 0)
6390 TRANS_FEAT(SADDWT
, aa64_sve2
, gen_gvec_ool_arg_zzz
, saddw_fns
[a
->esz
], a
, 1)
6392 static gen_helper_gvec_3
* const ssubw_fns
[4] = {
6393 NULL
, gen_helper_sve2_ssubw_h
,
6394 gen_helper_sve2_ssubw_s
, gen_helper_sve2_ssubw_d
,
6396 TRANS_FEAT(SSUBWB
, aa64_sve2
, gen_gvec_ool_arg_zzz
, ssubw_fns
[a
->esz
], a
, 0)
6397 TRANS_FEAT(SSUBWT
, aa64_sve2
, gen_gvec_ool_arg_zzz
, ssubw_fns
[a
->esz
], a
, 1)
6399 static gen_helper_gvec_3
* const uaddw_fns
[4] = {
6400 NULL
, gen_helper_sve2_uaddw_h
,
6401 gen_helper_sve2_uaddw_s
, gen_helper_sve2_uaddw_d
,
6403 TRANS_FEAT(UADDWB
, aa64_sve2
, gen_gvec_ool_arg_zzz
, uaddw_fns
[a
->esz
], a
, 0)
6404 TRANS_FEAT(UADDWT
, aa64_sve2
, gen_gvec_ool_arg_zzz
, uaddw_fns
[a
->esz
], a
, 1)
6406 static gen_helper_gvec_3
* const usubw_fns
[4] = {
6407 NULL
, gen_helper_sve2_usubw_h
,
6408 gen_helper_sve2_usubw_s
, gen_helper_sve2_usubw_d
,
6410 TRANS_FEAT(USUBWB
, aa64_sve2
, gen_gvec_ool_arg_zzz
, usubw_fns
[a
->esz
], a
, 0)
6411 TRANS_FEAT(USUBWT
, aa64_sve2
, gen_gvec_ool_arg_zzz
, usubw_fns
[a
->esz
], a
, 1)
6413 static void gen_sshll_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, int64_t imm
)
6417 int halfbits
= 4 << vece
;
6420 if (shl
== halfbits
) {
6421 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6422 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(halfbits
, halfbits
));
6423 tcg_gen_and_vec(vece
, d
, n
, t
);
6424 tcg_temp_free_vec(t
);
6426 tcg_gen_sari_vec(vece
, d
, n
, halfbits
);
6427 tcg_gen_shli_vec(vece
, d
, d
, shl
);
6430 tcg_gen_shli_vec(vece
, d
, n
, halfbits
);
6431 tcg_gen_sari_vec(vece
, d
, d
, halfbits
- shl
);
6435 static void gen_ushll_i64(unsigned vece
, TCGv_i64 d
, TCGv_i64 n
, int imm
)
6437 int halfbits
= 4 << vece
;
6439 int shl
= (imm
>> 1);
6443 mask
= MAKE_64BIT_MASK(0, halfbits
);
6445 mask
= dup_const(vece
, mask
);
6447 shift
= shl
- top
* halfbits
;
6449 tcg_gen_shri_i64(d
, n
, -shift
);
6451 tcg_gen_shli_i64(d
, n
, shift
);
6453 tcg_gen_andi_i64(d
, d
, mask
);
6456 static void gen_ushll16_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t imm
)
6458 gen_ushll_i64(MO_16
, d
, n
, imm
);
6461 static void gen_ushll32_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t imm
)
6463 gen_ushll_i64(MO_32
, d
, n
, imm
);
6466 static void gen_ushll64_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t imm
)
6468 gen_ushll_i64(MO_64
, d
, n
, imm
);
6471 static void gen_ushll_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, int64_t imm
)
6473 int halfbits
= 4 << vece
;
6478 if (shl
== halfbits
) {
6479 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6480 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(halfbits
, halfbits
));
6481 tcg_gen_and_vec(vece
, d
, n
, t
);
6482 tcg_temp_free_vec(t
);
6484 tcg_gen_shri_vec(vece
, d
, n
, halfbits
);
6485 tcg_gen_shli_vec(vece
, d
, d
, shl
);
6489 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6490 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(0, halfbits
));
6491 tcg_gen_and_vec(vece
, d
, n
, t
);
6492 tcg_temp_free_vec(t
);
6494 tcg_gen_shli_vec(vece
, d
, n
, halfbits
);
6495 tcg_gen_shri_vec(vece
, d
, d
, halfbits
- shl
);
6500 static bool do_sve2_shll_tb(DisasContext
*s
, arg_rri_esz
*a
,
6503 static const TCGOpcode sshll_list
[] = {
6504 INDEX_op_shli_vec
, INDEX_op_sari_vec
, 0
6506 static const TCGOpcode ushll_list
[] = {
6507 INDEX_op_shli_vec
, INDEX_op_shri_vec
, 0
6509 static const GVecGen2i ops
[2][3] = {
6510 { { .fniv
= gen_sshll_vec
,
6511 .opt_opc
= sshll_list
,
6512 .fno
= gen_helper_sve2_sshll_h
,
6514 { .fniv
= gen_sshll_vec
,
6515 .opt_opc
= sshll_list
,
6516 .fno
= gen_helper_sve2_sshll_s
,
6518 { .fniv
= gen_sshll_vec
,
6519 .opt_opc
= sshll_list
,
6520 .fno
= gen_helper_sve2_sshll_d
,
6522 { { .fni8
= gen_ushll16_i64
,
6523 .fniv
= gen_ushll_vec
,
6524 .opt_opc
= ushll_list
,
6525 .fno
= gen_helper_sve2_ushll_h
,
6527 { .fni8
= gen_ushll32_i64
,
6528 .fniv
= gen_ushll_vec
,
6529 .opt_opc
= ushll_list
,
6530 .fno
= gen_helper_sve2_ushll_s
,
6532 { .fni8
= gen_ushll64_i64
,
6533 .fniv
= gen_ushll_vec
,
6534 .opt_opc
= ushll_list
,
6535 .fno
= gen_helper_sve2_ushll_d
,
6539 if (a
->esz
< 0 || a
->esz
> 2 || !dc_isar_feature(aa64_sve2
, s
)) {
6542 if (sve_access_check(s
)) {
6543 unsigned vsz
= vec_full_reg_size(s
);
6544 tcg_gen_gvec_2i(vec_full_reg_offset(s
, a
->rd
),
6545 vec_full_reg_offset(s
, a
->rn
),
6546 vsz
, vsz
, (a
->imm
<< 1) | sel
,
6552 static bool trans_SSHLLB(DisasContext
*s
, arg_rri_esz
*a
)
6554 return do_sve2_shll_tb(s
, a
, false, false);
6557 static bool trans_SSHLLT(DisasContext
*s
, arg_rri_esz
*a
)
6559 return do_sve2_shll_tb(s
, a
, true, false);
6562 static bool trans_USHLLB(DisasContext
*s
, arg_rri_esz
*a
)
6564 return do_sve2_shll_tb(s
, a
, false, true);
6567 static bool trans_USHLLT(DisasContext
*s
, arg_rri_esz
*a
)
6569 return do_sve2_shll_tb(s
, a
, true, true);
6572 static gen_helper_gvec_3
* const bext_fns
[4] = {
6573 gen_helper_sve2_bext_b
, gen_helper_sve2_bext_h
,
6574 gen_helper_sve2_bext_s
, gen_helper_sve2_bext_d
,
6576 TRANS_FEAT(BEXT
, aa64_sve2_bitperm
, gen_gvec_ool_arg_zzz
,
6577 bext_fns
[a
->esz
], a
, 0)
6579 static gen_helper_gvec_3
* const bdep_fns
[4] = {
6580 gen_helper_sve2_bdep_b
, gen_helper_sve2_bdep_h
,
6581 gen_helper_sve2_bdep_s
, gen_helper_sve2_bdep_d
,
6583 TRANS_FEAT(BDEP
, aa64_sve2_bitperm
, gen_gvec_ool_arg_zzz
,
6584 bdep_fns
[a
->esz
], a
, 0)
6586 static gen_helper_gvec_3
* const bgrp_fns
[4] = {
6587 gen_helper_sve2_bgrp_b
, gen_helper_sve2_bgrp_h
,
6588 gen_helper_sve2_bgrp_s
, gen_helper_sve2_bgrp_d
,
6590 TRANS_FEAT(BGRP
, aa64_sve2_bitperm
, gen_gvec_ool_arg_zzz
,
6591 bgrp_fns
[a
->esz
], a
, 0)
6593 static gen_helper_gvec_3
* const cadd_fns
[4] = {
6594 gen_helper_sve2_cadd_b
, gen_helper_sve2_cadd_h
,
6595 gen_helper_sve2_cadd_s
, gen_helper_sve2_cadd_d
,
6597 TRANS_FEAT(CADD_rot90
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6598 cadd_fns
[a
->esz
], a
, 0)
6599 TRANS_FEAT(CADD_rot270
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6600 cadd_fns
[a
->esz
], a
, 1)
6602 static gen_helper_gvec_3
* const sqcadd_fns
[4] = {
6603 gen_helper_sve2_sqcadd_b
, gen_helper_sve2_sqcadd_h
,
6604 gen_helper_sve2_sqcadd_s
, gen_helper_sve2_sqcadd_d
,
6606 TRANS_FEAT(SQCADD_rot90
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6607 sqcadd_fns
[a
->esz
], a
, 0)
6608 TRANS_FEAT(SQCADD_rot270
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
6609 sqcadd_fns
[a
->esz
], a
, 1)
6611 static gen_helper_gvec_4
* const sabal_fns
[4] = {
6612 NULL
, gen_helper_sve2_sabal_h
,
6613 gen_helper_sve2_sabal_s
, gen_helper_sve2_sabal_d
,
6615 TRANS_FEAT(SABALB
, aa64_sve2
, gen_gvec_ool_arg_zzzz
, sabal_fns
[a
->esz
], a
, 0)
6616 TRANS_FEAT(SABALT
, aa64_sve2
, gen_gvec_ool_arg_zzzz
, sabal_fns
[a
->esz
], a
, 1)
6618 static gen_helper_gvec_4
* const uabal_fns
[4] = {
6619 NULL
, gen_helper_sve2_uabal_h
,
6620 gen_helper_sve2_uabal_s
, gen_helper_sve2_uabal_d
,
6622 TRANS_FEAT(UABALB
, aa64_sve2
, gen_gvec_ool_arg_zzzz
, uabal_fns
[a
->esz
], a
, 0)
6623 TRANS_FEAT(UABALT
, aa64_sve2
, gen_gvec_ool_arg_zzzz
, uabal_fns
[a
->esz
], a
, 1)
6625 static bool do_adcl(DisasContext
*s
, arg_rrrr_esz
*a
, bool sel
)
6627 static gen_helper_gvec_4
* const fns
[2] = {
6628 gen_helper_sve2_adcl_s
,
6629 gen_helper_sve2_adcl_d
,
6632 * Note that in this case the ESZ field encodes both size and sign.
6633 * Split out 'subtract' into bit 1 of the data field for the helper.
6635 return gen_gvec_ool_arg_zzzz(s
, fns
[a
->esz
& 1], a
, (a
->esz
& 2) | sel
);
6638 TRANS_FEAT(ADCLB
, aa64_sve2
, do_adcl
, a
, false)
6639 TRANS_FEAT(ADCLT
, aa64_sve2
, do_adcl
, a
, true)
6641 TRANS_FEAT(SSRA
, aa64_sve2
, gen_gvec_fn_arg_zzi
, gen_gvec_ssra
, a
)
6642 TRANS_FEAT(USRA
, aa64_sve2
, gen_gvec_fn_arg_zzi
, gen_gvec_usra
, a
)
6643 TRANS_FEAT(SRSRA
, aa64_sve2
, gen_gvec_fn_arg_zzi
, gen_gvec_srsra
, a
)
6644 TRANS_FEAT(URSRA
, aa64_sve2
, gen_gvec_fn_arg_zzi
, gen_gvec_ursra
, a
)
6645 TRANS_FEAT(SRI
, aa64_sve2
, gen_gvec_fn_arg_zzi
, gen_gvec_sri
, a
)
6646 TRANS_FEAT(SLI
, aa64_sve2
, gen_gvec_fn_arg_zzi
, gen_gvec_sli
, a
)
6648 TRANS_FEAT(SABA
, aa64_sve2
, gen_gvec_fn_arg_zzz
, gen_gvec_saba
, a
)
6649 TRANS_FEAT(UABA
, aa64_sve2
, gen_gvec_fn_arg_zzz
, gen_gvec_uaba
, a
)
6651 static bool do_sve2_narrow_extract(DisasContext
*s
, arg_rri_esz
*a
,
6652 const GVecGen2 ops
[3])
6654 if (a
->esz
< 0 || a
->esz
> MO_32
|| a
->imm
!= 0 ||
6655 !dc_isar_feature(aa64_sve2
, s
)) {
6658 if (sve_access_check(s
)) {
6659 unsigned vsz
= vec_full_reg_size(s
);
6660 tcg_gen_gvec_2(vec_full_reg_offset(s
, a
->rd
),
6661 vec_full_reg_offset(s
, a
->rn
),
6662 vsz
, vsz
, &ops
[a
->esz
]);
6667 static const TCGOpcode sqxtn_list
[] = {
6668 INDEX_op_shli_vec
, INDEX_op_smin_vec
, INDEX_op_smax_vec
, 0
6671 static void gen_sqxtnb_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
)
6673 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6674 int halfbits
= 4 << vece
;
6675 int64_t mask
= (1ull << halfbits
) - 1;
6676 int64_t min
= -1ull << (halfbits
- 1);
6677 int64_t max
= -min
- 1;
6679 tcg_gen_dupi_vec(vece
, t
, min
);
6680 tcg_gen_smax_vec(vece
, d
, n
, t
);
6681 tcg_gen_dupi_vec(vece
, t
, max
);
6682 tcg_gen_smin_vec(vece
, d
, d
, t
);
6683 tcg_gen_dupi_vec(vece
, t
, mask
);
6684 tcg_gen_and_vec(vece
, d
, d
, t
);
6685 tcg_temp_free_vec(t
);
6688 static bool trans_SQXTNB(DisasContext
*s
, arg_rri_esz
*a
)
6690 static const GVecGen2 ops
[3] = {
6691 { .fniv
= gen_sqxtnb_vec
,
6692 .opt_opc
= sqxtn_list
,
6693 .fno
= gen_helper_sve2_sqxtnb_h
,
6695 { .fniv
= gen_sqxtnb_vec
,
6696 .opt_opc
= sqxtn_list
,
6697 .fno
= gen_helper_sve2_sqxtnb_s
,
6699 { .fniv
= gen_sqxtnb_vec
,
6700 .opt_opc
= sqxtn_list
,
6701 .fno
= gen_helper_sve2_sqxtnb_d
,
6704 return do_sve2_narrow_extract(s
, a
, ops
);
6707 static void gen_sqxtnt_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
)
6709 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6710 int halfbits
= 4 << vece
;
6711 int64_t mask
= (1ull << halfbits
) - 1;
6712 int64_t min
= -1ull << (halfbits
- 1);
6713 int64_t max
= -min
- 1;
6715 tcg_gen_dupi_vec(vece
, t
, min
);
6716 tcg_gen_smax_vec(vece
, n
, n
, t
);
6717 tcg_gen_dupi_vec(vece
, t
, max
);
6718 tcg_gen_smin_vec(vece
, n
, n
, t
);
6719 tcg_gen_shli_vec(vece
, n
, n
, halfbits
);
6720 tcg_gen_dupi_vec(vece
, t
, mask
);
6721 tcg_gen_bitsel_vec(vece
, d
, t
, d
, n
);
6722 tcg_temp_free_vec(t
);
6725 static bool trans_SQXTNT(DisasContext
*s
, arg_rri_esz
*a
)
6727 static const GVecGen2 ops
[3] = {
6728 { .fniv
= gen_sqxtnt_vec
,
6729 .opt_opc
= sqxtn_list
,
6731 .fno
= gen_helper_sve2_sqxtnt_h
,
6733 { .fniv
= gen_sqxtnt_vec
,
6734 .opt_opc
= sqxtn_list
,
6736 .fno
= gen_helper_sve2_sqxtnt_s
,
6738 { .fniv
= gen_sqxtnt_vec
,
6739 .opt_opc
= sqxtn_list
,
6741 .fno
= gen_helper_sve2_sqxtnt_d
,
6744 return do_sve2_narrow_extract(s
, a
, ops
);
6747 static const TCGOpcode uqxtn_list
[] = {
6748 INDEX_op_shli_vec
, INDEX_op_umin_vec
, 0
6751 static void gen_uqxtnb_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
)
6753 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6754 int halfbits
= 4 << vece
;
6755 int64_t max
= (1ull << halfbits
) - 1;
6757 tcg_gen_dupi_vec(vece
, t
, max
);
6758 tcg_gen_umin_vec(vece
, d
, n
, t
);
6759 tcg_temp_free_vec(t
);
6762 static bool trans_UQXTNB(DisasContext
*s
, arg_rri_esz
*a
)
6764 static const GVecGen2 ops
[3] = {
6765 { .fniv
= gen_uqxtnb_vec
,
6766 .opt_opc
= uqxtn_list
,
6767 .fno
= gen_helper_sve2_uqxtnb_h
,
6769 { .fniv
= gen_uqxtnb_vec
,
6770 .opt_opc
= uqxtn_list
,
6771 .fno
= gen_helper_sve2_uqxtnb_s
,
6773 { .fniv
= gen_uqxtnb_vec
,
6774 .opt_opc
= uqxtn_list
,
6775 .fno
= gen_helper_sve2_uqxtnb_d
,
6778 return do_sve2_narrow_extract(s
, a
, ops
);
6781 static void gen_uqxtnt_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
)
6783 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6784 int halfbits
= 4 << vece
;
6785 int64_t max
= (1ull << halfbits
) - 1;
6787 tcg_gen_dupi_vec(vece
, t
, max
);
6788 tcg_gen_umin_vec(vece
, n
, n
, t
);
6789 tcg_gen_shli_vec(vece
, n
, n
, halfbits
);
6790 tcg_gen_bitsel_vec(vece
, d
, t
, d
, n
);
6791 tcg_temp_free_vec(t
);
6794 static bool trans_UQXTNT(DisasContext
*s
, arg_rri_esz
*a
)
6796 static const GVecGen2 ops
[3] = {
6797 { .fniv
= gen_uqxtnt_vec
,
6798 .opt_opc
= uqxtn_list
,
6800 .fno
= gen_helper_sve2_uqxtnt_h
,
6802 { .fniv
= gen_uqxtnt_vec
,
6803 .opt_opc
= uqxtn_list
,
6805 .fno
= gen_helper_sve2_uqxtnt_s
,
6807 { .fniv
= gen_uqxtnt_vec
,
6808 .opt_opc
= uqxtn_list
,
6810 .fno
= gen_helper_sve2_uqxtnt_d
,
6813 return do_sve2_narrow_extract(s
, a
, ops
);
6816 static const TCGOpcode sqxtun_list
[] = {
6817 INDEX_op_shli_vec
, INDEX_op_umin_vec
, INDEX_op_smax_vec
, 0
6820 static void gen_sqxtunb_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
)
6822 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6823 int halfbits
= 4 << vece
;
6824 int64_t max
= (1ull << halfbits
) - 1;
6826 tcg_gen_dupi_vec(vece
, t
, 0);
6827 tcg_gen_smax_vec(vece
, d
, n
, t
);
6828 tcg_gen_dupi_vec(vece
, t
, max
);
6829 tcg_gen_umin_vec(vece
, d
, d
, t
);
6830 tcg_temp_free_vec(t
);
6833 static bool trans_SQXTUNB(DisasContext
*s
, arg_rri_esz
*a
)
6835 static const GVecGen2 ops
[3] = {
6836 { .fniv
= gen_sqxtunb_vec
,
6837 .opt_opc
= sqxtun_list
,
6838 .fno
= gen_helper_sve2_sqxtunb_h
,
6840 { .fniv
= gen_sqxtunb_vec
,
6841 .opt_opc
= sqxtun_list
,
6842 .fno
= gen_helper_sve2_sqxtunb_s
,
6844 { .fniv
= gen_sqxtunb_vec
,
6845 .opt_opc
= sqxtun_list
,
6846 .fno
= gen_helper_sve2_sqxtunb_d
,
6849 return do_sve2_narrow_extract(s
, a
, ops
);
6852 static void gen_sqxtunt_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
)
6854 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6855 int halfbits
= 4 << vece
;
6856 int64_t max
= (1ull << halfbits
) - 1;
6858 tcg_gen_dupi_vec(vece
, t
, 0);
6859 tcg_gen_smax_vec(vece
, n
, n
, t
);
6860 tcg_gen_dupi_vec(vece
, t
, max
);
6861 tcg_gen_umin_vec(vece
, n
, n
, t
);
6862 tcg_gen_shli_vec(vece
, n
, n
, halfbits
);
6863 tcg_gen_bitsel_vec(vece
, d
, t
, d
, n
);
6864 tcg_temp_free_vec(t
);
6867 static bool trans_SQXTUNT(DisasContext
*s
, arg_rri_esz
*a
)
6869 static const GVecGen2 ops
[3] = {
6870 { .fniv
= gen_sqxtunt_vec
,
6871 .opt_opc
= sqxtun_list
,
6873 .fno
= gen_helper_sve2_sqxtunt_h
,
6875 { .fniv
= gen_sqxtunt_vec
,
6876 .opt_opc
= sqxtun_list
,
6878 .fno
= gen_helper_sve2_sqxtunt_s
,
6880 { .fniv
= gen_sqxtunt_vec
,
6881 .opt_opc
= sqxtun_list
,
6883 .fno
= gen_helper_sve2_sqxtunt_d
,
6886 return do_sve2_narrow_extract(s
, a
, ops
);
6889 static bool do_sve2_shr_narrow(DisasContext
*s
, arg_rri_esz
*a
,
6890 const GVecGen2i ops
[3])
6892 if (a
->esz
< 0 || a
->esz
> MO_32
|| !dc_isar_feature(aa64_sve2
, s
)) {
6895 assert(a
->imm
> 0 && a
->imm
<= (8 << a
->esz
));
6896 if (sve_access_check(s
)) {
6897 unsigned vsz
= vec_full_reg_size(s
);
6898 tcg_gen_gvec_2i(vec_full_reg_offset(s
, a
->rd
),
6899 vec_full_reg_offset(s
, a
->rn
),
6900 vsz
, vsz
, a
->imm
, &ops
[a
->esz
]);
6905 static void gen_shrnb_i64(unsigned vece
, TCGv_i64 d
, TCGv_i64 n
, int shr
)
6907 int halfbits
= 4 << vece
;
6908 uint64_t mask
= dup_const(vece
, MAKE_64BIT_MASK(0, halfbits
));
6910 tcg_gen_shri_i64(d
, n
, shr
);
6911 tcg_gen_andi_i64(d
, d
, mask
);
6914 static void gen_shrnb16_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t shr
)
6916 gen_shrnb_i64(MO_16
, d
, n
, shr
);
6919 static void gen_shrnb32_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t shr
)
6921 gen_shrnb_i64(MO_32
, d
, n
, shr
);
6924 static void gen_shrnb64_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t shr
)
6926 gen_shrnb_i64(MO_64
, d
, n
, shr
);
6929 static void gen_shrnb_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, int64_t shr
)
6931 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6932 int halfbits
= 4 << vece
;
6933 uint64_t mask
= MAKE_64BIT_MASK(0, halfbits
);
6935 tcg_gen_shri_vec(vece
, n
, n
, shr
);
6936 tcg_gen_dupi_vec(vece
, t
, mask
);
6937 tcg_gen_and_vec(vece
, d
, n
, t
);
6938 tcg_temp_free_vec(t
);
6941 static bool trans_SHRNB(DisasContext
*s
, arg_rri_esz
*a
)
6943 static const TCGOpcode vec_list
[] = { INDEX_op_shri_vec
, 0 };
6944 static const GVecGen2i ops
[3] = {
6945 { .fni8
= gen_shrnb16_i64
,
6946 .fniv
= gen_shrnb_vec
,
6947 .opt_opc
= vec_list
,
6948 .fno
= gen_helper_sve2_shrnb_h
,
6950 { .fni8
= gen_shrnb32_i64
,
6951 .fniv
= gen_shrnb_vec
,
6952 .opt_opc
= vec_list
,
6953 .fno
= gen_helper_sve2_shrnb_s
,
6955 { .fni8
= gen_shrnb64_i64
,
6956 .fniv
= gen_shrnb_vec
,
6957 .opt_opc
= vec_list
,
6958 .fno
= gen_helper_sve2_shrnb_d
,
6961 return do_sve2_shr_narrow(s
, a
, ops
);
6964 static void gen_shrnt_i64(unsigned vece
, TCGv_i64 d
, TCGv_i64 n
, int shr
)
6966 int halfbits
= 4 << vece
;
6967 uint64_t mask
= dup_const(vece
, MAKE_64BIT_MASK(0, halfbits
));
6969 tcg_gen_shli_i64(n
, n
, halfbits
- shr
);
6970 tcg_gen_andi_i64(n
, n
, ~mask
);
6971 tcg_gen_andi_i64(d
, d
, mask
);
6972 tcg_gen_or_i64(d
, d
, n
);
6975 static void gen_shrnt16_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t shr
)
6977 gen_shrnt_i64(MO_16
, d
, n
, shr
);
6980 static void gen_shrnt32_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t shr
)
6982 gen_shrnt_i64(MO_32
, d
, n
, shr
);
6985 static void gen_shrnt64_i64(TCGv_i64 d
, TCGv_i64 n
, int64_t shr
)
6987 tcg_gen_shri_i64(n
, n
, shr
);
6988 tcg_gen_deposit_i64(d
, d
, n
, 32, 32);
6991 static void gen_shrnt_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, int64_t shr
)
6993 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
6994 int halfbits
= 4 << vece
;
6995 uint64_t mask
= MAKE_64BIT_MASK(0, halfbits
);
6997 tcg_gen_shli_vec(vece
, n
, n
, halfbits
- shr
);
6998 tcg_gen_dupi_vec(vece
, t
, mask
);
6999 tcg_gen_bitsel_vec(vece
, d
, t
, d
, n
);
7000 tcg_temp_free_vec(t
);
7003 static bool trans_SHRNT(DisasContext
*s
, arg_rri_esz
*a
)
7005 static const TCGOpcode vec_list
[] = { INDEX_op_shli_vec
, 0 };
7006 static const GVecGen2i ops
[3] = {
7007 { .fni8
= gen_shrnt16_i64
,
7008 .fniv
= gen_shrnt_vec
,
7009 .opt_opc
= vec_list
,
7011 .fno
= gen_helper_sve2_shrnt_h
,
7013 { .fni8
= gen_shrnt32_i64
,
7014 .fniv
= gen_shrnt_vec
,
7015 .opt_opc
= vec_list
,
7017 .fno
= gen_helper_sve2_shrnt_s
,
7019 { .fni8
= gen_shrnt64_i64
,
7020 .fniv
= gen_shrnt_vec
,
7021 .opt_opc
= vec_list
,
7023 .fno
= gen_helper_sve2_shrnt_d
,
7026 return do_sve2_shr_narrow(s
, a
, ops
);
7029 static bool trans_RSHRNB(DisasContext
*s
, arg_rri_esz
*a
)
7031 static const GVecGen2i ops
[3] = {
7032 { .fno
= gen_helper_sve2_rshrnb_h
},
7033 { .fno
= gen_helper_sve2_rshrnb_s
},
7034 { .fno
= gen_helper_sve2_rshrnb_d
},
7036 return do_sve2_shr_narrow(s
, a
, ops
);
7039 static bool trans_RSHRNT(DisasContext
*s
, arg_rri_esz
*a
)
7041 static const GVecGen2i ops
[3] = {
7042 { .fno
= gen_helper_sve2_rshrnt_h
},
7043 { .fno
= gen_helper_sve2_rshrnt_s
},
7044 { .fno
= gen_helper_sve2_rshrnt_d
},
7046 return do_sve2_shr_narrow(s
, a
, ops
);
7049 static void gen_sqshrunb_vec(unsigned vece
, TCGv_vec d
,
7050 TCGv_vec n
, int64_t shr
)
7052 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
7053 int halfbits
= 4 << vece
;
7055 tcg_gen_sari_vec(vece
, n
, n
, shr
);
7056 tcg_gen_dupi_vec(vece
, t
, 0);
7057 tcg_gen_smax_vec(vece
, n
, n
, t
);
7058 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(0, halfbits
));
7059 tcg_gen_umin_vec(vece
, d
, n
, t
);
7060 tcg_temp_free_vec(t
);
7063 static bool trans_SQSHRUNB(DisasContext
*s
, arg_rri_esz
*a
)
7065 static const TCGOpcode vec_list
[] = {
7066 INDEX_op_sari_vec
, INDEX_op_smax_vec
, INDEX_op_umin_vec
, 0
7068 static const GVecGen2i ops
[3] = {
7069 { .fniv
= gen_sqshrunb_vec
,
7070 .opt_opc
= vec_list
,
7071 .fno
= gen_helper_sve2_sqshrunb_h
,
7073 { .fniv
= gen_sqshrunb_vec
,
7074 .opt_opc
= vec_list
,
7075 .fno
= gen_helper_sve2_sqshrunb_s
,
7077 { .fniv
= gen_sqshrunb_vec
,
7078 .opt_opc
= vec_list
,
7079 .fno
= gen_helper_sve2_sqshrunb_d
,
7082 return do_sve2_shr_narrow(s
, a
, ops
);
7085 static void gen_sqshrunt_vec(unsigned vece
, TCGv_vec d
,
7086 TCGv_vec n
, int64_t shr
)
7088 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
7089 int halfbits
= 4 << vece
;
7091 tcg_gen_sari_vec(vece
, n
, n
, shr
);
7092 tcg_gen_dupi_vec(vece
, t
, 0);
7093 tcg_gen_smax_vec(vece
, n
, n
, t
);
7094 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(0, halfbits
));
7095 tcg_gen_umin_vec(vece
, n
, n
, t
);
7096 tcg_gen_shli_vec(vece
, n
, n
, halfbits
);
7097 tcg_gen_bitsel_vec(vece
, d
, t
, d
, n
);
7098 tcg_temp_free_vec(t
);
7101 static bool trans_SQSHRUNT(DisasContext
*s
, arg_rri_esz
*a
)
7103 static const TCGOpcode vec_list
[] = {
7104 INDEX_op_shli_vec
, INDEX_op_sari_vec
,
7105 INDEX_op_smax_vec
, INDEX_op_umin_vec
, 0
7107 static const GVecGen2i ops
[3] = {
7108 { .fniv
= gen_sqshrunt_vec
,
7109 .opt_opc
= vec_list
,
7111 .fno
= gen_helper_sve2_sqshrunt_h
,
7113 { .fniv
= gen_sqshrunt_vec
,
7114 .opt_opc
= vec_list
,
7116 .fno
= gen_helper_sve2_sqshrunt_s
,
7118 { .fniv
= gen_sqshrunt_vec
,
7119 .opt_opc
= vec_list
,
7121 .fno
= gen_helper_sve2_sqshrunt_d
,
7124 return do_sve2_shr_narrow(s
, a
, ops
);
7127 static bool trans_SQRSHRUNB(DisasContext
*s
, arg_rri_esz
*a
)
7129 static const GVecGen2i ops
[3] = {
7130 { .fno
= gen_helper_sve2_sqrshrunb_h
},
7131 { .fno
= gen_helper_sve2_sqrshrunb_s
},
7132 { .fno
= gen_helper_sve2_sqrshrunb_d
},
7134 return do_sve2_shr_narrow(s
, a
, ops
);
7137 static bool trans_SQRSHRUNT(DisasContext
*s
, arg_rri_esz
*a
)
7139 static const GVecGen2i ops
[3] = {
7140 { .fno
= gen_helper_sve2_sqrshrunt_h
},
7141 { .fno
= gen_helper_sve2_sqrshrunt_s
},
7142 { .fno
= gen_helper_sve2_sqrshrunt_d
},
7144 return do_sve2_shr_narrow(s
, a
, ops
);
7147 static void gen_sqshrnb_vec(unsigned vece
, TCGv_vec d
,
7148 TCGv_vec n
, int64_t shr
)
7150 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
7151 int halfbits
= 4 << vece
;
7152 int64_t max
= MAKE_64BIT_MASK(0, halfbits
- 1);
7153 int64_t min
= -max
- 1;
7155 tcg_gen_sari_vec(vece
, n
, n
, shr
);
7156 tcg_gen_dupi_vec(vece
, t
, min
);
7157 tcg_gen_smax_vec(vece
, n
, n
, t
);
7158 tcg_gen_dupi_vec(vece
, t
, max
);
7159 tcg_gen_smin_vec(vece
, n
, n
, t
);
7160 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(0, halfbits
));
7161 tcg_gen_and_vec(vece
, d
, n
, t
);
7162 tcg_temp_free_vec(t
);
7165 static bool trans_SQSHRNB(DisasContext
*s
, arg_rri_esz
*a
)
7167 static const TCGOpcode vec_list
[] = {
7168 INDEX_op_sari_vec
, INDEX_op_smax_vec
, INDEX_op_smin_vec
, 0
7170 static const GVecGen2i ops
[3] = {
7171 { .fniv
= gen_sqshrnb_vec
,
7172 .opt_opc
= vec_list
,
7173 .fno
= gen_helper_sve2_sqshrnb_h
,
7175 { .fniv
= gen_sqshrnb_vec
,
7176 .opt_opc
= vec_list
,
7177 .fno
= gen_helper_sve2_sqshrnb_s
,
7179 { .fniv
= gen_sqshrnb_vec
,
7180 .opt_opc
= vec_list
,
7181 .fno
= gen_helper_sve2_sqshrnb_d
,
7184 return do_sve2_shr_narrow(s
, a
, ops
);
7187 static void gen_sqshrnt_vec(unsigned vece
, TCGv_vec d
,
7188 TCGv_vec n
, int64_t shr
)
7190 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
7191 int halfbits
= 4 << vece
;
7192 int64_t max
= MAKE_64BIT_MASK(0, halfbits
- 1);
7193 int64_t min
= -max
- 1;
7195 tcg_gen_sari_vec(vece
, n
, n
, shr
);
7196 tcg_gen_dupi_vec(vece
, t
, min
);
7197 tcg_gen_smax_vec(vece
, n
, n
, t
);
7198 tcg_gen_dupi_vec(vece
, t
, max
);
7199 tcg_gen_smin_vec(vece
, n
, n
, t
);
7200 tcg_gen_shli_vec(vece
, n
, n
, halfbits
);
7201 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(0, halfbits
));
7202 tcg_gen_bitsel_vec(vece
, d
, t
, d
, n
);
7203 tcg_temp_free_vec(t
);
7206 static bool trans_SQSHRNT(DisasContext
*s
, arg_rri_esz
*a
)
7208 static const TCGOpcode vec_list
[] = {
7209 INDEX_op_shli_vec
, INDEX_op_sari_vec
,
7210 INDEX_op_smax_vec
, INDEX_op_smin_vec
, 0
7212 static const GVecGen2i ops
[3] = {
7213 { .fniv
= gen_sqshrnt_vec
,
7214 .opt_opc
= vec_list
,
7216 .fno
= gen_helper_sve2_sqshrnt_h
,
7218 { .fniv
= gen_sqshrnt_vec
,
7219 .opt_opc
= vec_list
,
7221 .fno
= gen_helper_sve2_sqshrnt_s
,
7223 { .fniv
= gen_sqshrnt_vec
,
7224 .opt_opc
= vec_list
,
7226 .fno
= gen_helper_sve2_sqshrnt_d
,
7229 return do_sve2_shr_narrow(s
, a
, ops
);
7232 static bool trans_SQRSHRNB(DisasContext
*s
, arg_rri_esz
*a
)
7234 static const GVecGen2i ops
[3] = {
7235 { .fno
= gen_helper_sve2_sqrshrnb_h
},
7236 { .fno
= gen_helper_sve2_sqrshrnb_s
},
7237 { .fno
= gen_helper_sve2_sqrshrnb_d
},
7239 return do_sve2_shr_narrow(s
, a
, ops
);
7242 static bool trans_SQRSHRNT(DisasContext
*s
, arg_rri_esz
*a
)
7244 static const GVecGen2i ops
[3] = {
7245 { .fno
= gen_helper_sve2_sqrshrnt_h
},
7246 { .fno
= gen_helper_sve2_sqrshrnt_s
},
7247 { .fno
= gen_helper_sve2_sqrshrnt_d
},
7249 return do_sve2_shr_narrow(s
, a
, ops
);
7252 static void gen_uqshrnb_vec(unsigned vece
, TCGv_vec d
,
7253 TCGv_vec n
, int64_t shr
)
7255 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
7256 int halfbits
= 4 << vece
;
7258 tcg_gen_shri_vec(vece
, n
, n
, shr
);
7259 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(0, halfbits
));
7260 tcg_gen_umin_vec(vece
, d
, n
, t
);
7261 tcg_temp_free_vec(t
);
7264 static bool trans_UQSHRNB(DisasContext
*s
, arg_rri_esz
*a
)
7266 static const TCGOpcode vec_list
[] = {
7267 INDEX_op_shri_vec
, INDEX_op_umin_vec
, 0
7269 static const GVecGen2i ops
[3] = {
7270 { .fniv
= gen_uqshrnb_vec
,
7271 .opt_opc
= vec_list
,
7272 .fno
= gen_helper_sve2_uqshrnb_h
,
7274 { .fniv
= gen_uqshrnb_vec
,
7275 .opt_opc
= vec_list
,
7276 .fno
= gen_helper_sve2_uqshrnb_s
,
7278 { .fniv
= gen_uqshrnb_vec
,
7279 .opt_opc
= vec_list
,
7280 .fno
= gen_helper_sve2_uqshrnb_d
,
7283 return do_sve2_shr_narrow(s
, a
, ops
);
7286 static void gen_uqshrnt_vec(unsigned vece
, TCGv_vec d
,
7287 TCGv_vec n
, int64_t shr
)
7289 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
7290 int halfbits
= 4 << vece
;
7292 tcg_gen_shri_vec(vece
, n
, n
, shr
);
7293 tcg_gen_dupi_vec(vece
, t
, MAKE_64BIT_MASK(0, halfbits
));
7294 tcg_gen_umin_vec(vece
, n
, n
, t
);
7295 tcg_gen_shli_vec(vece
, n
, n
, halfbits
);
7296 tcg_gen_bitsel_vec(vece
, d
, t
, d
, n
);
7297 tcg_temp_free_vec(t
);
7300 static bool trans_UQSHRNT(DisasContext
*s
, arg_rri_esz
*a
)
7302 static const TCGOpcode vec_list
[] = {
7303 INDEX_op_shli_vec
, INDEX_op_shri_vec
, INDEX_op_umin_vec
, 0
7305 static const GVecGen2i ops
[3] = {
7306 { .fniv
= gen_uqshrnt_vec
,
7307 .opt_opc
= vec_list
,
7309 .fno
= gen_helper_sve2_uqshrnt_h
,
7311 { .fniv
= gen_uqshrnt_vec
,
7312 .opt_opc
= vec_list
,
7314 .fno
= gen_helper_sve2_uqshrnt_s
,
7316 { .fniv
= gen_uqshrnt_vec
,
7317 .opt_opc
= vec_list
,
7319 .fno
= gen_helper_sve2_uqshrnt_d
,
7322 return do_sve2_shr_narrow(s
, a
, ops
);
7325 static bool trans_UQRSHRNB(DisasContext
*s
, arg_rri_esz
*a
)
7327 static const GVecGen2i ops
[3] = {
7328 { .fno
= gen_helper_sve2_uqrshrnb_h
},
7329 { .fno
= gen_helper_sve2_uqrshrnb_s
},
7330 { .fno
= gen_helper_sve2_uqrshrnb_d
},
7332 return do_sve2_shr_narrow(s
, a
, ops
);
7335 static bool trans_UQRSHRNT(DisasContext
*s
, arg_rri_esz
*a
)
7337 static const GVecGen2i ops
[3] = {
7338 { .fno
= gen_helper_sve2_uqrshrnt_h
},
7339 { .fno
= gen_helper_sve2_uqrshrnt_s
},
7340 { .fno
= gen_helper_sve2_uqrshrnt_d
},
7342 return do_sve2_shr_narrow(s
, a
, ops
);
7345 #define DO_SVE2_ZZZ_NARROW(NAME, name) \
7346 static gen_helper_gvec_3 * const name##_fns[4] = { \
7347 NULL, gen_helper_sve2_##name##_h, \
7348 gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
7350 TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \
7351 name##_fns[a->esz], a, 0)
7353 DO_SVE2_ZZZ_NARROW(ADDHNB
, addhnb
)
7354 DO_SVE2_ZZZ_NARROW(ADDHNT
, addhnt
)
7355 DO_SVE2_ZZZ_NARROW(RADDHNB
, raddhnb
)
7356 DO_SVE2_ZZZ_NARROW(RADDHNT
, raddhnt
)
7358 DO_SVE2_ZZZ_NARROW(SUBHNB
, subhnb
)
7359 DO_SVE2_ZZZ_NARROW(SUBHNT
, subhnt
)
7360 DO_SVE2_ZZZ_NARROW(RSUBHNB
, rsubhnb
)
7361 DO_SVE2_ZZZ_NARROW(RSUBHNT
, rsubhnt
)
7363 static bool do_sve2_ppzz_flags(DisasContext
*s
, arg_rprr_esz
*a
,
7364 gen_helper_gvec_flags_4
*fn
)
7366 if (!dc_isar_feature(aa64_sve2
, s
)) {
7369 return do_ppzz_flags(s
, a
, fn
);
7372 #define DO_SVE2_PPZZ_MATCH(NAME, name) \
7373 static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
7375 static gen_helper_gvec_flags_4 * const fns[4] = { \
7376 gen_helper_sve2_##name##_ppzz_b, gen_helper_sve2_##name##_ppzz_h, \
7379 return do_sve2_ppzz_flags(s, a, fns[a->esz]); \
7382 DO_SVE2_PPZZ_MATCH(MATCH
, match
)
7383 DO_SVE2_PPZZ_MATCH(NMATCH
, nmatch
)
7385 static gen_helper_gvec_4
* const histcnt_fns
[4] = {
7386 NULL
, NULL
, gen_helper_sve2_histcnt_s
, gen_helper_sve2_histcnt_d
7388 TRANS_FEAT(HISTCNT
, aa64_sve2
, gen_gvec_ool_arg_zpzz
,
7389 histcnt_fns
[a
->esz
], a
, 0)
7391 TRANS_FEAT(HISTSEG
, aa64_sve2
, gen_gvec_ool_arg_zzz
,
7392 a
->esz
== 0 ? gen_helper_sve2_histseg
: NULL
, a
, 0)
7394 static bool do_sve2_zpzz_fp(DisasContext
*s
, arg_rprr_esz
*a
,
7395 gen_helper_gvec_4_ptr
*fn
)
7397 if (!dc_isar_feature(aa64_sve2
, s
)) {
7400 return do_zpzz_fp(s
, a
, fn
);
7403 #define DO_SVE2_ZPZZ_FP(NAME, name) \
7404 static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
7406 static gen_helper_gvec_4_ptr * const fns[4] = { \
7407 NULL, gen_helper_sve2_##name##_zpzz_h, \
7408 gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d \
7410 return do_sve2_zpzz_fp(s, a, fns[a->esz]); \
7413 DO_SVE2_ZPZZ_FP(FADDP
, faddp
)
7414 DO_SVE2_ZPZZ_FP(FMAXNMP
, fmaxnmp
)
7415 DO_SVE2_ZPZZ_FP(FMINNMP
, fminnmp
)
7416 DO_SVE2_ZPZZ_FP(FMAXP
, fmaxp
)
7417 DO_SVE2_ZPZZ_FP(FMINP
, fminp
)
7420 * SVE Integer Multiply-Add (unpredicated)
7423 static bool trans_FMMLA(DisasContext
*s
, arg_rrrr_esz
*a
)
7425 gen_helper_gvec_4_ptr
*fn
;
7429 if (!dc_isar_feature(aa64_sve_f32mm
, s
)) {
7432 fn
= gen_helper_fmmla_s
;
7435 if (!dc_isar_feature(aa64_sve_f64mm
, s
)) {
7438 fn
= gen_helper_fmmla_d
;
7444 if (sve_access_check(s
)) {
7445 unsigned vsz
= vec_full_reg_size(s
);
7446 TCGv_ptr status
= fpstatus_ptr(FPST_FPCR
);
7447 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
7448 vec_full_reg_offset(s
, a
->rn
),
7449 vec_full_reg_offset(s
, a
->rm
),
7450 vec_full_reg_offset(s
, a
->ra
),
7451 status
, vsz
, vsz
, 0, fn
);
7452 tcg_temp_free_ptr(status
);
7457 static gen_helper_gvec_4
* const sqdmlal_zzzw_fns
[] = {
7458 NULL
, gen_helper_sve2_sqdmlal_zzzw_h
,
7459 gen_helper_sve2_sqdmlal_zzzw_s
, gen_helper_sve2_sqdmlal_zzzw_d
,
7461 TRANS_FEAT(SQDMLALB_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7462 sqdmlal_zzzw_fns
[a
->esz
], a
, 0)
7463 TRANS_FEAT(SQDMLALT_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7464 sqdmlal_zzzw_fns
[a
->esz
], a
, 3)
7465 TRANS_FEAT(SQDMLALBT
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7466 sqdmlal_zzzw_fns
[a
->esz
], a
, 2)
7468 static gen_helper_gvec_4
* const sqdmlsl_zzzw_fns
[] = {
7469 NULL
, gen_helper_sve2_sqdmlsl_zzzw_h
,
7470 gen_helper_sve2_sqdmlsl_zzzw_s
, gen_helper_sve2_sqdmlsl_zzzw_d
,
7472 TRANS_FEAT(SQDMLSLB_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7473 sqdmlsl_zzzw_fns
[a
->esz
], a
, 0)
7474 TRANS_FEAT(SQDMLSLT_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7475 sqdmlsl_zzzw_fns
[a
->esz
], a
, 3)
7476 TRANS_FEAT(SQDMLSLBT
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7477 sqdmlsl_zzzw_fns
[a
->esz
], a
, 2)
7479 static gen_helper_gvec_4
* const sqrdmlah_fns
[] = {
7480 gen_helper_sve2_sqrdmlah_b
, gen_helper_sve2_sqrdmlah_h
,
7481 gen_helper_sve2_sqrdmlah_s
, gen_helper_sve2_sqrdmlah_d
,
7483 TRANS_FEAT(SQRDMLAH_zzzz
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7484 sqrdmlah_fns
[a
->esz
], a
, 0)
7486 static gen_helper_gvec_4
* const sqrdmlsh_fns
[] = {
7487 gen_helper_sve2_sqrdmlsh_b
, gen_helper_sve2_sqrdmlsh_h
,
7488 gen_helper_sve2_sqrdmlsh_s
, gen_helper_sve2_sqrdmlsh_d
,
7490 TRANS_FEAT(SQRDMLSH_zzzz
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7491 sqrdmlsh_fns
[a
->esz
], a
, 0)
7493 static gen_helper_gvec_4
* const smlal_zzzw_fns
[] = {
7494 NULL
, gen_helper_sve2_smlal_zzzw_h
,
7495 gen_helper_sve2_smlal_zzzw_s
, gen_helper_sve2_smlal_zzzw_d
,
7497 TRANS_FEAT(SMLALB_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7498 smlal_zzzw_fns
[a
->esz
], a
, 0)
7499 TRANS_FEAT(SMLALT_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7500 smlal_zzzw_fns
[a
->esz
], a
, 1)
7502 static gen_helper_gvec_4
* const umlal_zzzw_fns
[] = {
7503 NULL
, gen_helper_sve2_umlal_zzzw_h
,
7504 gen_helper_sve2_umlal_zzzw_s
, gen_helper_sve2_umlal_zzzw_d
,
7506 TRANS_FEAT(UMLALB_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7507 umlal_zzzw_fns
[a
->esz
], a
, 0)
7508 TRANS_FEAT(UMLALT_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7509 umlal_zzzw_fns
[a
->esz
], a
, 1)
7511 static gen_helper_gvec_4
* const smlsl_zzzw_fns
[] = {
7512 NULL
, gen_helper_sve2_smlsl_zzzw_h
,
7513 gen_helper_sve2_smlsl_zzzw_s
, gen_helper_sve2_smlsl_zzzw_d
,
7515 TRANS_FEAT(SMLSLB_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7516 smlsl_zzzw_fns
[a
->esz
], a
, 0)
7517 TRANS_FEAT(SMLSLT_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7518 smlsl_zzzw_fns
[a
->esz
], a
, 1)
7520 static gen_helper_gvec_4
* const umlsl_zzzw_fns
[] = {
7521 NULL
, gen_helper_sve2_umlsl_zzzw_h
,
7522 gen_helper_sve2_umlsl_zzzw_s
, gen_helper_sve2_umlsl_zzzw_d
,
7524 TRANS_FEAT(UMLSLB_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7525 umlsl_zzzw_fns
[a
->esz
], a
, 0)
7526 TRANS_FEAT(UMLSLT_zzzw
, aa64_sve2
, gen_gvec_ool_arg_zzzz
,
7527 umlsl_zzzw_fns
[a
->esz
], a
, 1)
7529 static gen_helper_gvec_4
* const cmla_fns
[] = {
7530 gen_helper_sve2_cmla_zzzz_b
, gen_helper_sve2_cmla_zzzz_h
,
7531 gen_helper_sve2_cmla_zzzz_s
, gen_helper_sve2_cmla_zzzz_d
,
7533 TRANS_FEAT(CMLA_zzzz
, aa64_sve2
, gen_gvec_ool_zzzz
,
7534 cmla_fns
[a
->esz
], a
->rd
, a
->rn
, a
->rm
, a
->ra
, a
->rot
)
7536 static gen_helper_gvec_4
* const cdot_fns
[] = {
7537 NULL
, NULL
, gen_helper_sve2_cdot_zzzz_s
, gen_helper_sve2_cdot_zzzz_d
7539 TRANS_FEAT(CDOT_zzzz
, aa64_sve2
, gen_gvec_ool_zzzz
,
7540 cdot_fns
[a
->esz
], a
->rd
, a
->rn
, a
->rm
, a
->ra
, a
->rot
)
7542 static gen_helper_gvec_4
* const sqrdcmlah_fns
[] = {
7543 gen_helper_sve2_sqrdcmlah_zzzz_b
, gen_helper_sve2_sqrdcmlah_zzzz_h
,
7544 gen_helper_sve2_sqrdcmlah_zzzz_s
, gen_helper_sve2_sqrdcmlah_zzzz_d
,
7546 TRANS_FEAT(SQRDCMLAH_zzzz
, aa64_sve2
, gen_gvec_ool_zzzz
,
7547 sqrdcmlah_fns
[a
->esz
], a
->rd
, a
->rn
, a
->rm
, a
->ra
, a
->rot
)
7549 TRANS_FEAT(USDOT_zzzz
, aa64_sve_i8mm
, gen_gvec_ool_arg_zzzz
,
7550 a
->esz
== 2 ? gen_helper_gvec_usdot_b
: NULL
, a
, 0)
7552 TRANS_FEAT(AESMC
, aa64_sve2_aes
, gen_gvec_ool_zz
,
7553 gen_helper_crypto_aesmc
, a
->rd
, a
->rd
, a
->decrypt
)
7555 TRANS_FEAT(AESE
, aa64_sve2_aes
, gen_gvec_ool_arg_zzz
,
7556 gen_helper_crypto_aese
, a
, false)
7557 TRANS_FEAT(AESD
, aa64_sve2_aes
, gen_gvec_ool_arg_zzz
,
7558 gen_helper_crypto_aese
, a
, true)
7560 TRANS_FEAT(SM4E
, aa64_sve2_sm4
, gen_gvec_ool_arg_zzz
,
7561 gen_helper_crypto_sm4e
, a
, 0)
7562 TRANS_FEAT(SM4EKEY
, aa64_sve2_sm4
, gen_gvec_ool_arg_zzz
,
7563 gen_helper_crypto_sm4ekey
, a
, 0)
7565 TRANS_FEAT(RAX1
, aa64_sve2_sha3
, gen_gvec_fn_arg_zzz
, gen_gvec_rax1
, a
)
7567 static bool trans_FCVTNT_sh(DisasContext
*s
, arg_rpr_esz
*a
)
7569 if (!dc_isar_feature(aa64_sve2
, s
)) {
7572 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve2_fcvtnt_sh
);
7575 static bool trans_BFCVTNT(DisasContext
*s
, arg_rpr_esz
*a
)
7577 if (!dc_isar_feature(aa64_sve_bf16
, s
)) {
7580 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve_bfcvtnt
);
7583 static bool trans_FCVTNT_ds(DisasContext
*s
, arg_rpr_esz
*a
)
7585 if (!dc_isar_feature(aa64_sve2
, s
)) {
7588 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve2_fcvtnt_ds
);
7591 static bool trans_FCVTLT_hs(DisasContext
*s
, arg_rpr_esz
*a
)
7593 if (!dc_isar_feature(aa64_sve2
, s
)) {
7596 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve2_fcvtlt_hs
);
7599 static bool trans_FCVTLT_sd(DisasContext
*s
, arg_rpr_esz
*a
)
7601 if (!dc_isar_feature(aa64_sve2
, s
)) {
7604 return do_zpz_ptr(s
, a
->rd
, a
->rn
, a
->pg
, false, gen_helper_sve2_fcvtlt_sd
);
7607 static bool trans_FCVTX_ds(DisasContext
*s
, arg_rpr_esz
*a
)
7609 if (!dc_isar_feature(aa64_sve2
, s
)) {
7612 return do_frint_mode(s
, a
, float_round_to_odd
, gen_helper_sve_fcvt_ds
);
7615 static bool trans_FCVTXNT_ds(DisasContext
*s
, arg_rpr_esz
*a
)
7617 if (!dc_isar_feature(aa64_sve2
, s
)) {
7620 return do_frint_mode(s
, a
, float_round_to_odd
, gen_helper_sve2_fcvtnt_ds
);
7623 static bool trans_FLOGB(DisasContext
*s
, arg_rpr_esz
*a
)
7625 static gen_helper_gvec_3_ptr
* const fns
[] = {
7626 NULL
, gen_helper_flogb_h
,
7627 gen_helper_flogb_s
, gen_helper_flogb_d
7630 if (!dc_isar_feature(aa64_sve2
, s
) || fns
[a
->esz
] == NULL
) {
7633 if (sve_access_check(s
)) {
7635 fpstatus_ptr(a
->esz
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7636 unsigned vsz
= vec_full_reg_size(s
);
7638 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, a
->rd
),
7639 vec_full_reg_offset(s
, a
->rn
),
7640 pred_full_reg_offset(s
, a
->pg
),
7641 status
, vsz
, vsz
, 0, fns
[a
->esz
]);
7642 tcg_temp_free_ptr(status
);
7647 static bool do_FMLAL_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
, bool sub
, bool sel
)
7649 if (!dc_isar_feature(aa64_sve2
, s
)) {
7652 if (sve_access_check(s
)) {
7653 unsigned vsz
= vec_full_reg_size(s
);
7654 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
7655 vec_full_reg_offset(s
, a
->rn
),
7656 vec_full_reg_offset(s
, a
->rm
),
7657 vec_full_reg_offset(s
, a
->ra
),
7658 cpu_env
, vsz
, vsz
, (sel
<< 1) | sub
,
7659 gen_helper_sve2_fmlal_zzzw_s
);
7664 static bool trans_FMLALB_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
)
7666 return do_FMLAL_zzzw(s
, a
, false, false);
7669 static bool trans_FMLALT_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
)
7671 return do_FMLAL_zzzw(s
, a
, false, true);
7674 static bool trans_FMLSLB_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
)
7676 return do_FMLAL_zzzw(s
, a
, true, false);
7679 static bool trans_FMLSLT_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
)
7681 return do_FMLAL_zzzw(s
, a
, true, true);
7684 static bool do_FMLAL_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
, bool sub
, bool sel
)
7686 if (!dc_isar_feature(aa64_sve2
, s
)) {
7689 if (sve_access_check(s
)) {
7690 unsigned vsz
= vec_full_reg_size(s
);
7691 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
7692 vec_full_reg_offset(s
, a
->rn
),
7693 vec_full_reg_offset(s
, a
->rm
),
7694 vec_full_reg_offset(s
, a
->ra
),
7696 (a
->index
<< 2) | (sel
<< 1) | sub
,
7697 gen_helper_sve2_fmlal_zzxw_s
);
7702 static bool trans_FMLALB_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
)
7704 return do_FMLAL_zzxw(s
, a
, false, false);
7707 static bool trans_FMLALT_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
)
7709 return do_FMLAL_zzxw(s
, a
, false, true);
7712 static bool trans_FMLSLB_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
)
7714 return do_FMLAL_zzxw(s
, a
, true, false);
7717 static bool trans_FMLSLT_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
)
7719 return do_FMLAL_zzxw(s
, a
, true, true);
7722 TRANS_FEAT(SMMLA
, aa64_sve_i8mm
, gen_gvec_ool_arg_zzzz
,
7723 gen_helper_gvec_smmla_b
, a
, 0)
7724 TRANS_FEAT(USMMLA
, aa64_sve_i8mm
, gen_gvec_ool_arg_zzzz
,
7725 gen_helper_gvec_usmmla_b
, a
, 0)
7726 TRANS_FEAT(UMMLA
, aa64_sve_i8mm
, gen_gvec_ool_arg_zzzz
,
7727 gen_helper_gvec_ummla_b
, a
, 0)
7729 TRANS_FEAT(BFDOT_zzzz
, aa64_sve_bf16
, gen_gvec_ool_arg_zzzz
,
7730 gen_helper_gvec_bfdot
, a
, 0)
7731 TRANS_FEAT(BFDOT_zzxz
, aa64_sve_bf16
, gen_gvec_ool_arg_zzxz
,
7732 gen_helper_gvec_bfdot_idx
, a
)
7734 TRANS_FEAT(BFMMLA
, aa64_sve_bf16
, gen_gvec_ool_arg_zzzz
,
7735 gen_helper_gvec_bfmmla
, a
, 0)
7737 static bool do_BFMLAL_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
, bool sel
)
7739 if (!dc_isar_feature(aa64_sve_bf16
, s
)) {
7742 if (sve_access_check(s
)) {
7743 TCGv_ptr status
= fpstatus_ptr(FPST_FPCR
);
7744 unsigned vsz
= vec_full_reg_size(s
);
7746 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
7747 vec_full_reg_offset(s
, a
->rn
),
7748 vec_full_reg_offset(s
, a
->rm
),
7749 vec_full_reg_offset(s
, a
->ra
),
7750 status
, vsz
, vsz
, sel
,
7751 gen_helper_gvec_bfmlal
);
7752 tcg_temp_free_ptr(status
);
7757 static bool trans_BFMLALB_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
)
7759 return do_BFMLAL_zzzw(s
, a
, false);
7762 static bool trans_BFMLALT_zzzw(DisasContext
*s
, arg_rrrr_esz
*a
)
7764 return do_BFMLAL_zzzw(s
, a
, true);
7767 static bool do_BFMLAL_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
, bool sel
)
7769 if (!dc_isar_feature(aa64_sve_bf16
, s
)) {
7772 if (sve_access_check(s
)) {
7773 TCGv_ptr status
= fpstatus_ptr(FPST_FPCR
);
7774 unsigned vsz
= vec_full_reg_size(s
);
7776 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, a
->rd
),
7777 vec_full_reg_offset(s
, a
->rn
),
7778 vec_full_reg_offset(s
, a
->rm
),
7779 vec_full_reg_offset(s
, a
->ra
),
7780 status
, vsz
, vsz
, (a
->index
<< 1) | sel
,
7781 gen_helper_gvec_bfmlal_idx
);
7782 tcg_temp_free_ptr(status
);
7787 static bool trans_BFMLALB_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
)
7789 return do_BFMLAL_zzxw(s
, a
, false);
7792 static bool trans_BFMLALT_zzxw(DisasContext
*s
, arg_rrxr_esz
*a
)
7794 return do_BFMLAL_zzxw(s
, a
, true);