hw/ppc/rs6000_mc.c

   1 /*
   2  * QEMU RS/6000 memory controller
   3  *
   4  * Copyright (c) 2017 Hervé Poussineau
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) version 3 or any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22 #include "hw/isa/isa.h"
  23 #include "migration/vmstate.h"
  24 #include "exec/address-spaces.h"
  25 #include "hw/boards.h"
  26 #include "qapi/error.h"
  27 #include "trace.h"
  28
  29 #define TYPE_RS6000MC "rs6000-mc"
  30 #define RS6000MC_DEVICE(obj) \
  31     OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC)
  32
  33 typedef struct RS6000MCState {
  34     ISADevice parent_obj;
  35     /* see US patent 5,684,979 for details (expired 2001-11-04) */
  36     uint32_t ram_size;
  37     bool autoconfigure;
  38     MemoryRegion simm[6];
  39     unsigned int simm_size[6];
  40     uint32_t end_address[8];
  41     uint8_t port0820_index;
  42     PortioList portio;
  43 } RS6000MCState;
  44
  45 /* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */
  46
  47 static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr)
  48 {
  49     RS6000MCState *s = opaque;
  50     uint32_t val = 0;
  51     int socket;
  52
  53     /* (1 << socket) indicates 32 MB SIMM at given socket */
  54     for (socket = 0; socket < 6; socket++) {
  55         if (s->simm_size[socket] == 32) {
  56             val |= (1 << socket);
  57         }
  58     }
  59
  60     trace_rs6000mc_id_read(addr, val);
  61     return val;
  62 }
  63
  64 /* PORT 0804 -- SIMM Presence Register (Read Only) */
  65
  66 static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr)
  67 {
  68     RS6000MCState *s = opaque;
  69     uint32_t val = 0xff;
  70     int socket;
  71
  72     /* (1 << socket) indicates SIMM absence at given socket */
  73     for (socket = 0; socket < 6; socket++) {
  74         if (s->simm_size[socket]) {
  75             val &= ~(1 << socket);
  76         }
  77     }
  78     s->port0820_index = 0;
  79
  80     trace_rs6000mc_presence_read(addr, val);
  81     return val;
  82 }
  83
  84 /* Memory Controller Size Programming Register */
  85
  86 static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr)
  87 {
  88     RS6000MCState *s = opaque;
  89     uint32_t val = s->end_address[s->port0820_index] & 0x1f;
  90     s->port0820_index = (s->port0820_index + 1) & 7;
  91     trace_rs6000mc_size_read(addr, val);
  92     return val;
  93 }
  94
  95 static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val)
  96 {
  97     RS6000MCState *s = opaque;
  98     uint8_t socket = val >> 5;
  99     uint32_t end_address = val & 0x1f;
 100
 101     trace_rs6000mc_size_write(addr, val);
 102     s->end_address[socket] = end_address;
 103     if (socket > 0 && socket < 7) {
 104         if (s->simm_size[socket - 1]) {
 105             uint32_t size;
 106             uint32_t start_address = 0;
 107             if (socket > 1) {
 108                 start_address = s->end_address[socket - 1];
 109             }
 110
 111             size = end_address - start_address;
 112             memory_region_set_enabled(&s->simm[socket - 1], size != 0);
 113             memory_region_set_address(&s->simm[socket - 1],
 114                                       start_address * 8 * MiB);
 115         }
 116     }
 117 }
 118
 119 /* Read Memory Parity Error */
 120
 121 enum {
 122     PORT0841_NO_ERROR_DETECTED = 0x01,
 123 };
 124
 125 static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr)
 126 {
 127     uint32_t val = PORT0841_NO_ERROR_DETECTED;
 128     trace_rs6000mc_parity_read(addr, val);
 129     return val;
 130 }
 131
 132 static const MemoryRegionPortio rs6000mc_port_list[] = {
 133     { 0x803, 1, 1, .read = rs6000mc_port0803_read },
 134     { 0x804, 1, 1, .read = rs6000mc_port0804_read },
 135     { 0x820, 1, 1, .read = rs6000mc_port0820_read,
 136                    .write = rs6000mc_port0820_write, },
 137     { 0x841, 1, 1, .read = rs6000mc_port0841_read },
 138     PORTIO_END_OF_LIST()
 139 };
 140
 141 static void rs6000mc_realize(DeviceState *dev, Error **errp)
 142 {
 143     RS6000MCState *s = RS6000MC_DEVICE(dev);
 144     int socket = 0;
 145     unsigned int ram_size = s->ram_size / MiB;
 146
 147     while (socket < 6) {
 148         if (ram_size >= 64) {
 149             s->simm_size[socket] = 32;
 150             s->simm_size[socket + 1] = 32;
 151             ram_size -= 64;
 152         } else if (ram_size >= 16) {
 153             s->simm_size[socket] = 8;
 154             s->simm_size[socket + 1] = 8;
 155             ram_size -= 16;
 156         } else {
 157             /* Not enough memory */
 158             break;
 159         }
 160         socket += 2;
 161     }
 162
 163     for (socket = 0; socket < 6; socket++) {
 164         if (s->simm_size[socket]) {
 165             char name[] = "simm.?";
 166             name[5] = socket + '0';
 167             memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
 168                                                  name,
 169                                                  s->simm_size[socket] * MiB);
 170             memory_region_add_subregion_overlap(get_system_memory(), 0,
 171                                                 &s->simm[socket], socket);
 172         }
 173     }
 174     if (ram_size) {
 175         /* unable to push all requested RAM in SIMMs */
 176         error_setg(errp, "RAM size incompatible with this board. "
 177                    "Try again with something else, like %" PRId64 " MB",
 178                    s->ram_size / MiB - ram_size);
 179         return;
 180     }
 181
 182     if (s->autoconfigure) {
 183         uint32_t start_address = 0;
 184         for (socket = 0; socket < 6; socket++) {
 185             if (s->simm_size[socket]) {
 186                 memory_region_set_enabled(&s->simm[socket], true);
 187                 memory_region_set_address(&s->simm[socket], start_address);
 188                 start_address += memory_region_size(&s->simm[socket]);
 189             }
 190         }
 191     }
 192
 193     isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0,
 194                              rs6000mc_port_list, s, "rs6000mc");
 195 }
 196
 197 static const VMStateDescription vmstate_rs6000mc = {
 198     .name = "rs6000-mc",
 199     .version_id = 1,
 200     .minimum_version_id = 1,
 201     .fields = (VMStateField[]) {
 202         VMSTATE_UINT8(port0820_index, RS6000MCState),
 203         VMSTATE_END_OF_LIST()
 204     },
 205 };
 206
 207 static Property rs6000mc_properties[] = {
 208     DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0),
 209     DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true),
 210     DEFINE_PROP_END_OF_LIST()
 211 };
 212
 213 static void rs6000mc_class_initfn(ObjectClass *klass, void *data)
 214 {
 215     DeviceClass *dc = DEVICE_CLASS(klass);
 216
 217     dc->realize = rs6000mc_realize;
 218     dc->vmsd = &vmstate_rs6000mc;
 219     dc->props = rs6000mc_properties;
 220 }
 221
 222 static const TypeInfo rs6000mc_info = {
 223     .name          = TYPE_RS6000MC,
 224     .parent        = TYPE_ISA_DEVICE,
 225     .instance_size = sizeof(RS6000MCState),
 226     .class_init    = rs6000mc_class_initfn,
 227 };
 228
 229 static void rs6000mc_types(void)
 230 {
 231     type_register_static(&rs6000mc_info);
 232 }
 233
 234 type_init(rs6000mc_types)