hw/ppc/prep_systemio.c

   1 /*
   2  * QEMU PReP System I/O emulation
   3  *
   4  * Copyright (c) 2017 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/irq.h"
  27 #include "hw/isa/isa.h"
  28 #include "migration/vmstate.h"
  29 #include "exec/address-spaces.h"
  30 #include "qemu/error-report.h" /* for error_report() */
  31 #include "qemu/module.h"
  32 #include "sysemu/sysemu.h" /* for vm_stop() */
  33 #include "cpu.h"
  34 #include "trace.h"
  35
  36 #define TYPE_PREP_SYSTEMIO "prep-systemio"
  37 #define PREP_SYSTEMIO(obj) \
  38     OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
  39
  40 /* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
  41 #define PREP_BIT(n) (1 << (7 - (n)))
  42
  43 typedef struct PrepSystemIoState {
  44     ISADevice parent_obj;
  45     MemoryRegion ppc_parity_mem;
  46
  47     qemu_irq non_contiguous_io_map_irq;
  48     uint8_t sreset; /* 0x0092 */
  49     uint8_t equipment; /* 0x080c */
  50     uint8_t system_control; /* 0x081c */
  51     uint8_t iomap_type; /* 0x0850 */
  52     uint8_t ibm_planar_id; /* 0x0852 */
  53     qemu_irq softreset_irq;
  54     PortioList portio;
  55 } PrepSystemIoState;
  56
  57 /* PORT 0092 -- Special Port 92 (Read/Write) */
  58
  59 enum {
  60     PORT0092_SOFTRESET  = PREP_BIT(7),
  61     PORT0092_LE_MODE    = PREP_BIT(6),
  62 };
  63
  64 static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val)
  65 {
  66     PrepSystemIoState *s = opaque;
  67
  68     trace_prep_systemio_write(addr, val);
  69
  70     s->sreset = val & PORT0092_SOFTRESET;
  71     qemu_set_irq(s->softreset_irq, s->sreset);
  72
  73     if ((val & PORT0092_LE_MODE) != 0) {
  74         /* XXX Not supported yet */
  75         error_report("little-endian mode not supported");
  76         vm_stop(RUN_STATE_PAUSED);
  77     } else {
  78         /* Nothing to do */
  79     }
  80 }
  81
  82 static uint32_t prep_port0092_read(void *opaque, uint32_t addr)
  83 {
  84     PrepSystemIoState *s = opaque;
  85     trace_prep_systemio_read(addr, s->sreset);
  86     return s->sreset;
  87 }
  88
  89 /* PORT 0808 -- Hardfile Light Register (Write Only) */
  90
  91 enum {
  92     PORT0808_HARDFILE_LIGHT_ON  = PREP_BIT(7),
  93 };
  94
  95 static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val)
  96 {
  97     trace_prep_systemio_write(addr, val);
  98 }
  99
 100 /* PORT 0810 -- Password Protect 1 Register (Write Only) */
 101
 102 /* reset by port 0x4D in the SIO */
 103 static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val)
 104 {
 105     trace_prep_systemio_write(addr, val);
 106 }
 107
 108 /* PORT 0812 -- Password Protect 2 Register (Write Only) */
 109
 110 /* reset by port 0x4D in the SIO */
 111 static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val)
 112 {
 113     trace_prep_systemio_write(addr, val);
 114 }
 115
 116 /* PORT 0814 -- L2 Invalidate Register (Write Only) */
 117
 118 static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val)
 119 {
 120     trace_prep_systemio_write(addr, val);
 121 }
 122
 123 /* PORT 0818 -- Reserved for Keylock (Read Only) */
 124
 125 enum {
 126     PORT0818_KEYLOCK_SIGNAL_HIGH    = PREP_BIT(7),
 127 };
 128
 129 static uint32_t prep_port0818_read(void *opaque, uint32_t addr)
 130 {
 131     uint32_t val = 0;
 132     trace_prep_systemio_read(addr, val);
 133     return val;
 134 }
 135
 136 /* PORT 080C -- Equipment */
 137
 138 enum {
 139     PORT080C_SCSIFUSE               = PREP_BIT(1),
 140     PORT080C_L2_COPYBACK            = PREP_BIT(4),
 141     PORT080C_L2_256                 = PREP_BIT(5),
 142     PORT080C_UPGRADE_CPU            = PREP_BIT(6),
 143     PORT080C_L2                     = PREP_BIT(7),
 144 };
 145
 146 static uint32_t prep_port080c_read(void *opaque, uint32_t addr)
 147 {
 148     PrepSystemIoState *s = opaque;
 149     trace_prep_systemio_read(addr, s->equipment);
 150     return s->equipment;
 151 }
 152
 153 /* PORT 081C -- System Control Register (Read/Write) */
 154
 155 enum {
 156     PORT081C_FLOPPY_MOTOR_INHIBIT   = PREP_BIT(3),
 157     PORT081C_MASK_TEA               = PREP_BIT(2),
 158     PORT081C_L2_UPDATE_INHIBIT      = PREP_BIT(1),
 159     PORT081C_L2_CACHEMISS_INHIBIT   = PREP_BIT(0),
 160 };
 161
 162 static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val)
 163 {
 164     static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT |
 165                                 PORT081C_MASK_TEA |
 166                                 PORT081C_L2_UPDATE_INHIBIT |
 167                                 PORT081C_L2_CACHEMISS_INHIBIT;
 168     PrepSystemIoState *s = opaque;
 169     trace_prep_systemio_write(addr, val);
 170     s->system_control = val & mask;
 171 }
 172
 173 static uint32_t prep_port081c_read(void *opaque, uint32_t addr)
 174 {
 175     PrepSystemIoState *s = opaque;
 176     trace_prep_systemio_read(addr, s->system_control);
 177     return s->system_control;
 178 }
 179
 180 /* System Board Identification */
 181
 182 static uint32_t prep_port0852_read(void *opaque, uint32_t addr)
 183 {
 184     PrepSystemIoState *s = opaque;
 185     trace_prep_systemio_read(addr, s->ibm_planar_id);
 186     return s->ibm_planar_id;
 187 }
 188
 189 /* PORT 0850 -- I/O Map Type Register (Read/Write) */
 190
 191 enum {
 192     PORT0850_IOMAP_NONCONTIGUOUS    = PREP_BIT(7),
 193 };
 194
 195 static uint32_t prep_port0850_read(void *opaque, uint32_t addr)
 196 {
 197     PrepSystemIoState *s = opaque;
 198     trace_prep_systemio_read(addr, s->iomap_type);
 199     return s->iomap_type;
 200 }
 201
 202 static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val)
 203 {
 204     PrepSystemIoState *s = opaque;
 205
 206     trace_prep_systemio_write(addr, val);
 207     qemu_set_irq(s->non_contiguous_io_map_irq,
 208                  val & PORT0850_IOMAP_NONCONTIGUOUS);
 209     s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS;
 210 }
 211
 212 static const MemoryRegionPortio ppc_io800_port_list[] = {
 213     { 0x092, 1, 1, .read = prep_port0092_read,
 214                    .write = prep_port0092_write, },
 215     { 0x808, 1, 1, .write = prep_port0808_write, },
 216     { 0x80c, 1, 1, .read = prep_port080c_read, },
 217     { 0x810, 1, 1, .write = prep_port0810_write, },
 218     { 0x812, 1, 1, .write = prep_port0812_write, },
 219     { 0x814, 1, 1, .write = prep_port0814_write, },
 220     { 0x818, 1, 1, .read = prep_port0818_read },
 221     { 0x81c, 1, 1, .read = prep_port081c_read,
 222                    .write = prep_port081c_write, },
 223     { 0x850, 1, 1, .read = prep_port0850_read,
 224                    .write = prep_port0850_write, },
 225     { 0x852, 1, 1, .read = prep_port0852_read, },
 226     PORTIO_END_OF_LIST()
 227 };
 228
 229 static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr,
 230                                        unsigned int size)
 231 {
 232     uint32_t val = 0;
 233     trace_prep_systemio_read((unsigned int)addr, val);
 234     return val;
 235 }
 236
 237 static const MemoryRegionOps ppc_parity_error_ops = {
 238     .read = ppc_parity_error_readl,
 239     .valid = {
 240         .min_access_size = 4,
 241         .max_access_size = 4,
 242     },
 243 };
 244
 245 static void prep_systemio_realize(DeviceState *dev, Error **errp)
 246 {
 247     ISADevice *isa = ISA_DEVICE(dev);
 248     PrepSystemIoState *s = PREP_SYSTEMIO(dev);
 249     PowerPCCPU *cpu;
 250
 251     qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1);
 252     s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS;
 253     qemu_set_irq(s->non_contiguous_io_map_irq,
 254                  s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
 255     cpu = POWERPC_CPU(first_cpu);
 256     s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
 257
 258     isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
 259                              "systemio800");
 260
 261     memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev),
 262                           &ppc_parity_error_ops, s, "ppc-parity", 0x4);
 263     memory_region_add_subregion(get_system_memory(), 0xbfffeff0,
 264                                 &s->ppc_parity_mem);
 265 }
 266
 267 static const VMStateDescription vmstate_prep_systemio = {
 268     .name = "prep_systemio",
 269     .version_id = 1,
 270     .minimum_version_id = 1,
 271     .fields = (VMStateField[]) {
 272         VMSTATE_UINT8(sreset, PrepSystemIoState),
 273         VMSTATE_UINT8(system_control, PrepSystemIoState),
 274         VMSTATE_UINT8(iomap_type, PrepSystemIoState),
 275         VMSTATE_END_OF_LIST()
 276     },
 277 };
 278
 279 static Property prep_systemio_properties[] = {
 280     DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0),
 281     DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0),
 282     DEFINE_PROP_END_OF_LIST()
 283 };
 284
 285 static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
 286 {
 287     DeviceClass *dc = DEVICE_CLASS(klass);
 288
 289     dc->realize = prep_systemio_realize;
 290     dc->vmsd = &vmstate_prep_systemio;
 291     dc->props = prep_systemio_properties;
 292 }
 293
 294 static TypeInfo prep_systemio800_info = {
 295     .name          = TYPE_PREP_SYSTEMIO,
 296     .parent        = TYPE_ISA_DEVICE,
 297     .instance_size = sizeof(PrepSystemIoState),
 298     .class_init    = prep_systemio_class_initfn,
 299 };
 300
 301 static void prep_systemio_register_types(void)
 302 {
 303     type_register_static(&prep_systemio800_info);
 304 }
 305
 306 type_init(prep_systemio_register_types)