2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "qemu/timer.h"
25 #include "qemu/queue.h"
26 #include "monitor/monitor.h"
27 #include "sysemu/sysemu.h"
33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
34 * such can be changed by the guest, so to avoid a guest trigerrable
35 * abort we just qxl_set_guest_bug and set the return to NULL. Still
36 * it may happen as a result of emulator bug as well.
38 #undef SPICE_RING_PROD_ITEM
39 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
41 if (prod >= ARRAY_SIZE((r)->items)) { \
42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
46 ret = &(r)->items[prod].el; \
50 #undef SPICE_RING_CONS_ITEM
51 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
53 if (cons >= ARRAY_SIZE((r)->items)) { \
54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
58 ret = &(r)->items[cons].el; \
63 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
65 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
67 #define QXL_MODE(_x, _y, _b, _o) \
71 .stride = (_x) * (_b) / 8, \
72 .x_mili = PIXEL_SIZE * (_x), \
73 .y_mili = PIXEL_SIZE * (_y), \
77 #define QXL_MODE_16_32(x_res, y_res, orientation) \
78 QXL_MODE(x_res, y_res, 16, orientation), \
79 QXL_MODE(x_res, y_res, 32, orientation)
81 #define QXL_MODE_EX(x_res, y_res) \
82 QXL_MODE_16_32(x_res, y_res, 0), \
83 QXL_MODE_16_32(x_res, y_res, 1)
85 static QXLMode qxl_modes
[] = {
86 QXL_MODE_EX(640, 480),
87 QXL_MODE_EX(800, 480),
88 QXL_MODE_EX(800, 600),
89 QXL_MODE_EX(832, 624),
90 QXL_MODE_EX(960, 640),
91 QXL_MODE_EX(1024, 600),
92 QXL_MODE_EX(1024, 768),
93 QXL_MODE_EX(1152, 864),
94 QXL_MODE_EX(1152, 870),
95 QXL_MODE_EX(1280, 720),
96 QXL_MODE_EX(1280, 760),
97 QXL_MODE_EX(1280, 768),
98 QXL_MODE_EX(1280, 800),
99 QXL_MODE_EX(1280, 960),
100 QXL_MODE_EX(1280, 1024),
101 QXL_MODE_EX(1360, 768),
102 QXL_MODE_EX(1366, 768),
103 QXL_MODE_EX(1400, 1050),
104 QXL_MODE_EX(1440, 900),
105 QXL_MODE_EX(1600, 900),
106 QXL_MODE_EX(1600, 1200),
107 QXL_MODE_EX(1680, 1050),
108 QXL_MODE_EX(1920, 1080),
109 /* these modes need more than 8 MB video memory */
110 QXL_MODE_EX(1920, 1200),
111 QXL_MODE_EX(1920, 1440),
112 QXL_MODE_EX(2000, 2000),
113 QXL_MODE_EX(2048, 1536),
114 QXL_MODE_EX(2048, 2048),
115 QXL_MODE_EX(2560, 1440),
116 QXL_MODE_EX(2560, 1600),
117 /* these modes need more than 16 MB video memory */
118 QXL_MODE_EX(2560, 2048),
119 QXL_MODE_EX(2800, 2100),
120 QXL_MODE_EX(3200, 2400),
121 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
122 QXL_MODE_EX(4096, 2160), /* 4k */
123 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
124 QXL_MODE_EX(8192, 4320), /* 8k */
127 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
128 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
129 static void qxl_reset_memslots(PCIQXLDevice
*d
);
130 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
131 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
133 void qxl_set_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
135 trace_qxl_set_guest_bug(qxl
->id
);
136 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
138 if (qxl
->guestdebug
) {
141 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
142 vfprintf(stderr
, msg
, ap
);
143 fprintf(stderr
, "\n");
148 static void qxl_clear_guest_bug(PCIQXLDevice
*qxl
)
153 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
154 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
155 uint32_t num_dirty_rects
,
156 uint32_t clear_dirty_region
,
157 qxl_async_io async
, struct QXLCookie
*cookie
)
159 trace_qxl_spice_update_area(qxl
->id
, surface_id
, area
->left
, area
->right
,
160 area
->top
, area
->bottom
);
161 trace_qxl_spice_update_area_rest(qxl
->id
, num_dirty_rects
,
163 if (async
== QXL_SYNC
) {
164 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
165 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
167 assert(cookie
!= NULL
);
168 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
169 clear_dirty_region
, (uintptr_t)cookie
);
173 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
176 trace_qxl_spice_destroy_surface_wait_complete(qxl
->id
, id
);
177 qemu_mutex_lock(&qxl
->track_lock
);
178 qxl
->guest_surfaces
.cmds
[id
] = 0;
179 qxl
->guest_surfaces
.count
--;
180 qemu_mutex_unlock(&qxl
->track_lock
);
183 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
188 trace_qxl_spice_destroy_surface_wait(qxl
->id
, id
, async
);
190 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
191 QXL_IO_DESTROY_SURFACE_ASYNC
);
192 cookie
->u
.surface_id
= id
;
193 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uintptr_t)cookie
);
195 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
196 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
200 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
202 trace_qxl_spice_flush_surfaces_async(qxl
->id
, qxl
->guest_surfaces
.count
,
204 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
205 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
206 QXL_IO_FLUSH_SURFACES_ASYNC
));
209 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
212 trace_qxl_spice_loadvm_commands(qxl
->id
, ext
, count
);
213 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
216 void qxl_spice_oom(PCIQXLDevice
*qxl
)
218 trace_qxl_spice_oom(qxl
->id
);
219 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
222 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
224 trace_qxl_spice_reset_memslots(qxl
->id
);
225 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
228 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
230 trace_qxl_spice_destroy_surfaces_complete(qxl
->id
);
231 qemu_mutex_lock(&qxl
->track_lock
);
232 memset(qxl
->guest_surfaces
.cmds
, 0,
233 sizeof(qxl
->guest_surfaces
.cmds
[0]) * qxl
->ssd
.num_surfaces
);
234 qxl
->guest_surfaces
.count
= 0;
235 qemu_mutex_unlock(&qxl
->track_lock
);
238 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
240 trace_qxl_spice_destroy_surfaces(qxl
->id
, async
);
242 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
243 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
244 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
246 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
247 qxl_spice_destroy_surfaces_complete(qxl
);
251 static void qxl_spice_monitors_config_async(PCIQXLDevice
*qxl
, int replay
)
253 trace_qxl_spice_monitors_config(qxl
->id
);
256 * don't use QXL_COOKIE_TYPE_IO:
257 * - we are not running yet (post_load), we will assert
259 * - this is not a guest io, but a reply, so async_io isn't set.
261 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
262 qxl
->guest_monitors_config
,
264 (uintptr_t)qxl_cookie_new(
265 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
,
268 qxl
->guest_monitors_config
= qxl
->ram
->monitors_config
;
269 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
270 qxl
->ram
->monitors_config
,
272 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
273 QXL_IO_MONITORS_CONFIG_ASYNC
));
277 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
279 trace_qxl_spice_reset_image_cache(qxl
->id
);
280 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
283 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
285 trace_qxl_spice_reset_cursor(qxl
->id
);
286 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
287 qemu_mutex_lock(&qxl
->track_lock
);
288 qxl
->guest_cursor
= 0;
289 qemu_mutex_unlock(&qxl
->track_lock
);
290 if (qxl
->ssd
.cursor
) {
291 cursor_put(qxl
->ssd
.cursor
);
293 qxl
->ssd
.cursor
= cursor_builtin_hidden();
297 static inline uint32_t msb_mask(uint32_t val
)
302 mask
= ~(val
- 1) & val
;
304 } while (mask
< val
);
309 static ram_addr_t
qxl_rom_size(void)
311 uint32_t required_rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) +
313 uint32_t rom_size
= 8192; /* two pages */
315 required_rom_size
= MAX(required_rom_size
, TARGET_PAGE_SIZE
);
316 required_rom_size
= msb_mask(required_rom_size
* 2 - 1);
317 assert(required_rom_size
<= rom_size
);
321 static void init_qxl_rom(PCIQXLDevice
*d
)
323 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
324 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
325 uint32_t ram_header_size
;
326 uint32_t surface0_area_size
;
331 memset(rom
, 0, d
->rom_size
);
333 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
334 rom
->id
= cpu_to_le32(d
->id
);
335 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
336 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
338 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
339 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
340 rom
->slots_start
= 1;
341 rom
->slots_end
= NUM_MEMSLOTS
- 1;
342 rom
->n_surfaces
= cpu_to_le32(d
->ssd
.num_surfaces
);
344 for (i
= 0, n
= 0; i
< ARRAY_SIZE(qxl_modes
); i
++) {
345 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
346 if (fb
> d
->vgamem_size
) {
349 modes
->modes
[n
].id
= cpu_to_le32(i
);
350 modes
->modes
[n
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
351 modes
->modes
[n
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
352 modes
->modes
[n
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
353 modes
->modes
[n
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
354 modes
->modes
[n
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
355 modes
->modes
[n
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
356 modes
->modes
[n
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
359 modes
->n_modes
= cpu_to_le32(n
);
361 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
362 surface0_area_size
= ALIGN(d
->vgamem_size
, 4096);
363 num_pages
= d
->vga
.vram_size
;
364 num_pages
-= ram_header_size
;
365 num_pages
-= surface0_area_size
;
366 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
368 rom
->draw_area_offset
= cpu_to_le32(0);
369 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
370 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
371 rom
->num_pages
= cpu_to_le32(num_pages
);
372 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
374 d
->shadow_rom
= *rom
;
379 static void init_qxl_ram(PCIQXLDevice
*d
)
384 buf
= d
->vga
.vram_ptr
;
385 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
386 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
387 d
->ram
->int_pending
= cpu_to_le32(0);
388 d
->ram
->int_mask
= cpu_to_le32(0);
389 d
->ram
->update_surface
= 0;
390 d
->ram
->monitors_config
= 0;
391 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
392 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
393 SPICE_RING_INIT(&d
->ram
->release_ring
);
394 SPICE_RING_PROD_ITEM(d
, &d
->ram
->release_ring
, item
);
397 qxl_ring_set_dirty(d
);
400 /* can be called from spice server thread context */
401 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
403 memory_region_set_dirty(mr
, addr
, end
- addr
);
406 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
408 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
411 /* called from spice server thread context only */
412 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
414 void *base
= qxl
->vga
.vram_ptr
;
418 offset
&= ~(TARGET_PAGE_SIZE
-1);
419 assert(offset
< qxl
->vga
.vram_size
);
420 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
423 /* can be called from spice server thread context */
424 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
426 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
427 ram_addr_t end
= qxl
->vga
.vram_size
;
428 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
432 * keep track of some command state, for savevm/loadvm.
433 * called from spice server thread context only
435 static int qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
437 switch (le32_to_cpu(ext
->cmd
.type
)) {
438 case QXL_CMD_SURFACE
:
440 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
445 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
447 if (id
>= qxl
->ssd
.num_surfaces
) {
448 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE id %d >= %d", id
,
449 qxl
->ssd
.num_surfaces
);
452 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
&&
453 (cmd
->u
.surface_create
.stride
& 0x03) != 0) {
454 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
455 cmd
->u
.surface_create
.stride
);
458 qemu_mutex_lock(&qxl
->track_lock
);
459 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
460 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
461 qxl
->guest_surfaces
.count
++;
462 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
463 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
465 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
466 qxl
->guest_surfaces
.cmds
[id
] = 0;
467 qxl
->guest_surfaces
.count
--;
469 qemu_mutex_unlock(&qxl
->track_lock
);
474 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
479 if (cmd
->type
== QXL_CURSOR_SET
) {
480 qemu_mutex_lock(&qxl
->track_lock
);
481 qxl
->guest_cursor
= ext
->cmd
.data
;
482 qemu_mutex_unlock(&qxl
->track_lock
);
490 /* spice display interface callbacks */
492 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
494 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
496 trace_qxl_interface_attach_worker(qxl
->id
);
497 qxl
->ssd
.worker
= qxl_worker
;
500 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
502 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
504 trace_qxl_interface_set_compression_level(qxl
->id
, level
);
505 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
506 qxl
->rom
->compression_level
= cpu_to_le32(level
);
507 qxl_rom_set_dirty(qxl
);
510 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
512 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
514 trace_qxl_interface_set_mm_time(qxl
->id
, mm_time
);
515 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
516 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
517 qxl_rom_set_dirty(qxl
);
520 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
522 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
524 trace_qxl_interface_get_init_info(qxl
->id
);
525 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
526 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
527 info
->num_memslots
= NUM_MEMSLOTS
;
528 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
529 info
->internal_groupslot_id
= 0;
530 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
531 info
->n_surfaces
= qxl
->ssd
.num_surfaces
;
534 static const char *qxl_mode_to_string(int mode
)
537 case QXL_MODE_COMPAT
:
539 case QXL_MODE_NATIVE
:
541 case QXL_MODE_UNDEFINED
:
549 static const char *io_port_to_string(uint32_t io_port
)
551 if (io_port
>= QXL_IO_RANGE_SIZE
) {
552 return "out of range";
554 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
555 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
556 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
557 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
558 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
559 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
560 [QXL_IO_RESET
] = "QXL_IO_RESET",
561 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
562 [QXL_IO_LOG
] = "QXL_IO_LOG",
563 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
564 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
565 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
566 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
567 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
568 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
569 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
570 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
571 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
572 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
573 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
574 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
575 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
576 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
577 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
578 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
579 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
580 [QXL_IO_MONITORS_CONFIG_ASYNC
] = "QXL_IO_MONITORS_CONFIG_ASYNC",
582 return io_port_to_string
[io_port
];
585 /* called from spice server thread context only */
586 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
588 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
589 SimpleSpiceUpdate
*update
;
590 QXLCommandRing
*ring
;
594 trace_qxl_ring_command_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
599 qemu_mutex_lock(&qxl
->ssd
.lock
);
600 update
= QTAILQ_FIRST(&qxl
->ssd
.updates
);
601 if (update
!= NULL
) {
602 QTAILQ_REMOVE(&qxl
->ssd
.updates
, update
, next
);
606 qemu_mutex_unlock(&qxl
->ssd
.lock
);
608 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
609 qxl_log_command(qxl
, "vga", ext
);
612 case QXL_MODE_COMPAT
:
613 case QXL_MODE_NATIVE
:
614 case QXL_MODE_UNDEFINED
:
615 ring
= &qxl
->ram
->cmd_ring
;
616 if (qxl
->guest_bug
|| SPICE_RING_IS_EMPTY(ring
)) {
619 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
624 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
625 ext
->flags
= qxl
->cmdflags
;
626 SPICE_RING_POP(ring
, notify
);
627 qxl_ring_set_dirty(qxl
);
629 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
631 qxl
->guest_primary
.commands
++;
632 qxl_track_command(qxl
, ext
);
633 qxl_log_command(qxl
, "cmd", ext
);
634 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
641 /* called from spice server thread context only */
642 static int interface_req_cmd_notification(QXLInstance
*sin
)
644 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
647 trace_qxl_ring_command_req_notification(qxl
->id
);
649 case QXL_MODE_COMPAT
:
650 case QXL_MODE_NATIVE
:
651 case QXL_MODE_UNDEFINED
:
652 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
653 qxl_ring_set_dirty(qxl
);
662 /* called from spice server thread context only */
663 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
665 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
669 #define QXL_FREE_BUNCH_SIZE 32
671 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
672 /* ring full -- can't push */
675 if (!flush
&& d
->oom_running
) {
676 /* collect everything from oom handler before pushing */
679 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
680 /* collect a bit more before pushing */
684 SPICE_RING_PUSH(ring
, notify
);
685 trace_qxl_ring_res_push(d
->id
, qxl_mode_to_string(d
->mode
),
686 d
->guest_surfaces
.count
, d
->num_free_res
,
687 d
->last_release
, notify
? "yes" : "no");
688 trace_qxl_ring_res_push_rest(d
->id
, ring
->prod
- ring
->cons
,
689 ring
->num_items
, ring
->prod
, ring
->cons
);
691 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
693 SPICE_RING_PROD_ITEM(d
, ring
, item
);
699 d
->last_release
= NULL
;
700 qxl_ring_set_dirty(d
);
703 /* called from spice server thread context only */
704 static void interface_release_resource(QXLInstance
*sin
,
705 struct QXLReleaseInfoExt ext
)
707 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
708 QXLReleaseRing
*ring
;
711 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
712 /* host group -> vga mode update request */
713 qemu_spice_destroy_update(&qxl
->ssd
, (void *)(intptr_t)ext
.info
->id
);
718 * ext->info points into guest-visible memory
719 * pci bar 0, $command.release_info
721 ring
= &qxl
->ram
->release_ring
;
722 SPICE_RING_PROD_ITEM(qxl
, ring
, item
);
727 /* stick head into the ring */
730 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
732 qxl_ring_set_dirty(qxl
);
734 /* append item to the list */
735 qxl
->last_release
->next
= ext
.info
->id
;
736 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
738 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
740 qxl
->last_release
= ext
.info
;
742 trace_qxl_ring_res_put(qxl
->id
, qxl
->num_free_res
);
743 qxl_push_free_res(qxl
, 0);
746 /* called from spice server thread context only */
747 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
749 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
754 trace_qxl_ring_cursor_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
757 case QXL_MODE_COMPAT
:
758 case QXL_MODE_NATIVE
:
759 case QXL_MODE_UNDEFINED
:
760 ring
= &qxl
->ram
->cursor_ring
;
761 if (SPICE_RING_IS_EMPTY(ring
)) {
764 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
769 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
770 ext
->flags
= qxl
->cmdflags
;
771 SPICE_RING_POP(ring
, notify
);
772 qxl_ring_set_dirty(qxl
);
774 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
776 qxl
->guest_primary
.commands
++;
777 qxl_track_command(qxl
, ext
);
778 qxl_log_command(qxl
, "csr", ext
);
780 qxl_render_cursor(qxl
, ext
);
782 trace_qxl_ring_cursor_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
789 /* called from spice server thread context only */
790 static int interface_req_cursor_notification(QXLInstance
*sin
)
792 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
795 trace_qxl_ring_cursor_req_notification(qxl
->id
);
797 case QXL_MODE_COMPAT
:
798 case QXL_MODE_NATIVE
:
799 case QXL_MODE_UNDEFINED
:
800 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
801 qxl_ring_set_dirty(qxl
);
810 /* called from spice server thread context */
811 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
814 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
815 * use by xf86-video-qxl and is defined out in the qxl windows driver.
816 * Probably was at some earlier version that is prior to git start (2009),
817 * and is still guest trigerrable.
819 fprintf(stderr
, "%s: deprecated\n", __func__
);
822 /* called from spice server thread context only */
823 static int interface_flush_resources(QXLInstance
*sin
)
825 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
828 ret
= qxl
->num_free_res
;
830 qxl_push_free_res(qxl
, 1);
835 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
837 /* called from spice server thread context only */
838 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
840 uint32_t current_async
;
842 qemu_mutex_lock(&qxl
->async_lock
);
843 current_async
= qxl
->current_async
;
844 qxl
->current_async
= QXL_UNDEFINED_IO
;
845 qemu_mutex_unlock(&qxl
->async_lock
);
847 trace_qxl_interface_async_complete_io(qxl
->id
, current_async
, cookie
);
849 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
852 if (cookie
&& current_async
!= cookie
->io
) {
854 "qxl: %s: error: current_async = %d != %"
855 PRId64
" = cookie->io\n", __func__
, current_async
, cookie
->io
);
857 switch (current_async
) {
858 case QXL_IO_MEMSLOT_ADD_ASYNC
:
859 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
860 case QXL_IO_UPDATE_AREA_ASYNC
:
861 case QXL_IO_FLUSH_SURFACES_ASYNC
:
862 case QXL_IO_MONITORS_CONFIG_ASYNC
:
864 case QXL_IO_CREATE_PRIMARY_ASYNC
:
865 qxl_create_guest_primary_complete(qxl
);
867 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
868 qxl_spice_destroy_surfaces_complete(qxl
);
870 case QXL_IO_DESTROY_SURFACE_ASYNC
:
871 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
874 fprintf(stderr
, "qxl: %s: unexpected current_async %d\n", __func__
,
877 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
880 /* called from spice server thread context only */
881 static void interface_update_area_complete(QXLInstance
*sin
,
883 QXLRect
*dirty
, uint32_t num_updated_rects
)
885 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
889 qemu_mutex_lock(&qxl
->ssd
.lock
);
890 if (surface_id
!= 0 || !qxl
->render_update_cookie_num
) {
891 qemu_mutex_unlock(&qxl
->ssd
.lock
);
894 trace_qxl_interface_update_area_complete(qxl
->id
, surface_id
, dirty
->left
,
895 dirty
->right
, dirty
->top
, dirty
->bottom
);
896 trace_qxl_interface_update_area_complete_rest(qxl
->id
, num_updated_rects
);
897 if (qxl
->num_dirty_rects
+ num_updated_rects
> QXL_NUM_DIRTY_RECTS
) {
899 * overflow - treat this as a full update. Not expected to be common.
901 trace_qxl_interface_update_area_complete_overflow(qxl
->id
,
902 QXL_NUM_DIRTY_RECTS
);
903 qxl
->guest_primary
.resized
= 1;
905 if (qxl
->guest_primary
.resized
) {
907 * Don't bother copying or scheduling the bh since we will flip
908 * the whole area anyway on completion of the update_area async call
910 qemu_mutex_unlock(&qxl
->ssd
.lock
);
913 qxl_i
= qxl
->num_dirty_rects
;
914 for (i
= 0; i
< num_updated_rects
; i
++) {
915 qxl
->dirty
[qxl_i
++] = dirty
[i
];
917 qxl
->num_dirty_rects
+= num_updated_rects
;
918 trace_qxl_interface_update_area_complete_schedule_bh(qxl
->id
,
919 qxl
->num_dirty_rects
);
920 qemu_bh_schedule(qxl
->update_area_bh
);
921 qemu_mutex_unlock(&qxl
->ssd
.lock
);
924 /* called from spice server thread context only */
925 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
927 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
928 QXLCookie
*cookie
= (QXLCookie
*)(uintptr_t)cookie_token
;
930 switch (cookie
->type
) {
931 case QXL_COOKIE_TYPE_IO
:
932 interface_async_complete_io(qxl
, cookie
);
935 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA
:
936 qxl_render_update_area_done(qxl
, cookie
);
938 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
:
941 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
942 __func__
, cookie
->type
);
947 /* called from spice server thread context only */
948 static void interface_set_client_capabilities(QXLInstance
*sin
,
949 uint8_t client_present
,
952 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
954 if (qxl
->revision
< 4) {
955 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl
->id
,
960 if (runstate_check(RUN_STATE_INMIGRATE
) ||
961 runstate_check(RUN_STATE_POSTMIGRATE
)) {
965 qxl
->shadow_rom
.client_present
= client_present
;
966 memcpy(qxl
->shadow_rom
.client_capabilities
, caps
,
967 sizeof(qxl
->shadow_rom
.client_capabilities
));
968 qxl
->rom
->client_present
= client_present
;
969 memcpy(qxl
->rom
->client_capabilities
, caps
,
970 sizeof(qxl
->rom
->client_capabilities
));
971 qxl_rom_set_dirty(qxl
);
973 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT
);
976 static uint32_t qxl_crc32(const uint8_t *p
, unsigned len
)
979 * zlib xors the seed with 0xffffffff, and xors the result
980 * again with 0xffffffff; Both are not done with linux's crc32,
981 * which we want to be compatible with, so undo that.
983 return crc32(0xffffffff, p
, len
) ^ 0xffffffff;
986 /* called from main context only */
987 static int interface_client_monitors_config(QXLInstance
*sin
,
988 VDAgentMonitorsConfig
*monitors_config
)
990 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
991 QXLRom
*rom
= memory_region_get_ram_ptr(&qxl
->rom_bar
);
994 if (qxl
->revision
< 4) {
995 trace_qxl_client_monitors_config_unsupported_by_device(qxl
->id
,
1000 * Older windows drivers set int_mask to 0 when their ISR is called,
1001 * then later set it to ~0. So it doesn't relate to the actual interrupts
1002 * handled. However, they are old, so clearly they don't support this
1005 if (qxl
->ram
->int_mask
== 0 || qxl
->ram
->int_mask
== ~0 ||
1006 !(qxl
->ram
->int_mask
& QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
)) {
1007 trace_qxl_client_monitors_config_unsupported_by_guest(qxl
->id
,
1012 if (!monitors_config
) {
1015 memset(&rom
->client_monitors_config
, 0,
1016 sizeof(rom
->client_monitors_config
));
1017 rom
->client_monitors_config
.count
= monitors_config
->num_of_monitors
;
1018 /* monitors_config->flags ignored */
1019 if (rom
->client_monitors_config
.count
>=
1020 ARRAY_SIZE(rom
->client_monitors_config
.heads
)) {
1021 trace_qxl_client_monitors_config_capped(qxl
->id
,
1022 monitors_config
->num_of_monitors
,
1023 ARRAY_SIZE(rom
->client_monitors_config
.heads
));
1024 rom
->client_monitors_config
.count
=
1025 ARRAY_SIZE(rom
->client_monitors_config
.heads
);
1027 for (i
= 0 ; i
< rom
->client_monitors_config
.count
; ++i
) {
1028 VDAgentMonConfig
*monitor
= &monitors_config
->monitors
[i
];
1029 QXLURect
*rect
= &rom
->client_monitors_config
.heads
[i
];
1030 /* monitor->depth ignored */
1031 rect
->left
= monitor
->x
;
1032 rect
->top
= monitor
->y
;
1033 rect
->right
= monitor
->x
+ monitor
->width
;
1034 rect
->bottom
= monitor
->y
+ monitor
->height
;
1036 rom
->client_monitors_config_crc
= qxl_crc32(
1037 (const uint8_t *)&rom
->client_monitors_config
,
1038 sizeof(rom
->client_monitors_config
));
1039 trace_qxl_client_monitors_config_crc(qxl
->id
,
1040 sizeof(rom
->client_monitors_config
),
1041 rom
->client_monitors_config_crc
);
1043 trace_qxl_interrupt_client_monitors_config(qxl
->id
,
1044 rom
->client_monitors_config
.count
,
1045 rom
->client_monitors_config
.heads
);
1046 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
);
1050 static const QXLInterface qxl_interface
= {
1051 .base
.type
= SPICE_INTERFACE_QXL
,
1052 .base
.description
= "qxl gpu",
1053 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
1054 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
1056 .attache_worker
= interface_attach_worker
,
1057 .set_compression_level
= interface_set_compression_level
,
1058 .set_mm_time
= interface_set_mm_time
,
1059 .get_init_info
= interface_get_init_info
,
1061 /* the callbacks below are called from spice server thread context */
1062 .get_command
= interface_get_command
,
1063 .req_cmd_notification
= interface_req_cmd_notification
,
1064 .release_resource
= interface_release_resource
,
1065 .get_cursor_command
= interface_get_cursor_command
,
1066 .req_cursor_notification
= interface_req_cursor_notification
,
1067 .notify_update
= interface_notify_update
,
1068 .flush_resources
= interface_flush_resources
,
1069 .async_complete
= interface_async_complete
,
1070 .update_area_complete
= interface_update_area_complete
,
1071 .set_client_capabilities
= interface_set_client_capabilities
,
1072 .client_monitors_config
= interface_client_monitors_config
,
1075 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
1077 if (d
->mode
== QXL_MODE_VGA
) {
1080 trace_qxl_enter_vga_mode(d
->id
);
1081 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1082 spice_qxl_driver_unload(&d
->ssd
.qxl
);
1084 qemu_spice_create_host_primary(&d
->ssd
);
1085 d
->mode
= QXL_MODE_VGA
;
1086 vga_dirty_log_start(&d
->vga
);
1087 graphic_hw_update(d
->vga
.con
);
1090 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
1092 if (d
->mode
!= QXL_MODE_VGA
) {
1095 trace_qxl_exit_vga_mode(d
->id
);
1096 vga_dirty_log_stop(&d
->vga
);
1097 qxl_destroy_primary(d
, QXL_SYNC
);
1100 static void qxl_update_irq(PCIQXLDevice
*d
)
1102 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
1103 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
1104 int level
= !!(pending
& mask
);
1105 qemu_set_irq(d
->pci
.irq
[0], level
);
1106 qxl_ring_set_dirty(d
);
1109 static void qxl_check_state(PCIQXLDevice
*d
)
1111 QXLRam
*ram
= d
->ram
;
1112 int spice_display_running
= qemu_spice_display_is_running(&d
->ssd
);
1114 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
1115 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
1118 static void qxl_reset_state(PCIQXLDevice
*d
)
1120 QXLRom
*rom
= d
->rom
;
1123 d
->shadow_rom
.update_id
= cpu_to_le32(0);
1124 *rom
= d
->shadow_rom
;
1125 qxl_rom_set_dirty(d
);
1127 d
->num_free_res
= 0;
1128 d
->last_release
= NULL
;
1129 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1132 static void qxl_soft_reset(PCIQXLDevice
*d
)
1134 trace_qxl_soft_reset(d
->id
);
1136 qxl_clear_guest_bug(d
);
1137 d
->current_async
= QXL_UNDEFINED_IO
;
1140 qxl_enter_vga_mode(d
);
1142 d
->mode
= QXL_MODE_UNDEFINED
;
1146 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
1148 trace_qxl_hard_reset(d
->id
, loadvm
);
1150 qxl_spice_reset_cursor(d
);
1151 qxl_spice_reset_image_cache(d
);
1152 qxl_reset_surfaces(d
);
1153 qxl_reset_memslots(d
);
1155 /* pre loadvm reset must not touch QXLRam. This lives in
1156 * device memory, is migrated together with RAM and thus
1157 * already loaded at this point */
1161 qemu_spice_create_host_memslot(&d
->ssd
);
1165 static void qxl_reset_handler(DeviceState
*dev
)
1167 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
1169 qxl_hard_reset(d
, 0);
1172 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1174 VGACommonState
*vga
= opaque
;
1175 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
1177 trace_qxl_io_write_vga(qxl
->id
, qxl_mode_to_string(qxl
->mode
), addr
, val
);
1178 if (qxl
->mode
!= QXL_MODE_VGA
) {
1179 qxl_destroy_primary(qxl
, QXL_SYNC
);
1180 qxl_soft_reset(qxl
);
1182 vga_ioport_write(opaque
, addr
, val
);
1185 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
1186 { 0x04, 2, 1, .read
= vga_ioport_read
,
1187 .write
= qxl_vga_ioport_write
}, /* 3b4 */
1188 { 0x0a, 1, 1, .read
= vga_ioport_read
,
1189 .write
= qxl_vga_ioport_write
}, /* 3ba */
1190 { 0x10, 16, 1, .read
= vga_ioport_read
,
1191 .write
= qxl_vga_ioport_write
}, /* 3c0 */
1192 { 0x24, 2, 1, .read
= vga_ioport_read
,
1193 .write
= qxl_vga_ioport_write
}, /* 3d4 */
1194 { 0x2a, 1, 1, .read
= vga_ioport_read
,
1195 .write
= qxl_vga_ioport_write
}, /* 3da */
1196 PORTIO_END_OF_LIST(),
1199 static int qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
1202 static const int regions
[] = {
1203 QXL_RAM_RANGE_INDEX
,
1204 QXL_VRAM_RANGE_INDEX
,
1205 QXL_VRAM64_RANGE_INDEX
,
1207 uint64_t guest_start
;
1212 intptr_t virt_start
;
1213 QXLDevMemSlot memslot
;
1216 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
1217 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
1219 trace_qxl_memslot_add_guest(d
->id
, slot_id
, guest_start
, guest_end
);
1221 if (slot_id
>= NUM_MEMSLOTS
) {
1222 qxl_set_guest_bug(d
, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__
,
1223 slot_id
, NUM_MEMSLOTS
);
1226 if (guest_start
> guest_end
) {
1227 qxl_set_guest_bug(d
, "%s: guest_start > guest_end 0x%" PRIx64
1228 " > 0x%" PRIx64
, __func__
, guest_start
, guest_end
);
1232 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
1233 pci_region
= regions
[i
];
1234 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
1235 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
1237 if (pci_start
== -1) {
1240 /* start address in range ? */
1241 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
1244 /* end address in range ? */
1245 if (guest_end
> pci_end
) {
1251 if (i
== ARRAY_SIZE(regions
)) {
1252 qxl_set_guest_bug(d
, "%s: finished loop without match", __func__
);
1256 switch (pci_region
) {
1257 case QXL_RAM_RANGE_INDEX
:
1258 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
1260 case QXL_VRAM_RANGE_INDEX
:
1261 case 4 /* vram 64bit */:
1262 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
1265 /* should not happen */
1266 qxl_set_guest_bug(d
, "%s: pci_region = %d", __func__
, pci_region
);
1270 memslot
.slot_id
= slot_id
;
1271 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
1272 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
1273 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
1274 memslot
.addr_delta
= memslot
.virt_start
- delta
;
1275 memslot
.generation
= d
->rom
->slot_generation
= 0;
1276 qxl_rom_set_dirty(d
);
1278 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
1279 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
1280 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
1281 d
->guest_slots
[slot_id
].delta
= delta
;
1282 d
->guest_slots
[slot_id
].active
= 1;
1286 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1288 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1289 d
->guest_slots
[slot_id
].active
= 0;
1292 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1294 qxl_spice_reset_memslots(d
);
1295 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1298 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1300 trace_qxl_reset_surfaces(d
->id
);
1301 d
->mode
= QXL_MODE_UNDEFINED
;
1302 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1305 /* can be also called from spice server thread context */
1306 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1308 uint64_t phys
= le64_to_cpu(pqxl
);
1309 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1310 uint64_t offset
= phys
& 0xffffffffffff;
1313 case MEMSLOT_GROUP_HOST
:
1314 return (void *)(intptr_t)offset
;
1315 case MEMSLOT_GROUP_GUEST
:
1316 if (slot
>= NUM_MEMSLOTS
) {
1317 qxl_set_guest_bug(qxl
, "slot too large %d >= %d", slot
,
1321 if (!qxl
->guest_slots
[slot
].active
) {
1322 qxl_set_guest_bug(qxl
, "inactive slot %d\n", slot
);
1325 if (offset
< qxl
->guest_slots
[slot
].delta
) {
1326 qxl_set_guest_bug(qxl
,
1327 "slot %d offset %"PRIu64
" < delta %"PRIu64
"\n",
1328 slot
, offset
, qxl
->guest_slots
[slot
].delta
);
1331 offset
-= qxl
->guest_slots
[slot
].delta
;
1332 if (offset
> qxl
->guest_slots
[slot
].size
) {
1333 qxl_set_guest_bug(qxl
,
1334 "slot %d offset %"PRIu64
" > size %"PRIu64
"\n",
1335 slot
, offset
, qxl
->guest_slots
[slot
].size
);
1338 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1343 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1345 /* for local rendering */
1346 qxl_render_resize(qxl
);
1349 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1352 QXLDevSurfaceCreate surface
;
1353 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1355 int requested_height
= le32_to_cpu(sc
->height
);
1356 int requested_stride
= le32_to_cpu(sc
->stride
);
1358 size
= abs(requested_stride
) * requested_height
;
1359 if (size
> qxl
->vgamem_size
) {
1360 qxl_set_guest_bug(qxl
, "%s: requested primary larger then framebuffer"
1365 if (qxl
->mode
== QXL_MODE_NATIVE
) {
1366 qxl_set_guest_bug(qxl
, "%s: nop since already in QXL_MODE_NATIVE",
1369 qxl_exit_vga_mode(qxl
);
1371 surface
.format
= le32_to_cpu(sc
->format
);
1372 surface
.height
= le32_to_cpu(sc
->height
);
1373 surface
.mem
= le64_to_cpu(sc
->mem
);
1374 surface
.position
= le32_to_cpu(sc
->position
);
1375 surface
.stride
= le32_to_cpu(sc
->stride
);
1376 surface
.width
= le32_to_cpu(sc
->width
);
1377 surface
.type
= le32_to_cpu(sc
->type
);
1378 surface
.flags
= le32_to_cpu(sc
->flags
);
1379 trace_qxl_create_guest_primary(qxl
->id
, sc
->width
, sc
->height
, sc
->mem
,
1380 sc
->format
, sc
->position
);
1381 trace_qxl_create_guest_primary_rest(qxl
->id
, sc
->stride
, sc
->type
,
1384 if ((surface
.stride
& 0x3) != 0) {
1385 qxl_set_guest_bug(qxl
, "primary surface stride = %d %% 4 != 0",
1390 surface
.mouse_mode
= true;
1391 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1393 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1396 qxl
->mode
= QXL_MODE_NATIVE
;
1398 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1400 if (async
== QXL_SYNC
) {
1401 qxl_create_guest_primary_complete(qxl
);
1405 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1406 * done (in QXL_SYNC case), 0 otherwise. */
1407 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1409 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1412 trace_qxl_destroy_primary(d
->id
);
1413 d
->mode
= QXL_MODE_UNDEFINED
;
1414 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1415 qxl_spice_reset_cursor(d
);
1419 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1421 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1422 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1423 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1424 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1429 QXLSurfaceCreate surface
= {
1430 .width
= mode
->x_res
,
1431 .height
= mode
->y_res
,
1432 .stride
= -mode
->x_res
* 4,
1433 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1434 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1436 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1439 trace_qxl_set_mode(d
->id
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
,
1442 qxl_hard_reset(d
, 0);
1445 d
->guest_slots
[0].slot
= slot
;
1446 assert(qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
) == 0);
1448 d
->guest_primary
.surface
= surface
;
1449 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1451 d
->mode
= QXL_MODE_COMPAT
;
1452 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1453 if (mode
->bits
== 16) {
1454 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1456 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1457 d
->rom
->mode
= cpu_to_le32(modenr
);
1458 qxl_rom_set_dirty(d
);
1461 static void ioport_write(void *opaque
, hwaddr addr
,
1462 uint64_t val
, unsigned size
)
1464 PCIQXLDevice
*d
= opaque
;
1465 uint32_t io_port
= addr
;
1466 qxl_async_io async
= QXL_SYNC
;
1467 uint32_t orig_io_port
= io_port
;
1469 if (d
->guest_bug
&& io_port
!= QXL_IO_RESET
) {
1473 if (d
->revision
<= QXL_REVISION_STABLE_V10
&&
1474 io_port
> QXL_IO_FLUSH_RELEASE
) {
1475 qxl_set_guest_bug(d
, "unsupported io %d for revision %d\n",
1476 io_port
, d
->revision
);
1482 case QXL_IO_SET_MODE
:
1483 case QXL_IO_MEMSLOT_ADD
:
1484 case QXL_IO_MEMSLOT_DEL
:
1485 case QXL_IO_CREATE_PRIMARY
:
1486 case QXL_IO_UPDATE_IRQ
:
1488 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1489 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1492 if (d
->mode
!= QXL_MODE_VGA
) {
1495 trace_qxl_io_unexpected_vga_mode(d
->id
,
1496 addr
, val
, io_port_to_string(io_port
));
1497 /* be nice to buggy guest drivers */
1498 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1499 io_port
< QXL_IO_RANGE_SIZE
) {
1500 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1505 /* we change the io_port to avoid ifdeffery in the main switch */
1506 orig_io_port
= io_port
;
1508 case QXL_IO_UPDATE_AREA_ASYNC
:
1509 io_port
= QXL_IO_UPDATE_AREA
;
1511 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1512 io_port
= QXL_IO_MEMSLOT_ADD
;
1514 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1515 io_port
= QXL_IO_CREATE_PRIMARY
;
1517 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1518 io_port
= QXL_IO_DESTROY_PRIMARY
;
1520 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1521 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1523 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1524 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1526 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1527 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1530 qemu_mutex_lock(&d
->async_lock
);
1531 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1532 qxl_set_guest_bug(d
, "%d async started before last (%d) complete",
1533 io_port
, d
->current_async
);
1534 qemu_mutex_unlock(&d
->async_lock
);
1537 d
->current_async
= orig_io_port
;
1538 qemu_mutex_unlock(&d
->async_lock
);
1543 trace_qxl_io_write(d
->id
, qxl_mode_to_string(d
->mode
), addr
, val
, size
,
1547 case QXL_IO_UPDATE_AREA
:
1549 QXLCookie
*cookie
= NULL
;
1550 QXLRect update
= d
->ram
->update_area
;
1552 if (d
->ram
->update_surface
> d
->ssd
.num_surfaces
) {
1553 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1554 d
->ram
->update_surface
);
1557 if (update
.left
>= update
.right
|| update
.top
>= update
.bottom
||
1558 update
.left
< 0 || update
.top
< 0) {
1559 qxl_set_guest_bug(d
,
1560 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1561 update
.left
, update
.top
, update
.right
, update
.bottom
);
1564 if (async
== QXL_ASYNC
) {
1565 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1566 QXL_IO_UPDATE_AREA_ASYNC
);
1567 cookie
->u
.area
= update
;
1569 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1570 cookie
? &cookie
->u
.area
: &update
,
1571 NULL
, 0, 0, async
, cookie
);
1574 case QXL_IO_NOTIFY_CMD
:
1575 qemu_spice_wakeup(&d
->ssd
);
1577 case QXL_IO_NOTIFY_CURSOR
:
1578 qemu_spice_wakeup(&d
->ssd
);
1580 case QXL_IO_UPDATE_IRQ
:
1583 case QXL_IO_NOTIFY_OOM
:
1584 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1591 case QXL_IO_SET_MODE
:
1592 qxl_set_mode(d
, val
, 0);
1595 trace_qxl_io_log(d
->id
, d
->ram
->log_buf
);
1596 if (d
->guestdebug
) {
1597 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1598 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1602 qxl_hard_reset(d
, 0);
1604 case QXL_IO_MEMSLOT_ADD
:
1605 if (val
>= NUM_MEMSLOTS
) {
1606 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1609 if (d
->guest_slots
[val
].active
) {
1610 qxl_set_guest_bug(d
,
1611 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1614 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1615 qxl_add_memslot(d
, val
, 0, async
);
1617 case QXL_IO_MEMSLOT_DEL
:
1618 if (val
>= NUM_MEMSLOTS
) {
1619 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1622 qxl_del_memslot(d
, val
);
1624 case QXL_IO_CREATE_PRIMARY
:
1626 qxl_set_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1630 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1631 qxl_create_guest_primary(d
, 0, async
);
1633 case QXL_IO_DESTROY_PRIMARY
:
1635 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1639 if (!qxl_destroy_primary(d
, async
)) {
1640 trace_qxl_io_destroy_primary_ignored(d
->id
,
1641 qxl_mode_to_string(d
->mode
));
1645 case QXL_IO_DESTROY_SURFACE_WAIT
:
1646 if (val
>= d
->ssd
.num_surfaces
) {
1647 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1648 "%" PRIu64
" >= NUM_SURFACES", async
, val
);
1651 qxl_spice_destroy_surface_wait(d
, val
, async
);
1653 case QXL_IO_FLUSH_RELEASE
: {
1654 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1655 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1657 "ERROR: no flush, full release ring [p%d,%dc]\n",
1658 ring
->prod
, ring
->cons
);
1660 qxl_push_free_res(d
, 1 /* flush */);
1663 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1664 qxl_spice_flush_surfaces_async(d
);
1666 case QXL_IO_DESTROY_ALL_SURFACES
:
1667 d
->mode
= QXL_MODE_UNDEFINED
;
1668 qxl_spice_destroy_surfaces(d
, async
);
1670 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1671 qxl_spice_monitors_config_async(d
, 0);
1674 qxl_set_guest_bug(d
, "%s: unexpected ioport=0x%x\n", __func__
, io_port
);
1679 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1680 qemu_mutex_lock(&d
->async_lock
);
1681 d
->current_async
= QXL_UNDEFINED_IO
;
1682 qemu_mutex_unlock(&d
->async_lock
);
1686 static uint64_t ioport_read(void *opaque
, hwaddr addr
,
1689 PCIQXLDevice
*qxl
= opaque
;
1691 trace_qxl_io_read_unexpected(qxl
->id
);
1695 static const MemoryRegionOps qxl_io_ops
= {
1696 .read
= ioport_read
,
1697 .write
= ioport_write
,
1699 .min_access_size
= 1,
1700 .max_access_size
= 1,
1704 static void pipe_read(void *opaque
)
1706 PCIQXLDevice
*d
= opaque
;
1711 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1712 } while (len
== sizeof(dummy
));
1716 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1718 uint32_t old_pending
;
1719 uint32_t le_events
= cpu_to_le32(events
);
1721 trace_qxl_send_events(d
->id
, events
);
1722 if (!qemu_spice_display_is_running(&d
->ssd
)) {
1723 /* spice-server tracks guest running state and should not do this */
1724 fprintf(stderr
, "%s: spice-server bug: guest stopped, ignoring\n",
1726 trace_qxl_send_events_vm_stopped(d
->id
, events
);
1729 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1730 if ((old_pending
& le_events
) == le_events
) {
1733 if (qemu_thread_is_self(&d
->main
)) {
1736 if (write(d
->pipe
[1], d
, 1) != 1) {
1737 dprint(d
, 1, "%s: write to pipe failed\n", __func__
);
1742 static void init_pipe_signaling(PCIQXLDevice
*d
)
1744 if (pipe(d
->pipe
) < 0) {
1745 fprintf(stderr
, "%s:%s: qxl pipe creation failed\n",
1746 __FILE__
, __func__
);
1749 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1750 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1751 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1753 qemu_thread_get_self(&d
->main
);
1754 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1757 /* graphics console */
1759 static void qxl_hw_update(void *opaque
)
1761 PCIQXLDevice
*qxl
= opaque
;
1762 VGACommonState
*vga
= &qxl
->vga
;
1764 switch (qxl
->mode
) {
1766 vga
->hw_ops
->gfx_update(vga
);
1768 case QXL_MODE_COMPAT
:
1769 case QXL_MODE_NATIVE
:
1770 qxl_render_update(qxl
);
1777 static void qxl_hw_invalidate(void *opaque
)
1779 PCIQXLDevice
*qxl
= opaque
;
1780 VGACommonState
*vga
= &qxl
->vga
;
1782 if (qxl
->mode
== QXL_MODE_VGA
) {
1783 vga
->hw_ops
->invalidate(vga
);
1788 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1790 PCIQXLDevice
*qxl
= opaque
;
1791 VGACommonState
*vga
= &qxl
->vga
;
1793 if (qxl
->mode
== QXL_MODE_VGA
) {
1794 vga
->hw_ops
->text_update(vga
, chardata
);
1799 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1801 uintptr_t vram_start
;
1804 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1808 /* dirty the primary surface */
1809 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1810 qxl
->shadow_rom
.surface0_area_size
);
1812 vram_start
= (uintptr_t)memory_region_get_ram_ptr(&qxl
->vram_bar
);
1814 /* dirty the off-screen surfaces */
1815 for (i
= 0; i
< qxl
->ssd
.num_surfaces
; i
++) {
1817 intptr_t surface_offset
;
1820 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1824 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1825 MEMSLOT_GROUP_GUEST
);
1827 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1828 surface_offset
= (intptr_t)qxl_phys2virt(qxl
,
1829 cmd
->u
.surface_create
.data
,
1830 MEMSLOT_GROUP_GUEST
);
1831 assert(surface_offset
);
1832 surface_offset
-= vram_start
;
1833 surface_size
= cmd
->u
.surface_create
.height
*
1834 abs(cmd
->u
.surface_create
.stride
);
1835 trace_qxl_surfaces_dirty(qxl
->id
, i
, (int)surface_offset
, surface_size
);
1836 qxl_set_dirty(&qxl
->vram_bar
, surface_offset
, surface_size
);
1840 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1843 PCIQXLDevice
*qxl
= opaque
;
1847 * if qxl_send_events was called from spice server context before
1848 * migration ended, qxl_update_irq for these events might not have been
1851 qxl_update_irq(qxl
);
1853 /* make sure surfaces are saved before migration */
1854 qxl_dirty_surfaces(qxl
);
1858 /* display change listener */
1860 static void display_update(DisplayChangeListener
*dcl
,
1861 int x
, int y
, int w
, int h
)
1863 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1865 if (qxl
->mode
== QXL_MODE_VGA
) {
1866 qemu_spice_display_update(&qxl
->ssd
, x
, y
, w
, h
);
1870 static void display_switch(DisplayChangeListener
*dcl
,
1871 struct DisplaySurface
*surface
)
1873 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1875 qxl
->ssd
.ds
= surface
;
1876 if (qxl
->mode
== QXL_MODE_VGA
) {
1877 qemu_spice_display_switch(&qxl
->ssd
, surface
);
1881 static void display_refresh(DisplayChangeListener
*dcl
)
1883 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1885 if (qxl
->mode
== QXL_MODE_VGA
) {
1886 qemu_spice_display_refresh(&qxl
->ssd
);
1888 qemu_mutex_lock(&qxl
->ssd
.lock
);
1889 qemu_spice_cursor_refresh_unlocked(&qxl
->ssd
);
1890 qemu_mutex_unlock(&qxl
->ssd
.lock
);
1894 static DisplayChangeListenerOps display_listener_ops
= {
1895 .dpy_name
= "spice/qxl",
1896 .dpy_gfx_update
= display_update
,
1897 .dpy_gfx_switch
= display_switch
,
1898 .dpy_refresh
= display_refresh
,
1901 static void qxl_init_ramsize(PCIQXLDevice
*qxl
)
1903 /* vga mode framebuffer / primary surface (bar 0, first part) */
1904 if (qxl
->vgamem_size_mb
< 8) {
1905 qxl
->vgamem_size_mb
= 8;
1907 qxl
->vgamem_size
= qxl
->vgamem_size_mb
* 1024 * 1024;
1909 /* vga ram (bar 0, total) */
1910 if (qxl
->ram_size_mb
!= -1) {
1911 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
1913 if (qxl
->vga
.vram_size
< qxl
->vgamem_size
* 2) {
1914 qxl
->vga
.vram_size
= qxl
->vgamem_size
* 2;
1917 /* vram32 (surfaces, 32bit, bar 1) */
1918 if (qxl
->vram32_size_mb
!= -1) {
1919 qxl
->vram32_size
= qxl
->vram32_size_mb
* 1024 * 1024;
1921 if (qxl
->vram32_size
< 4096) {
1922 qxl
->vram32_size
= 4096;
1925 /* vram (surfaces, 64bit, bar 4+5) */
1926 if (qxl
->vram_size_mb
!= -1) {
1927 qxl
->vram_size
= qxl
->vram_size_mb
* 1024 * 1024;
1929 if (qxl
->vram_size
< qxl
->vram32_size
) {
1930 qxl
->vram_size
= qxl
->vram32_size
;
1933 if (qxl
->revision
== 1) {
1934 qxl
->vram32_size
= 4096;
1935 qxl
->vram_size
= 4096;
1937 qxl
->vgamem_size
= msb_mask(qxl
->vgamem_size
* 2 - 1);
1938 qxl
->vga
.vram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1939 qxl
->vram32_size
= msb_mask(qxl
->vram32_size
* 2 - 1);
1940 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1943 static int qxl_init_common(PCIQXLDevice
*qxl
)
1945 uint8_t* config
= qxl
->pci
.config
;
1946 uint32_t pci_device_rev
;
1949 qxl
->mode
= QXL_MODE_UNDEFINED
;
1950 qxl
->generation
= 1;
1951 qxl
->num_memslots
= NUM_MEMSLOTS
;
1952 qemu_mutex_init(&qxl
->track_lock
);
1953 qemu_mutex_init(&qxl
->async_lock
);
1954 qxl
->current_async
= QXL_UNDEFINED_IO
;
1957 switch (qxl
->revision
) {
1958 case 1: /* spice 0.4 -- qxl-1 */
1959 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1962 case 2: /* spice 0.6 -- qxl-2 */
1963 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1967 pci_device_rev
= QXL_REVISION_STABLE_V10
;
1968 io_size
= 32; /* PCI region size must be pow2 */
1971 pci_device_rev
= QXL_REVISION_STABLE_V12
;
1972 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1975 error_report("Invalid revision %d for qxl device (max %d)",
1976 qxl
->revision
, QXL_DEFAULT_REVISION
);
1980 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1981 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1983 qxl
->rom_size
= qxl_rom_size();
1984 memory_region_init_ram(&qxl
->rom_bar
, NULL
, "qxl.vrom", qxl
->rom_size
);
1985 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
1989 qxl
->guest_surfaces
.cmds
= g_new0(QXLPHYSICAL
, qxl
->ssd
.num_surfaces
);
1990 memory_region_init_ram(&qxl
->vram_bar
, NULL
, "qxl.vram", qxl
->vram_size
);
1991 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
1992 memory_region_init_alias(&qxl
->vram32_bar
, NULL
, "qxl.vram32", &qxl
->vram_bar
,
1993 0, qxl
->vram32_size
);
1995 memory_region_init_io(&qxl
->io_bar
, NULL
, &qxl_io_ops
, qxl
,
1996 "qxl-ioports", io_size
);
1998 vga_dirty_log_start(&qxl
->vga
);
2000 memory_region_set_flush_coalesced(&qxl
->io_bar
);
2003 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
2004 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
2006 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
2007 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
2009 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
2010 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
2012 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
2013 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram32_bar
);
2015 if (qxl
->vram32_size
< qxl
->vram_size
) {
2017 * Make the 64bit vram bar show up only in case it is
2018 * configured to be larger than the 32bit vram bar.
2020 pci_register_bar(&qxl
->pci
, QXL_VRAM64_RANGE_INDEX
,
2021 PCI_BASE_ADDRESS_SPACE_MEMORY
|
2022 PCI_BASE_ADDRESS_MEM_TYPE_64
|
2023 PCI_BASE_ADDRESS_MEM_PREFETCH
,
2027 /* print pci bar details */
2028 dprint(qxl
, 1, "ram/%s: %d MB [region 0]\n",
2029 qxl
->id
== 0 ? "pri" : "sec",
2030 qxl
->vga
.vram_size
/ (1024*1024));
2031 dprint(qxl
, 1, "vram/32: %d MB [region 1]\n",
2032 qxl
->vram32_size
/ (1024*1024));
2033 dprint(qxl
, 1, "vram/64: %d MB %s\n",
2034 qxl
->vram_size
/ (1024*1024),
2035 qxl
->vram32_size
< qxl
->vram_size
? "[region 4]" : "[unmapped]");
2037 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
2038 qxl
->ssd
.qxl
.id
= qxl
->id
;
2039 if (qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
) != 0) {
2040 error_report("qxl interface %d.%d not supported by spice-server",
2041 SPICE_INTERFACE_QXL_MAJOR
, SPICE_INTERFACE_QXL_MINOR
);
2044 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
2046 init_pipe_signaling(qxl
);
2047 qxl_reset_state(qxl
);
2049 qxl
->update_area_bh
= qemu_bh_new(qxl_render_update_area_bh
, qxl
);
2054 static const GraphicHwOps qxl_ops
= {
2055 .invalidate
= qxl_hw_invalidate
,
2056 .gfx_update
= qxl_hw_update
,
2057 .text_update
= qxl_hw_text_update
,
2060 static int qxl_init_primary(PCIDevice
*dev
)
2062 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
2063 VGACommonState
*vga
= &qxl
->vga
;
2064 PortioList
*qxl_vga_port_list
= g_new(PortioList
, 1);
2068 qxl_init_ramsize(qxl
);
2069 vga
->vram_size_mb
= qxl
->vga
.vram_size
>> 20;
2070 vga_common_init(vga
, OBJECT(dev
));
2071 vga_init(vga
, OBJECT(dev
),
2072 pci_address_space(dev
), pci_address_space_io(dev
), false);
2073 portio_list_init(qxl_vga_port_list
, OBJECT(dev
), qxl_vga_portio_list
,
2075 portio_list_add(qxl_vga_port_list
, pci_address_space_io(dev
), 0x3b0);
2077 vga
->con
= graphic_console_init(DEVICE(dev
), &qxl_ops
, qxl
);
2078 qemu_spice_display_init_common(&qxl
->ssd
);
2080 rc
= qxl_init_common(qxl
);
2085 qxl
->ssd
.dcl
.ops
= &display_listener_ops
;
2086 qxl
->ssd
.dcl
.con
= vga
->con
;
2087 register_displaychangelistener(&qxl
->ssd
.dcl
);
2091 static int qxl_init_secondary(PCIDevice
*dev
)
2093 static int device_id
= 1;
2094 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
2096 qxl
->id
= device_id
++;
2097 qxl_init_ramsize(qxl
);
2098 memory_region_init_ram(&qxl
->vga
.vram
, NULL
, "qxl.vgavram", qxl
->vga
.vram_size
);
2099 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
2100 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
2101 qxl
->vga
.con
= graphic_console_init(DEVICE(dev
), &qxl_ops
, qxl
);
2103 return qxl_init_common(qxl
);
2106 static void qxl_pre_save(void *opaque
)
2108 PCIQXLDevice
* d
= opaque
;
2109 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2111 trace_qxl_pre_save(d
->id
);
2112 if (d
->last_release
== NULL
) {
2113 d
->last_release_offset
= 0;
2115 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
2117 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2120 static int qxl_pre_load(void *opaque
)
2122 PCIQXLDevice
* d
= opaque
;
2124 trace_qxl_pre_load(d
->id
);
2125 qxl_hard_reset(d
, 1);
2126 qxl_exit_vga_mode(d
);
2130 static void qxl_create_memslots(PCIQXLDevice
*d
)
2134 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
2135 if (!d
->guest_slots
[i
].active
) {
2138 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
2142 static int qxl_post_load(void *opaque
, int version
)
2144 PCIQXLDevice
* d
= opaque
;
2145 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2146 QXLCommandExt
*cmds
;
2147 int in
, out
, newmode
;
2149 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2150 if (d
->last_release_offset
== 0) {
2151 d
->last_release
= NULL
;
2153 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
2156 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
2158 trace_qxl_post_load(d
->id
, qxl_mode_to_string(d
->mode
));
2160 d
->mode
= QXL_MODE_UNDEFINED
;
2163 case QXL_MODE_UNDEFINED
:
2164 qxl_create_memslots(d
);
2167 qxl_create_memslots(d
);
2168 qxl_enter_vga_mode(d
);
2170 case QXL_MODE_NATIVE
:
2171 qxl_create_memslots(d
);
2172 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
2174 /* replay surface-create and cursor-set commands */
2175 cmds
= g_malloc0(sizeof(QXLCommandExt
) * (d
->ssd
.num_surfaces
+ 1));
2176 for (in
= 0, out
= 0; in
< d
->ssd
.num_surfaces
; in
++) {
2177 if (d
->guest_surfaces
.cmds
[in
] == 0) {
2180 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
2181 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
2182 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2185 if (d
->guest_cursor
) {
2186 cmds
[out
].cmd
.data
= d
->guest_cursor
;
2187 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
2188 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2191 qxl_spice_loadvm_commands(d
, cmds
, out
);
2193 if (d
->guest_monitors_config
) {
2194 qxl_spice_monitors_config_async(d
, 1);
2197 case QXL_MODE_COMPAT
:
2198 /* note: no need to call qxl_create_memslots, qxl_set_mode
2199 * creates the mem slot. */
2200 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
2206 #define QXL_SAVE_VERSION 21
2208 static bool qxl_monitors_config_needed(void *opaque
)
2210 PCIQXLDevice
*qxl
= opaque
;
2212 return qxl
->guest_monitors_config
!= 0;
2216 static VMStateDescription qxl_memslot
= {
2217 .name
= "qxl-memslot",
2218 .version_id
= QXL_SAVE_VERSION
,
2219 .minimum_version_id
= QXL_SAVE_VERSION
,
2220 .fields
= (VMStateField
[]) {
2221 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
2222 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
2223 VMSTATE_UINT32(active
, struct guest_slots
),
2224 VMSTATE_END_OF_LIST()
2228 static VMStateDescription qxl_surface
= {
2229 .name
= "qxl-surface",
2230 .version_id
= QXL_SAVE_VERSION
,
2231 .minimum_version_id
= QXL_SAVE_VERSION
,
2232 .fields
= (VMStateField
[]) {
2233 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
2234 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
2235 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
2236 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
2237 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
2238 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
2239 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
2240 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
2241 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
2242 VMSTATE_END_OF_LIST()
2246 static VMStateDescription qxl_vmstate_monitors_config
= {
2247 .name
= "qxl/monitors-config",
2249 .minimum_version_id
= 1,
2250 .fields
= (VMStateField
[]) {
2251 VMSTATE_UINT64(guest_monitors_config
, PCIQXLDevice
),
2252 VMSTATE_END_OF_LIST()
2256 static VMStateDescription qxl_vmstate
= {
2258 .version_id
= QXL_SAVE_VERSION
,
2259 .minimum_version_id
= QXL_SAVE_VERSION
,
2260 .pre_save
= qxl_pre_save
,
2261 .pre_load
= qxl_pre_load
,
2262 .post_load
= qxl_post_load
,
2263 .fields
= (VMStateField
[]) {
2264 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
2265 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
2266 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
2267 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
2268 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
2269 VMSTATE_UINT32(mode
, PCIQXLDevice
),
2270 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
2271 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
2272 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
2273 qxl_memslot
, struct guest_slots
),
2274 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
2275 qxl_surface
, QXLSurfaceCreate
),
2276 VMSTATE_INT32_EQUAL(ssd
.num_surfaces
, PCIQXLDevice
),
2277 VMSTATE_VARRAY_INT32(guest_surfaces
.cmds
, PCIQXLDevice
,
2278 ssd
.num_surfaces
, 0,
2279 vmstate_info_uint64
, uint64_t),
2280 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
2281 VMSTATE_END_OF_LIST()
2283 .subsections
= (VMStateSubsection
[]) {
2285 .vmsd
= &qxl_vmstate_monitors_config
,
2286 .needed
= qxl_monitors_config_needed
,
2293 static Property qxl_properties
[] = {
2294 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
2296 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram32_size
,
2298 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
2299 QXL_DEFAULT_REVISION
),
2300 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
2301 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
2302 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
2303 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
2304 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram32_size_mb
, -1),
2305 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
2306 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice
, vgamem_size_mb
, 16),
2307 DEFINE_PROP_INT32("surfaces", PCIQXLDevice
, ssd
.num_surfaces
, 1024),
2308 DEFINE_PROP_END_OF_LIST(),
2311 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
2313 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2314 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2317 k
->init
= qxl_init_primary
;
2318 k
->romfile
= "vgabios-qxl.bin";
2319 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2320 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2321 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
2322 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
2323 dc
->reset
= qxl_reset_handler
;
2324 dc
->vmsd
= &qxl_vmstate
;
2325 dc
->props
= qxl_properties
;
2328 static const TypeInfo qxl_primary_info
= {
2330 .parent
= TYPE_PCI_DEVICE
,
2331 .instance_size
= sizeof(PCIQXLDevice
),
2332 .class_init
= qxl_primary_class_init
,
2335 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
2337 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2338 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2340 k
->init
= qxl_init_secondary
;
2341 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2342 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2343 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2344 dc
->desc
= "Spice QXL GPU (secondary)";
2345 dc
->reset
= qxl_reset_handler
;
2346 dc
->vmsd
= &qxl_vmstate
;
2347 dc
->props
= qxl_properties
;
2350 static const TypeInfo qxl_secondary_info
= {
2352 .parent
= TYPE_PCI_DEVICE
,
2353 .instance_size
= sizeof(PCIQXLDevice
),
2354 .class_init
= qxl_secondary_class_init
,
2357 static void qxl_register_types(void)
2359 type_register_static(&qxl_primary_info
);
2360 type_register_static(&qxl_secondary_info
);
2363 type_init(qxl_register_types
)