include/hw/net/imx_fec.h

   1 /*
   2  * i.MX Fast Ethernet Controller emulation.
   3  *
   4  * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
   5  *
   6  * Based on Coldfire Fast Ethernet Controller emulation.
   7  *
   8  * Copyright (c) 2007 CodeSourcery.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the
  12  *  Free Software Foundation; either version 2 of the License, or
  13  *  (at your option) any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  18  *  for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along
  21  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #ifndef IMX_FEC_H
  25 #define IMX_FEC_H
  26
  27 #define TYPE_IMX_FEC "imx.fec"
  28 #define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC)
  29
  30 #include "hw/sysbus.h"
  31 #include "net/net.h"
  32
  33 #define ENET_EIR               1
  34 #define ENET_EIMR              2
  35 #define ENET_RDAR              4
  36 #define ENET_TDAR              5
  37 #define ENET_ECR               9
  38 #define ENET_MMFR              16
  39 #define ENET_MSCR              17
  40 #define ENET_MIBC              25
  41 #define ENET_RCR               33
  42 #define ENET_TCR               49
  43 #define ENET_PALR              57
  44 #define ENET_PAUR              58
  45 #define ENET_OPD               59
  46 #define ENET_IAUR              70
  47 #define ENET_IALR              71
  48 #define ENET_GAUR              72
  49 #define ENET_GALR              73
  50 #define ENET_TFWR              81
  51 #define ENET_FRBR              83
  52 #define ENET_FRSR              84
  53 #define ENET_RDSR              96
  54 #define ENET_TDSR              97
  55 #define ENET_MRBR              98
  56 #define ENET_MIIGSK_CFGR       192
  57 #define ENET_MIIGSK_ENR        194
  58 #define ENET_MAX               400
  59
  60 #define ENET_MAX_FRAME_SIZE    2032
  61
  62 #define ENET_INT_HB            (1 << 31)
  63 #define ENET_INT_BABR          (1 << 30)
  64 #define ENET_INT_BABT          (1 << 29)
  65 #define ENET_INT_GRA           (1 << 28)
  66 #define ENET_INT_TXF           (1 << 27)
  67 #define ENET_INT_TXB           (1 << 26)
  68 #define ENET_INT_RXF           (1 << 25)
  69 #define ENET_INT_RXB           (1 << 24)
  70 #define ENET_INT_MII           (1 << 23)
  71 #define ENET_INT_EBERR         (1 << 22)
  72 #define ENET_INT_LC            (1 << 21)
  73 #define ENET_INT_RL            (1 << 20)
  74 #define ENET_INT_UN            (1 << 19)
  75
  76 /* RDAR */
  77 #define ENET_RDAR_RDAR         (1 << 24)
  78
  79 /* TDAR */
  80 #define ENET_TDAR_TDAR         (1 << 24)
  81
  82 #define ENET_ECR_RESET         (1 << 0)
  83 #define ENET_ECR_ETHEREN       (1 << 1)
  84
  85 /* Buffer Descriptor.  */
  86 typedef struct {
  87     uint16_t length;
  88     uint16_t flags;
  89     uint32_t data;
  90 } IMXFECBufDesc;
  91
  92 #define ENET_BD_R              (1 << 15)
  93 #define ENET_BD_E              (1 << 15)
  94 #define ENET_BD_O1             (1 << 14)
  95 #define ENET_BD_W              (1 << 13)
  96 #define ENET_BD_O2             (1 << 12)
  97 #define ENET_BD_L              (1 << 11)
  98 #define ENET_BD_TC             (1 << 10)
  99 #define ENET_BD_ABC            (1 << 9)
 100 #define ENET_BD_M              (1 << 8)
 101 #define ENET_BD_BC             (1 << 7)
 102 #define ENET_BD_MC             (1 << 6)
 103 #define ENET_BD_LG             (1 << 5)
 104 #define ENET_BD_NO             (1 << 4)
 105 #define ENET_BD_CR             (1 << 2)
 106 #define ENET_BD_OV             (1 << 1)
 107 #define ENET_BD_TR             (1 << 0)
 108
 109 typedef struct IMXFECState {
 110     /*< private >*/
 111     SysBusDevice parent_obj;
 112
 113     /*< public >*/
 114     NICState *nic;
 115     NICConf conf;
 116     qemu_irq irq;
 117     MemoryRegion iomem;
 118
 119     uint32_t regs[ENET_MAX];
 120     uint32_t rx_descriptor;
 121     uint32_t tx_descriptor;
 122
 123     uint32_t phy_status;
 124     uint32_t phy_control;
 125     uint32_t phy_advertise;
 126     uint32_t phy_int;
 127     uint32_t phy_int_mask;
 128 } IMXFECState;
 129
 130 #endif