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s390x/s390-virtio-ccw: Reset PCI devices during subsystem reset
[qemu/ar7.git] / hw / sparc / sun4m.c
blob38d1e0fd129435bd0883521febe46c9e2f91edbf
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/rtc/m48t59.h"
35 #include "migration/vmstate.h"
36 #include "hw/sparc/sparc32_dma.h"
37 #include "hw/block/fdc.h"
38 #include "sysemu/reset.h"
39 #include "sysemu/runstate.h"
40 #include "sysemu/sysemu.h"
41 #include "net/net.h"
42 #include "hw/boards.h"
43 #include "hw/scsi/esp.h"
44 #include "hw/nvram/sun_nvram.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/nvram/chrp_nvram.h"
47 #include "hw/nvram/fw_cfg.h"
48 #include "hw/char/escc.h"
49 #include "hw/misc/empty_slot.h"
50 #include "hw/misc/unimp.h"
51 #include "hw/irq.h"
52 #include "hw/loader.h"
53 #include "elf.h"
54 #include "trace.h"
55 #include "qom/object.h"
56
57 /*
58 * Sun4m architecture was used in the following machines:
59 *
60 * SPARCserver 6xxMP/xx
61 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
62 * SPARCclassic X (4/10)
63 * SPARCstation LX/ZX (4/30)
64 * SPARCstation Voyager
65 * SPARCstation 10/xx, SPARCserver 10/xx
66 * SPARCstation 5, SPARCserver 5
67 * SPARCstation 20/xx, SPARCserver 20
68 * SPARCstation 4
69 *
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
71 */
72
73 #define KERNEL_LOAD_ADDR 0x00004000
74 #define CMDLINE_ADDR 0x007ff000
75 #define INITRD_LOAD_ADDR 0x00800000
76 #define PROM_SIZE_MAX (1 * MiB)
77 #define PROM_VADDR 0xffd00000
78 #define PROM_FILENAME "openbios-sparc32"
79 #define CFG_ADDR 0xd00000510ULL
80 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
81 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
82 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
83
84 #define MAX_CPUS 16
85 #define MAX_PILS 16
86 #define MAX_VSIMMS 4
87
88 #define ESCC_CLOCK 4915200
89
90 struct sun4m_hwdef {
91 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
92 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
93 hwaddr serial_base, fd_base;
94 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
95 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
96 hwaddr bpp_base, dbri_base, sx_base;
97 struct {
98 hwaddr reg_base, vram_base;
99 } vsimm[MAX_VSIMMS];
100 hwaddr ecc_base;
101 uint64_t max_mem;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 const char *fw_cfg_arch_key_name(uint16_t key)
109 {
110 static const struct {
111 uint16_t key;
112 const char *name;
113 } fw_cfg_arch_wellknown_keys[] = {
114 {FW_CFG_SUN4M_DEPTH, "depth"},
115 {FW_CFG_SUN4M_WIDTH, "width"},
116 {FW_CFG_SUN4M_HEIGHT, "height"},
117 };
118
119 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
120 if (fw_cfg_arch_wellknown_keys[i].key == key) {
121 return fw_cfg_arch_wellknown_keys[i].name;
122 }
123 }
124 return NULL;
125 }
126
127 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
128 Error **errp)
129 {
130 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
131 }
132
133 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
134 const char *cmdline, const char *boot_devices,
135 ram_addr_t RAM_size, uint32_t kernel_size,
136 int width, int height, int depth,
137 int nvram_machine_id, const char *arch)
138 {
139 unsigned int i;
140 int sysp_end;
141 uint8_t image[0x1ff0];
142 NvramClass *k = NVRAM_GET_CLASS(nvram);
143
144 memset(image, '\0', sizeof(image));
145
146 /* OpenBIOS nvram variables partition */
147 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
148
149 /* Free space partition */
150 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
151
152 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
153 nvram_machine_id);
154
155 for (i = 0; i < sizeof(image); i++) {
156 (k->write)(nvram, i, image[i]);
157 }
158 }
159
160 void cpu_check_irqs(CPUSPARCState *env)
161 {
162 CPUState *cs;
163
164 /* We should be holding the BQL before we mess with IRQs */
165 g_assert(qemu_mutex_iothread_locked());
166
167 if (env->pil_in && (env->interrupt_index == 0 ||
168 (env->interrupt_index & ~15) == TT_EXTINT)) {
169 unsigned int i;
170
171 for (i = 15; i > 0; i--) {
172 if (env->pil_in & (1 << i)) {
173 int old_interrupt = env->interrupt_index;
174
175 env->interrupt_index = TT_EXTINT | i;
176 if (old_interrupt != env->interrupt_index) {
177 cs = env_cpu(env);
178 trace_sun4m_cpu_interrupt(i);
179 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
180 }
181 break;
182 }
183 }
184 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
185 cs = env_cpu(env);
186 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
187 env->interrupt_index = 0;
188 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
189 }
190 }
191
192 static void cpu_kick_irq(SPARCCPU *cpu)
193 {
194 CPUSPARCState *env = &cpu->env;
195 CPUState *cs = CPU(cpu);
196
197 cs->halted = 0;
198 cpu_check_irqs(env);
199 qemu_cpu_kick(cs);
200 }
201
202 static void cpu_set_irq(void *opaque, int irq, int level)
203 {
204 SPARCCPU *cpu = opaque;
205 CPUSPARCState *env = &cpu->env;
206
207 if (level) {
208 trace_sun4m_cpu_set_irq_raise(irq);
209 env->pil_in |= 1 << irq;
210 cpu_kick_irq(cpu);
211 } else {
212 trace_sun4m_cpu_set_irq_lower(irq);
213 env->pil_in &= ~(1 << irq);
214 cpu_check_irqs(env);
215 }
216 }
217
218 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
219 {
220 }
221
222 static void sun4m_cpu_reset(void *opaque)
223 {
224 SPARCCPU *cpu = opaque;
225 CPUState *cs = CPU(cpu);
226
227 cpu_reset(cs);
228 }
229
230 static void cpu_halt_signal(void *opaque, int irq, int level)
231 {
232 if (level && current_cpu) {
233 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
234 }
235 }
236
237 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
238 {
239 return addr - 0xf0000000ULL;
240 }
241
242 static unsigned long sun4m_load_kernel(const char *kernel_filename,
243 const char *initrd_filename,
244 ram_addr_t RAM_size,
245 uint32_t *initrd_size)
246 {
247 int linux_boot;
248 unsigned int i;
249 long kernel_size;
250 uint8_t *ptr;
251
252 linux_boot = (kernel_filename != NULL);
253
254 kernel_size = 0;
255 if (linux_boot) {
256 int bswap_needed;
257
258 #ifdef BSWAP_NEEDED
259 bswap_needed = 1;
260 #else
261 bswap_needed = 0;
262 #endif
263 kernel_size = load_elf(kernel_filename, NULL,
264 translate_kernel_address, NULL,
265 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
266 if (kernel_size < 0)
267 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
268 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
269 TARGET_PAGE_SIZE);
270 if (kernel_size < 0)
271 kernel_size = load_image_targphys(kernel_filename,
272 KERNEL_LOAD_ADDR,
273 RAM_size - KERNEL_LOAD_ADDR);
274 if (kernel_size < 0) {
275 error_report("could not load kernel '%s'", kernel_filename);
276 exit(1);
277 }
278
279 /* load initrd */
280 *initrd_size = 0;
281 if (initrd_filename) {
282 *initrd_size = load_image_targphys(initrd_filename,
283 INITRD_LOAD_ADDR,
284 RAM_size - INITRD_LOAD_ADDR);
285 if ((int)*initrd_size < 0) {
286 error_report("could not load initial ram disk '%s'",
287 initrd_filename);
288 exit(1);
289 }
290 }
291 if (*initrd_size > 0) {
292 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
293 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
294 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
295 stl_p(ptr + 16, INITRD_LOAD_ADDR);
296 stl_p(ptr + 20, *initrd_size);
297 break;
298 }
299 }
300 }
301 }
302 return kernel_size;
303 }
304
305 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
306 {
307 DeviceState *dev;
308 SysBusDevice *s;
309
310 dev = qdev_new(TYPE_SUN4M_IOMMU);
311 qdev_prop_set_uint32(dev, "version", version);
312 s = SYS_BUS_DEVICE(dev);
313 sysbus_realize_and_unref(s, &error_fatal);
314 sysbus_connect_irq(s, 0, irq);
315 sysbus_mmio_map(s, 0, addr);
316
317 return s;
318 }
319
320 static void *sparc32_dma_init(hwaddr dma_base,
321 hwaddr esp_base, qemu_irq espdma_irq,
322 hwaddr le_base, qemu_irq ledma_irq)
323 {
324 DeviceState *dma;
325 ESPDMADeviceState *espdma;
326 LEDMADeviceState *ledma;
327 SysBusESPState *esp;
328 SysBusPCNetState *lance;
329
330 dma = qdev_new(TYPE_SPARC32_DMA);
331 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
332 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
333
334 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
335 OBJECT(dma), "espdma"));
336 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
337
338 esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
339 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
340 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
341
342 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
343 OBJECT(dma), "ledma"));
344 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
345
346 lance = SYSBUS_PCNET(object_resolve_path_component(
347 OBJECT(ledma), "lance"));
348 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
349
350 return dma;
351 }
352
353 static DeviceState *slavio_intctl_init(hwaddr addr,
354 hwaddr addrg,
355 qemu_irq **parent_irq)
356 {
357 DeviceState *dev;
358 SysBusDevice *s;
359 unsigned int i, j;
360
361 dev = qdev_new("slavio_intctl");
362
363 s = SYS_BUS_DEVICE(dev);
364 sysbus_realize_and_unref(s, &error_fatal);
365
366 for (i = 0; i < MAX_CPUS; i++) {
367 for (j = 0; j < MAX_PILS; j++) {
368 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
369 }
370 }
371 sysbus_mmio_map(s, 0, addrg);
372 for (i = 0; i < MAX_CPUS; i++) {
373 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
374 }
375
376 return dev;
377 }
378
379 #define SYS_TIMER_OFFSET 0x10000ULL
380 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
381
382 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
383 qemu_irq *cpu_irqs, unsigned int num_cpus)
384 {
385 DeviceState *dev;
386 SysBusDevice *s;
387 unsigned int i;
388
389 dev = qdev_new("slavio_timer");
390 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
391 s = SYS_BUS_DEVICE(dev);
392 sysbus_realize_and_unref(s, &error_fatal);
393 sysbus_connect_irq(s, 0, master_irq);
394 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
395
396 for (i = 0; i < MAX_CPUS; i++) {
397 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
398 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
399 }
400 }
401
402 static qemu_irq slavio_system_powerdown;
403
404 static void slavio_powerdown_req(Notifier *n, void *opaque)
405 {
406 qemu_irq_raise(slavio_system_powerdown);
407 }
408
409 static Notifier slavio_system_powerdown_notifier = {
410 .notify = slavio_powerdown_req
411 };
412
413 #define MISC_LEDS 0x01600000
414 #define MISC_CFG 0x01800000
415 #define MISC_DIAG 0x01a00000
416 #define MISC_MDM 0x01b00000
417 #define MISC_SYS 0x01f00000
418
419 static void slavio_misc_init(hwaddr base,
420 hwaddr aux1_base,
421 hwaddr aux2_base, qemu_irq irq,
422 qemu_irq fdc_tc)
423 {
424 DeviceState *dev;
425 SysBusDevice *s;
426
427 dev = qdev_new("slavio_misc");
428 s = SYS_BUS_DEVICE(dev);
429 sysbus_realize_and_unref(s, &error_fatal);
430 if (base) {
431 /* 8 bit registers */
432 /* Slavio control */
433 sysbus_mmio_map(s, 0, base + MISC_CFG);
434 /* Diagnostics */
435 sysbus_mmio_map(s, 1, base + MISC_DIAG);
436 /* Modem control */
437 sysbus_mmio_map(s, 2, base + MISC_MDM);
438 /* 16 bit registers */
439 /* ss600mp diag LEDs */
440 sysbus_mmio_map(s, 3, base + MISC_LEDS);
441 /* 32 bit registers */
442 /* System control */
443 sysbus_mmio_map(s, 4, base + MISC_SYS);
444 }
445 if (aux1_base) {
446 /* AUX 1 (Misc System Functions) */
447 sysbus_mmio_map(s, 5, aux1_base);
448 }
449 if (aux2_base) {
450 /* AUX 2 (Software Powerdown Control) */
451 sysbus_mmio_map(s, 6, aux2_base);
452 }
453 sysbus_connect_irq(s, 0, irq);
454 sysbus_connect_irq(s, 1, fdc_tc);
455 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
456 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
457 }
458
459 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
460 {
461 DeviceState *dev;
462 SysBusDevice *s;
463
464 dev = qdev_new("eccmemctl");
465 qdev_prop_set_uint32(dev, "version", version);
466 s = SYS_BUS_DEVICE(dev);
467 sysbus_realize_and_unref(s, &error_fatal);
468 sysbus_connect_irq(s, 0, irq);
469 sysbus_mmio_map(s, 0, base);
470 if (version == 0) { // SS-600MP only
471 sysbus_mmio_map(s, 1, base + 0x1000);
472 }
473 }
474
475 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
476 {
477 DeviceState *dev;
478 SysBusDevice *s;
479
480 dev = qdev_new("apc");
481 s = SYS_BUS_DEVICE(dev);
482 sysbus_realize_and_unref(s, &error_fatal);
483 /* Power management (APC) XXX: not a Slavio device */
484 sysbus_mmio_map(s, 0, power_base);
485 sysbus_connect_irq(s, 0, cpu_halt);
486 }
487
488 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
489 int height, int depth)
490 {
491 DeviceState *dev;
492 SysBusDevice *s;
493
494 dev = qdev_new("SUNW,tcx");
495 qdev_prop_set_uint32(dev, "vram_size", vram_size);
496 qdev_prop_set_uint16(dev, "width", width);
497 qdev_prop_set_uint16(dev, "height", height);
498 qdev_prop_set_uint16(dev, "depth", depth);
499 s = SYS_BUS_DEVICE(dev);
500 sysbus_realize_and_unref(s, &error_fatal);
501
502 /* 10/ROM : FCode ROM */
503 sysbus_mmio_map(s, 0, addr);
504 /* 2/STIP : Stipple */
505 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
506 /* 3/BLIT : Blitter */
507 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
508 /* 5/RSTIP : Raw Stipple */
509 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
510 /* 6/RBLIT : Raw Blitter */
511 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
512 /* 7/TEC : Transform Engine */
513 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
514 /* 8/CMAP : DAC */
515 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
516 /* 9/THC : */
517 if (depth == 8) {
518 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
519 } else {
520 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
521 }
522 /* 11/DHC : */
523 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
524 /* 12/ALT : */
525 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
526 /* 0/DFB8 : 8-bit plane */
527 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
528 /* 1/DFB24 : 24bit plane */
529 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
530 /* 4/RDFB32: Raw framebuffer. Control plane */
531 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
532 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
533 if (depth == 8) {
534 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
535 }
536
537 sysbus_connect_irq(s, 0, irq);
538 }
539
540 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
541 int height, int depth)
542 {
543 DeviceState *dev;
544 SysBusDevice *s;
545
546 dev = qdev_new("cgthree");
547 qdev_prop_set_uint32(dev, "vram-size", vram_size);
548 qdev_prop_set_uint16(dev, "width", width);
549 qdev_prop_set_uint16(dev, "height", height);
550 qdev_prop_set_uint16(dev, "depth", depth);
551 s = SYS_BUS_DEVICE(dev);
552 sysbus_realize_and_unref(s, &error_fatal);
553
554 /* FCode ROM */
555 sysbus_mmio_map(s, 0, addr);
556 /* DAC */
557 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
558 /* 8-bit plane */
559 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
560
561 sysbus_connect_irq(s, 0, irq);
562 }
563
564 /* NCR89C100/MACIO Internal ID register */
565
566 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
567
568 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
569
570 static void idreg_init(hwaddr addr)
571 {
572 DeviceState *dev;
573 SysBusDevice *s;
574
575 dev = qdev_new(TYPE_MACIO_ID_REGISTER);
576 s = SYS_BUS_DEVICE(dev);
577 sysbus_realize_and_unref(s, &error_fatal);
578
579 sysbus_mmio_map(s, 0, addr);
580 address_space_write_rom(&address_space_memory, addr,
581 MEMTXATTRS_UNSPECIFIED,
582 idreg_data, sizeof(idreg_data));
583 }
584
585 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER)
586
587 struct IDRegState {
588 SysBusDevice parent_obj;
589
590 MemoryRegion mem;
591 };
592
593 static void idreg_realize(DeviceState *ds, Error **errp)
594 {
595 IDRegState *s = MACIO_ID_REGISTER(ds);
596 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
597 Error *local_err = NULL;
598
599 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
600 sizeof(idreg_data), &local_err);
601 if (local_err) {
602 error_propagate(errp, local_err);
603 return;
604 }
605
606 vmstate_register_ram_global(&s->mem);
607 memory_region_set_readonly(&s->mem, true);
608 sysbus_init_mmio(dev, &s->mem);
609 }
610
611 static void idreg_class_init(ObjectClass *oc, void *data)
612 {
613 DeviceClass *dc = DEVICE_CLASS(oc);
614
615 dc->realize = idreg_realize;
616 }
617
618 static const TypeInfo idreg_info = {
619 .name = TYPE_MACIO_ID_REGISTER,
620 .parent = TYPE_SYS_BUS_DEVICE,
621 .instance_size = sizeof(IDRegState),
622 .class_init = idreg_class_init,
623 };
624
625 #define TYPE_TCX_AFX "tcx_afx"
626 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX)
627
628 struct AFXState {
629 SysBusDevice parent_obj;
630
631 MemoryRegion mem;
632 };
633
634 /* SS-5 TCX AFX register */
635 static void afx_init(hwaddr addr)
636 {
637 DeviceState *dev;
638 SysBusDevice *s;
639
640 dev = qdev_new(TYPE_TCX_AFX);
641 s = SYS_BUS_DEVICE(dev);
642 sysbus_realize_and_unref(s, &error_fatal);
643
644 sysbus_mmio_map(s, 0, addr);
645 }
646
647 static void afx_realize(DeviceState *ds, Error **errp)
648 {
649 AFXState *s = TCX_AFX(ds);
650 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
651 Error *local_err = NULL;
652
653 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
654 &local_err);
655 if (local_err) {
656 error_propagate(errp, local_err);
657 return;
658 }
659
660 vmstate_register_ram_global(&s->mem);
661 sysbus_init_mmio(dev, &s->mem);
662 }
663
664 static void afx_class_init(ObjectClass *oc, void *data)
665 {
666 DeviceClass *dc = DEVICE_CLASS(oc);
667
668 dc->realize = afx_realize;
669 }
670
671 static const TypeInfo afx_info = {
672 .name = TYPE_TCX_AFX,
673 .parent = TYPE_SYS_BUS_DEVICE,
674 .instance_size = sizeof(AFXState),
675 .class_init = afx_class_init,
676 };
677
678 #define TYPE_OPENPROM "openprom"
679 typedef struct PROMState PROMState;
680 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
681 TYPE_OPENPROM)
682
683 struct PROMState {
684 SysBusDevice parent_obj;
685
686 MemoryRegion prom;
687 };
688
689 /* Boot PROM (OpenBIOS) */
690 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
691 {
692 hwaddr *base_addr = (hwaddr *)opaque;
693 return addr + *base_addr - PROM_VADDR;
694 }
695
696 static void prom_init(hwaddr addr, const char *bios_name)
697 {
698 DeviceState *dev;
699 SysBusDevice *s;
700 char *filename;
701 int ret;
702
703 dev = qdev_new(TYPE_OPENPROM);
704 s = SYS_BUS_DEVICE(dev);
705 sysbus_realize_and_unref(s, &error_fatal);
706
707 sysbus_mmio_map(s, 0, addr);
708
709 /* load boot prom */
710 if (bios_name == NULL) {
711 bios_name = PROM_FILENAME;
712 }
713 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
714 if (filename) {
715 ret = load_elf(filename, NULL,
716 translate_prom_address, &addr, NULL,
717 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
718 if (ret < 0 || ret > PROM_SIZE_MAX) {
719 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
720 }
721 g_free(filename);
722 } else {
723 ret = -1;
724 }
725 if (ret < 0 || ret > PROM_SIZE_MAX) {
726 error_report("could not load prom '%s'", bios_name);
727 exit(1);
728 }
729 }
730
731 static void prom_realize(DeviceState *ds, Error **errp)
732 {
733 PROMState *s = OPENPROM(ds);
734 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
735 Error *local_err = NULL;
736
737 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
738 PROM_SIZE_MAX, &local_err);
739 if (local_err) {
740 error_propagate(errp, local_err);
741 return;
742 }
743
744 vmstate_register_ram_global(&s->prom);
745 memory_region_set_readonly(&s->prom, true);
746 sysbus_init_mmio(dev, &s->prom);
747 }
748
749 static Property prom_properties[] = {
750 {/* end of property list */},
751 };
752
753 static void prom_class_init(ObjectClass *klass, void *data)
754 {
755 DeviceClass *dc = DEVICE_CLASS(klass);
756
757 device_class_set_props(dc, prom_properties);
758 dc->realize = prom_realize;
759 }
760
761 static const TypeInfo prom_info = {
762 .name = TYPE_OPENPROM,
763 .parent = TYPE_SYS_BUS_DEVICE,
764 .instance_size = sizeof(PROMState),
765 .class_init = prom_class_init,
766 };
767
768 #define TYPE_SUN4M_MEMORY "memory"
769 typedef struct RamDevice RamDevice;
770 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM,
771 TYPE_SUN4M_MEMORY)
772
773 struct RamDevice {
774 SysBusDevice parent_obj;
775 HostMemoryBackend *memdev;
776 };
777
778 /* System RAM */
779 static void ram_realize(DeviceState *dev, Error **errp)
780 {
781 RamDevice *d = SUN4M_RAM(dev);
782 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
783
784 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
785 }
786
787 static void ram_initfn(Object *obj)
788 {
789 RamDevice *d = SUN4M_RAM(obj);
790 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
791 (Object **)&d->memdev,
792 object_property_allow_set_link,
793 OBJ_PROP_LINK_STRONG);
794 object_property_set_description(obj, "memdev", "Set RAM backend"
795 "Valid value is ID of a hostmem backend");
796 }
797
798 static void ram_class_init(ObjectClass *klass, void *data)
799 {
800 DeviceClass *dc = DEVICE_CLASS(klass);
801
802 dc->realize = ram_realize;
803 }
804
805 static const TypeInfo ram_info = {
806 .name = TYPE_SUN4M_MEMORY,
807 .parent = TYPE_SYS_BUS_DEVICE,
808 .instance_size = sizeof(RamDevice),
809 .instance_init = ram_initfn,
810 .class_init = ram_class_init,
811 };
812
813 static void cpu_devinit(const char *cpu_type, unsigned int id,
814 uint64_t prom_addr, qemu_irq **cpu_irqs)
815 {
816 SPARCCPU *cpu;
817 CPUSPARCState *env;
818
819 cpu = SPARC_CPU(object_new(cpu_type));
820 env = &cpu->env;
821
822 cpu_sparc_set_id(env, id);
823 qemu_register_reset(sun4m_cpu_reset, cpu);
824 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
825 &error_fatal);
826 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
827 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
828 env->prom_addr = prom_addr;
829 }
830
831 static void dummy_fdc_tc(void *opaque, int irq, int level)
832 {
833 }
834
835 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
836 MachineState *machine)
837 {
838 DeviceState *slavio_intctl;
839 unsigned int i;
840 Nvram *nvram;
841 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
842 qemu_irq fdc_tc;
843 unsigned long kernel_size;
844 uint32_t initrd_size;
845 DriveInfo *fd[MAX_FD];
846 FWCfgState *fw_cfg;
847 DeviceState *dev;
848 SysBusDevice *s;
849 unsigned int smp_cpus = machine->smp.cpus;
850 unsigned int max_cpus = machine->smp.max_cpus;
851 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
852 TYPE_MEMORY_BACKEND, NULL);
853
854 if (machine->ram_size > hwdef->max_mem) {
855 error_report("Too much memory for this machine: %" PRId64 ","
856 " maximum %" PRId64,
857 machine->ram_size / MiB, hwdef->max_mem / MiB);
858 exit(1);
859 }
860
861 /* init CPUs */
862 for(i = 0; i < smp_cpus; i++) {
863 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
864 }
865
866 for (i = smp_cpus; i < MAX_CPUS; i++)
867 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
868
869 /* Create and map RAM frontend */
870 dev = qdev_new("memory");
871 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal);
872 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
873 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
874
875 /* models without ECC don't trap when missing ram is accessed */
876 if (!hwdef->ecc_base) {
877 empty_slot_init("ecc", machine->ram_size,
878 hwdef->max_mem - machine->ram_size);
879 }
880
881 prom_init(hwdef->slavio_base, bios_name);
882
883 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
884 hwdef->intctl_base + 0x10000ULL,
885 cpu_irqs);
886
887 for (i = 0; i < 32; i++) {
888 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
889 }
890 for (i = 0; i < MAX_CPUS; i++) {
891 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
892 }
893
894 if (hwdef->idreg_base) {
895 idreg_init(hwdef->idreg_base);
896 }
897
898 if (hwdef->afx_base) {
899 afx_init(hwdef->afx_base);
900 }
901
902 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
903
904 if (hwdef->iommu_pad_base) {
905 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
906 Software shouldn't use aliased addresses, neither should it crash
907 when does. Using empty_slot instead of aliasing can help with
908 debugging such accesses */
909 empty_slot_init("iommu.alias",
910 hwdef->iommu_pad_base, hwdef->iommu_pad_len);
911 }
912
913 sparc32_dma_init(hwdef->dma_base,
914 hwdef->esp_base, slavio_irq[18],
915 hwdef->le_base, slavio_irq[16]);
916
917 if (graphic_depth != 8 && graphic_depth != 24) {
918 error_report("Unsupported depth: %d", graphic_depth);
919 exit (1);
920 }
921 if (vga_interface_type != VGA_NONE) {
922 if (vga_interface_type == VGA_CG3) {
923 if (graphic_depth != 8) {
924 error_report("Unsupported depth: %d", graphic_depth);
925 exit(1);
926 }
927
928 if (!(graphic_width == 1024 && graphic_height == 768) &&
929 !(graphic_width == 1152 && graphic_height == 900)) {
930 error_report("Unsupported resolution: %d x %d", graphic_width,
931 graphic_height);
932 exit(1);
933 }
934
935 /* sbus irq 5 */
936 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
937 graphic_width, graphic_height, graphic_depth);
938 } else {
939 /* If no display specified, default to TCX */
940 if (graphic_depth != 8 && graphic_depth != 24) {
941 error_report("Unsupported depth: %d", graphic_depth);
942 exit(1);
943 }
944
945 if (!(graphic_width == 1024 && graphic_height == 768)) {
946 error_report("Unsupported resolution: %d x %d",
947 graphic_width, graphic_height);
948 exit(1);
949 }
950
951 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
952 graphic_width, graphic_height, graphic_depth);
953 }
954 }
955
956 for (i = 0; i < MAX_VSIMMS; i++) {
957 /* vsimm registers probed by OBP */
958 if (hwdef->vsimm[i].reg_base) {
959 char *name = g_strdup_printf("vsimm[%d]", i);
960 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
961 g_free(name);
962 }
963 }
964
965 if (hwdef->sx_base) {
966 create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
967 }
968
969 dev = qdev_new("sysbus-m48t08");
970 qdev_prop_set_int32(dev, "base-year", 1968);
971 s = SYS_BUS_DEVICE(dev);
972 sysbus_realize_and_unref(s, &error_fatal);
973 sysbus_connect_irq(s, 0, slavio_irq[0]);
974 sysbus_mmio_map(s, 0, hwdef->nvram_base);
975 nvram = NVRAM(dev);
976
977 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
978
979 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
980 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
981 dev = qdev_new(TYPE_ESCC);
982 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
983 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
984 qdev_prop_set_uint32(dev, "it_shift", 1);
985 qdev_prop_set_chr(dev, "chrB", NULL);
986 qdev_prop_set_chr(dev, "chrA", NULL);
987 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
988 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
989 s = SYS_BUS_DEVICE(dev);
990 sysbus_realize_and_unref(s, &error_fatal);
991 sysbus_connect_irq(s, 0, slavio_irq[14]);
992 sysbus_connect_irq(s, 1, slavio_irq[14]);
993 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
994
995 dev = qdev_new(TYPE_ESCC);
996 qdev_prop_set_uint32(dev, "disabled", 0);
997 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
998 qdev_prop_set_uint32(dev, "it_shift", 1);
999 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1000 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1001 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1002 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1003
1004 s = SYS_BUS_DEVICE(dev);
1005 sysbus_realize_and_unref(s, &error_fatal);
1006 sysbus_connect_irq(s, 0, slavio_irq[15]);
1007 sysbus_connect_irq(s, 1, slavio_irq[15]);
1008 sysbus_mmio_map(s, 0, hwdef->serial_base);
1009
1010 if (hwdef->apc_base) {
1011 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1012 }
1013
1014 if (hwdef->fd_base) {
1015 /* there is zero or one floppy drive */
1016 memset(fd, 0, sizeof(fd));
1017 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1018 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1019 &fdc_tc);
1020 } else {
1021 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1022 }
1023
1024 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1025 slavio_irq[30], fdc_tc);
1026
1027 if (hwdef->cs_base) {
1028 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1029 slavio_irq[5]);
1030 }
1031
1032 if (hwdef->dbri_base) {
1033 /* ISDN chip with attached CS4215 audio codec */
1034 /* prom space */
1035 create_unimplemented_device("SUNW,DBRI.prom",
1036 hwdef->dbri_base + 0x1000, 0x30);
1037 /* reg space */
1038 create_unimplemented_device("SUNW,DBRI",
1039 hwdef->dbri_base + 0x10000, 0x100);
1040 }
1041
1042 if (hwdef->bpp_base) {
1043 /* parallel port */
1044 create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20);
1045 }
1046
1047 initrd_size = 0;
1048 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1049 machine->initrd_filename,
1050 machine->ram_size, &initrd_size);
1051
1052 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1053 machine->boot_order, machine->ram_size, kernel_size,
1054 graphic_width, graphic_height, graphic_depth,
1055 hwdef->nvram_machine_id, "Sun4m");
1056
1057 if (hwdef->ecc_base)
1058 ecc_init(hwdef->ecc_base, slavio_irq[28],
1059 hwdef->ecc_version);
1060
1061 dev = qdev_new(TYPE_FW_CFG_MEM);
1062 fw_cfg = FW_CFG(dev);
1063 qdev_prop_set_uint32(dev, "data_width", 1);
1064 qdev_prop_set_bit(dev, "dma_enabled", false);
1065 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1066 OBJECT(fw_cfg));
1067 s = SYS_BUS_DEVICE(dev);
1068 sysbus_realize_and_unref(s, &error_fatal);
1069 sysbus_mmio_map(s, 0, CFG_ADDR);
1070 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1071
1072 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1073 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1074 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1075 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1077 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1078 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1080 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1081 if (machine->kernel_cmdline) {
1082 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1083 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1084 machine->kernel_cmdline);
1085 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1086 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1087 strlen(machine->kernel_cmdline) + 1);
1088 } else {
1089 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1090 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1091 }
1092 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1093 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1094 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1095 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1096 }
1097
1098 enum {
1099 ss5_id = 32,
1100 vger_id,
1101 lx_id,
1102 ss4_id,
1103 scls_id,
1104 sbook_id,
1105 ss10_id = 64,
1106 ss20_id,
1107 ss600mp_id,
1108 };
1109
1110 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1111 /* SS-5 */
1112 {
1113 .iommu_base = 0x10000000,
1114 .iommu_pad_base = 0x10004000,
1115 .iommu_pad_len = 0x0fffb000,
1116 .tcx_base = 0x50000000,
1117 .cs_base = 0x6c000000,
1118 .slavio_base = 0x70000000,
1119 .ms_kb_base = 0x71000000,
1120 .serial_base = 0x71100000,
1121 .nvram_base = 0x71200000,
1122 .fd_base = 0x71400000,
1123 .counter_base = 0x71d00000,
1124 .intctl_base = 0x71e00000,
1125 .idreg_base = 0x78000000,
1126 .dma_base = 0x78400000,
1127 .esp_base = 0x78800000,
1128 .le_base = 0x78c00000,
1129 .apc_base = 0x6a000000,
1130 .afx_base = 0x6e000000,
1131 .aux1_base = 0x71900000,
1132 .aux2_base = 0x71910000,
1133 .nvram_machine_id = 0x80,
1134 .machine_id = ss5_id,
1135 .iommu_version = 0x05000000,
1136 .max_mem = 0x10000000,
1137 },
1138 /* SS-10 */
1139 {
1140 .iommu_base = 0xfe0000000ULL,
1141 .tcx_base = 0xe20000000ULL,
1142 .slavio_base = 0xff0000000ULL,
1143 .ms_kb_base = 0xff1000000ULL,
1144 .serial_base = 0xff1100000ULL,
1145 .nvram_base = 0xff1200000ULL,
1146 .fd_base = 0xff1700000ULL,
1147 .counter_base = 0xff1300000ULL,
1148 .intctl_base = 0xff1400000ULL,
1149 .idreg_base = 0xef0000000ULL,
1150 .dma_base = 0xef0400000ULL,
1151 .esp_base = 0xef0800000ULL,
1152 .le_base = 0xef0c00000ULL,
1153 .apc_base = 0xefa000000ULL, // XXX should not exist
1154 .aux1_base = 0xff1800000ULL,
1155 .aux2_base = 0xff1a01000ULL,
1156 .ecc_base = 0xf00000000ULL,
1157 .ecc_version = 0x10000000, // version 0, implementation 1
1158 .nvram_machine_id = 0x72,
1159 .machine_id = ss10_id,
1160 .iommu_version = 0x03000000,
1161 .max_mem = 0xf00000000ULL,
1162 },
1163 /* SS-600MP */
1164 {
1165 .iommu_base = 0xfe0000000ULL,
1166 .tcx_base = 0xe20000000ULL,
1167 .slavio_base = 0xff0000000ULL,
1168 .ms_kb_base = 0xff1000000ULL,
1169 .serial_base = 0xff1100000ULL,
1170 .nvram_base = 0xff1200000ULL,
1171 .counter_base = 0xff1300000ULL,
1172 .intctl_base = 0xff1400000ULL,
1173 .dma_base = 0xef0081000ULL,
1174 .esp_base = 0xef0080000ULL,
1175 .le_base = 0xef0060000ULL,
1176 .apc_base = 0xefa000000ULL, // XXX should not exist
1177 .aux1_base = 0xff1800000ULL,
1178 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1179 .ecc_base = 0xf00000000ULL,
1180 .ecc_version = 0x00000000, // version 0, implementation 0
1181 .nvram_machine_id = 0x71,
1182 .machine_id = ss600mp_id,
1183 .iommu_version = 0x01000000,
1184 .max_mem = 0xf00000000ULL,
1185 },
1186 /* SS-20 */
1187 {
1188 .iommu_base = 0xfe0000000ULL,
1189 .tcx_base = 0xe20000000ULL,
1190 .slavio_base = 0xff0000000ULL,
1191 .ms_kb_base = 0xff1000000ULL,
1192 .serial_base = 0xff1100000ULL,
1193 .nvram_base = 0xff1200000ULL,
1194 .fd_base = 0xff1700000ULL,
1195 .counter_base = 0xff1300000ULL,
1196 .intctl_base = 0xff1400000ULL,
1197 .idreg_base = 0xef0000000ULL,
1198 .dma_base = 0xef0400000ULL,
1199 .esp_base = 0xef0800000ULL,
1200 .le_base = 0xef0c00000ULL,
1201 .bpp_base = 0xef4800000ULL,
1202 .apc_base = 0xefa000000ULL, // XXX should not exist
1203 .aux1_base = 0xff1800000ULL,
1204 .aux2_base = 0xff1a01000ULL,
1205 .dbri_base = 0xee0000000ULL,
1206 .sx_base = 0xf80000000ULL,
1207 .vsimm = {
1208 {
1209 .reg_base = 0x9c000000ULL,
1210 .vram_base = 0xfc000000ULL
1211 }, {
1212 .reg_base = 0x90000000ULL,
1213 .vram_base = 0xf0000000ULL
1214 }, {
1215 .reg_base = 0x94000000ULL
1216 }, {
1217 .reg_base = 0x98000000ULL
1218 }
1219 },
1220 .ecc_base = 0xf00000000ULL,
1221 .ecc_version = 0x20000000, // version 0, implementation 2
1222 .nvram_machine_id = 0x72,
1223 .machine_id = ss20_id,
1224 .iommu_version = 0x13000000,
1225 .max_mem = 0xf00000000ULL,
1226 },
1227 /* Voyager */
1228 {
1229 .iommu_base = 0x10000000,
1230 .tcx_base = 0x50000000,
1231 .slavio_base = 0x70000000,
1232 .ms_kb_base = 0x71000000,
1233 .serial_base = 0x71100000,
1234 .nvram_base = 0x71200000,
1235 .fd_base = 0x71400000,
1236 .counter_base = 0x71d00000,
1237 .intctl_base = 0x71e00000,
1238 .idreg_base = 0x78000000,
1239 .dma_base = 0x78400000,
1240 .esp_base = 0x78800000,
1241 .le_base = 0x78c00000,
1242 .apc_base = 0x71300000, // pmc
1243 .aux1_base = 0x71900000,
1244 .aux2_base = 0x71910000,
1245 .nvram_machine_id = 0x80,
1246 .machine_id = vger_id,
1247 .iommu_version = 0x05000000,
1248 .max_mem = 0x10000000,
1249 },
1250 /* LX */
1251 {
1252 .iommu_base = 0x10000000,
1253 .iommu_pad_base = 0x10004000,
1254 .iommu_pad_len = 0x0fffb000,
1255 .tcx_base = 0x50000000,
1256 .slavio_base = 0x70000000,
1257 .ms_kb_base = 0x71000000,
1258 .serial_base = 0x71100000,
1259 .nvram_base = 0x71200000,
1260 .fd_base = 0x71400000,
1261 .counter_base = 0x71d00000,
1262 .intctl_base = 0x71e00000,
1263 .idreg_base = 0x78000000,
1264 .dma_base = 0x78400000,
1265 .esp_base = 0x78800000,
1266 .le_base = 0x78c00000,
1267 .aux1_base = 0x71900000,
1268 .aux2_base = 0x71910000,
1269 .nvram_machine_id = 0x80,
1270 .machine_id = lx_id,
1271 .iommu_version = 0x04000000,
1272 .max_mem = 0x10000000,
1273 },
1274 /* SS-4 */
1275 {
1276 .iommu_base = 0x10000000,
1277 .tcx_base = 0x50000000,
1278 .cs_base = 0x6c000000,
1279 .slavio_base = 0x70000000,
1280 .ms_kb_base = 0x71000000,
1281 .serial_base = 0x71100000,
1282 .nvram_base = 0x71200000,
1283 .fd_base = 0x71400000,
1284 .counter_base = 0x71d00000,
1285 .intctl_base = 0x71e00000,
1286 .idreg_base = 0x78000000,
1287 .dma_base = 0x78400000,
1288 .esp_base = 0x78800000,
1289 .le_base = 0x78c00000,
1290 .apc_base = 0x6a000000,
1291 .aux1_base = 0x71900000,
1292 .aux2_base = 0x71910000,
1293 .nvram_machine_id = 0x80,
1294 .machine_id = ss4_id,
1295 .iommu_version = 0x05000000,
1296 .max_mem = 0x10000000,
1297 },
1298 /* SPARCClassic */
1299 {
1300 .iommu_base = 0x10000000,
1301 .tcx_base = 0x50000000,
1302 .slavio_base = 0x70000000,
1303 .ms_kb_base = 0x71000000,
1304 .serial_base = 0x71100000,
1305 .nvram_base = 0x71200000,
1306 .fd_base = 0x71400000,
1307 .counter_base = 0x71d00000,
1308 .intctl_base = 0x71e00000,
1309 .idreg_base = 0x78000000,
1310 .dma_base = 0x78400000,
1311 .esp_base = 0x78800000,
1312 .le_base = 0x78c00000,
1313 .apc_base = 0x6a000000,
1314 .aux1_base = 0x71900000,
1315 .aux2_base = 0x71910000,
1316 .nvram_machine_id = 0x80,
1317 .machine_id = scls_id,
1318 .iommu_version = 0x05000000,
1319 .max_mem = 0x10000000,
1320 },
1321 /* SPARCbook */
1322 {
1323 .iommu_base = 0x10000000,
1324 .tcx_base = 0x50000000, // XXX
1325 .slavio_base = 0x70000000,
1326 .ms_kb_base = 0x71000000,
1327 .serial_base = 0x71100000,
1328 .nvram_base = 0x71200000,
1329 .fd_base = 0x71400000,
1330 .counter_base = 0x71d00000,
1331 .intctl_base = 0x71e00000,
1332 .idreg_base = 0x78000000,
1333 .dma_base = 0x78400000,
1334 .esp_base = 0x78800000,
1335 .le_base = 0x78c00000,
1336 .apc_base = 0x6a000000,
1337 .aux1_base = 0x71900000,
1338 .aux2_base = 0x71910000,
1339 .nvram_machine_id = 0x80,
1340 .machine_id = sbook_id,
1341 .iommu_version = 0x05000000,
1342 .max_mem = 0x10000000,
1343 },
1344 };
1345
1346 /* SPARCstation 5 hardware initialisation */
1347 static void ss5_init(MachineState *machine)
1348 {
1349 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1350 }
1351
1352 /* SPARCstation 10 hardware initialisation */
1353 static void ss10_init(MachineState *machine)
1354 {
1355 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1356 }
1357
1358 /* SPARCserver 600MP hardware initialisation */
1359 static void ss600mp_init(MachineState *machine)
1360 {
1361 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1362 }
1363
1364 /* SPARCstation 20 hardware initialisation */
1365 static void ss20_init(MachineState *machine)
1366 {
1367 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1368 }
1369
1370 /* SPARCstation Voyager hardware initialisation */
1371 static void vger_init(MachineState *machine)
1372 {
1373 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1374 }
1375
1376 /* SPARCstation LX hardware initialisation */
1377 static void ss_lx_init(MachineState *machine)
1378 {
1379 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1380 }
1381
1382 /* SPARCstation 4 hardware initialisation */
1383 static void ss4_init(MachineState *machine)
1384 {
1385 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1386 }
1387
1388 /* SPARCClassic hardware initialisation */
1389 static void scls_init(MachineState *machine)
1390 {
1391 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1392 }
1393
1394 /* SPARCbook hardware initialisation */
1395 static void sbook_init(MachineState *machine)
1396 {
1397 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1398 }
1399
1400 static void ss5_class_init(ObjectClass *oc, void *data)
1401 {
1402 MachineClass *mc = MACHINE_CLASS(oc);
1403
1404 mc->desc = "Sun4m platform, SPARCstation 5";
1405 mc->init = ss5_init;
1406 mc->block_default_type = IF_SCSI;
1407 mc->is_default = true;
1408 mc->default_boot_order = "c";
1409 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1410 mc->default_display = "tcx";
1411 mc->default_ram_id = "sun4m.ram";
1412 }
1413
1414 static const TypeInfo ss5_type = {
1415 .name = MACHINE_TYPE_NAME("SS-5"),
1416 .parent = TYPE_MACHINE,
1417 .class_init = ss5_class_init,
1418 };
1419
1420 static void ss10_class_init(ObjectClass *oc, void *data)
1421 {
1422 MachineClass *mc = MACHINE_CLASS(oc);
1423
1424 mc->desc = "Sun4m platform, SPARCstation 10";
1425 mc->init = ss10_init;
1426 mc->block_default_type = IF_SCSI;
1427 mc->max_cpus = 4;
1428 mc->default_boot_order = "c";
1429 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1430 mc->default_display = "tcx";
1431 mc->default_ram_id = "sun4m.ram";
1432 }
1433
1434 static const TypeInfo ss10_type = {
1435 .name = MACHINE_TYPE_NAME("SS-10"),
1436 .parent = TYPE_MACHINE,
1437 .class_init = ss10_class_init,
1438 };
1439
1440 static void ss600mp_class_init(ObjectClass *oc, void *data)
1441 {
1442 MachineClass *mc = MACHINE_CLASS(oc);
1443
1444 mc->desc = "Sun4m platform, SPARCserver 600MP";
1445 mc->init = ss600mp_init;
1446 mc->block_default_type = IF_SCSI;
1447 mc->max_cpus = 4;
1448 mc->default_boot_order = "c";
1449 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1450 mc->default_display = "tcx";
1451 mc->default_ram_id = "sun4m.ram";
1452 }
1453
1454 static const TypeInfo ss600mp_type = {
1455 .name = MACHINE_TYPE_NAME("SS-600MP"),
1456 .parent = TYPE_MACHINE,
1457 .class_init = ss600mp_class_init,
1458 };
1459
1460 static void ss20_class_init(ObjectClass *oc, void *data)
1461 {
1462 MachineClass *mc = MACHINE_CLASS(oc);
1463
1464 mc->desc = "Sun4m platform, SPARCstation 20";
1465 mc->init = ss20_init;
1466 mc->block_default_type = IF_SCSI;
1467 mc->max_cpus = 4;
1468 mc->default_boot_order = "c";
1469 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1470 mc->default_display = "tcx";
1471 mc->default_ram_id = "sun4m.ram";
1472 }
1473
1474 static const TypeInfo ss20_type = {
1475 .name = MACHINE_TYPE_NAME("SS-20"),
1476 .parent = TYPE_MACHINE,
1477 .class_init = ss20_class_init,
1478 };
1479
1480 static void voyager_class_init(ObjectClass *oc, void *data)
1481 {
1482 MachineClass *mc = MACHINE_CLASS(oc);
1483
1484 mc->desc = "Sun4m platform, SPARCstation Voyager";
1485 mc->init = vger_init;
1486 mc->block_default_type = IF_SCSI;
1487 mc->default_boot_order = "c";
1488 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1489 mc->default_display = "tcx";
1490 mc->default_ram_id = "sun4m.ram";
1491 }
1492
1493 static const TypeInfo voyager_type = {
1494 .name = MACHINE_TYPE_NAME("Voyager"),
1495 .parent = TYPE_MACHINE,
1496 .class_init = voyager_class_init,
1497 };
1498
1499 static void ss_lx_class_init(ObjectClass *oc, void *data)
1500 {
1501 MachineClass *mc = MACHINE_CLASS(oc);
1502
1503 mc->desc = "Sun4m platform, SPARCstation LX";
1504 mc->init = ss_lx_init;
1505 mc->block_default_type = IF_SCSI;
1506 mc->default_boot_order = "c";
1507 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1508 mc->default_display = "tcx";
1509 mc->default_ram_id = "sun4m.ram";
1510 }
1511
1512 static const TypeInfo ss_lx_type = {
1513 .name = MACHINE_TYPE_NAME("LX"),
1514 .parent = TYPE_MACHINE,
1515 .class_init = ss_lx_class_init,
1516 };
1517
1518 static void ss4_class_init(ObjectClass *oc, void *data)
1519 {
1520 MachineClass *mc = MACHINE_CLASS(oc);
1521
1522 mc->desc = "Sun4m platform, SPARCstation 4";
1523 mc->init = ss4_init;
1524 mc->block_default_type = IF_SCSI;
1525 mc->default_boot_order = "c";
1526 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1527 mc->default_display = "tcx";
1528 mc->default_ram_id = "sun4m.ram";
1529 }
1530
1531 static const TypeInfo ss4_type = {
1532 .name = MACHINE_TYPE_NAME("SS-4"),
1533 .parent = TYPE_MACHINE,
1534 .class_init = ss4_class_init,
1535 };
1536
1537 static void scls_class_init(ObjectClass *oc, void *data)
1538 {
1539 MachineClass *mc = MACHINE_CLASS(oc);
1540
1541 mc->desc = "Sun4m platform, SPARCClassic";
1542 mc->init = scls_init;
1543 mc->block_default_type = IF_SCSI;
1544 mc->default_boot_order = "c";
1545 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1546 mc->default_display = "tcx";
1547 mc->default_ram_id = "sun4m.ram";
1548 }
1549
1550 static const TypeInfo scls_type = {
1551 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1552 .parent = TYPE_MACHINE,
1553 .class_init = scls_class_init,
1554 };
1555
1556 static void sbook_class_init(ObjectClass *oc, void *data)
1557 {
1558 MachineClass *mc = MACHINE_CLASS(oc);
1559
1560 mc->desc = "Sun4m platform, SPARCbook";
1561 mc->init = sbook_init;
1562 mc->block_default_type = IF_SCSI;
1563 mc->default_boot_order = "c";
1564 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1565 mc->default_display = "tcx";
1566 mc->default_ram_id = "sun4m.ram";
1567 }
1568
1569 static const TypeInfo sbook_type = {
1570 .name = MACHINE_TYPE_NAME("SPARCbook"),
1571 .parent = TYPE_MACHINE,
1572 .class_init = sbook_class_init,
1573 };
1574
1575 static void sun4m_register_types(void)
1576 {
1577 type_register_static(&idreg_info);
1578 type_register_static(&afx_info);
1579 type_register_static(&prom_info);
1580 type_register_static(&ram_info);
1581
1582 type_register_static(&ss5_type);
1583 type_register_static(&ss10_type);
1584 type_register_static(&ss600mp_type);
1585 type_register_static(&ss20_type);
1586 type_register_static(&voyager_type);
1587 type_register_static(&ss_lx_type);
1588 type_register_static(&ss4_type);
1589 type_register_static(&scls_type);
1590 type_register_static(&sbook_type);
1591 }
1592
1593 type_init(sun4m_register_types)
AR7 emulation for QEMU