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Merge tag 'v3.1.0-rc3'
[qemu/ar7.git] / target / i386 / kvm.c
blob81c8997c0a411df4603bd0b85118d1d98009ee69
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "hw/pci/msix.h"
46 #include "migration/blocker.h"
47 #include "exec/memattrs.h"
48 #include "trace.h"
49
50 //#define DEBUG_KVM
51
52 #ifdef DEBUG_KVM
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #else
56 #define DPRINTF(fmt, ...) \
57 do { } while (0)
58 #endif
59
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
62
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
66
67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72 };
73
74 static bool has_msr_star;
75 static bool has_msr_hsave_pa;
76 static bool has_msr_tsc_aux;
77 static bool has_msr_tsc_adjust;
78 static bool has_msr_tsc_deadline;
79 static bool has_msr_feature_control;
80 static bool has_msr_misc_enable;
81 static bool has_msr_smbase;
82 static bool has_msr_bndcfgs;
83 static int lm_capable_kernel;
84 static bool has_msr_hv_hypercall;
85 static bool has_msr_hv_crash;
86 static bool has_msr_hv_reset;
87 static bool has_msr_hv_vpindex;
88 static bool hv_vpindex_settable;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_hv_reenlightenment;
94 static bool has_msr_xss;
95 static bool has_msr_spec_ctrl;
96 static bool has_msr_virt_ssbd;
97 static bool has_msr_smi_count;
98 static bool has_msr_arch_capabs;
99
100 static uint32_t has_architectural_pmu_version;
101 static uint32_t num_architectural_pmu_gp_counters;
102 static uint32_t num_architectural_pmu_fixed_counters;
103
104 static int has_xsave;
105 static int has_xcrs;
106 static int has_pit_state2;
107
108 static bool has_msr_mcg_ext_ctl;
109
110 static struct kvm_cpuid2 *cpuid_cache;
111 static struct kvm_msr_list *kvm_feature_msrs;
112
113 int kvm_has_pit_state2(void)
114 {
115 return has_pit_state2;
116 }
117
118 bool kvm_has_smm(void)
119 {
120 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
121 }
122
123 bool kvm_has_adjust_clock_stable(void)
124 {
125 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
126
127 return (ret == KVM_CLOCK_TSC_STABLE);
128 }
129
130 bool kvm_allows_irq0_override(void)
131 {
132 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
133 }
134
135 static bool kvm_x2apic_api_set_flags(uint64_t flags)
136 {
137 KVMState *s = KVM_STATE(current_machine->accelerator);
138
139 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
140 }
141
142 #define MEMORIZE(fn, _result) \
143 ({ \
144 static bool _memorized; \
145 \
146 if (_memorized) { \
147 return _result; \
148 } \
149 _memorized = true; \
150 _result = fn; \
151 })
152
153 static bool has_x2apic_api;
154
155 bool kvm_has_x2apic_api(void)
156 {
157 return has_x2apic_api;
158 }
159
160 bool kvm_enable_x2apic(void)
161 {
162 return MEMORIZE(
163 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
164 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
165 has_x2apic_api);
166 }
167
168 bool kvm_hv_vpindex_settable(void)
169 {
170 return hv_vpindex_settable;
171 }
172
173 static int kvm_get_tsc(CPUState *cs)
174 {
175 X86CPU *cpu = X86_CPU(cs);
176 CPUX86State *env = &cpu->env;
177 struct {
178 struct kvm_msrs info;
179 struct kvm_msr_entry entries[1];
180 } msr_data;
181 int ret;
182
183 if (env->tsc_valid) {
184 return 0;
185 }
186
187 msr_data.info.nmsrs = 1;
188 msr_data.entries[0].index = MSR_IA32_TSC;
189 env->tsc_valid = !runstate_is_running();
190
191 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
192 if (ret < 0) {
193 return ret;
194 }
195
196 assert(ret == 1);
197 env->tsc = msr_data.entries[0].data;
198 return 0;
199 }
200
201 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
202 {
203 kvm_get_tsc(cpu);
204 }
205
206 void kvm_synchronize_all_tsc(void)
207 {
208 CPUState *cpu;
209
210 if (kvm_enabled()) {
211 CPU_FOREACH(cpu) {
212 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
213 }
214 }
215 }
216
217 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
218 {
219 struct kvm_cpuid2 *cpuid;
220 int r, size;
221
222 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
223 cpuid = g_malloc0(size);
224 cpuid->nent = max;
225 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
226 if (r == 0 && cpuid->nent >= max) {
227 r = -E2BIG;
228 }
229 if (r < 0) {
230 if (r == -E2BIG) {
231 g_free(cpuid);
232 return NULL;
233 } else {
234 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
235 strerror(-r));
236 exit(1);
237 }
238 }
239 return cpuid;
240 }
241
242 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
243 * for all entries.
244 */
245 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
246 {
247 struct kvm_cpuid2 *cpuid;
248 int max = 1;
249
250 if (cpuid_cache != NULL) {
251 return cpuid_cache;
252 }
253 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
254 max *= 2;
255 }
256 cpuid_cache = cpuid;
257 return cpuid;
258 }
259
260 static const struct kvm_para_features {
261 int cap;
262 int feature;
263 } para_features[] = {
264 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
265 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
266 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
267 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
268 };
269
270 static int get_para_features(KVMState *s)
271 {
272 int i, features = 0;
273
274 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
275 if (kvm_check_extension(s, para_features[i].cap)) {
276 features |= (1 << para_features[i].feature);
277 }
278 }
279
280 return features;
281 }
282
283 static bool host_tsx_blacklisted(void)
284 {
285 int family, model, stepping;\
286 char vendor[CPUID_VENDOR_SZ + 1];
287
288 host_vendor_fms(vendor, &family, &model, &stepping);
289
290 /* Check if we are running on a Haswell host known to have broken TSX */
291 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
292 (family == 6) &&
293 ((model == 63 && stepping < 4) ||
294 model == 60 || model == 69 || model == 70);
295 }
296
297 /* Returns the value for a specific register on the cpuid entry
298 */
299 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
300 {
301 uint32_t ret = 0;
302 switch (reg) {
303 case R_EAX:
304 ret = entry->eax;
305 break;
306 case R_EBX:
307 ret = entry->ebx;
308 break;
309 case R_ECX:
310 ret = entry->ecx;
311 break;
312 case R_EDX:
313 ret = entry->edx;
314 break;
315 }
316 return ret;
317 }
318
319 /* Find matching entry for function/index on kvm_cpuid2 struct
320 */
321 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
322 uint32_t function,
323 uint32_t index)
324 {
325 int i;
326 for (i = 0; i < cpuid->nent; ++i) {
327 if (cpuid->entries[i].function == function &&
328 cpuid->entries[i].index == index) {
329 return &cpuid->entries[i];
330 }
331 }
332 /* not found: */
333 return NULL;
334 }
335
336 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
337 uint32_t index, int reg)
338 {
339 struct kvm_cpuid2 *cpuid;
340 uint32_t ret = 0;
341 uint32_t cpuid_1_edx;
342 bool found = false;
343
344 cpuid = get_supported_cpuid(s);
345
346 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
347 if (entry) {
348 found = true;
349 ret = cpuid_entry_get_reg(entry, reg);
350 }
351
352 /* Fixups for the data returned by KVM, below */
353
354 if (function == 1 && reg == R_EDX) {
355 /* KVM before 2.6.30 misreports the following features */
356 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
357 } else if (function == 1 && reg == R_ECX) {
358 /* We can set the hypervisor flag, even if KVM does not return it on
359 * GET_SUPPORTED_CPUID
360 */
361 ret |= CPUID_EXT_HYPERVISOR;
362 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
363 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
364 * and the irqchip is in the kernel.
365 */
366 if (kvm_irqchip_in_kernel() &&
367 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
368 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
369 }
370
371 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
372 * without the in-kernel irqchip
373 */
374 if (!kvm_irqchip_in_kernel()) {
375 ret &= ~CPUID_EXT_X2APIC;
376 }
377
378 if (enable_cpu_pm) {
379 int disable_exits = kvm_check_extension(s,
380 KVM_CAP_X86_DISABLE_EXITS);
381
382 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
383 ret |= CPUID_EXT_MONITOR;
384 }
385 }
386 } else if (function == 6 && reg == R_EAX) {
387 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
388 } else if (function == 7 && index == 0 && reg == R_EBX) {
389 if (host_tsx_blacklisted()) {
390 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
391 }
392 } else if (function == 0x80000001 && reg == R_ECX) {
393 /*
394 * It's safe to enable TOPOEXT even if it's not returned by
395 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
396 * us to keep CPU models including TOPOEXT runnable on older kernels.
397 */
398 ret |= CPUID_EXT3_TOPOEXT;
399 } else if (function == 0x80000001 && reg == R_EDX) {
400 /* On Intel, kvm returns cpuid according to the Intel spec,
401 * so add missing bits according to the AMD spec:
402 */
403 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
404 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
405 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
406 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
407 * be enabled without the in-kernel irqchip
408 */
409 if (!kvm_irqchip_in_kernel()) {
410 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
411 }
412 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
413 ret |= 1U << KVM_HINTS_REALTIME;
414 found = 1;
415 }
416
417 /* fallback for older kernels */
418 if ((function == KVM_CPUID_FEATURES) && !found) {
419 ret = get_para_features(s);
420 }
421
422 return ret;
423 }
424
425 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
426 {
427 struct {
428 struct kvm_msrs info;
429 struct kvm_msr_entry entries[1];
430 } msr_data;
431 uint32_t ret;
432
433 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
434 return 0;
435 }
436
437 /* Check if requested MSR is supported feature MSR */
438 int i;
439 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
440 if (kvm_feature_msrs->indices[i] == index) {
441 break;
442 }
443 if (i == kvm_feature_msrs->nmsrs) {
444 return 0; /* if the feature MSR is not supported, simply return 0 */
445 }
446
447 msr_data.info.nmsrs = 1;
448 msr_data.entries[0].index = index;
449
450 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
451 if (ret != 1) {
452 error_report("KVM get MSR (index=0x%x) feature failed, %s",
453 index, strerror(-ret));
454 exit(1);
455 }
456
457 return msr_data.entries[0].data;
458 }
459
460
461 typedef struct HWPoisonPage {
462 ram_addr_t ram_addr;
463 QLIST_ENTRY(HWPoisonPage) list;
464 } HWPoisonPage;
465
466 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
467 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
468
469 static void kvm_unpoison_all(void *param)
470 {
471 HWPoisonPage *page, *next_page;
472
473 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
474 QLIST_REMOVE(page, list);
475 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
476 g_free(page);
477 }
478 }
479
480 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
481 {
482 HWPoisonPage *page;
483
484 QLIST_FOREACH(page, &hwpoison_page_list, list) {
485 if (page->ram_addr == ram_addr) {
486 return;
487 }
488 }
489 page = g_new(HWPoisonPage, 1);
490 page->ram_addr = ram_addr;
491 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
492 }
493
494 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
495 int *max_banks)
496 {
497 int r;
498
499 r = kvm_check_extension(s, KVM_CAP_MCE);
500 if (r > 0) {
501 *max_banks = r;
502 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
503 }
504 return -ENOSYS;
505 }
506
507 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
508 {
509 CPUState *cs = CPU(cpu);
510 CPUX86State *env = &cpu->env;
511 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
512 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
513 uint64_t mcg_status = MCG_STATUS_MCIP;
514 int flags = 0;
515
516 if (code == BUS_MCEERR_AR) {
517 status |= MCI_STATUS_AR | 0x134;
518 mcg_status |= MCG_STATUS_EIPV;
519 } else {
520 status |= 0xc0;
521 mcg_status |= MCG_STATUS_RIPV;
522 }
523
524 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
525 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
526 * guest kernel back into env->mcg_ext_ctl.
527 */
528 cpu_synchronize_state(cs);
529 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
530 mcg_status |= MCG_STATUS_LMCE;
531 flags = 0;
532 }
533
534 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
535 (MCM_ADDR_PHYS << 6) | 0xc, flags);
536 }
537
538 static void hardware_memory_error(void)
539 {
540 fprintf(stderr, "Hardware memory error!\n");
541 exit(1);
542 }
543
544 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
545 {
546 X86CPU *cpu = X86_CPU(c);
547 CPUX86State *env = &cpu->env;
548 ram_addr_t ram_addr;
549 hwaddr paddr;
550
551 /* If we get an action required MCE, it has been injected by KVM
552 * while the VM was running. An action optional MCE instead should
553 * be coming from the main thread, which qemu_init_sigbus identifies
554 * as the "early kill" thread.
555 */
556 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
557
558 if ((env->mcg_cap & MCG_SER_P) && addr) {
559 ram_addr = qemu_ram_addr_from_host(addr);
560 if (ram_addr != RAM_ADDR_INVALID &&
561 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
562 kvm_hwpoison_page_add(ram_addr);
563 kvm_mce_inject(cpu, paddr, code);
564 return;
565 }
566
567 fprintf(stderr, "Hardware memory error for memory used by "
568 "QEMU itself instead of guest system!\n");
569 }
570
571 if (code == BUS_MCEERR_AR) {
572 hardware_memory_error();
573 }
574
575 /* Hope we are lucky for AO MCE */
576 }
577
578 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
579 {
580 CPUX86State *env = &cpu->env;
581
582 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
583 unsigned int bank, bank_num = env->mcg_cap & 0xff;
584 struct kvm_x86_mce mce;
585
586 env->exception_injected = -1;
587
588 /*
589 * There must be at least one bank in use if an MCE is pending.
590 * Find it and use its values for the event injection.
591 */
592 for (bank = 0; bank < bank_num; bank++) {
593 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
594 break;
595 }
596 }
597 assert(bank < bank_num);
598
599 mce.bank = bank;
600 mce.status = env->mce_banks[bank * 4 + 1];
601 mce.mcg_status = env->mcg_status;
602 mce.addr = env->mce_banks[bank * 4 + 2];
603 mce.misc = env->mce_banks[bank * 4 + 3];
604
605 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
606 }
607 return 0;
608 }
609
610 static void cpu_update_state(void *opaque, int running, RunState state)
611 {
612 CPUX86State *env = opaque;
613
614 if (running) {
615 env->tsc_valid = false;
616 }
617 }
618
619 unsigned long kvm_arch_vcpu_id(CPUState *cs)
620 {
621 X86CPU *cpu = X86_CPU(cs);
622 return cpu->apic_id;
623 }
624
625 #ifndef KVM_CPUID_SIGNATURE_NEXT
626 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
627 #endif
628
629 static bool hyperv_hypercall_available(X86CPU *cpu)
630 {
631 return cpu->hyperv_vapic ||
632 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
633 }
634
635 static bool hyperv_enabled(X86CPU *cpu)
636 {
637 CPUState *cs = CPU(cpu);
638 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
639 (hyperv_hypercall_available(cpu) ||
640 cpu->hyperv_time ||
641 cpu->hyperv_relaxed_timing ||
642 cpu->hyperv_crash ||
643 cpu->hyperv_reset ||
644 cpu->hyperv_vpindex ||
645 cpu->hyperv_runtime ||
646 cpu->hyperv_synic ||
647 cpu->hyperv_stimer ||
648 cpu->hyperv_reenlightenment ||
649 cpu->hyperv_tlbflush ||
650 cpu->hyperv_ipi);
651 }
652
653 static int kvm_arch_set_tsc_khz(CPUState *cs)
654 {
655 X86CPU *cpu = X86_CPU(cs);
656 CPUX86State *env = &cpu->env;
657 int r;
658
659 if (!env->tsc_khz) {
660 return 0;
661 }
662
663 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
664 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
665 -ENOTSUP;
666 if (r < 0) {
667 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
668 * TSC frequency doesn't match the one we want.
669 */
670 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
671 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
672 -ENOTSUP;
673 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
674 warn_report("TSC frequency mismatch between "
675 "VM (%" PRId64 " kHz) and host (%d kHz), "
676 "and TSC scaling unavailable",
677 env->tsc_khz, cur_freq);
678 return r;
679 }
680 }
681
682 return 0;
683 }
684
685 static bool tsc_is_stable_and_known(CPUX86State *env)
686 {
687 if (!env->tsc_khz) {
688 return false;
689 }
690 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
691 || env->user_tsc_khz;
692 }
693
694 static int hyperv_handle_properties(CPUState *cs)
695 {
696 X86CPU *cpu = X86_CPU(cs);
697 CPUX86State *env = &cpu->env;
698
699 if (cpu->hyperv_relaxed_timing) {
700 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
701 }
702 if (cpu->hyperv_vapic) {
703 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
704 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
705 }
706 if (cpu->hyperv_time) {
707 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
708 fprintf(stderr, "Hyper-V clocksources "
709 "(requested by 'hv-time' cpu flag) "
710 "are not supported by kernel\n");
711 return -ENOSYS;
712 }
713 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
714 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
715 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
716 }
717 if (cpu->hyperv_frequencies) {
718 if (!has_msr_hv_frequencies) {
719 fprintf(stderr, "Hyper-V frequency MSRs "
720 "(requested by 'hv-frequencies' cpu flag) "
721 "are not supported by kernel\n");
722 return -ENOSYS;
723 }
724 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
725 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
726 }
727 if (cpu->hyperv_crash) {
728 if (!has_msr_hv_crash) {
729 fprintf(stderr, "Hyper-V crash MSRs "
730 "(requested by 'hv-crash' cpu flag) "
731 "are not supported by kernel\n");
732 return -ENOSYS;
733 }
734 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
735 }
736 if (cpu->hyperv_reenlightenment) {
737 if (!has_msr_hv_reenlightenment) {
738 fprintf(stderr,
739 "Hyper-V Reenlightenment MSRs "
740 "(requested by 'hv-reenlightenment' cpu flag) "
741 "are not supported by kernel\n");
742 return -ENOSYS;
743 }
744 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
745 }
746 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
747 if (cpu->hyperv_reset) {
748 if (!has_msr_hv_reset) {
749 fprintf(stderr, "Hyper-V reset MSR "
750 "(requested by 'hv-reset' cpu flag) "
751 "is not supported by kernel\n");
752 return -ENOSYS;
753 }
754 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
755 }
756 if (cpu->hyperv_vpindex) {
757 if (!has_msr_hv_vpindex) {
758 fprintf(stderr, "Hyper-V VP_INDEX MSR "
759 "(requested by 'hv-vpindex' cpu flag) "
760 "is not supported by kernel\n");
761 return -ENOSYS;
762 }
763 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
764 }
765 if (cpu->hyperv_runtime) {
766 if (!has_msr_hv_runtime) {
767 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
768 "(requested by 'hv-runtime' cpu flag) "
769 "is not supported by kernel\n");
770 return -ENOSYS;
771 }
772 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
773 }
774 if (cpu->hyperv_synic) {
775 unsigned int cap = KVM_CAP_HYPERV_SYNIC;
776 if (!cpu->hyperv_synic_kvm_only) {
777 if (!cpu->hyperv_vpindex) {
778 fprintf(stderr, "Hyper-V SynIC "
779 "(requested by 'hv-synic' cpu flag) "
780 "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
781 return -ENOSYS;
782 }
783 cap = KVM_CAP_HYPERV_SYNIC2;
784 }
785
786 if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
787 fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
788 "is not supported by kernel\n");
789 return -ENOSYS;
790 }
791
792 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
793 }
794 if (cpu->hyperv_stimer) {
795 if (!has_msr_hv_stimer) {
796 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
797 return -ENOSYS;
798 }
799 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
800 }
801 return 0;
802 }
803
804 static int hyperv_init_vcpu(X86CPU *cpu)
805 {
806 CPUState *cs = CPU(cpu);
807 int ret;
808
809 if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
810 /*
811 * the kernel doesn't support setting vp_index; assert that its value
812 * is in sync
813 */
814 struct {
815 struct kvm_msrs info;
816 struct kvm_msr_entry entries[1];
817 } msr_data = {
818 .info.nmsrs = 1,
819 .entries[0].index = HV_X64_MSR_VP_INDEX,
820 };
821
822 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
823 if (ret < 0) {
824 return ret;
825 }
826 assert(ret == 1);
827
828 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
829 error_report("kernel's vp_index != QEMU's vp_index");
830 return -ENXIO;
831 }
832 }
833
834 if (cpu->hyperv_synic) {
835 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
836 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
837 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
838 if (ret < 0) {
839 error_report("failed to turn on HyperV SynIC in KVM: %s",
840 strerror(-ret));
841 return ret;
842 }
843
844 if (!cpu->hyperv_synic_kvm_only) {
845 ret = hyperv_x86_synic_add(cpu);
846 if (ret < 0) {
847 error_report("failed to create HyperV SynIC: %s",
848 strerror(-ret));
849 return ret;
850 }
851 }
852 }
853
854 return 0;
855 }
856
857 static Error *invtsc_mig_blocker;
858 static Error *vmx_mig_blocker;
859
860 #define KVM_MAX_CPUID_ENTRIES 100
861
862 int kvm_arch_init_vcpu(CPUState *cs)
863 {
864 struct {
865 struct kvm_cpuid2 cpuid;
866 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
867 } QEMU_PACKED cpuid_data;
868 X86CPU *cpu = X86_CPU(cs);
869 CPUX86State *env = &cpu->env;
870 uint32_t limit, i, j, cpuid_i;
871 uint32_t unused;
872 struct kvm_cpuid_entry2 *c;
873 uint32_t signature[3];
874 uint16_t evmcs_version;
875 int kvm_base = KVM_CPUID_SIGNATURE;
876 int r;
877 Error *local_err = NULL;
878
879 memset(&cpuid_data, 0, sizeof(cpuid_data));
880
881 cpuid_i = 0;
882
883 r = kvm_arch_set_tsc_khz(cs);
884 if (r < 0) {
885 goto fail;
886 }
887
888 /* vcpu's TSC frequency is either specified by user, or following
889 * the value used by KVM if the former is not present. In the
890 * latter case, we query it from KVM and record in env->tsc_khz,
891 * so that vcpu's TSC frequency can be migrated later via this field.
892 */
893 if (!env->tsc_khz) {
894 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
895 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
896 -ENOTSUP;
897 if (r > 0) {
898 env->tsc_khz = r;
899 }
900 }
901
902 /* Paravirtualization CPUIDs */
903 if (hyperv_enabled(cpu)) {
904 c = &cpuid_data.entries[cpuid_i++];
905 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
906 if (!cpu->hyperv_vendor_id) {
907 memcpy(signature, "Microsoft Hv", 12);
908 } else {
909 size_t len = strlen(cpu->hyperv_vendor_id);
910
911 if (len > 12) {
912 error_report("hv-vendor-id truncated to 12 characters");
913 len = 12;
914 }
915 memset(signature, 0, 12);
916 memcpy(signature, cpu->hyperv_vendor_id, len);
917 }
918 c->eax = cpu->hyperv_evmcs ?
919 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
920 c->ebx = signature[0];
921 c->ecx = signature[1];
922 c->edx = signature[2];
923
924 c = &cpuid_data.entries[cpuid_i++];
925 c->function = HV_CPUID_INTERFACE;
926 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
927 c->eax = signature[0];
928 c->ebx = 0;
929 c->ecx = 0;
930 c->edx = 0;
931
932 c = &cpuid_data.entries[cpuid_i++];
933 c->function = HV_CPUID_VERSION;
934 c->eax = 0x00001bbc;
935 c->ebx = 0x00060001;
936
937 c = &cpuid_data.entries[cpuid_i++];
938 c->function = HV_CPUID_FEATURES;
939 r = hyperv_handle_properties(cs);
940 if (r) {
941 return r;
942 }
943 c->eax = env->features[FEAT_HYPERV_EAX];
944 c->ebx = env->features[FEAT_HYPERV_EBX];
945 c->edx = env->features[FEAT_HYPERV_EDX];
946
947 c = &cpuid_data.entries[cpuid_i++];
948 c->function = HV_CPUID_ENLIGHTMENT_INFO;
949 if (cpu->hyperv_relaxed_timing) {
950 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
951 }
952 if (cpu->hyperv_vapic) {
953 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
954 }
955 if (cpu->hyperv_tlbflush) {
956 if (kvm_check_extension(cs->kvm_state,
957 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
958 fprintf(stderr, "Hyper-V TLB flush support "
959 "(requested by 'hv-tlbflush' cpu flag) "
960 " is not supported by kernel\n");
961 return -ENOSYS;
962 }
963 c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
964 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
965 }
966 if (cpu->hyperv_ipi) {
967 if (kvm_check_extension(cs->kvm_state,
968 KVM_CAP_HYPERV_SEND_IPI) <= 0) {
969 fprintf(stderr, "Hyper-V IPI send support "
970 "(requested by 'hv-ipi' cpu flag) "
971 " is not supported by kernel\n");
972 return -ENOSYS;
973 }
974 c->eax |= HV_CLUSTER_IPI_RECOMMENDED;
975 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
976 }
977 if (cpu->hyperv_evmcs) {
978 if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
979 (uintptr_t)&evmcs_version)) {
980 fprintf(stderr, "Hyper-V Enlightened VMCS "
981 "(requested by 'hv-evmcs' cpu flag) "
982 "is not supported by kernel\n");
983 return -ENOSYS;
984 }
985 c->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
986 }
987 c->ebx = cpu->hyperv_spinlock_attempts;
988
989 c = &cpuid_data.entries[cpuid_i++];
990 c->function = HV_CPUID_IMPLEMENT_LIMITS;
991
992 c->eax = cpu->hv_max_vps;
993 c->ebx = 0x40;
994
995 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
996 has_msr_hv_hypercall = true;
997
998 if (cpu->hyperv_evmcs) {
999 __u32 function;
1000
1001 /* Create zeroed 0x40000006..0x40000009 leaves */
1002 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1003 function < HV_CPUID_NESTED_FEATURES; function++) {
1004 c = &cpuid_data.entries[cpuid_i++];
1005 c->function = function;
1006 }
1007
1008 c = &cpuid_data.entries[cpuid_i++];
1009 c->function = HV_CPUID_NESTED_FEATURES;
1010 c->eax = evmcs_version;
1011 }
1012 }
1013
1014 if (cpu->expose_kvm) {
1015 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1016 c = &cpuid_data.entries[cpuid_i++];
1017 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1018 c->eax = KVM_CPUID_FEATURES | kvm_base;
1019 c->ebx = signature[0];
1020 c->ecx = signature[1];
1021 c->edx = signature[2];
1022
1023 c = &cpuid_data.entries[cpuid_i++];
1024 c->function = KVM_CPUID_FEATURES | kvm_base;
1025 c->eax = env->features[FEAT_KVM];
1026 c->edx = env->features[FEAT_KVM_HINTS];
1027 }
1028
1029 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1030
1031 for (i = 0; i <= limit; i++) {
1032 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1033 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1034 abort();
1035 }
1036 c = &cpuid_data.entries[cpuid_i++];
1037 assert(cpuid_i < 100);
1038
1039 switch (i) {
1040 case 2: {
1041 /* Keep reading function 2 till all the input is received */
1042 int times;
1043
1044 c->function = i;
1045 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1046 KVM_CPUID_FLAG_STATE_READ_NEXT;
1047 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1048 times = c->eax & 0xff;
1049
1050 for (j = 1; j < times; ++j) {
1051 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1052 fprintf(stderr, "cpuid_data is full, no space for "
1053 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1054 abort();
1055 }
1056 c = &cpuid_data.entries[cpuid_i++];
1057 c->function = i;
1058 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1059 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1060 }
1061 break;
1062 }
1063 case 4:
1064 case 0xb:
1065 case 0xd:
1066 for (j = 0; ; j++) {
1067 if (i == 0xd && j == 64) {
1068 break;
1069 }
1070 c->function = i;
1071 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1072 c->index = j;
1073 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1074
1075 if (i == 4 && c->eax == 0) {
1076 break;
1077 }
1078 if (i == 0xb && !(c->ecx & 0xff00)) {
1079 break;
1080 }
1081 if (i == 0xd && c->eax == 0) {
1082 continue;
1083 }
1084 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1085 fprintf(stderr, "cpuid_data is full, no space for "
1086 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1087 abort();
1088 }
1089 c = &cpuid_data.entries[cpuid_i++];
1090 }
1091 break;
1092 case 0x14: {
1093 uint32_t times;
1094
1095 c->function = i;
1096 c->index = 0;
1097 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1098 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1099 times = c->eax;
1100
1101 for (j = 1; j <= times; ++j) {
1102 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1103 fprintf(stderr, "cpuid_data is full, no space for "
1104 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1105 abort();
1106 }
1107 c = &cpuid_data.entries[cpuid_i++];
1108 c->function = i;
1109 c->index = j;
1110 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1111 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1112 }
1113 break;
1114 }
1115 default:
1116 c->function = i;
1117 c->flags = 0;
1118 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1119 break;
1120 }
1121 }
1122
1123 if (limit >= 0x0a) {
1124 uint32_t eax, edx;
1125
1126 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1127
1128 has_architectural_pmu_version = eax & 0xff;
1129 if (has_architectural_pmu_version > 0) {
1130 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1131
1132 /* Shouldn't be more than 32, since that's the number of bits
1133 * available in EBX to tell us _which_ counters are available.
1134 * Play it safe.
1135 */
1136 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1137 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1138 }
1139
1140 if (has_architectural_pmu_version > 1) {
1141 num_architectural_pmu_fixed_counters = edx & 0x1f;
1142
1143 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1144 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1145 }
1146 }
1147 }
1148 }
1149
1150 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1151
1152 for (i = 0x80000000; i <= limit; i++) {
1153 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1154 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1155 abort();
1156 }
1157 c = &cpuid_data.entries[cpuid_i++];
1158 assert(cpuid_i < 100);
1159
1160 switch (i) {
1161 case 0x8000001d:
1162 /* Query for all AMD cache information leaves */
1163 for (j = 0; ; j++) {
1164 c->function = i;
1165 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1166 c->index = j;
1167 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1168
1169 if (c->eax == 0) {
1170 break;
1171 }
1172 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1173 fprintf(stderr, "cpuid_data is full, no space for "
1174 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1175 abort();
1176 }
1177 c = &cpuid_data.entries[cpuid_i++];
1178 }
1179 break;
1180 default:
1181 c->function = i;
1182 c->flags = 0;
1183 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1184 break;
1185 }
1186 }
1187
1188 /* Call Centaur's CPUID instructions they are supported. */
1189 if (env->cpuid_xlevel2 > 0) {
1190 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1191
1192 for (i = 0xC0000000; i <= limit; i++) {
1193 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1194 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1195 abort();
1196 }
1197 c = &cpuid_data.entries[cpuid_i++];
1198
1199 c->function = i;
1200 c->flags = 0;
1201 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1202 }
1203 }
1204
1205 cpuid_data.cpuid.nent = cpuid_i;
1206
1207 if (((env->cpuid_version >> 8)&0xF) >= 6
1208 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1209 (CPUID_MCE | CPUID_MCA)
1210 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1211 uint64_t mcg_cap, unsupported_caps;
1212 int banks;
1213 int ret;
1214
1215 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1216 if (ret < 0) {
1217 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1218 return ret;
1219 }
1220
1221 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1222 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1223 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1224 return -ENOTSUP;
1225 }
1226
1227 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1228 if (unsupported_caps) {
1229 if (unsupported_caps & MCG_LMCE_P) {
1230 error_report("kvm: LMCE not supported");
1231 return -ENOTSUP;
1232 }
1233 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1234 unsupported_caps);
1235 }
1236
1237 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1238 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1239 if (ret < 0) {
1240 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1241 return ret;
1242 }
1243 }
1244
1245 qemu_add_vm_change_state_handler(cpu_update_state, env);
1246
1247 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1248 if (c) {
1249 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1250 !!(c->ecx & CPUID_EXT_SMX);
1251 }
1252
1253 if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1254 error_setg(&vmx_mig_blocker,
1255 "Nested VMX virtualization does not support live migration yet");
1256 r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1257 if (local_err) {
1258 error_report_err(local_err);
1259 error_free(vmx_mig_blocker);
1260 return r;
1261 }
1262 }
1263
1264 if (env->mcg_cap & MCG_LMCE_P) {
1265 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1266 }
1267
1268 if (!env->user_tsc_khz) {
1269 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1270 invtsc_mig_blocker == NULL) {
1271 error_setg(&invtsc_mig_blocker,
1272 "State blocked by non-migratable CPU device"
1273 " (invtsc flag)");
1274 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1275 if (local_err) {
1276 error_report_err(local_err);
1277 error_free(invtsc_mig_blocker);
1278 return r;
1279 }
1280 }
1281 }
1282
1283 if (cpu->vmware_cpuid_freq
1284 /* Guests depend on 0x40000000 to detect this feature, so only expose
1285 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1286 && cpu->expose_kvm
1287 && kvm_base == KVM_CPUID_SIGNATURE
1288 /* TSC clock must be stable and known for this feature. */
1289 && tsc_is_stable_and_known(env)) {
1290
1291 c = &cpuid_data.entries[cpuid_i++];
1292 c->function = KVM_CPUID_SIGNATURE | 0x10;
1293 c->eax = env->tsc_khz;
1294 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1295 * APIC_BUS_CYCLE_NS */
1296 c->ebx = 1000000;
1297 c->ecx = c->edx = 0;
1298
1299 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1300 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1301 }
1302
1303 cpuid_data.cpuid.nent = cpuid_i;
1304
1305 cpuid_data.cpuid.padding = 0;
1306 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1307 if (r) {
1308 goto fail;
1309 }
1310
1311 if (has_xsave) {
1312 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1313 }
1314 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1315
1316 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1317 has_msr_tsc_aux = false;
1318 }
1319
1320 r = hyperv_init_vcpu(cpu);
1321 if (r) {
1322 goto fail;
1323 }
1324
1325 return 0;
1326
1327 fail:
1328 migrate_del_blocker(invtsc_mig_blocker);
1329 return r;
1330 }
1331
1332 void kvm_arch_reset_vcpu(X86CPU *cpu)
1333 {
1334 CPUX86State *env = &cpu->env;
1335
1336 env->xcr0 = 1;
1337 if (kvm_irqchip_in_kernel()) {
1338 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1339 KVM_MP_STATE_UNINITIALIZED;
1340 } else {
1341 env->mp_state = KVM_MP_STATE_RUNNABLE;
1342 }
1343
1344 if (cpu->hyperv_synic) {
1345 int i;
1346 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1347 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1348 }
1349
1350 hyperv_x86_synic_reset(cpu);
1351 }
1352 }
1353
1354 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1355 {
1356 CPUX86State *env = &cpu->env;
1357
1358 /* APs get directly into wait-for-SIPI state. */
1359 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1360 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1361 }
1362 }
1363
1364 static int kvm_get_supported_feature_msrs(KVMState *s)
1365 {
1366 int ret = 0;
1367
1368 if (kvm_feature_msrs != NULL) {
1369 return 0;
1370 }
1371
1372 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1373 return 0;
1374 }
1375
1376 struct kvm_msr_list msr_list;
1377
1378 msr_list.nmsrs = 0;
1379 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1380 if (ret < 0 && ret != -E2BIG) {
1381 error_report("Fetch KVM feature MSR list failed: %s",
1382 strerror(-ret));
1383 return ret;
1384 }
1385
1386 assert(msr_list.nmsrs > 0);
1387 kvm_feature_msrs = (struct kvm_msr_list *) \
1388 g_malloc0(sizeof(msr_list) +
1389 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1390
1391 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1392 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1393
1394 if (ret < 0) {
1395 error_report("Fetch KVM feature MSR list failed: %s",
1396 strerror(-ret));
1397 g_free(kvm_feature_msrs);
1398 kvm_feature_msrs = NULL;
1399 return ret;
1400 }
1401
1402 return 0;
1403 }
1404
1405 static int kvm_get_supported_msrs(KVMState *s)
1406 {
1407 static int kvm_supported_msrs;
1408 int ret = 0;
1409
1410 /* first time */
1411 if (kvm_supported_msrs == 0) {
1412 struct kvm_msr_list msr_list, *kvm_msr_list;
1413
1414 kvm_supported_msrs = -1;
1415
1416 /* Obtain MSR list from KVM. These are the MSRs that we must
1417 * save/restore */
1418 msr_list.nmsrs = 0;
1419 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1420 if (ret < 0 && ret != -E2BIG) {
1421 return ret;
1422 }
1423 /* Old kernel modules had a bug and could write beyond the provided
1424 memory. Allocate at least a safe amount of 1K. */
1425 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1426 msr_list.nmsrs *
1427 sizeof(msr_list.indices[0])));
1428
1429 kvm_msr_list->nmsrs = msr_list.nmsrs;
1430 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1431 if (ret >= 0) {
1432 int i;
1433
1434 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1435 switch (kvm_msr_list->indices[i]) {
1436 case MSR_STAR:
1437 has_msr_star = true;
1438 break;
1439 case MSR_VM_HSAVE_PA:
1440 has_msr_hsave_pa = true;
1441 break;
1442 case MSR_TSC_AUX:
1443 has_msr_tsc_aux = true;
1444 break;
1445 case MSR_TSC_ADJUST:
1446 has_msr_tsc_adjust = true;
1447 break;
1448 case MSR_IA32_TSCDEADLINE:
1449 has_msr_tsc_deadline = true;
1450 break;
1451 case MSR_IA32_SMBASE:
1452 has_msr_smbase = true;
1453 break;
1454 case MSR_SMI_COUNT:
1455 has_msr_smi_count = true;
1456 break;
1457 case MSR_IA32_MISC_ENABLE:
1458 has_msr_misc_enable = true;
1459 break;
1460 case MSR_IA32_BNDCFGS:
1461 has_msr_bndcfgs = true;
1462 break;
1463 case MSR_IA32_XSS:
1464 has_msr_xss = true;
1465 break;
1466 case HV_X64_MSR_CRASH_CTL:
1467 has_msr_hv_crash = true;
1468 break;
1469 case HV_X64_MSR_RESET:
1470 has_msr_hv_reset = true;
1471 break;
1472 case HV_X64_MSR_VP_INDEX:
1473 has_msr_hv_vpindex = true;
1474 break;
1475 case HV_X64_MSR_VP_RUNTIME:
1476 has_msr_hv_runtime = true;
1477 break;
1478 case HV_X64_MSR_SCONTROL:
1479 has_msr_hv_synic = true;
1480 break;
1481 case HV_X64_MSR_STIMER0_CONFIG:
1482 has_msr_hv_stimer = true;
1483 break;
1484 case HV_X64_MSR_TSC_FREQUENCY:
1485 has_msr_hv_frequencies = true;
1486 break;
1487 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1488 has_msr_hv_reenlightenment = true;
1489 break;
1490 case MSR_IA32_SPEC_CTRL:
1491 has_msr_spec_ctrl = true;
1492 break;
1493 case MSR_VIRT_SSBD:
1494 has_msr_virt_ssbd = true;
1495 break;
1496 case MSR_IA32_ARCH_CAPABILITIES:
1497 has_msr_arch_capabs = true;
1498 break;
1499 }
1500 }
1501 }
1502
1503 g_free(kvm_msr_list);
1504 }
1505
1506 return ret;
1507 }
1508
1509 static Notifier smram_machine_done;
1510 static KVMMemoryListener smram_listener;
1511 static AddressSpace smram_address_space;
1512 static MemoryRegion smram_as_root;
1513 static MemoryRegion smram_as_mem;
1514
1515 static void register_smram_listener(Notifier *n, void *unused)
1516 {
1517 MemoryRegion *smram =
1518 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1519
1520 /* Outer container... */
1521 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1522 memory_region_set_enabled(&smram_as_root, true);
1523
1524 /* ... with two regions inside: normal system memory with low
1525 * priority, and...
1526 */
1527 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1528 get_system_memory(), 0, ~0ull);
1529 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1530 memory_region_set_enabled(&smram_as_mem, true);
1531
1532 if (smram) {
1533 /* ... SMRAM with higher priority */
1534 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1535 memory_region_set_enabled(smram, true);
1536 }
1537
1538 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1539 kvm_memory_listener_register(kvm_state, &smram_listener,
1540 &smram_address_space, 1);
1541 }
1542
1543 int kvm_arch_init(MachineState *ms, KVMState *s)
1544 {
1545 uint64_t identity_base = 0xfffbc000;
1546 uint64_t shadow_mem;
1547 int ret;
1548 struct utsname utsname;
1549
1550 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1551 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1552 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1553
1554 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1555
1556 ret = kvm_get_supported_msrs(s);
1557 if (ret < 0) {
1558 return ret;
1559 }
1560
1561 kvm_get_supported_feature_msrs(s);
1562
1563 uname(&utsname);
1564 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1565
1566 /*
1567 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1568 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1569 * Since these must be part of guest physical memory, we need to allocate
1570 * them, both by setting their start addresses in the kernel and by
1571 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1572 *
1573 * Older KVM versions may not support setting the identity map base. In
1574 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1575 * size.
1576 */
1577 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1578 /* Allows up to 16M BIOSes. */
1579 identity_base = 0xfeffc000;
1580
1581 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1582 if (ret < 0) {
1583 return ret;
1584 }
1585 }
1586
1587 /* Set TSS base one page after EPT identity map. */
1588 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1589 if (ret < 0) {
1590 return ret;
1591 }
1592
1593 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1594 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1595 if (ret < 0) {
1596 fprintf(stderr, "e820_add_entry() table is full\n");
1597 return ret;
1598 }
1599 qemu_register_reset(kvm_unpoison_all, NULL);
1600
1601 shadow_mem = machine_kvm_shadow_mem(ms);
1602 if (shadow_mem != -1) {
1603 shadow_mem /= 4096;
1604 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1605 if (ret < 0) {
1606 return ret;
1607 }
1608 }
1609
1610 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1611 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1612 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1613 smram_machine_done.notify = register_smram_listener;
1614 qemu_add_machine_init_done_notifier(&smram_machine_done);
1615 }
1616
1617 if (enable_cpu_pm) {
1618 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1619 int ret;
1620
1621 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1622 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1623 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1624 #endif
1625 if (disable_exits) {
1626 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1627 KVM_X86_DISABLE_EXITS_HLT |
1628 KVM_X86_DISABLE_EXITS_PAUSE);
1629 }
1630
1631 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1632 disable_exits);
1633 if (ret < 0) {
1634 error_report("kvm: guest stopping CPU not supported: %s",
1635 strerror(-ret));
1636 }
1637 }
1638
1639 return 0;
1640 }
1641
1642 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1643 {
1644 lhs->selector = rhs->selector;
1645 lhs->base = rhs->base;
1646 lhs->limit = rhs->limit;
1647 lhs->type = 3;
1648 lhs->present = 1;
1649 lhs->dpl = 3;
1650 lhs->db = 0;
1651 lhs->s = 1;
1652 lhs->l = 0;
1653 lhs->g = 0;
1654 lhs->avl = 0;
1655 lhs->unusable = 0;
1656 }
1657
1658 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1659 {
1660 unsigned flags = rhs->flags;
1661 lhs->selector = rhs->selector;
1662 lhs->base = rhs->base;
1663 lhs->limit = rhs->limit;
1664 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1665 lhs->present = (flags & DESC_P_MASK) != 0;
1666 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1667 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1668 lhs->s = (flags & DESC_S_MASK) != 0;
1669 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1670 lhs->g = (flags & DESC_G_MASK) != 0;
1671 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1672 lhs->unusable = !lhs->present;
1673 lhs->padding = 0;
1674 }
1675
1676 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1677 {
1678 lhs->selector = rhs->selector;
1679 lhs->base = rhs->base;
1680 lhs->limit = rhs->limit;
1681 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1682 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1683 (rhs->dpl << DESC_DPL_SHIFT) |
1684 (rhs->db << DESC_B_SHIFT) |
1685 (rhs->s * DESC_S_MASK) |
1686 (rhs->l << DESC_L_SHIFT) |
1687 (rhs->g * DESC_G_MASK) |
1688 (rhs->avl * DESC_AVL_MASK);
1689 }
1690
1691 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1692 {
1693 if (set) {
1694 *kvm_reg = *qemu_reg;
1695 } else {
1696 *qemu_reg = *kvm_reg;
1697 }
1698 }
1699
1700 static int kvm_getput_regs(X86CPU *cpu, int set)
1701 {
1702 CPUX86State *env = &cpu->env;
1703 struct kvm_regs regs;
1704 int ret = 0;
1705
1706 if (!set) {
1707 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1708 if (ret < 0) {
1709 return ret;
1710 }
1711 }
1712
1713 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1714 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1715 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1716 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1717 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1718 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1719 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1720 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1721 #ifdef TARGET_X86_64
1722 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1723 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1724 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1725 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1726 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1727 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1728 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1729 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1730 #endif
1731
1732 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1733 kvm_getput_reg(&regs.rip, &env->eip, set);
1734
1735 if (set) {
1736 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1737 }
1738
1739 return ret;
1740 }
1741
1742 static int kvm_put_fpu(X86CPU *cpu)
1743 {
1744 CPUX86State *env = &cpu->env;
1745 struct kvm_fpu fpu;
1746 int i;
1747
1748 memset(&fpu, 0, sizeof fpu);
1749 fpu.fsw = env->fpus & ~(7 << 11);
1750 fpu.fsw |= (env->fpstt & 7) << 11;
1751 fpu.fcw = env->fpuc;
1752 fpu.last_opcode = env->fpop;
1753 fpu.last_ip = env->fpip;
1754 fpu.last_dp = env->fpdp;
1755 for (i = 0; i < 8; ++i) {
1756 fpu.ftwx |= (!env->fptags[i]) << i;
1757 }
1758 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1759 for (i = 0; i < CPU_NB_REGS; i++) {
1760 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1761 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1762 }
1763 fpu.mxcsr = env->mxcsr;
1764
1765 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1766 }
1767
1768 #define XSAVE_FCW_FSW 0
1769 #define XSAVE_FTW_FOP 1
1770 #define XSAVE_CWD_RIP 2
1771 #define XSAVE_CWD_RDP 4
1772 #define XSAVE_MXCSR 6
1773 #define XSAVE_ST_SPACE 8
1774 #define XSAVE_XMM_SPACE 40
1775 #define XSAVE_XSTATE_BV 128
1776 #define XSAVE_YMMH_SPACE 144
1777 #define XSAVE_BNDREGS 240
1778 #define XSAVE_BNDCSR 256
1779 #define XSAVE_OPMASK 272
1780 #define XSAVE_ZMM_Hi256 288
1781 #define XSAVE_Hi16_ZMM 416
1782 #define XSAVE_PKRU 672
1783
1784 #define XSAVE_BYTE_OFFSET(word_offset) \
1785 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1786
1787 #define ASSERT_OFFSET(word_offset, field) \
1788 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1789 offsetof(X86XSaveArea, field))
1790
1791 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1792 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1793 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1794 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1795 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1796 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1797 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1798 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1799 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1800 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1801 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1802 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1803 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1804 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1805 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1806
1807 static int kvm_put_xsave(X86CPU *cpu)
1808 {
1809 CPUX86State *env = &cpu->env;
1810 X86XSaveArea *xsave = env->xsave_buf;
1811
1812 if (!has_xsave) {
1813 return kvm_put_fpu(cpu);
1814 }
1815 x86_cpu_xsave_all_areas(cpu, xsave);
1816
1817 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1818 }
1819
1820 static int kvm_put_xcrs(X86CPU *cpu)
1821 {
1822 CPUX86State *env = &cpu->env;
1823 struct kvm_xcrs xcrs = {};
1824
1825 if (!has_xcrs) {
1826 return 0;
1827 }
1828
1829 xcrs.nr_xcrs = 1;
1830 xcrs.flags = 0;
1831 xcrs.xcrs[0].xcr = 0;
1832 xcrs.xcrs[0].value = env->xcr0;
1833 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1834 }
1835
1836 static int kvm_put_sregs(X86CPU *cpu)
1837 {
1838 CPUX86State *env = &cpu->env;
1839 struct kvm_sregs sregs;
1840
1841 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1842 if (env->interrupt_injected >= 0) {
1843 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1844 (uint64_t)1 << (env->interrupt_injected % 64);
1845 }
1846
1847 if ((env->eflags & VM_MASK)) {
1848 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1849 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1850 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1851 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1852 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1853 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1854 } else {
1855 set_seg(&sregs.cs, &env->segs[R_CS]);
1856 set_seg(&sregs.ds, &env->segs[R_DS]);
1857 set_seg(&sregs.es, &env->segs[R_ES]);
1858 set_seg(&sregs.fs, &env->segs[R_FS]);
1859 set_seg(&sregs.gs, &env->segs[R_GS]);
1860 set_seg(&sregs.ss, &env->segs[R_SS]);
1861 }
1862
1863 set_seg(&sregs.tr, &env->tr);
1864 set_seg(&sregs.ldt, &env->ldt);
1865
1866 sregs.idt.limit = env->idt.limit;
1867 sregs.idt.base = env->idt.base;
1868 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1869 sregs.gdt.limit = env->gdt.limit;
1870 sregs.gdt.base = env->gdt.base;
1871 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1872
1873 sregs.cr0 = env->cr[0];
1874 sregs.cr2 = env->cr[2];
1875 sregs.cr3 = env->cr[3];
1876 sregs.cr4 = env->cr[4];
1877
1878 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1879 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1880
1881 sregs.efer = env->efer;
1882
1883 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1884 }
1885
1886 static void kvm_msr_buf_reset(X86CPU *cpu)
1887 {
1888 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1889 }
1890
1891 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1892 {
1893 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1894 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1895 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1896
1897 assert((void *)(entry + 1) <= limit);
1898
1899 entry->index = index;
1900 entry->reserved = 0;
1901 entry->data = value;
1902 msrs->nmsrs++;
1903 }
1904
1905 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1906 {
1907 kvm_msr_buf_reset(cpu);
1908 kvm_msr_entry_add(cpu, index, value);
1909
1910 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1911 }
1912
1913 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1914 {
1915 int ret;
1916
1917 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1918 assert(ret == 1);
1919 }
1920
1921 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1922 {
1923 CPUX86State *env = &cpu->env;
1924 int ret;
1925
1926 if (!has_msr_tsc_deadline) {
1927 return 0;
1928 }
1929
1930 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1931 if (ret < 0) {
1932 return ret;
1933 }
1934
1935 assert(ret == 1);
1936 return 0;
1937 }
1938
1939 /*
1940 * Provide a separate write service for the feature control MSR in order to
1941 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1942 * before writing any other state because forcibly leaving nested mode
1943 * invalidates the VCPU state.
1944 */
1945 static int kvm_put_msr_feature_control(X86CPU *cpu)
1946 {
1947 int ret;
1948
1949 if (!has_msr_feature_control) {
1950 return 0;
1951 }
1952
1953 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1954 cpu->env.msr_ia32_feature_control);
1955 if (ret < 0) {
1956 return ret;
1957 }
1958
1959 assert(ret == 1);
1960 return 0;
1961 }
1962
1963 static int kvm_put_msrs(X86CPU *cpu, int level)
1964 {
1965 CPUX86State *env = &cpu->env;
1966 int i;
1967 int ret;
1968
1969 kvm_msr_buf_reset(cpu);
1970
1971 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1972 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1973 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1974 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1975 if (has_msr_star) {
1976 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1977 }
1978 if (has_msr_hsave_pa) {
1979 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1980 }
1981 if (has_msr_tsc_aux) {
1982 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1983 }
1984 if (has_msr_tsc_adjust) {
1985 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1986 }
1987 if (has_msr_misc_enable) {
1988 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1989 env->msr_ia32_misc_enable);
1990 }
1991 if (has_msr_smbase) {
1992 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1993 }
1994 if (has_msr_smi_count) {
1995 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1996 }
1997 if (has_msr_bndcfgs) {
1998 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1999 }
2000 if (has_msr_xss) {
2001 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2002 }
2003 if (has_msr_spec_ctrl) {
2004 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2005 }
2006 if (has_msr_virt_ssbd) {
2007 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2008 }
2009
2010 #ifdef TARGET_X86_64
2011 if (lm_capable_kernel) {
2012 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2013 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2014 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2015 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2016 }
2017 #endif
2018
2019 /* If host supports feature MSR, write down. */
2020 if (has_msr_arch_capabs) {
2021 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2022 env->features[FEAT_ARCH_CAPABILITIES]);
2023 }
2024
2025 /*
2026 * The following MSRs have side effects on the guest or are too heavy
2027 * for normal writeback. Limit them to reset or full state updates.
2028 */
2029 if (level >= KVM_PUT_RESET_STATE) {
2030 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2031 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2032 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2033 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2034 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2035 }
2036 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2037 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2038 }
2039 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2040 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2041 }
2042 if (has_architectural_pmu_version > 0) {
2043 if (has_architectural_pmu_version > 1) {
2044 /* Stop the counter. */
2045 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2046 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2047 }
2048
2049 /* Set the counter values. */
2050 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2051 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2052 env->msr_fixed_counters[i]);
2053 }
2054 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2055 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2056 env->msr_gp_counters[i]);
2057 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2058 env->msr_gp_evtsel[i]);
2059 }
2060 if (has_architectural_pmu_version > 1) {
2061 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2062 env->msr_global_status);
2063 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2064 env->msr_global_ovf_ctrl);
2065
2066 /* Now start the PMU. */
2067 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2068 env->msr_fixed_ctr_ctrl);
2069 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2070 env->msr_global_ctrl);
2071 }
2072 }
2073 /*
2074 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2075 * only sync them to KVM on the first cpu
2076 */
2077 if (current_cpu == first_cpu) {
2078 if (has_msr_hv_hypercall) {
2079 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2080 env->msr_hv_guest_os_id);
2081 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2082 env->msr_hv_hypercall);
2083 }
2084 if (cpu->hyperv_time) {
2085 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2086 env->msr_hv_tsc);
2087 }
2088 if (cpu->hyperv_reenlightenment) {
2089 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2090 env->msr_hv_reenlightenment_control);
2091 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2092 env->msr_hv_tsc_emulation_control);
2093 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2094 env->msr_hv_tsc_emulation_status);
2095 }
2096 }
2097 if (cpu->hyperv_vapic) {
2098 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2099 env->msr_hv_vapic);
2100 }
2101 if (has_msr_hv_crash) {
2102 int j;
2103
2104 for (j = 0; j < HV_CRASH_PARAMS; j++)
2105 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2106 env->msr_hv_crash_params[j]);
2107
2108 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2109 }
2110 if (has_msr_hv_runtime) {
2111 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2112 }
2113 if (cpu->hyperv_vpindex && hv_vpindex_settable) {
2114 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2115 hyperv_vp_index(CPU(cpu)));
2116 }
2117 if (cpu->hyperv_synic) {
2118 int j;
2119
2120 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2121
2122 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2123 env->msr_hv_synic_control);
2124 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2125 env->msr_hv_synic_evt_page);
2126 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2127 env->msr_hv_synic_msg_page);
2128
2129 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2130 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2131 env->msr_hv_synic_sint[j]);
2132 }
2133 }
2134 if (has_msr_hv_stimer) {
2135 int j;
2136
2137 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2138 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2139 env->msr_hv_stimer_config[j]);
2140 }
2141
2142 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2143 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2144 env->msr_hv_stimer_count[j]);
2145 }
2146 }
2147 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2148 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2149
2150 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2151 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2152 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2153 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2154 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2155 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2156 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2157 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2158 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2159 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2160 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2161 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2162 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2163 /* The CPU GPs if we write to a bit above the physical limit of
2164 * the host CPU (and KVM emulates that)
2165 */
2166 uint64_t mask = env->mtrr_var[i].mask;
2167 mask &= phys_mask;
2168
2169 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2170 env->mtrr_var[i].base);
2171 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2172 }
2173 }
2174 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2175 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2176 0x14, 1, R_EAX) & 0x7;
2177
2178 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2179 env->msr_rtit_ctrl);
2180 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2181 env->msr_rtit_status);
2182 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2183 env->msr_rtit_output_base);
2184 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2185 env->msr_rtit_output_mask);
2186 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2187 env->msr_rtit_cr3_match);
2188 for (i = 0; i < addr_num; i++) {
2189 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2190 env->msr_rtit_addrs[i]);
2191 }
2192 }
2193
2194 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2195 * kvm_put_msr_feature_control. */
2196 }
2197 if (env->mcg_cap) {
2198 int i;
2199
2200 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2201 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2202 if (has_msr_mcg_ext_ctl) {
2203 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2204 }
2205 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2206 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2207 }
2208 }
2209
2210 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2211 if (ret < 0) {
2212 return ret;
2213 }
2214
2215 if (ret < cpu->kvm_msr_buf->nmsrs) {
2216 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2217 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2218 (uint32_t)e->index, (uint64_t)e->data);
2219 }
2220
2221 assert(ret == cpu->kvm_msr_buf->nmsrs);
2222 return 0;
2223 }
2224
2225
2226 static int kvm_get_fpu(X86CPU *cpu)
2227 {
2228 CPUX86State *env = &cpu->env;
2229 struct kvm_fpu fpu;
2230 int i, ret;
2231
2232 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2233 if (ret < 0) {
2234 return ret;
2235 }
2236
2237 env->fpstt = (fpu.fsw >> 11) & 7;
2238 env->fpus = fpu.fsw;
2239 env->fpuc = fpu.fcw;
2240 env->fpop = fpu.last_opcode;
2241 env->fpip = fpu.last_ip;
2242 env->fpdp = fpu.last_dp;
2243 for (i = 0; i < 8; ++i) {
2244 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2245 }
2246 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2247 for (i = 0; i < CPU_NB_REGS; i++) {
2248 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2249 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2250 }
2251 env->mxcsr = fpu.mxcsr;
2252
2253 return 0;
2254 }
2255
2256 static int kvm_get_xsave(X86CPU *cpu)
2257 {
2258 CPUX86State *env = &cpu->env;
2259 X86XSaveArea *xsave = env->xsave_buf;
2260 int ret;
2261
2262 if (!has_xsave) {
2263 return kvm_get_fpu(cpu);
2264 }
2265
2266 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2267 if (ret < 0) {
2268 return ret;
2269 }
2270 x86_cpu_xrstor_all_areas(cpu, xsave);
2271
2272 return 0;
2273 }
2274
2275 static int kvm_get_xcrs(X86CPU *cpu)
2276 {
2277 CPUX86State *env = &cpu->env;
2278 int i, ret;
2279 struct kvm_xcrs xcrs;
2280
2281 if (!has_xcrs) {
2282 return 0;
2283 }
2284
2285 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2286 if (ret < 0) {
2287 return ret;
2288 }
2289
2290 for (i = 0; i < xcrs.nr_xcrs; i++) {
2291 /* Only support xcr0 now */
2292 if (xcrs.xcrs[i].xcr == 0) {
2293 env->xcr0 = xcrs.xcrs[i].value;
2294 break;
2295 }
2296 }
2297 return 0;
2298 }
2299
2300 static int kvm_get_sregs(X86CPU *cpu)
2301 {
2302 CPUX86State *env = &cpu->env;
2303 struct kvm_sregs sregs;
2304 int bit, i, ret;
2305
2306 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2307 if (ret < 0) {
2308 return ret;
2309 }
2310
2311 /* There can only be one pending IRQ set in the bitmap at a time, so try
2312 to find it and save its number instead (-1 for none). */
2313 env->interrupt_injected = -1;
2314 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2315 if (sregs.interrupt_bitmap[i]) {
2316 bit = ctz64(sregs.interrupt_bitmap[i]);
2317 env->interrupt_injected = i * 64 + bit;
2318 break;
2319 }
2320 }
2321
2322 get_seg(&env->segs[R_CS], &sregs.cs);
2323 get_seg(&env->segs[R_DS], &sregs.ds);
2324 get_seg(&env->segs[R_ES], &sregs.es);
2325 get_seg(&env->segs[R_FS], &sregs.fs);
2326 get_seg(&env->segs[R_GS], &sregs.gs);
2327 get_seg(&env->segs[R_SS], &sregs.ss);
2328
2329 get_seg(&env->tr, &sregs.tr);
2330 get_seg(&env->ldt, &sregs.ldt);
2331
2332 env->idt.limit = sregs.idt.limit;
2333 env->idt.base = sregs.idt.base;
2334 env->gdt.limit = sregs.gdt.limit;
2335 env->gdt.base = sregs.gdt.base;
2336
2337 env->cr[0] = sregs.cr0;
2338 env->cr[2] = sregs.cr2;
2339 env->cr[3] = sregs.cr3;
2340 env->cr[4] = sregs.cr4;
2341
2342 env->efer = sregs.efer;
2343
2344 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2345 x86_update_hflags(env);
2346
2347 return 0;
2348 }
2349
2350 static int kvm_get_msrs(X86CPU *cpu)
2351 {
2352 CPUX86State *env = &cpu->env;
2353 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2354 int ret, i;
2355 uint64_t mtrr_top_bits;
2356
2357 kvm_msr_buf_reset(cpu);
2358
2359 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2360 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2361 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2362 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2363 if (has_msr_star) {
2364 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2365 }
2366 if (has_msr_hsave_pa) {
2367 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2368 }
2369 if (has_msr_tsc_aux) {
2370 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2371 }
2372 if (has_msr_tsc_adjust) {
2373 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2374 }
2375 if (has_msr_tsc_deadline) {
2376 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2377 }
2378 if (has_msr_misc_enable) {
2379 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2380 }
2381 if (has_msr_smbase) {
2382 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2383 }
2384 if (has_msr_smi_count) {
2385 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2386 }
2387 if (has_msr_feature_control) {
2388 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2389 }
2390 if (has_msr_bndcfgs) {
2391 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2392 }
2393 if (has_msr_xss) {
2394 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2395 }
2396 if (has_msr_spec_ctrl) {
2397 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2398 }
2399 if (has_msr_virt_ssbd) {
2400 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2401 }
2402 if (!env->tsc_valid) {
2403 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2404 env->tsc_valid = !runstate_is_running();
2405 }
2406
2407 #ifdef TARGET_X86_64
2408 if (lm_capable_kernel) {
2409 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2410 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2411 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2412 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2413 }
2414 #endif
2415 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2416 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2417 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2418 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2419 }
2420 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2421 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2422 }
2423 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2424 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2425 }
2426 if (has_architectural_pmu_version > 0) {
2427 if (has_architectural_pmu_version > 1) {
2428 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2429 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2430 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2431 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2432 }
2433 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2434 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2435 }
2436 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2437 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2438 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2439 }
2440 }
2441
2442 if (env->mcg_cap) {
2443 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2444 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2445 if (has_msr_mcg_ext_ctl) {
2446 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2447 }
2448 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2449 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2450 }
2451 }
2452
2453 if (has_msr_hv_hypercall) {
2454 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2455 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2456 }
2457 if (cpu->hyperv_vapic) {
2458 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2459 }
2460 if (cpu->hyperv_time) {
2461 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2462 }
2463 if (cpu->hyperv_reenlightenment) {
2464 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2465 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2466 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2467 }
2468 if (has_msr_hv_crash) {
2469 int j;
2470
2471 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2472 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2473 }
2474 }
2475 if (has_msr_hv_runtime) {
2476 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2477 }
2478 if (cpu->hyperv_synic) {
2479 uint32_t msr;
2480
2481 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2482 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2483 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2484 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2485 kvm_msr_entry_add(cpu, msr, 0);
2486 }
2487 }
2488 if (has_msr_hv_stimer) {
2489 uint32_t msr;
2490
2491 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2492 msr++) {
2493 kvm_msr_entry_add(cpu, msr, 0);
2494 }
2495 }
2496 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2497 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2498 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2499 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2500 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2501 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2502 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2503 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2504 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2505 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2506 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2507 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2508 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2509 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2510 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2511 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2512 }
2513 }
2514
2515 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2516 int addr_num =
2517 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2518
2519 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2520 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2521 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2522 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2523 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2524 for (i = 0; i < addr_num; i++) {
2525 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2526 }
2527 }
2528
2529 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2530 if (ret < 0) {
2531 return ret;
2532 }
2533
2534 if (ret < cpu->kvm_msr_buf->nmsrs) {
2535 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2536 error_report("error: failed to get MSR 0x%" PRIx32,
2537 (uint32_t)e->index);
2538 }
2539
2540 assert(ret == cpu->kvm_msr_buf->nmsrs);
2541 /*
2542 * MTRR masks: Each mask consists of 5 parts
2543 * a 10..0: must be zero
2544 * b 11 : valid bit
2545 * c n-1.12: actual mask bits
2546 * d 51..n: reserved must be zero
2547 * e 63.52: reserved must be zero
2548 *
2549 * 'n' is the number of physical bits supported by the CPU and is
2550 * apparently always <= 52. We know our 'n' but don't know what
2551 * the destinations 'n' is; it might be smaller, in which case
2552 * it masks (c) on loading. It might be larger, in which case
2553 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2554 * we're migrating to.
2555 */
2556
2557 if (cpu->fill_mtrr_mask) {
2558 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2559 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2560 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2561 } else {
2562 mtrr_top_bits = 0;
2563 }
2564
2565 for (i = 0; i < ret; i++) {
2566 uint32_t index = msrs[i].index;
2567 switch (index) {
2568 case MSR_IA32_SYSENTER_CS:
2569 env->sysenter_cs = msrs[i].data;
2570 break;
2571 case MSR_IA32_SYSENTER_ESP:
2572 env->sysenter_esp = msrs[i].data;
2573 break;
2574 case MSR_IA32_SYSENTER_EIP:
2575 env->sysenter_eip = msrs[i].data;
2576 break;
2577 case MSR_PAT:
2578 env->pat = msrs[i].data;
2579 break;
2580 case MSR_STAR:
2581 env->star = msrs[i].data;
2582 break;
2583 #ifdef TARGET_X86_64
2584 case MSR_CSTAR:
2585 env->cstar = msrs[i].data;
2586 break;
2587 case MSR_KERNELGSBASE:
2588 env->kernelgsbase = msrs[i].data;
2589 break;
2590 case MSR_FMASK:
2591 env->fmask = msrs[i].data;
2592 break;
2593 case MSR_LSTAR:
2594 env->lstar = msrs[i].data;
2595 break;
2596 #endif
2597 case MSR_IA32_TSC:
2598 env->tsc = msrs[i].data;
2599 break;
2600 case MSR_TSC_AUX:
2601 env->tsc_aux = msrs[i].data;
2602 break;
2603 case MSR_TSC_ADJUST:
2604 env->tsc_adjust = msrs[i].data;
2605 break;
2606 case MSR_IA32_TSCDEADLINE:
2607 env->tsc_deadline = msrs[i].data;
2608 break;
2609 case MSR_VM_HSAVE_PA:
2610 env->vm_hsave = msrs[i].data;
2611 break;
2612 case MSR_KVM_SYSTEM_TIME:
2613 env->system_time_msr = msrs[i].data;
2614 break;
2615 case MSR_KVM_WALL_CLOCK:
2616 env->wall_clock_msr = msrs[i].data;
2617 break;
2618 case MSR_MCG_STATUS:
2619 env->mcg_status = msrs[i].data;
2620 break;
2621 case MSR_MCG_CTL:
2622 env->mcg_ctl = msrs[i].data;
2623 break;
2624 case MSR_MCG_EXT_CTL:
2625 env->mcg_ext_ctl = msrs[i].data;
2626 break;
2627 case MSR_IA32_MISC_ENABLE:
2628 env->msr_ia32_misc_enable = msrs[i].data;
2629 break;
2630 case MSR_IA32_SMBASE:
2631 env->smbase = msrs[i].data;
2632 break;
2633 case MSR_SMI_COUNT:
2634 env->msr_smi_count = msrs[i].data;
2635 break;
2636 case MSR_IA32_FEATURE_CONTROL:
2637 env->msr_ia32_feature_control = msrs[i].data;
2638 break;
2639 case MSR_IA32_BNDCFGS:
2640 env->msr_bndcfgs = msrs[i].data;
2641 break;
2642 case MSR_IA32_XSS:
2643 env->xss = msrs[i].data;
2644 break;
2645 default:
2646 if (msrs[i].index >= MSR_MC0_CTL &&
2647 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2648 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2649 }
2650 break;
2651 case MSR_KVM_ASYNC_PF_EN:
2652 env->async_pf_en_msr = msrs[i].data;
2653 break;
2654 case MSR_KVM_PV_EOI_EN:
2655 env->pv_eoi_en_msr = msrs[i].data;
2656 break;
2657 case MSR_KVM_STEAL_TIME:
2658 env->steal_time_msr = msrs[i].data;
2659 break;
2660 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2661 env->msr_fixed_ctr_ctrl = msrs[i].data;
2662 break;
2663 case MSR_CORE_PERF_GLOBAL_CTRL:
2664 env->msr_global_ctrl = msrs[i].data;
2665 break;
2666 case MSR_CORE_PERF_GLOBAL_STATUS:
2667 env->msr_global_status = msrs[i].data;
2668 break;
2669 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2670 env->msr_global_ovf_ctrl = msrs[i].data;
2671 break;
2672 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2673 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2674 break;
2675 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2676 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2677 break;
2678 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2679 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2680 break;
2681 case HV_X64_MSR_HYPERCALL:
2682 env->msr_hv_hypercall = msrs[i].data;
2683 break;
2684 case HV_X64_MSR_GUEST_OS_ID:
2685 env->msr_hv_guest_os_id = msrs[i].data;
2686 break;
2687 case HV_X64_MSR_APIC_ASSIST_PAGE:
2688 env->msr_hv_vapic = msrs[i].data;
2689 break;
2690 case HV_X64_MSR_REFERENCE_TSC:
2691 env->msr_hv_tsc = msrs[i].data;
2692 break;
2693 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2694 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2695 break;
2696 case HV_X64_MSR_VP_RUNTIME:
2697 env->msr_hv_runtime = msrs[i].data;
2698 break;
2699 case HV_X64_MSR_SCONTROL:
2700 env->msr_hv_synic_control = msrs[i].data;
2701 break;
2702 case HV_X64_MSR_SIEFP:
2703 env->msr_hv_synic_evt_page = msrs[i].data;
2704 break;
2705 case HV_X64_MSR_SIMP:
2706 env->msr_hv_synic_msg_page = msrs[i].data;
2707 break;
2708 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2709 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2710 break;
2711 case HV_X64_MSR_STIMER0_CONFIG:
2712 case HV_X64_MSR_STIMER1_CONFIG:
2713 case HV_X64_MSR_STIMER2_CONFIG:
2714 case HV_X64_MSR_STIMER3_CONFIG:
2715 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2716 msrs[i].data;
2717 break;
2718 case HV_X64_MSR_STIMER0_COUNT:
2719 case HV_X64_MSR_STIMER1_COUNT:
2720 case HV_X64_MSR_STIMER2_COUNT:
2721 case HV_X64_MSR_STIMER3_COUNT:
2722 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2723 msrs[i].data;
2724 break;
2725 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2726 env->msr_hv_reenlightenment_control = msrs[i].data;
2727 break;
2728 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2729 env->msr_hv_tsc_emulation_control = msrs[i].data;
2730 break;
2731 case HV_X64_MSR_TSC_EMULATION_STATUS:
2732 env->msr_hv_tsc_emulation_status = msrs[i].data;
2733 break;
2734 case MSR_MTRRdefType:
2735 env->mtrr_deftype = msrs[i].data;
2736 break;
2737 case MSR_MTRRfix64K_00000:
2738 env->mtrr_fixed[0] = msrs[i].data;
2739 break;
2740 case MSR_MTRRfix16K_80000:
2741 env->mtrr_fixed[1] = msrs[i].data;
2742 break;
2743 case MSR_MTRRfix16K_A0000:
2744 env->mtrr_fixed[2] = msrs[i].data;
2745 break;
2746 case MSR_MTRRfix4K_C0000:
2747 env->mtrr_fixed[3] = msrs[i].data;
2748 break;
2749 case MSR_MTRRfix4K_C8000:
2750 env->mtrr_fixed[4] = msrs[i].data;
2751 break;
2752 case MSR_MTRRfix4K_D0000:
2753 env->mtrr_fixed[5] = msrs[i].data;
2754 break;
2755 case MSR_MTRRfix4K_D8000:
2756 env->mtrr_fixed[6] = msrs[i].data;
2757 break;
2758 case MSR_MTRRfix4K_E0000:
2759 env->mtrr_fixed[7] = msrs[i].data;
2760 break;
2761 case MSR_MTRRfix4K_E8000:
2762 env->mtrr_fixed[8] = msrs[i].data;
2763 break;
2764 case MSR_MTRRfix4K_F0000:
2765 env->mtrr_fixed[9] = msrs[i].data;
2766 break;
2767 case MSR_MTRRfix4K_F8000:
2768 env->mtrr_fixed[10] = msrs[i].data;
2769 break;
2770 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2771 if (index & 1) {
2772 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2773 mtrr_top_bits;
2774 } else {
2775 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2776 }
2777 break;
2778 case MSR_IA32_SPEC_CTRL:
2779 env->spec_ctrl = msrs[i].data;
2780 break;
2781 case MSR_VIRT_SSBD:
2782 env->virt_ssbd = msrs[i].data;
2783 break;
2784 case MSR_IA32_RTIT_CTL:
2785 env->msr_rtit_ctrl = msrs[i].data;
2786 break;
2787 case MSR_IA32_RTIT_STATUS:
2788 env->msr_rtit_status = msrs[i].data;
2789 break;
2790 case MSR_IA32_RTIT_OUTPUT_BASE:
2791 env->msr_rtit_output_base = msrs[i].data;
2792 break;
2793 case MSR_IA32_RTIT_OUTPUT_MASK:
2794 env->msr_rtit_output_mask = msrs[i].data;
2795 break;
2796 case MSR_IA32_RTIT_CR3_MATCH:
2797 env->msr_rtit_cr3_match = msrs[i].data;
2798 break;
2799 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2800 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2801 break;
2802 }
2803 }
2804
2805 return 0;
2806 }
2807
2808 static int kvm_put_mp_state(X86CPU *cpu)
2809 {
2810 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2811
2812 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2813 }
2814
2815 static int kvm_get_mp_state(X86CPU *cpu)
2816 {
2817 CPUState *cs = CPU(cpu);
2818 CPUX86State *env = &cpu->env;
2819 struct kvm_mp_state mp_state;
2820 int ret;
2821
2822 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2823 if (ret < 0) {
2824 return ret;
2825 }
2826 env->mp_state = mp_state.mp_state;
2827 if (kvm_irqchip_in_kernel()) {
2828 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2829 }
2830 return 0;
2831 }
2832
2833 static int kvm_get_apic(X86CPU *cpu)
2834 {
2835 DeviceState *apic = cpu->apic_state;
2836 struct kvm_lapic_state kapic;
2837 int ret;
2838
2839 if (apic && kvm_irqchip_in_kernel()) {
2840 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2841 if (ret < 0) {
2842 return ret;
2843 }
2844
2845 kvm_get_apic_state(apic, &kapic);
2846 }
2847 return 0;
2848 }
2849
2850 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2851 {
2852 CPUState *cs = CPU(cpu);
2853 CPUX86State *env = &cpu->env;
2854 struct kvm_vcpu_events events = {};
2855
2856 if (!kvm_has_vcpu_events()) {
2857 return 0;
2858 }
2859
2860 events.exception.injected = (env->exception_injected >= 0);
2861 events.exception.nr = env->exception_injected;
2862 events.exception.has_error_code = env->has_error_code;
2863 events.exception.error_code = env->error_code;
2864
2865 events.interrupt.injected = (env->interrupt_injected >= 0);
2866 events.interrupt.nr = env->interrupt_injected;
2867 events.interrupt.soft = env->soft_interrupt;
2868
2869 events.nmi.injected = env->nmi_injected;
2870 events.nmi.pending = env->nmi_pending;
2871 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2872
2873 events.sipi_vector = env->sipi_vector;
2874 events.flags = 0;
2875
2876 if (has_msr_smbase) {
2877 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2878 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2879 if (kvm_irqchip_in_kernel()) {
2880 /* As soon as these are moved to the kernel, remove them
2881 * from cs->interrupt_request.
2882 */
2883 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2884 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2885 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2886 } else {
2887 /* Keep these in cs->interrupt_request. */
2888 events.smi.pending = 0;
2889 events.smi.latched_init = 0;
2890 }
2891 /* Stop SMI delivery on old machine types to avoid a reboot
2892 * on an inward migration of an old VM.
2893 */
2894 if (!cpu->kvm_no_smi_migration) {
2895 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2896 }
2897 }
2898
2899 if (level >= KVM_PUT_RESET_STATE) {
2900 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2901 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2902 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2903 }
2904 }
2905
2906 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2907 }
2908
2909 static int kvm_get_vcpu_events(X86CPU *cpu)
2910 {
2911 CPUX86State *env = &cpu->env;
2912 struct kvm_vcpu_events events;
2913 int ret;
2914
2915 if (!kvm_has_vcpu_events()) {
2916 return 0;
2917 }
2918
2919 memset(&events, 0, sizeof(events));
2920 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2921 if (ret < 0) {
2922 return ret;
2923 }
2924 env->exception_injected =
2925 events.exception.injected ? events.exception.nr : -1;
2926 env->has_error_code = events.exception.has_error_code;
2927 env->error_code = events.exception.error_code;
2928
2929 env->interrupt_injected =
2930 events.interrupt.injected ? events.interrupt.nr : -1;
2931 env->soft_interrupt = events.interrupt.soft;
2932
2933 env->nmi_injected = events.nmi.injected;
2934 env->nmi_pending = events.nmi.pending;
2935 if (events.nmi.masked) {
2936 env->hflags2 |= HF2_NMI_MASK;
2937 } else {
2938 env->hflags2 &= ~HF2_NMI_MASK;
2939 }
2940
2941 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2942 if (events.smi.smm) {
2943 env->hflags |= HF_SMM_MASK;
2944 } else {
2945 env->hflags &= ~HF_SMM_MASK;
2946 }
2947 if (events.smi.pending) {
2948 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2949 } else {
2950 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2951 }
2952 if (events.smi.smm_inside_nmi) {
2953 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2954 } else {
2955 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2956 }
2957 if (events.smi.latched_init) {
2958 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2959 } else {
2960 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2961 }
2962 }
2963
2964 env->sipi_vector = events.sipi_vector;
2965
2966 return 0;
2967 }
2968
2969 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2970 {
2971 CPUState *cs = CPU(cpu);
2972 CPUX86State *env = &cpu->env;
2973 int ret = 0;
2974 unsigned long reinject_trap = 0;
2975
2976 if (!kvm_has_vcpu_events()) {
2977 if (env->exception_injected == 1) {
2978 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2979 } else if (env->exception_injected == 3) {
2980 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2981 }
2982 env->exception_injected = -1;
2983 }
2984
2985 /*
2986 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2987 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2988 * by updating the debug state once again if single-stepping is on.
2989 * Another reason to call kvm_update_guest_debug here is a pending debug
2990 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2991 * reinject them via SET_GUEST_DEBUG.
2992 */
2993 if (reinject_trap ||
2994 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2995 ret = kvm_update_guest_debug(cs, reinject_trap);
2996 }
2997 return ret;
2998 }
2999
3000 static int kvm_put_debugregs(X86CPU *cpu)
3001 {
3002 CPUX86State *env = &cpu->env;
3003 struct kvm_debugregs dbgregs;
3004 int i;
3005
3006 if (!kvm_has_debugregs()) {
3007 return 0;
3008 }
3009
3010 for (i = 0; i < 4; i++) {
3011 dbgregs.db[i] = env->dr[i];
3012 }
3013 dbgregs.dr6 = env->dr[6];
3014 dbgregs.dr7 = env->dr[7];
3015 dbgregs.flags = 0;
3016
3017 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3018 }
3019
3020 static int kvm_get_debugregs(X86CPU *cpu)
3021 {
3022 CPUX86State *env = &cpu->env;
3023 struct kvm_debugregs dbgregs;
3024 int i, ret;
3025
3026 if (!kvm_has_debugregs()) {
3027 return 0;
3028 }
3029
3030 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3031 if (ret < 0) {
3032 return ret;
3033 }
3034 for (i = 0; i < 4; i++) {
3035 env->dr[i] = dbgregs.db[i];
3036 }
3037 env->dr[4] = env->dr[6] = dbgregs.dr6;
3038 env->dr[5] = env->dr[7] = dbgregs.dr7;
3039
3040 return 0;
3041 }
3042
3043 int kvm_arch_put_registers(CPUState *cpu, int level)
3044 {
3045 X86CPU *x86_cpu = X86_CPU(cpu);
3046 int ret;
3047
3048 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3049
3050 if (level >= KVM_PUT_RESET_STATE) {
3051 ret = kvm_put_msr_feature_control(x86_cpu);
3052 if (ret < 0) {
3053 return ret;
3054 }
3055 }
3056
3057 if (level == KVM_PUT_FULL_STATE) {
3058 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3059 * because TSC frequency mismatch shouldn't abort migration,
3060 * unless the user explicitly asked for a more strict TSC
3061 * setting (e.g. using an explicit "tsc-freq" option).
3062 */
3063 kvm_arch_set_tsc_khz(cpu);
3064 }
3065
3066 ret = kvm_getput_regs(x86_cpu, 1);
3067 if (ret < 0) {
3068 return ret;
3069 }
3070 ret = kvm_put_xsave(x86_cpu);
3071 if (ret < 0) {
3072 return ret;
3073 }
3074 ret = kvm_put_xcrs(x86_cpu);
3075 if (ret < 0) {
3076 return ret;
3077 }
3078 ret = kvm_put_sregs(x86_cpu);
3079 if (ret < 0) {
3080 return ret;
3081 }
3082 /* must be before kvm_put_msrs */
3083 ret = kvm_inject_mce_oldstyle(x86_cpu);
3084 if (ret < 0) {
3085 return ret;
3086 }
3087 ret = kvm_put_msrs(x86_cpu, level);
3088 if (ret < 0) {
3089 return ret;
3090 }
3091 ret = kvm_put_vcpu_events(x86_cpu, level);
3092 if (ret < 0) {
3093 return ret;
3094 }
3095 if (level >= KVM_PUT_RESET_STATE) {
3096 ret = kvm_put_mp_state(x86_cpu);
3097 if (ret < 0) {
3098 return ret;
3099 }
3100 }
3101
3102 ret = kvm_put_tscdeadline_msr(x86_cpu);
3103 if (ret < 0) {
3104 return ret;
3105 }
3106 ret = kvm_put_debugregs(x86_cpu);
3107 if (ret < 0) {
3108 return ret;
3109 }
3110 /* must be last */
3111 ret = kvm_guest_debug_workarounds(x86_cpu);
3112 if (ret < 0) {
3113 return ret;
3114 }
3115 return 0;
3116 }
3117
3118 int kvm_arch_get_registers(CPUState *cs)
3119 {
3120 X86CPU *cpu = X86_CPU(cs);
3121 int ret;
3122
3123 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3124
3125 ret = kvm_get_vcpu_events(cpu);
3126 if (ret < 0) {
3127 goto out;
3128 }
3129 /*
3130 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3131 * KVM_GET_REGS and KVM_GET_SREGS.
3132 */
3133 ret = kvm_get_mp_state(cpu);
3134 if (ret < 0) {
3135 goto out;
3136 }
3137 ret = kvm_getput_regs(cpu, 0);
3138 if (ret < 0) {
3139 goto out;
3140 }
3141 ret = kvm_get_xsave(cpu);
3142 if (ret < 0) {
3143 goto out;
3144 }
3145 ret = kvm_get_xcrs(cpu);
3146 if (ret < 0) {
3147 goto out;
3148 }
3149 ret = kvm_get_sregs(cpu);
3150 if (ret < 0) {
3151 goto out;
3152 }
3153 ret = kvm_get_msrs(cpu);
3154 if (ret < 0) {
3155 goto out;
3156 }
3157 ret = kvm_get_apic(cpu);
3158 if (ret < 0) {
3159 goto out;
3160 }
3161 ret = kvm_get_debugregs(cpu);
3162 if (ret < 0) {
3163 goto out;
3164 }
3165 ret = 0;
3166 out:
3167 cpu_sync_bndcs_hflags(&cpu->env);
3168 return ret;
3169 }
3170
3171 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3172 {
3173 X86CPU *x86_cpu = X86_CPU(cpu);
3174 CPUX86State *env = &x86_cpu->env;
3175 int ret;
3176
3177 /* Inject NMI */
3178 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3179 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3180 qemu_mutex_lock_iothread();
3181 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3182 qemu_mutex_unlock_iothread();
3183 DPRINTF("injected NMI\n");
3184 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3185 if (ret < 0) {
3186 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3187 strerror(-ret));
3188 }
3189 }
3190 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3191 qemu_mutex_lock_iothread();
3192 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3193 qemu_mutex_unlock_iothread();
3194 DPRINTF("injected SMI\n");
3195 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3196 if (ret < 0) {
3197 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3198 strerror(-ret));
3199 }
3200 }
3201 }
3202
3203 if (!kvm_pic_in_kernel()) {
3204 qemu_mutex_lock_iothread();
3205 }
3206
3207 /* Force the VCPU out of its inner loop to process any INIT requests
3208 * or (for userspace APIC, but it is cheap to combine the checks here)
3209 * pending TPR access reports.
3210 */
3211 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3212 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3213 !(env->hflags & HF_SMM_MASK)) {
3214 cpu->exit_request = 1;
3215 }
3216 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3217 cpu->exit_request = 1;
3218 }
3219 }
3220
3221 if (!kvm_pic_in_kernel()) {
3222 /* Try to inject an interrupt if the guest can accept it */
3223 if (run->ready_for_interrupt_injection &&
3224 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3225 (env->eflags & IF_MASK)) {
3226 int irq;
3227
3228 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3229 irq = cpu_get_pic_interrupt(env);
3230 if (irq >= 0) {
3231 struct kvm_interrupt intr;
3232
3233 intr.irq = irq;
3234 DPRINTF("injected interrupt %d\n", irq);
3235 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3236 if (ret < 0) {
3237 fprintf(stderr,
3238 "KVM: injection failed, interrupt lost (%s)\n",
3239 strerror(-ret));
3240 }
3241 }
3242 }
3243
3244 /* If we have an interrupt but the guest is not ready to receive an
3245 * interrupt, request an interrupt window exit. This will
3246 * cause a return to userspace as soon as the guest is ready to
3247 * receive interrupts. */
3248 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3249 run->request_interrupt_window = 1;
3250 } else {
3251 run->request_interrupt_window = 0;
3252 }
3253
3254 DPRINTF("setting tpr\n");
3255 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3256
3257 qemu_mutex_unlock_iothread();
3258 }
3259 }
3260
3261 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3262 {
3263 X86CPU *x86_cpu = X86_CPU(cpu);
3264 CPUX86State *env = &x86_cpu->env;
3265
3266 if (run->flags & KVM_RUN_X86_SMM) {
3267 env->hflags |= HF_SMM_MASK;
3268 } else {
3269 env->hflags &= ~HF_SMM_MASK;
3270 }
3271 if (run->if_flag) {
3272 env->eflags |= IF_MASK;
3273 } else {
3274 env->eflags &= ~IF_MASK;
3275 }
3276
3277 /* We need to protect the apic state against concurrent accesses from
3278 * different threads in case the userspace irqchip is used. */
3279 if (!kvm_irqchip_in_kernel()) {
3280 qemu_mutex_lock_iothread();
3281 }
3282 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3283 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3284 if (!kvm_irqchip_in_kernel()) {
3285 qemu_mutex_unlock_iothread();
3286 }
3287 return cpu_get_mem_attrs(env);
3288 }
3289
3290 int kvm_arch_process_async_events(CPUState *cs)
3291 {
3292 X86CPU *cpu = X86_CPU(cs);
3293 CPUX86State *env = &cpu->env;
3294
3295 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3296 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3297 assert(env->mcg_cap);
3298
3299 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3300
3301 kvm_cpu_synchronize_state(cs);
3302
3303 if (env->exception_injected == EXCP08_DBLE) {
3304 /* this means triple fault */
3305 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3306 cs->exit_request = 1;
3307 return 0;
3308 }
3309 env->exception_injected = EXCP12_MCHK;
3310 env->has_error_code = 0;
3311
3312 cs->halted = 0;
3313 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3314 env->mp_state = KVM_MP_STATE_RUNNABLE;
3315 }
3316 }
3317
3318 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3319 !(env->hflags & HF_SMM_MASK)) {
3320 kvm_cpu_synchronize_state(cs);
3321 do_cpu_init(cpu);
3322 }
3323
3324 if (kvm_irqchip_in_kernel()) {
3325 return 0;
3326 }
3327
3328 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3329 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3330 apic_poll_irq(cpu->apic_state);
3331 }
3332 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3333 (env->eflags & IF_MASK)) ||
3334 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3335 cs->halted = 0;
3336 }
3337 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3338 kvm_cpu_synchronize_state(cs);
3339 do_cpu_sipi(cpu);
3340 }
3341 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3342 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3343 kvm_cpu_synchronize_state(cs);
3344 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3345 env->tpr_access_type);
3346 }
3347
3348 return cs->halted;
3349 }
3350
3351 static int kvm_handle_halt(X86CPU *cpu)
3352 {
3353 CPUState *cs = CPU(cpu);
3354 CPUX86State *env = &cpu->env;
3355
3356 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3357 (env->eflags & IF_MASK)) &&
3358 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3359 cs->halted = 1;
3360 return EXCP_HLT;
3361 }
3362
3363 return 0;
3364 }
3365
3366 static int kvm_handle_tpr_access(X86CPU *cpu)
3367 {
3368 CPUState *cs = CPU(cpu);
3369 struct kvm_run *run = cs->kvm_run;
3370
3371 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3372 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3373 : TPR_ACCESS_READ);
3374 return 1;
3375 }
3376
3377 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3378 {
3379 static const uint8_t int3 = 0xcc;
3380
3381 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3382 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3383 return -EINVAL;
3384 }
3385 return 0;
3386 }
3387
3388 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3389 {
3390 uint8_t int3;
3391
3392 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3393 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3394 return -EINVAL;
3395 }
3396 return 0;
3397 }
3398
3399 static struct {
3400 target_ulong addr;
3401 int len;
3402 int type;
3403 } hw_breakpoint[4];
3404
3405 static int nb_hw_breakpoint;
3406
3407 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3408 {
3409 int n;
3410
3411 for (n = 0; n < nb_hw_breakpoint; n++) {
3412 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3413 (hw_breakpoint[n].len == len || len == -1)) {
3414 return n;
3415 }
3416 }
3417 return -1;
3418 }
3419
3420 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3421 target_ulong len, int type)
3422 {
3423 switch (type) {
3424 case GDB_BREAKPOINT_HW:
3425 len = 1;
3426 break;
3427 case GDB_WATCHPOINT_WRITE:
3428 case GDB_WATCHPOINT_ACCESS:
3429 switch (len) {
3430 case 1:
3431 break;
3432 case 2:
3433 case 4:
3434 case 8:
3435 if (addr & (len - 1)) {
3436 return -EINVAL;
3437 }
3438 break;
3439 default:
3440 return -EINVAL;
3441 }
3442 break;
3443 default:
3444 return -ENOSYS;
3445 }
3446
3447 if (nb_hw_breakpoint == 4) {
3448 return -ENOBUFS;
3449 }
3450 if (find_hw_breakpoint(addr, len, type) >= 0) {
3451 return -EEXIST;
3452 }
3453 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3454 hw_breakpoint[nb_hw_breakpoint].len = len;
3455 hw_breakpoint[nb_hw_breakpoint].type = type;
3456 nb_hw_breakpoint++;
3457
3458 return 0;
3459 }
3460
3461 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3462 target_ulong len, int type)
3463 {
3464 int n;
3465
3466 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3467 if (n < 0) {
3468 return -ENOENT;
3469 }
3470 nb_hw_breakpoint--;
3471 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3472
3473 return 0;
3474 }
3475
3476 void kvm_arch_remove_all_hw_breakpoints(void)
3477 {
3478 nb_hw_breakpoint = 0;
3479 }
3480
3481 static CPUWatchpoint hw_watchpoint;
3482
3483 static int kvm_handle_debug(X86CPU *cpu,
3484 struct kvm_debug_exit_arch *arch_info)
3485 {
3486 CPUState *cs = CPU(cpu);
3487 CPUX86State *env = &cpu->env;
3488 int ret = 0;
3489 int n;
3490
3491 if (arch_info->exception == 1) {
3492 if (arch_info->dr6 & (1 << 14)) {
3493 if (cs->singlestep_enabled) {
3494 ret = EXCP_DEBUG;
3495 }
3496 } else {
3497 for (n = 0; n < 4; n++) {
3498 if (arch_info->dr6 & (1 << n)) {
3499 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3500 case 0x0:
3501 ret = EXCP_DEBUG;
3502 break;
3503 case 0x1:
3504 ret = EXCP_DEBUG;
3505 cs->watchpoint_hit = &hw_watchpoint;
3506 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3507 hw_watchpoint.flags = BP_MEM_WRITE;
3508 break;
3509 case 0x3:
3510 ret = EXCP_DEBUG;
3511 cs->watchpoint_hit = &hw_watchpoint;
3512 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3513 hw_watchpoint.flags = BP_MEM_ACCESS;
3514 break;
3515 }
3516 }
3517 }
3518 }
3519 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3520 ret = EXCP_DEBUG;
3521 }
3522 if (ret == 0) {
3523 cpu_synchronize_state(cs);
3524 assert(env->exception_injected == -1);
3525
3526 /* pass to guest */
3527 env->exception_injected = arch_info->exception;
3528 env->has_error_code = 0;
3529 }
3530
3531 return ret;
3532 }
3533
3534 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3535 {
3536 const uint8_t type_code[] = {
3537 [GDB_BREAKPOINT_HW] = 0x0,
3538 [GDB_WATCHPOINT_WRITE] = 0x1,
3539 [GDB_WATCHPOINT_ACCESS] = 0x3
3540 };
3541 const uint8_t len_code[] = {
3542 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3543 };
3544 int n;
3545
3546 if (kvm_sw_breakpoints_active(cpu)) {
3547 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3548 }
3549 if (nb_hw_breakpoint > 0) {
3550 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3551 dbg->arch.debugreg[7] = 0x0600;
3552 for (n = 0; n < nb_hw_breakpoint; n++) {
3553 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3554 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3555 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3556 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3557 }
3558 }
3559 }
3560
3561 static bool host_supports_vmx(void)
3562 {
3563 uint32_t ecx, unused;
3564
3565 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3566 return ecx & CPUID_EXT_VMX;
3567 }
3568
3569 #define VMX_INVALID_GUEST_STATE 0x80000021
3570
3571 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3572 {
3573 X86CPU *cpu = X86_CPU(cs);
3574 uint64_t code;
3575 int ret;
3576
3577 switch (run->exit_reason) {
3578 case KVM_EXIT_HLT:
3579 DPRINTF("handle_hlt\n");
3580 qemu_mutex_lock_iothread();
3581 ret = kvm_handle_halt(cpu);
3582 qemu_mutex_unlock_iothread();
3583 break;
3584 case KVM_EXIT_SET_TPR:
3585 ret = 0;
3586 break;
3587 case KVM_EXIT_TPR_ACCESS:
3588 qemu_mutex_lock_iothread();
3589 ret = kvm_handle_tpr_access(cpu);
3590 qemu_mutex_unlock_iothread();
3591 break;
3592 case KVM_EXIT_FAIL_ENTRY:
3593 code = run->fail_entry.hardware_entry_failure_reason;
3594 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3595 code);
3596 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3597 fprintf(stderr,
3598 "\nIf you're running a guest on an Intel machine without "
3599 "unrestricted mode\n"
3600 "support, the failure can be most likely due to the guest "
3601 "entering an invalid\n"
3602 "state for Intel VT. For example, the guest maybe running "
3603 "in big real mode\n"
3604 "which is not supported on less recent Intel processors."
3605 "\n\n");
3606 }
3607 ret = -1;
3608 break;
3609 case KVM_EXIT_EXCEPTION:
3610 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3611 run->ex.exception, run->ex.error_code);
3612 ret = -1;
3613 break;
3614 case KVM_EXIT_DEBUG:
3615 DPRINTF("kvm_exit_debug\n");
3616 qemu_mutex_lock_iothread();
3617 ret = kvm_handle_debug(cpu, &run->debug.arch);
3618 qemu_mutex_unlock_iothread();
3619 break;
3620 case KVM_EXIT_HYPERV:
3621 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3622 break;
3623 case KVM_EXIT_IOAPIC_EOI:
3624 ioapic_eoi_broadcast(run->eoi.vector);
3625 ret = 0;
3626 break;
3627 default:
3628 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3629 ret = -1;
3630 break;
3631 }
3632
3633 return ret;
3634 }
3635
3636 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3637 {
3638 X86CPU *cpu = X86_CPU(cs);
3639 CPUX86State *env = &cpu->env;
3640
3641 kvm_cpu_synchronize_state(cs);
3642 return !(env->cr[0] & CR0_PE_MASK) ||
3643 ((env->segs[R_CS].selector & 3) != 3);
3644 }
3645
3646 void kvm_arch_init_irq_routing(KVMState *s)
3647 {
3648 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3649 /* If kernel can't do irq routing, interrupt source
3650 * override 0->2 cannot be set up as required by HPET.
3651 * So we have to disable it.
3652 */
3653 no_hpet = 1;
3654 }
3655 /* We know at this point that we're using the in-kernel
3656 * irqchip, so we can use irqfds, and on x86 we know
3657 * we can use msi via irqfd and GSI routing.
3658 */
3659 kvm_msi_via_irqfd_allowed = true;
3660 kvm_gsi_routing_allowed = true;
3661
3662 if (kvm_irqchip_is_split()) {
3663 int i;
3664
3665 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3666 MSI routes for signaling interrupts to the local apics. */
3667 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3668 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3669 error_report("Could not enable split IRQ mode.");
3670 exit(1);
3671 }
3672 }
3673 }
3674 }
3675
3676 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3677 {
3678 int ret;
3679 if (machine_kernel_irqchip_split(ms)) {
3680 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3681 if (ret) {
3682 error_report("Could not enable split irqchip mode: %s",
3683 strerror(-ret));
3684 exit(1);
3685 } else {
3686 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3687 kvm_split_irqchip = true;
3688 return 1;
3689 }
3690 } else {
3691 return 0;
3692 }
3693 }
3694
3695 /* Classic KVM device assignment interface. Will remain x86 only. */
3696 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3697 uint32_t flags, uint32_t *dev_id)
3698 {
3699 struct kvm_assigned_pci_dev dev_data = {
3700 .segnr = dev_addr->domain,
3701 .busnr = dev_addr->bus,
3702 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3703 .flags = flags,
3704 };
3705 int ret;
3706
3707 dev_data.assigned_dev_id =
3708 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3709
3710 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3711 if (ret < 0) {
3712 return ret;
3713 }
3714
3715 *dev_id = dev_data.assigned_dev_id;
3716
3717 return 0;
3718 }
3719
3720 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3721 {
3722 struct kvm_assigned_pci_dev dev_data = {
3723 .assigned_dev_id = dev_id,
3724 };
3725
3726 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3727 }
3728
3729 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3730 uint32_t irq_type, uint32_t guest_irq)
3731 {
3732 struct kvm_assigned_irq assigned_irq = {
3733 .assigned_dev_id = dev_id,
3734 .guest_irq = guest_irq,
3735 .flags = irq_type,
3736 };
3737
3738 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3739 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3740 } else {
3741 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3742 }
3743 }
3744
3745 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3746 uint32_t guest_irq)
3747 {
3748 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3749 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3750
3751 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3752 }
3753
3754 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3755 {
3756 struct kvm_assigned_pci_dev dev_data = {
3757 .assigned_dev_id = dev_id,
3758 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3759 };
3760
3761 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3762 }
3763
3764 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3765 uint32_t type)
3766 {
3767 struct kvm_assigned_irq assigned_irq = {
3768 .assigned_dev_id = dev_id,
3769 .flags = type,
3770 };
3771
3772 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3773 }
3774
3775 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3776 {
3777 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3778 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3779 }
3780
3781 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3782 {
3783 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3784 KVM_DEV_IRQ_GUEST_MSI, virq);
3785 }
3786
3787 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3788 {
3789 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3790 KVM_DEV_IRQ_HOST_MSI);
3791 }
3792
3793 bool kvm_device_msix_supported(KVMState *s)
3794 {
3795 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3796 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3797 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3798 }
3799
3800 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3801 uint32_t nr_vectors)
3802 {
3803 struct kvm_assigned_msix_nr msix_nr = {
3804 .assigned_dev_id = dev_id,
3805 .entry_nr = nr_vectors,
3806 };
3807
3808 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3809 }
3810
3811 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3812 int virq)
3813 {
3814 struct kvm_assigned_msix_entry msix_entry = {
3815 .assigned_dev_id = dev_id,
3816 .gsi = virq,
3817 .entry = vector,
3818 };
3819
3820 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3821 }
3822
3823 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3824 {
3825 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3826 KVM_DEV_IRQ_GUEST_MSIX, 0);
3827 }
3828
3829 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3830 {
3831 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3832 KVM_DEV_IRQ_HOST_MSIX);
3833 }
3834
3835 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3836 uint64_t address, uint32_t data, PCIDevice *dev)
3837 {
3838 X86IOMMUState *iommu = x86_iommu_get_default();
3839
3840 if (iommu) {
3841 int ret;
3842 MSIMessage src, dst;
3843 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3844
3845 if (!class->int_remap) {
3846 return 0;
3847 }
3848
3849 src.address = route->u.msi.address_hi;
3850 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3851 src.address |= route->u.msi.address_lo;
3852 src.data = route->u.msi.data;
3853
3854 ret = class->int_remap(iommu, &src, &dst, dev ? \
3855 pci_requester_id(dev) : \
3856 X86_IOMMU_SID_INVALID);
3857 if (ret) {
3858 trace_kvm_x86_fixup_msi_error(route->gsi);
3859 return 1;
3860 }
3861
3862 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3863 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3864 route->u.msi.data = dst.data;
3865 }
3866
3867 return 0;
3868 }
3869
3870 typedef struct MSIRouteEntry MSIRouteEntry;
3871
3872 struct MSIRouteEntry {
3873 PCIDevice *dev; /* Device pointer */
3874 int vector; /* MSI/MSIX vector index */
3875 int virq; /* Virtual IRQ index */
3876 QLIST_ENTRY(MSIRouteEntry) list;
3877 };
3878
3879 /* List of used GSI routes */
3880 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3881 QLIST_HEAD_INITIALIZER(msi_route_list);
3882
3883 static void kvm_update_msi_routes_all(void *private, bool global,
3884 uint32_t index, uint32_t mask)
3885 {
3886 int cnt = 0;
3887 MSIRouteEntry *entry;
3888 MSIMessage msg;
3889 PCIDevice *dev;
3890
3891 /* TODO: explicit route update */
3892 QLIST_FOREACH(entry, &msi_route_list, list) {
3893 cnt++;
3894 dev = entry->dev;
3895 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3896 continue;
3897 }
3898 msg = pci_get_msi_message(dev, entry->vector);
3899 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3900 }
3901 kvm_irqchip_commit_routes(kvm_state);
3902 trace_kvm_x86_update_msi_routes(cnt);
3903 }
3904
3905 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3906 int vector, PCIDevice *dev)
3907 {
3908 static bool notify_list_inited = false;
3909 MSIRouteEntry *entry;
3910
3911 if (!dev) {
3912 /* These are (possibly) IOAPIC routes only used for split
3913 * kernel irqchip mode, while what we are housekeeping are
3914 * PCI devices only. */
3915 return 0;
3916 }
3917
3918 entry = g_new0(MSIRouteEntry, 1);
3919 entry->dev = dev;
3920 entry->vector = vector;
3921 entry->virq = route->gsi;
3922 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3923
3924 trace_kvm_x86_add_msi_route(route->gsi);
3925
3926 if (!notify_list_inited) {
3927 /* For the first time we do add route, add ourselves into
3928 * IOMMU's IEC notify list if needed. */
3929 X86IOMMUState *iommu = x86_iommu_get_default();
3930 if (iommu) {
3931 x86_iommu_iec_register_notifier(iommu,
3932 kvm_update_msi_routes_all,
3933 NULL);
3934 }
3935 notify_list_inited = true;
3936 }
3937 return 0;
3938 }
3939
3940 int kvm_arch_release_virq_post(int virq)
3941 {
3942 MSIRouteEntry *entry, *next;
3943 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3944 if (entry->virq == virq) {
3945 trace_kvm_x86_remove_msi_route(virq);
3946 QLIST_REMOVE(entry, list);
3947 g_free(entry);
3948 break;
3949 }
3950 }
3951 return 0;
3952 }
3953
3954 int kvm_arch_msi_data_to_gsi(uint32_t data)
3955 {
3956 abort();
3957 }
AR7 emulation for QEMU