target/openrisc/cpu.h

   1 /*
   2  * OpenRISC virtual CPU header.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef OPENRISC_CPU_H
  21 #define OPENRISC_CPU_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUArchState struct CPUOpenRISCState
  26
  27 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
  28 struct OpenRISCCPU;
  29
  30 #include "qemu-common.h"
  31 #include "exec/cpu-defs.h"
  32 #include "fpu/softfloat.h"
  33 #include "qom/cpu.h"
  34
  35 #define TYPE_OPENRISC_CPU "or1k-cpu"
  36
  37 #define OPENRISC_CPU_CLASS(klass) \
  38     OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
  39 #define OPENRISC_CPU(obj) \
  40     OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
  41 #define OPENRISC_CPU_GET_CLASS(obj) \
  42     OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
  43
  44 /**
  45  * OpenRISCCPUClass:
  46  * @parent_realize: The parent class' realize handler.
  47  * @parent_reset: The parent class' reset handler.
  48  *
  49  * A OpenRISC CPU model.
  50  */
  51 typedef struct OpenRISCCPUClass {
  52     /*< private >*/
  53     CPUClass parent_class;
  54     /*< public >*/
  55
  56     DeviceRealize parent_realize;
  57     void (*parent_reset)(CPUState *cpu);
  58 } OpenRISCCPUClass;
  59
  60 #define NB_MMU_MODES    3
  61 #define TARGET_INSN_START_EXTRA_WORDS 1
  62
  63 enum {
  64     MMU_NOMMU_IDX = 0,
  65     MMU_SUPERVISOR_IDX = 1,
  66     MMU_USER_IDX = 2,
  67 };
  68
  69 #define TARGET_PAGE_BITS 13
  70
  71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  73
  74 #define SET_FP_CAUSE(reg, v)    do {\
  75                                     (reg) = ((reg) & ~(0x3f << 12)) | \
  76                                             ((v & 0x3f) << 12);\
  77                                 } while (0)
  78 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  79 #define UPDATE_FP_FLAGS(reg, v)   do {\
  80                                       (reg) |= ((v & 0x1f) << 2);\
  81                                   } while (0)
  82
  83 /* Version Register */
  84 #define SPR_VR 0xFFFF003F
  85
  86 /* Interrupt */
  87 #define NR_IRQS  32
  88
  89 /* Unit presece register */
  90 enum {
  91     UPR_UP = (1 << 0),
  92     UPR_DCP = (1 << 1),
  93     UPR_ICP = (1 << 2),
  94     UPR_DMP = (1 << 3),
  95     UPR_IMP = (1 << 4),
  96     UPR_MP = (1 << 5),
  97     UPR_DUP = (1 << 6),
  98     UPR_PCUR = (1 << 7),
  99     UPR_PMP = (1 << 8),
 100     UPR_PICP = (1 << 9),
 101     UPR_TTP = (1 << 10),
 102     UPR_CUP = (255 << 24),
 103 };
 104
 105 /* CPU configure register */
 106 enum {
 107     CPUCFGR_NSGF = (15 << 0),
 108     CPUCFGR_CGF = (1 << 4),
 109     CPUCFGR_OB32S = (1 << 5),
 110     CPUCFGR_OB64S = (1 << 6),
 111     CPUCFGR_OF32S = (1 << 7),
 112     CPUCFGR_OF64S = (1 << 8),
 113     CPUCFGR_OV64S = (1 << 9),
 114     /* CPUCFGR_ND = (1 << 10), */
 115     /* CPUCFGR_AVRP = (1 << 11), */
 116     CPUCFGR_EVBARP = (1 << 12),
 117     /* CPUCFGR_ISRP = (1 << 13), */
 118     /* CPUCFGR_AECSRP = (1 << 14), */
 119 };
 120
 121 /* DMMU configure register */
 122 enum {
 123     DMMUCFGR_NTW = (3 << 0),
 124     DMMUCFGR_NTS = (7 << 2),
 125     DMMUCFGR_NAE = (7 << 5),
 126     DMMUCFGR_CRI = (1 << 8),
 127     DMMUCFGR_PRI = (1 << 9),
 128     DMMUCFGR_TEIRI = (1 << 10),
 129     DMMUCFGR_HTR = (1 << 11),
 130 };
 131
 132 /* IMMU configure register */
 133 enum {
 134     IMMUCFGR_NTW = (3 << 0),
 135     IMMUCFGR_NTS = (7 << 2),
 136     IMMUCFGR_NAE = (7 << 5),
 137     IMMUCFGR_CRI = (1 << 8),
 138     IMMUCFGR_PRI = (1 << 9),
 139     IMMUCFGR_TEIRI = (1 << 10),
 140     IMMUCFGR_HTR = (1 << 11),
 141 };
 142
 143 /* Power management register */
 144 enum {
 145     PMR_SDF = (15 << 0),
 146     PMR_DME = (1 << 4),
 147     PMR_SME = (1 << 5),
 148     PMR_DCGE = (1 << 6),
 149     PMR_SUME = (1 << 7),
 150 };
 151
 152 /* Float point control status register */
 153 enum {
 154     FPCSR_FPEE = 1,
 155     FPCSR_RM = (3 << 1),
 156     FPCSR_OVF = (1 << 3),
 157     FPCSR_UNF = (1 << 4),
 158     FPCSR_SNF = (1 << 5),
 159     FPCSR_QNF = (1 << 6),
 160     FPCSR_ZF = (1 << 7),
 161     FPCSR_IXF = (1 << 8),
 162     FPCSR_IVF = (1 << 9),
 163     FPCSR_INF = (1 << 10),
 164     FPCSR_DZF = (1 << 11),
 165 };
 166
 167 /* Exceptions indices */
 168 enum {
 169     EXCP_RESET    = 0x1,
 170     EXCP_BUSERR   = 0x2,
 171     EXCP_DPF      = 0x3,
 172     EXCP_IPF      = 0x4,
 173     EXCP_TICK     = 0x5,
 174     EXCP_ALIGN    = 0x6,
 175     EXCP_ILLEGAL  = 0x7,
 176     EXCP_INT      = 0x8,
 177     EXCP_DTLBMISS = 0x9,
 178     EXCP_ITLBMISS = 0xa,
 179     EXCP_RANGE    = 0xb,
 180     EXCP_SYSCALL  = 0xc,
 181     EXCP_FPE      = 0xd,
 182     EXCP_TRAP     = 0xe,
 183     EXCP_NR,
 184 };
 185
 186 /* Supervisor register */
 187 enum {
 188     SR_SM = (1 << 0),
 189     SR_TEE = (1 << 1),
 190     SR_IEE = (1 << 2),
 191     SR_DCE = (1 << 3),
 192     SR_ICE = (1 << 4),
 193     SR_DME = (1 << 5),
 194     SR_IME = (1 << 6),
 195     SR_LEE = (1 << 7),
 196     SR_CE  = (1 << 8),
 197     SR_F   = (1 << 9),
 198     SR_CY  = (1 << 10),
 199     SR_OV  = (1 << 11),
 200     SR_OVE = (1 << 12),
 201     SR_DSX = (1 << 13),
 202     SR_EPH = (1 << 14),
 203     SR_FO  = (1 << 15),
 204     SR_SUMRA = (1 << 16),
 205     SR_SCE = (1 << 17),
 206 };
 207
 208 /* Tick Timer Mode Register */
 209 enum {
 210     TTMR_TP = (0xfffffff),
 211     TTMR_IP = (1 << 28),
 212     TTMR_IE = (1 << 29),
 213     TTMR_M  = (3 << 30),
 214 };
 215
 216 /* Timer Mode */
 217 enum {
 218     TIMER_NONE = (0 << 30),
 219     TIMER_INTR = (1 << 30),
 220     TIMER_SHOT = (2 << 30),
 221     TIMER_CONT = (3 << 30),
 222 };
 223
 224 /* TLB size */
 225 enum {
 226     DTLB_WAYS = 1,
 227     DTLB_SIZE = 64,
 228     DTLB_MASK = (DTLB_SIZE-1),
 229     ITLB_WAYS = 1,
 230     ITLB_SIZE = 64,
 231     ITLB_MASK = (ITLB_SIZE-1),
 232 };
 233
 234 /* TLB prot */
 235 enum {
 236     URE = (1 << 6),
 237     UWE = (1 << 7),
 238     SRE = (1 << 8),
 239     SWE = (1 << 9),
 240
 241     SXE = (1 << 6),
 242     UXE = (1 << 7),
 243 };
 244
 245 /* check if tlb available */
 246 enum {
 247     TLBRET_INVALID = -3,
 248     TLBRET_NOMATCH = -2,
 249     TLBRET_BADADDR = -1,
 250     TLBRET_MATCH = 0
 251 };
 252
 253 typedef struct OpenRISCTLBEntry {
 254     uint32_t mr;
 255     uint32_t tr;
 256 } OpenRISCTLBEntry;
 257
 258 #ifndef CONFIG_USER_ONLY
 259 typedef struct CPUOpenRISCTLBContext {
 260     OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
 261     OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
 262
 263     int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
 264                                          hwaddr *physical,
 265                                          int *prot,
 266                                          target_ulong address, int rw);
 267     int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
 268                                          hwaddr *physical,
 269                                          int *prot,
 270                                          target_ulong address, int rw);
 271 } CPUOpenRISCTLBContext;
 272 #endif
 273
 274 typedef struct CPUOpenRISCState {
 275     target_ulong shadow_gpr[16][32]; /* Shadow registers */
 276
 277     target_ulong pc;          /* Program counter */
 278     target_ulong ppc;         /* Prev PC */
 279     target_ulong jmp_pc;      /* Jump PC */
 280
 281     uint64_t mac;             /* Multiply registers MACHI:MACLO */
 282
 283     target_ulong epcr;        /* Exception PC register */
 284     target_ulong eear;        /* Exception EA register */
 285
 286     target_ulong sr_f;        /* the SR_F bit, values 0, 1.  */
 287     target_ulong sr_cy;       /* the SR_CY bit, values 0, 1.  */
 288     target_long  sr_ov;       /* the SR_OV bit (in the sign bit only) */
 289     uint32_t sr;              /* Supervisor register, without SR_{F,CY,OV} */
 290     uint32_t vr;              /* Version register */
 291     uint32_t upr;             /* Unit presence register */
 292     uint32_t dmmucfgr;        /* DMMU configure register */
 293     uint32_t immucfgr;        /* IMMU configure register */
 294     uint32_t esr;             /* Exception supervisor register */
 295     uint32_t evbar;           /* Exception vector base address register */
 296     uint32_t pmr;             /* Power Management Register */
 297     uint32_t fpcsr;           /* Float register */
 298     float_status fp_status;
 299
 300     target_ulong lock_addr;
 301     target_ulong lock_value;
 302
 303     uint32_t dflag;           /* In delay slot (boolean) */
 304
 305     /* Fields up to this point are cleared by a CPU reset */
 306     struct {} end_reset_fields;
 307
 308     CPU_COMMON
 309
 310     /* Fields from here on are preserved across CPU reset. */
 311     uint32_t cpucfgr;         /* CPU configure register */
 312
 313 #ifndef CONFIG_USER_ONLY
 314     CPUOpenRISCTLBContext * tlb;
 315
 316     QEMUTimer *timer;
 317     uint32_t ttmr;          /* Timer tick mode register */
 318     uint32_t ttcr;          /* Timer tick count register */
 319
 320     uint32_t picmr;         /* Interrupt mask register */
 321     uint32_t picsr;         /* Interrupt contrl register*/
 322 #endif
 323     void *irq[32];          /* Interrupt irq input */
 324 } CPUOpenRISCState;
 325
 326 /**
 327  * OpenRISCCPU:
 328  * @env: #CPUOpenRISCState
 329  *
 330  * A OpenRISC CPU.
 331  */
 332 typedef struct OpenRISCCPU {
 333     /*< private >*/
 334     CPUState parent_obj;
 335     /*< public >*/
 336
 337     CPUOpenRISCState env;
 338
 339 } OpenRISCCPU;
 340
 341 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
 342 {
 343     return container_of(env, OpenRISCCPU, env);
 344 }
 345
 346 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
 347
 348 #define ENV_OFFSET offsetof(OpenRISCCPU, env)
 349
 350 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
 351
 352 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
 353 void openrisc_cpu_do_interrupt(CPUState *cpu);
 354 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
 355 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
 356                              fprintf_function cpu_fprintf, int flags);
 357 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 358 int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 359 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 360 void openrisc_translate_init(void);
 361 int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
 362                                   int rw, int mmu_idx);
 363 int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
 364
 365 #define cpu_list cpu_openrisc_list
 366 #define cpu_signal_handler cpu_openrisc_signal_handler
 367
 368 #ifndef CONFIG_USER_ONLY
 369 extern const struct VMStateDescription vmstate_openrisc_cpu;
 370
 371 /* hw/openrisc_pic.c */
 372 void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
 373
 374 /* hw/openrisc_timer.c */
 375 void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
 376 void cpu_openrisc_count_update(OpenRISCCPU *cpu);
 377 void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
 378 void cpu_openrisc_count_start(OpenRISCCPU *cpu);
 379 void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 380
 381 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
 382 int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
 383                                 hwaddr *physical,
 384                                 int *prot, target_ulong address, int rw);
 385 int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
 386                                hwaddr *physical,
 387                                int *prot, target_ulong address, int rw);
 388 int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
 389                                hwaddr *physical,
 390                                int *prot, target_ulong address, int rw);
 391 #endif
 392
 393 #define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))
 394
 395 #include "exec/cpu-all.h"
 396
 397 #define TB_FLAGS_DFLAG 1
 398 #define TB_FLAGS_R0_0  2
 399 #define TB_FLAGS_OVE   SR_OVE
 400
 401 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i)
 402 {
 403     return env->shadow_gpr[0][i];
 404 }
 405
 406 static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
 407 {
 408     env->shadow_gpr[0][i] = val;
 409 }
 410
 411 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
 412                                         target_ulong *pc,
 413                                         target_ulong *cs_base, uint32_t *flags)
 414 {
 415     *pc = env->pc;
 416     *cs_base = 0;
 417     *flags = (env->dflag
 418               | (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0)
 419               | (env->sr & SR_OVE));
 420 }
 421
 422 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
 423 {
 424     if (!(env->sr & SR_IME)) {
 425         return MMU_NOMMU_IDX;
 426     }
 427     return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
 428 }
 429
 430 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
 431 {
 432     return (env->sr
 433             + env->sr_f * SR_F
 434             + env->sr_cy * SR_CY
 435             + (env->sr_ov < 0) * SR_OV);
 436 }
 437
 438 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val)
 439 {
 440     env->sr_f = (val & SR_F) != 0;
 441     env->sr_cy = (val & SR_CY) != 0;
 442     env->sr_ov = (val & SR_OV ? -1 : 0);
 443     env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
 444 }
 445
 446 #define CPU_INTERRUPT_TIMER   CPU_INTERRUPT_TGT_INT_0
 447
 448 #endif /* OPENRISC_CPU_H */