hw/ioh3420.c

   1 /*
   2  * ioh3420.c
   3  * Intel X58 north bridge IOH
   4  * PCI Express root port device id 3420
   5  *
   6  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   7  *                    VA Linux Systems Japan K.K.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "pci/pci_ids.h"
  24 #include "pci/msi.h"
  25 #include "pci/pcie.h"
  26 #include "ioh3420.h"
  27
  28 #define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
  29 #define PCI_DEVICE_ID_IOH_REV           0x2
  30 #define IOH_EP_SSVID_OFFSET             0x40
  31 #define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
  32 #define IOH_EP_SSVID_SSID               0
  33 #define IOH_EP_MSI_OFFSET               0x60
  34 #define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
  35 #define IOH_EP_MSI_NR_VECTOR            2
  36 #define IOH_EP_EXP_OFFSET               0x90
  37 #define IOH_EP_AER_OFFSET               0x100
  38
  39 /*
  40  * If two MSI vector are allocated, Advanced Error Interrupt Message Number
  41  * is 1. otherwise 0.
  42  * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
  43  */
  44 static uint8_t ioh3420_aer_vector(const PCIDevice *d)
  45 {
  46     switch (msi_nr_vectors_allocated(d)) {
  47     case 1:
  48         return 0;
  49     case 2:
  50         return 1;
  51     case 4:
  52     case 8:
  53     case 16:
  54     case 32:
  55     default:
  56         break;
  57     }
  58     abort();
  59     return 0;
  60 }
  61
  62 static void ioh3420_aer_vector_update(PCIDevice *d)
  63 {
  64     pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
  65 }
  66
  67 static void ioh3420_write_config(PCIDevice *d,
  68                                    uint32_t address, uint32_t val, int len)
  69 {
  70     uint32_t root_cmd =
  71         pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
  72
  73     pci_bridge_write_config(d, address, val, len);
  74     ioh3420_aer_vector_update(d);
  75     pcie_cap_slot_write_config(d, address, val, len);
  76     pcie_aer_write_config(d, address, val, len);
  77     pcie_aer_root_write_config(d, address, val, len, root_cmd);
  78 }
  79
  80 static void ioh3420_reset(DeviceState *qdev)
  81 {
  82     PCIDevice *d = PCI_DEVICE(qdev);
  83
  84     ioh3420_aer_vector_update(d);
  85     pcie_cap_root_reset(d);
  86     pcie_cap_deverr_reset(d);
  87     pcie_cap_slot_reset(d);
  88     pcie_aer_root_reset(d);
  89     pci_bridge_reset(qdev);
  90     pci_bridge_disable_base_limit(d);
  91 }
  92
  93 static int ioh3420_initfn(PCIDevice *d)
  94 {
  95     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  96     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  97     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
  98     int rc;
  99
 100     rc = pci_bridge_initfn(d);
 101     if (rc < 0) {
 102         return rc;
 103     }
 104
 105     pcie_port_init_reg(d);
 106
 107     rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
 108                                IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
 109     if (rc < 0) {
 110         goto err_bridge;
 111     }
 112     rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
 113                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
 114                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
 115     if (rc < 0) {
 116         goto err_bridge;
 117     }
 118     rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
 119     if (rc < 0) {
 120         goto err_msi;
 121     }
 122     pcie_cap_deverr_init(d);
 123     pcie_cap_slot_init(d, s->slot);
 124     pcie_chassis_create(s->chassis);
 125     rc = pcie_chassis_add_slot(s);
 126     if (rc < 0) {
 127         goto err_pcie_cap;
 128     }
 129     pcie_cap_root_init(d);
 130     rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
 131     if (rc < 0) {
 132         goto err;
 133     }
 134     pcie_aer_root_init(d);
 135     ioh3420_aer_vector_update(d);
 136     return 0;
 137
 138 err:
 139     pcie_chassis_del_slot(s);
 140 err_pcie_cap:
 141     pcie_cap_exit(d);
 142 err_msi:
 143     msi_uninit(d);
 144 err_bridge:
 145     pci_bridge_exitfn(d);
 146     return rc;
 147 }
 148
 149 static void ioh3420_exitfn(PCIDevice *d)
 150 {
 151     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
 152     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
 153     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
 154
 155     pcie_aer_exit(d);
 156     pcie_chassis_del_slot(s);
 157     pcie_cap_exit(d);
 158     msi_uninit(d);
 159     pci_bridge_exitfn(d);
 160 }
 161
 162 PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
 163                          const char *bus_name, pci_map_irq_fn map_irq,
 164                          uint8_t port, uint8_t chassis, uint16_t slot)
 165 {
 166     PCIDevice *d;
 167     PCIBridge *br;
 168     DeviceState *qdev;
 169
 170     d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
 171     if (!d) {
 172         return NULL;
 173     }
 174     br = DO_UPCAST(PCIBridge, dev, d);
 175
 176     qdev = &br->dev.qdev;
 177     pci_bridge_map_irq(br, bus_name, map_irq);
 178     qdev_prop_set_uint8(qdev, "port", port);
 179     qdev_prop_set_uint8(qdev, "chassis", chassis);
 180     qdev_prop_set_uint16(qdev, "slot", slot);
 181     qdev_init_nofail(qdev);
 182
 183     return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
 184 }
 185
 186 static const VMStateDescription vmstate_ioh3420 = {
 187     .name = "ioh-3240-express-root-port",
 188     .version_id = 1,
 189     .minimum_version_id = 1,
 190     .minimum_version_id_old = 1,
 191     .post_load = pcie_cap_slot_post_load,
 192     .fields = (VMStateField[]) {
 193         VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
 194         VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
 195                        vmstate_pcie_aer_log, PCIEAERLog),
 196         VMSTATE_END_OF_LIST()
 197     }
 198 };
 199
 200 static Property ioh3420_properties[] = {
 201     DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
 202     DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 203     DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 204     DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
 205     port.br.dev.exp.aer_log.log_max,
 206     PCIE_AER_LOG_MAX_DEFAULT),
 207     DEFINE_PROP_END_OF_LIST(),
 208 };
 209
 210 static void ioh3420_class_init(ObjectClass *klass, void *data)
 211 {
 212     DeviceClass *dc = DEVICE_CLASS(klass);
 213     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 214
 215     k->is_express = 1;
 216     k->is_bridge = 1;
 217     k->config_write = ioh3420_write_config;
 218     k->init = ioh3420_initfn;
 219     k->exit = ioh3420_exitfn;
 220     k->vendor_id = PCI_VENDOR_ID_INTEL;
 221     k->device_id = PCI_DEVICE_ID_IOH_EPORT;
 222     k->revision = PCI_DEVICE_ID_IOH_REV;
 223     dc->desc = "Intel IOH device id 3420 PCIE Root Port";
 224     dc->reset = ioh3420_reset;
 225     dc->vmsd = &vmstate_ioh3420;
 226     dc->props = ioh3420_properties;
 227 }
 228
 229 static const TypeInfo ioh3420_info = {
 230     .name          = "ioh3420",
 231     .parent        = TYPE_PCI_DEVICE,
 232     .instance_size = sizeof(PCIESlot),
 233     .class_init    = ioh3420_class_init,
 234 };
 235
 236 static void ioh3420_register_types(void)
 237 {
 238     type_register_static(&ioh3420_info);
 239 }
 240
 241 type_init(ioh3420_register_types)
 242
 243 /*
 244  * Local variables:
 245  *  c-indent-level: 4
 246  *  c-basic-offset: 4
 247  *  tab-width: 8
 248  *  indent-tab-mode: nil
 249  * End:
 250  */