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ahci: add host register enumeration
[qemu/ar7.git] / hw / ide / ahci.c
blob5be43ba2d07bf5f573f4f75316b23dd93234c1fe
1 /*
2 * QEMU AHCI Emulation
3 *
4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci.h"
28
29 #include "qemu/error-report.h"
30 #include "qemu/log.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/dma.h"
33 #include "hw/ide/internal.h"
34 #include "hw/ide/pci.h"
35 #include "ahci_internal.h"
36
37 #include "trace.h"
38
39 static void check_cmd(AHCIState *s, int port);
40 static int handle_cmd(AHCIState *s, int port, uint8_t slot);
41 static void ahci_reset_port(AHCIState *s, int port);
42 static bool ahci_write_fis_d2h(AHCIDevice *ad);
43 static void ahci_init_d2h(AHCIDevice *ad);
44 static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit);
45 static bool ahci_map_clb_address(AHCIDevice *ad);
46 static bool ahci_map_fis_address(AHCIDevice *ad);
47 static void ahci_unmap_clb_address(AHCIDevice *ad);
48 static void ahci_unmap_fis_address(AHCIDevice *ad);
49
50 __attribute__((__unused__)) /* TODO */
51 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = {
52 [AHCI_HOST_REG_CAP] = "CAP",
53 [AHCI_HOST_REG_CTL] = "GHC",
54 [AHCI_HOST_REG_IRQ_STAT] = "IS",
55 [AHCI_HOST_REG_PORTS_IMPL] = "PI",
56 [AHCI_HOST_REG_VERSION] = "VS",
57 [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL",
58 [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS",
59 [AHCI_HOST_REG_EM_LOC] = "EM_LOC",
60 [AHCI_HOST_REG_EM_CTL] = "EM_CTL",
61 [AHCI_HOST_REG_CAP2] = "CAP2",
62 [AHCI_HOST_REG_BOHC] = "BOHC",
63 };
64
65 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = {
66 [AHCI_PORT_REG_LST_ADDR] = "PxCLB",
67 [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU",
68 [AHCI_PORT_REG_FIS_ADDR] = "PxFB",
69 [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU",
70 [AHCI_PORT_REG_IRQ_STAT] = "PxIS",
71 [AHCI_PORT_REG_IRQ_MASK] = "PXIE",
72 [AHCI_PORT_REG_CMD] = "PxCMD",
73 [7] = "Reserved",
74 [AHCI_PORT_REG_TFDATA] = "PxTFD",
75 [AHCI_PORT_REG_SIG] = "PxSIG",
76 [AHCI_PORT_REG_SCR_STAT] = "PxSSTS",
77 [AHCI_PORT_REG_SCR_CTL] = "PxSCTL",
78 [AHCI_PORT_REG_SCR_ERR] = "PxSERR",
79 [AHCI_PORT_REG_SCR_ACT] = "PxSACT",
80 [AHCI_PORT_REG_CMD_ISSUE] = "PxCI",
81 [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF",
82 [AHCI_PORT_REG_FIS_CTL] = "PxFBS",
83 [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP",
84 [18 ... 27] = "Reserved",
85 [AHCI_PORT_REG_VENDOR_1 ...
86 AHCI_PORT_REG_VENDOR_4] = "PxVS",
87 };
88
89 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = {
90 [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
91 [AHCI_PORT_IRQ_BIT_PSS] = "PSS",
92 [AHCI_PORT_IRQ_BIT_DSS] = "DSS",
93 [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS",
94 [AHCI_PORT_IRQ_BIT_UFS] = "UFS",
95 [AHCI_PORT_IRQ_BIT_DPS] = "DPS",
96 [AHCI_PORT_IRQ_BIT_PCS] = "PCS",
97 [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS",
98 [8 ... 21] = "RESERVED",
99 [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS",
100 [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS",
101 [AHCI_PORT_IRQ_BIT_OFS] = "OFS",
102 [25] = "RESERVED",
103 [AHCI_PORT_IRQ_BIT_INFS] = "INFS",
104 [AHCI_PORT_IRQ_BIT_IFS] = "IFS",
105 [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS",
106 [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS",
107 [AHCI_PORT_IRQ_BIT_TFES] = "TFES",
108 [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
109 };
110
111 static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
112 {
113 uint32_t val;
114 AHCIPortRegs *pr = &s->dev[port].port_regs;
115 enum AHCIPortReg regnum = offset / sizeof(uint32_t);
116 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
117
118 switch (regnum) {
119 case AHCI_PORT_REG_LST_ADDR:
120 val = pr->lst_addr;
121 break;
122 case AHCI_PORT_REG_LST_ADDR_HI:
123 val = pr->lst_addr_hi;
124 break;
125 case AHCI_PORT_REG_FIS_ADDR:
126 val = pr->fis_addr;
127 break;
128 case AHCI_PORT_REG_FIS_ADDR_HI:
129 val = pr->fis_addr_hi;
130 break;
131 case AHCI_PORT_REG_IRQ_STAT:
132 val = pr->irq_stat;
133 break;
134 case AHCI_PORT_REG_IRQ_MASK:
135 val = pr->irq_mask;
136 break;
137 case AHCI_PORT_REG_CMD:
138 val = pr->cmd;
139 break;
140 case AHCI_PORT_REG_TFDATA:
141 val = pr->tfdata;
142 break;
143 case AHCI_PORT_REG_SIG:
144 val = pr->sig;
145 break;
146 case AHCI_PORT_REG_SCR_STAT:
147 if (s->dev[port].port.ifs[0].blk) {
148 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
149 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
150 } else {
151 val = SATA_SCR_SSTATUS_DET_NODEV;
152 }
153 break;
154 case AHCI_PORT_REG_SCR_CTL:
155 val = pr->scr_ctl;
156 break;
157 case AHCI_PORT_REG_SCR_ERR:
158 val = pr->scr_err;
159 break;
160 case AHCI_PORT_REG_SCR_ACT:
161 val = pr->scr_act;
162 break;
163 case AHCI_PORT_REG_CMD_ISSUE:
164 val = pr->cmd_issue;
165 break;
166 default:
167 trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum],
168 offset);
169 val = 0;
170 }
171
172 trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val);
173 return val;
174 }
175
176 static void ahci_irq_raise(AHCIState *s)
177 {
178 DeviceState *dev_state = s->container;
179 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
180 TYPE_PCI_DEVICE);
181
182 trace_ahci_irq_raise(s);
183
184 if (pci_dev && msi_enabled(pci_dev)) {
185 msi_notify(pci_dev, 0);
186 } else {
187 qemu_irq_raise(s->irq);
188 }
189 }
190
191 static void ahci_irq_lower(AHCIState *s)
192 {
193 DeviceState *dev_state = s->container;
194 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
195 TYPE_PCI_DEVICE);
196
197 trace_ahci_irq_lower(s);
198
199 if (!pci_dev || !msi_enabled(pci_dev)) {
200 qemu_irq_lower(s->irq);
201 }
202 }
203
204 static void ahci_check_irq(AHCIState *s)
205 {
206 int i;
207 uint32_t old_irq = s->control_regs.irqstatus;
208
209 s->control_regs.irqstatus = 0;
210 for (i = 0; i < s->ports; i++) {
211 AHCIPortRegs *pr = &s->dev[i].port_regs;
212 if (pr->irq_stat & pr->irq_mask) {
213 s->control_regs.irqstatus |= (1 << i);
214 }
215 }
216 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus);
217 if (s->control_regs.irqstatus &&
218 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
219 ahci_irq_raise(s);
220 } else {
221 ahci_irq_lower(s);
222 }
223 }
224
225 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
226 enum AHCIPortIRQ irqbit)
227 {
228 g_assert((unsigned)irqbit < 32);
229 uint32_t irq = 1U << irqbit;
230 uint32_t irqstat = d->port_regs.irq_stat | irq;
231
232 trace_ahci_trigger_irq(s, d->port_no,
233 AHCIPortIRQ_lookup[irqbit], irq,
234 d->port_regs.irq_stat, irqstat,
235 irqstat & d->port_regs.irq_mask);
236
237 d->port_regs.irq_stat = irqstat;
238 ahci_check_irq(s);
239 }
240
241 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr,
242 uint32_t wanted)
243 {
244 hwaddr len = wanted;
245
246 if (*ptr) {
247 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
248 }
249
250 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE);
251 if (len < wanted) {
252 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
253 *ptr = NULL;
254 }
255 }
256
257 /**
258 * Check the cmd register to see if we should start or stop
259 * the DMA or FIS RX engines.
260 *
261 * @ad: Device to dis/engage.
262 *
263 * @return 0 on success, -1 on error.
264 */
265 static int ahci_cond_start_engines(AHCIDevice *ad)
266 {
267 AHCIPortRegs *pr = &ad->port_regs;
268 bool cmd_start = pr->cmd & PORT_CMD_START;
269 bool cmd_on = pr->cmd & PORT_CMD_LIST_ON;
270 bool fis_start = pr->cmd & PORT_CMD_FIS_RX;
271 bool fis_on = pr->cmd & PORT_CMD_FIS_ON;
272
273 if (cmd_start && !cmd_on) {
274 if (!ahci_map_clb_address(ad)) {
275 pr->cmd &= ~PORT_CMD_START;
276 error_report("AHCI: Failed to start DMA engine: "
277 "bad command list buffer address");
278 return -1;
279 }
280 } else if (!cmd_start && cmd_on) {
281 ahci_unmap_clb_address(ad);
282 }
283
284 if (fis_start && !fis_on) {
285 if (!ahci_map_fis_address(ad)) {
286 pr->cmd &= ~PORT_CMD_FIS_RX;
287 error_report("AHCI: Failed to start FIS receive engine: "
288 "bad FIS receive buffer address");
289 return -1;
290 }
291 } else if (!fis_start && fis_on) {
292 ahci_unmap_fis_address(ad);
293 }
294
295 return 0;
296 }
297
298 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
299 {
300 AHCIPortRegs *pr = &s->dev[port].port_regs;
301 enum AHCIPortReg regnum = offset / sizeof(uint32_t);
302 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
303 trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val);
304
305 switch (regnum) {
306 case AHCI_PORT_REG_LST_ADDR:
307 pr->lst_addr = val;
308 break;
309 case AHCI_PORT_REG_LST_ADDR_HI:
310 pr->lst_addr_hi = val;
311 break;
312 case AHCI_PORT_REG_FIS_ADDR:
313 pr->fis_addr = val;
314 break;
315 case AHCI_PORT_REG_FIS_ADDR_HI:
316 pr->fis_addr_hi = val;
317 break;
318 case AHCI_PORT_REG_IRQ_STAT:
319 pr->irq_stat &= ~val;
320 ahci_check_irq(s);
321 break;
322 case AHCI_PORT_REG_IRQ_MASK:
323 pr->irq_mask = val & 0xfdc000ff;
324 ahci_check_irq(s);
325 break;
326 case AHCI_PORT_REG_CMD:
327 /* Block any Read-only fields from being set;
328 * including LIST_ON and FIS_ON.
329 * The spec requires to set ICC bits to zero after the ICC change
330 * is done. We don't support ICC state changes, therefore always
331 * force the ICC bits to zero.
332 */
333 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
334 (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK));
335
336 /* Check FIS RX and CLB engines */
337 ahci_cond_start_engines(&s->dev[port]);
338
339 /* XXX usually the FIS would be pending on the bus here and
340 issuing deferred until the OS enables FIS receival.
341 Instead, we only submit it once - which works in most
342 cases, but is a hack. */
343 if ((pr->cmd & PORT_CMD_FIS_ON) &&
344 !s->dev[port].init_d2h_sent) {
345 ahci_init_d2h(&s->dev[port]);
346 }
347
348 check_cmd(s, port);
349 break;
350 case AHCI_PORT_REG_TFDATA:
351 case AHCI_PORT_REG_SIG:
352 case AHCI_PORT_REG_SCR_STAT:
353 /* Read Only */
354 break;
355 case AHCI_PORT_REG_SCR_CTL:
356 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
357 ((val & AHCI_SCR_SCTL_DET) == 0)) {
358 ahci_reset_port(s, port);
359 }
360 pr->scr_ctl = val;
361 break;
362 case AHCI_PORT_REG_SCR_ERR:
363 pr->scr_err &= ~val;
364 break;
365 case AHCI_PORT_REG_SCR_ACT:
366 /* RW1 */
367 pr->scr_act |= val;
368 break;
369 case AHCI_PORT_REG_CMD_ISSUE:
370 pr->cmd_issue |= val;
371 check_cmd(s, port);
372 break;
373 default:
374 trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum],
375 offset, val);
376 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
377 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32,
378 port, AHCIPortReg_lookup[regnum], offset, val);
379 break;
380 }
381 }
382
383 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
384 {
385 AHCIState *s = opaque;
386 uint32_t val = 0;
387
388 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
389 switch (addr) {
390 case HOST_CAP:
391 val = s->control_regs.cap;
392 break;
393 case HOST_CTL:
394 val = s->control_regs.ghc;
395 break;
396 case HOST_IRQ_STAT:
397 val = s->control_regs.irqstatus;
398 break;
399 case HOST_PORTS_IMPL:
400 val = s->control_regs.impl;
401 break;
402 case HOST_VERSION:
403 val = s->control_regs.version;
404 break;
405 }
406 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
407 (addr < (AHCI_PORT_REGS_START_ADDR +
408 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
409 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
410 addr & AHCI_PORT_ADDR_OFFSET_MASK);
411 }
412
413 trace_ahci_mem_read_32(s, addr, val);
414 return val;
415 }
416
417
418 /**
419 * AHCI 1.3 section 3 ("HBA Memory Registers")
420 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
421 * Caller is responsible for masking unwanted higher order bytes.
422 */
423 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)
424 {
425 hwaddr aligned = addr & ~0x3;
426 int ofst = addr - aligned;
427 uint64_t lo = ahci_mem_read_32(opaque, aligned);
428 uint64_t hi;
429 uint64_t val;
430
431 /* if < 8 byte read does not cross 4 byte boundary */
432 if (ofst + size <= 4) {
433 val = lo >> (ofst * 8);
434 } else {
435 g_assert_cmpint(size, >, 1);
436
437 /* If the 64bit read is unaligned, we will produce undefined
438 * results. AHCI does not support unaligned 64bit reads. */
439 hi = ahci_mem_read_32(opaque, aligned + 4);
440 val = (hi << 32 | lo) >> (ofst * 8);
441 }
442
443 trace_ahci_mem_read(opaque, size, addr, val);
444 return val;
445 }
446
447
448 static void ahci_mem_write(void *opaque, hwaddr addr,
449 uint64_t val, unsigned size)
450 {
451 AHCIState *s = opaque;
452
453 trace_ahci_mem_write(s, size, addr, val);
454
455 /* Only aligned reads are allowed on AHCI */
456 if (addr & 3) {
457 fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
458 TARGET_FMT_plx "\n", addr);
459 return;
460 }
461
462 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
463 switch (addr) {
464 case HOST_CAP: /* R/WO, RO */
465 /* FIXME handle R/WO */
466 break;
467 case HOST_CTL: /* R/W */
468 if (val & HOST_CTL_RESET) {
469 ahci_reset(s);
470 } else {
471 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
472 ahci_check_irq(s);
473 }
474 break;
475 case HOST_IRQ_STAT: /* R/WC, RO */
476 s->control_regs.irqstatus &= ~val;
477 ahci_check_irq(s);
478 break;
479 case HOST_PORTS_IMPL: /* R/WO, RO */
480 /* FIXME handle R/WO */
481 break;
482 case HOST_VERSION: /* RO */
483 /* FIXME report write? */
484 break;
485 default:
486 trace_ahci_mem_write_unknown(s, size, addr, val);
487 }
488 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
489 (addr < (AHCI_PORT_REGS_START_ADDR +
490 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
491 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
492 addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
493 }
494
495 }
496
497 static const MemoryRegionOps ahci_mem_ops = {
498 .read = ahci_mem_read,
499 .write = ahci_mem_write,
500 .endianness = DEVICE_LITTLE_ENDIAN,
501 };
502
503 static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
504 unsigned size)
505 {
506 AHCIState *s = opaque;
507
508 if (addr == s->idp_offset) {
509 /* index register */
510 return s->idp_index;
511 } else if (addr == s->idp_offset + 4) {
512 /* data register - do memory read at location selected by index */
513 return ahci_mem_read(opaque, s->idp_index, size);
514 } else {
515 return 0;
516 }
517 }
518
519 static void ahci_idp_write(void *opaque, hwaddr addr,
520 uint64_t val, unsigned size)
521 {
522 AHCIState *s = opaque;
523
524 if (addr == s->idp_offset) {
525 /* index register - mask off reserved bits */
526 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3);
527 } else if (addr == s->idp_offset + 4) {
528 /* data register - do memory write at location selected by index */
529 ahci_mem_write(opaque, s->idp_index, val, size);
530 }
531 }
532
533 static const MemoryRegionOps ahci_idp_ops = {
534 .read = ahci_idp_read,
535 .write = ahci_idp_write,
536 .endianness = DEVICE_LITTLE_ENDIAN,
537 };
538
539
540 static void ahci_reg_init(AHCIState *s)
541 {
542 int i;
543
544 s->control_regs.cap = (s->ports - 1) |
545 (AHCI_NUM_COMMAND_SLOTS << 8) |
546 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
547 HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64;
548
549 s->control_regs.impl = (1 << s->ports) - 1;
550
551 s->control_regs.version = AHCI_VERSION_1_0;
552
553 for (i = 0; i < s->ports; i++) {
554 s->dev[i].port_state = STATE_RUN;
555 }
556 }
557
558 static void check_cmd(AHCIState *s, int port)
559 {
560 AHCIPortRegs *pr = &s->dev[port].port_regs;
561 uint8_t slot;
562
563 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {
564 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
565 if ((pr->cmd_issue & (1U << slot)) &&
566 !handle_cmd(s, port, slot)) {
567 pr->cmd_issue &= ~(1U << slot);
568 }
569 }
570 }
571 }
572
573 static void ahci_check_cmd_bh(void *opaque)
574 {
575 AHCIDevice *ad = opaque;
576
577 qemu_bh_delete(ad->check_bh);
578 ad->check_bh = NULL;
579
580 check_cmd(ad->hba, ad->port_no);
581 }
582
583 static void ahci_init_d2h(AHCIDevice *ad)
584 {
585 IDEState *ide_state = &ad->port.ifs[0];
586 AHCIPortRegs *pr = &ad->port_regs;
587
588 if (ad->init_d2h_sent) {
589 return;
590 }
591
592 if (ahci_write_fis_d2h(ad)) {
593 ad->init_d2h_sent = true;
594 /* We're emulating receiving the first Reg H2D Fis from the device;
595 * Update the SIG register, but otherwise proceed as normal. */
596 pr->sig = ((uint32_t)ide_state->hcyl << 24) |
597 (ide_state->lcyl << 16) |
598 (ide_state->sector << 8) |
599 (ide_state->nsector & 0xFF);
600 }
601 }
602
603 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig)
604 {
605 IDEState *s = &ad->port.ifs[0];
606 s->hcyl = sig >> 24 & 0xFF;
607 s->lcyl = sig >> 16 & 0xFF;
608 s->sector = sig >> 8 & 0xFF;
609 s->nsector = sig & 0xFF;
610
611 trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector,
612 s->lcyl, s->hcyl, sig);
613 }
614
615 static void ahci_reset_port(AHCIState *s, int port)
616 {
617 AHCIDevice *d = &s->dev[port];
618 AHCIPortRegs *pr = &d->port_regs;
619 IDEState *ide_state = &d->port.ifs[0];
620 int i;
621
622 trace_ahci_reset_port(s, port);
623
624 ide_bus_reset(&d->port);
625 ide_state->ncq_queues = AHCI_MAX_CMDS;
626
627 pr->scr_stat = 0;
628 pr->scr_err = 0;
629 pr->scr_act = 0;
630 pr->tfdata = 0x7F;
631 pr->sig = 0xFFFFFFFF;
632 d->busy_slot = -1;
633 d->init_d2h_sent = false;
634
635 ide_state = &s->dev[port].port.ifs[0];
636 if (!ide_state->blk) {
637 return;
638 }
639
640 /* reset ncq queue */
641 for (i = 0; i < AHCI_MAX_CMDS; i++) {
642 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];
643 ncq_tfs->halt = false;
644 if (!ncq_tfs->used) {
645 continue;
646 }
647
648 if (ncq_tfs->aiocb) {
649 blk_aio_cancel(ncq_tfs->aiocb);
650 ncq_tfs->aiocb = NULL;
651 }
652
653 /* Maybe we just finished the request thanks to blk_aio_cancel() */
654 if (!ncq_tfs->used) {
655 continue;
656 }
657
658 qemu_sglist_destroy(&ncq_tfs->sglist);
659 ncq_tfs->used = 0;
660 }
661
662 s->dev[port].port_state = STATE_RUN;
663 if (ide_state->drive_kind == IDE_CD) {
664 ahci_set_signature(d, SATA_SIGNATURE_CDROM);\
665 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
666 } else {
667 ahci_set_signature(d, SATA_SIGNATURE_DISK);
668 ide_state->status = SEEK_STAT | WRERR_STAT;
669 }
670
671 ide_state->error = 1;
672 ahci_init_d2h(d);
673 }
674
675 /* Buffer pretty output based on a raw FIS structure. */
676 static char *ahci_pretty_buffer_fis(uint8_t *fis, int cmd_len)
677 {
678 int i;
679 GString *s = g_string_new("FIS:");
680
681 for (i = 0; i < cmd_len; i++) {
682 if ((i & 0xf) == 0) {
683 g_string_append_printf(s, "\n0x%02x: ", i);
684 }
685 g_string_append_printf(s, "%02x ", fis[i]);
686 }
687 g_string_append_c(s, '\n');
688
689 return g_string_free(s, FALSE);
690 }
691
692 static bool ahci_map_fis_address(AHCIDevice *ad)
693 {
694 AHCIPortRegs *pr = &ad->port_regs;
695 map_page(ad->hba->as, &ad->res_fis,
696 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
697 if (ad->res_fis != NULL) {
698 pr->cmd |= PORT_CMD_FIS_ON;
699 return true;
700 }
701
702 pr->cmd &= ~PORT_CMD_FIS_ON;
703 return false;
704 }
705
706 static void ahci_unmap_fis_address(AHCIDevice *ad)
707 {
708 if (ad->res_fis == NULL) {
709 trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no);
710 return;
711 }
712 ad->port_regs.cmd &= ~PORT_CMD_FIS_ON;
713 dma_memory_unmap(ad->hba->as, ad->res_fis, 256,
714 DMA_DIRECTION_FROM_DEVICE, 256);
715 ad->res_fis = NULL;
716 }
717
718 static bool ahci_map_clb_address(AHCIDevice *ad)
719 {
720 AHCIPortRegs *pr = &ad->port_regs;
721 ad->cur_cmd = NULL;
722 map_page(ad->hba->as, &ad->lst,
723 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
724 if (ad->lst != NULL) {
725 pr->cmd |= PORT_CMD_LIST_ON;
726 return true;
727 }
728
729 pr->cmd &= ~PORT_CMD_LIST_ON;
730 return false;
731 }
732
733 static void ahci_unmap_clb_address(AHCIDevice *ad)
734 {
735 if (ad->lst == NULL) {
736 trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no);
737 return;
738 }
739 ad->port_regs.cmd &= ~PORT_CMD_LIST_ON;
740 dma_memory_unmap(ad->hba->as, ad->lst, 1024,
741 DMA_DIRECTION_FROM_DEVICE, 1024);
742 ad->lst = NULL;
743 }
744
745 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs)
746 {
747 AHCIDevice *ad = ncq_tfs->drive;
748 AHCIPortRegs *pr = &ad->port_regs;
749 IDEState *ide_state;
750 SDBFIS *sdb_fis;
751
752 if (!ad->res_fis ||
753 !(pr->cmd & PORT_CMD_FIS_RX)) {
754 return;
755 }
756
757 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS];
758 ide_state = &ad->port.ifs[0];
759
760 sdb_fis->type = SATA_FIS_TYPE_SDB;
761 /* Interrupt pending & Notification bit */
762 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */
763 sdb_fis->status = ide_state->status & 0x77;
764 sdb_fis->error = ide_state->error;
765 /* update SAct field in SDB_FIS */
766 sdb_fis->payload = cpu_to_le32(ad->finished);
767
768 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
769 pr->tfdata = (ad->port.ifs[0].error << 8) |
770 (ad->port.ifs[0].status & 0x77) |
771 (pr->tfdata & 0x88);
772 pr->scr_act &= ~ad->finished;
773 ad->finished = 0;
774
775 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */
776 if (sdb_fis->flags & 0x40) {
777 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);
778 }
779 }
780
781 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)
782 {
783 AHCIPortRegs *pr = &ad->port_regs;
784 uint8_t *pio_fis;
785 IDEState *s = &ad->port.ifs[0];
786
787 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
788 return;
789 }
790
791 pio_fis = &ad->res_fis[RES_FIS_PSFIS];
792
793 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP;
794 pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
795 pio_fis[2] = s->status;
796 pio_fis[3] = s->error;
797
798 pio_fis[4] = s->sector;
799 pio_fis[5] = s->lcyl;
800 pio_fis[6] = s->hcyl;
801 pio_fis[7] = s->select;
802 pio_fis[8] = s->hob_sector;
803 pio_fis[9] = s->hob_lcyl;
804 pio_fis[10] = s->hob_hcyl;
805 pio_fis[11] = 0;
806 pio_fis[12] = s->nsector & 0xFF;
807 pio_fis[13] = (s->nsector >> 8) & 0xFF;
808 pio_fis[14] = 0;
809 pio_fis[15] = s->status;
810 pio_fis[16] = len & 255;
811 pio_fis[17] = len >> 8;
812 pio_fis[18] = 0;
813 pio_fis[19] = 0;
814
815 /* Update shadow registers: */
816 pr->tfdata = (ad->port.ifs[0].error << 8) |
817 ad->port.ifs[0].status;
818
819 if (pio_fis[2] & ERR_STAT) {
820 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
821 }
822
823 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
824 }
825
826 static bool ahci_write_fis_d2h(AHCIDevice *ad)
827 {
828 AHCIPortRegs *pr = &ad->port_regs;
829 uint8_t *d2h_fis;
830 int i;
831 IDEState *s = &ad->port.ifs[0];
832
833 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
834 return false;
835 }
836
837 d2h_fis = &ad->res_fis[RES_FIS_RFIS];
838
839 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H;
840 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
841 d2h_fis[2] = s->status;
842 d2h_fis[3] = s->error;
843
844 d2h_fis[4] = s->sector;
845 d2h_fis[5] = s->lcyl;
846 d2h_fis[6] = s->hcyl;
847 d2h_fis[7] = s->select;
848 d2h_fis[8] = s->hob_sector;
849 d2h_fis[9] = s->hob_lcyl;
850 d2h_fis[10] = s->hob_hcyl;
851 d2h_fis[11] = 0;
852 d2h_fis[12] = s->nsector & 0xFF;
853 d2h_fis[13] = (s->nsector >> 8) & 0xFF;
854 for (i = 14; i < 20; i++) {
855 d2h_fis[i] = 0;
856 }
857
858 /* Update shadow registers: */
859 pr->tfdata = (ad->port.ifs[0].error << 8) |
860 ad->port.ifs[0].status;
861
862 if (d2h_fis[2] & ERR_STAT) {
863 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
864 }
865
866 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);
867 return true;
868 }
869
870 static int prdt_tbl_entry_size(const AHCI_SG *tbl)
871 {
872 /* flags_size is zero-based */
873 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;
874 }
875
876 /**
877 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
878 * @ad: The AHCIDevice for whom we are building the SGList.
879 * @sglist: The SGList target to add PRD entries to.
880 * @cmd: The AHCI Command Header that describes where the PRDT is.
881 * @limit: The remaining size of the S/ATA transaction, in bytes.
882 * @offset: The number of bytes already transferred, in bytes.
883 *
884 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
885 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
886 * building the sglist from the PRDT as soon as we hit @limit bytes,
887 * which is <= INT32_MAX/2GiB.
888 */
889 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,
890 AHCICmdHdr *cmd, int64_t limit, uint64_t offset)
891 {
892 uint16_t opts = le16_to_cpu(cmd->opts);
893 uint16_t prdtl = le16_to_cpu(cmd->prdtl);
894 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr);
895 uint64_t prdt_addr = cfis_addr + 0x80;
896 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG));
897 dma_addr_t real_prdt_len = prdt_len;
898 uint8_t *prdt;
899 int i;
900 int r = 0;
901 uint64_t sum = 0;
902 int off_idx = -1;
903 int64_t off_pos = -1;
904 int tbl_entry_size;
905 IDEBus *bus = &ad->port;
906 BusState *qbus = BUS(bus);
907
908 trace_ahci_populate_sglist(ad->hba, ad->port_no);
909
910 if (!prdtl) {
911 trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts);
912 return -1;
913 }
914
915 /* map PRDT */
916 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,
917 DMA_DIRECTION_TO_DEVICE))){
918 trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no);
919 return -1;
920 }
921
922 if (prdt_len < real_prdt_len) {
923 trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no);
924 r = -1;
925 goto out;
926 }
927
928 /* Get entries in the PRDT, init a qemu sglist accordingly */
929 if (prdtl > 0) {
930 AHCI_SG *tbl = (AHCI_SG *)prdt;
931 sum = 0;
932 for (i = 0; i < prdtl; i++) {
933 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]);
934 if (offset < (sum + tbl_entry_size)) {
935 off_idx = i;
936 off_pos = offset - sum;
937 break;
938 }
939 sum += tbl_entry_size;
940 }
941 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {
942 trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no,
943 off_idx, off_pos);
944 r = -1;
945 goto out;
946 }
947
948 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx),
949 ad->hba->as);
950 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos,
951 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos,
952 limit));
953
954 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) {
955 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
956 MIN(prdt_tbl_entry_size(&tbl[i]),
957 limit - sglist->size));
958 }
959 }
960
961 out:
962 dma_memory_unmap(ad->hba->as, prdt, prdt_len,
963 DMA_DIRECTION_TO_DEVICE, prdt_len);
964 return r;
965 }
966
967 static void ncq_err(NCQTransferState *ncq_tfs)
968 {
969 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
970
971 ide_state->error = ABRT_ERR;
972 ide_state->status = READY_STAT | ERR_STAT;
973 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag);
974 qemu_sglist_destroy(&ncq_tfs->sglist);
975 ncq_tfs->used = 0;
976 }
977
978 static void ncq_finish(NCQTransferState *ncq_tfs)
979 {
980 /* If we didn't error out, set our finished bit. Errored commands
981 * do not get a bit set for the SDB FIS ACT register, nor do they
982 * clear the outstanding bit in scr_act (PxSACT). */
983 if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) {
984 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag);
985 }
986
987 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs);
988
989 trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
990 ncq_tfs->tag);
991
992 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk),
993 &ncq_tfs->acct);
994 qemu_sglist_destroy(&ncq_tfs->sglist);
995 ncq_tfs->used = 0;
996 }
997
998 static void ncq_cb(void *opaque, int ret)
999 {
1000 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
1001 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
1002
1003 ncq_tfs->aiocb = NULL;
1004 if (ret == -ECANCELED) {
1005 return;
1006 }
1007
1008 if (ret < 0) {
1009 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED;
1010 BlockErrorAction action = blk_get_error_action(ide_state->blk,
1011 is_read, -ret);
1012 if (action == BLOCK_ERROR_ACTION_STOP) {
1013 ncq_tfs->halt = true;
1014 ide_state->bus->error_status = IDE_RETRY_HBA;
1015 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
1016 ncq_err(ncq_tfs);
1017 }
1018 blk_error_action(ide_state->blk, action, is_read, -ret);
1019 } else {
1020 ide_state->status = READY_STAT | SEEK_STAT;
1021 }
1022
1023 if (!ncq_tfs->halt) {
1024 ncq_finish(ncq_tfs);
1025 }
1026 }
1027
1028 static int is_ncq(uint8_t ata_cmd)
1029 {
1030 /* Based on SATA 3.2 section 13.6.3.2 */
1031 switch (ata_cmd) {
1032 case READ_FPDMA_QUEUED:
1033 case WRITE_FPDMA_QUEUED:
1034 case NCQ_NON_DATA:
1035 case RECEIVE_FPDMA_QUEUED:
1036 case SEND_FPDMA_QUEUED:
1037 return 1;
1038 default:
1039 return 0;
1040 }
1041 }
1042
1043 static void execute_ncq_command(NCQTransferState *ncq_tfs)
1044 {
1045 AHCIDevice *ad = ncq_tfs->drive;
1046 IDEState *ide_state = &ad->port.ifs[0];
1047 int port = ad->port_no;
1048
1049 g_assert(is_ncq(ncq_tfs->cmd));
1050 ncq_tfs->halt = false;
1051
1052 switch (ncq_tfs->cmd) {
1053 case READ_FPDMA_QUEUED:
1054 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
1055 ncq_tfs->sector_count, ncq_tfs->lba);
1056 dma_acct_start(ide_state->blk, &ncq_tfs->acct,
1057 &ncq_tfs->sglist, BLOCK_ACCT_READ);
1058 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist,
1059 ncq_tfs->lba << BDRV_SECTOR_BITS,
1060 BDRV_SECTOR_SIZE,
1061 ncq_cb, ncq_tfs);
1062 break;
1063 case WRITE_FPDMA_QUEUED:
1064 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
1065 ncq_tfs->sector_count, ncq_tfs->lba);
1066 dma_acct_start(ide_state->blk, &ncq_tfs->acct,
1067 &ncq_tfs->sglist, BLOCK_ACCT_WRITE);
1068 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,
1069 ncq_tfs->lba << BDRV_SECTOR_BITS,
1070 BDRV_SECTOR_SIZE,
1071 ncq_cb, ncq_tfs);
1072 break;
1073 default:
1074 trace_execute_ncq_command_unsup(ad->hba, port,
1075 ncq_tfs->tag, ncq_tfs->cmd);
1076 ncq_err(ncq_tfs);
1077 }
1078 }
1079
1080
1081 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,
1082 uint8_t slot)
1083 {
1084 AHCIDevice *ad = &s->dev[port];
1085 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;
1086 uint8_t tag = ncq_fis->tag >> 3;
1087 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag];
1088 size_t size;
1089
1090 g_assert(is_ncq(ncq_fis->command));
1091 if (ncq_tfs->used) {
1092 /* error - already in use */
1093 fprintf(stderr, "%s: tag %d already used\n", __func__, tag);
1094 return;
1095 }
1096
1097 ncq_tfs->used = 1;
1098 ncq_tfs->drive = ad;
1099 ncq_tfs->slot = slot;
1100 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot];
1101 ncq_tfs->cmd = ncq_fis->command;
1102 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
1103 ((uint64_t)ncq_fis->lba4 << 32) |
1104 ((uint64_t)ncq_fis->lba3 << 24) |
1105 ((uint64_t)ncq_fis->lba2 << 16) |
1106 ((uint64_t)ncq_fis->lba1 << 8) |
1107 (uint64_t)ncq_fis->lba0;
1108 ncq_tfs->tag = tag;
1109
1110 /* Sanity-check the NCQ packet */
1111 if (tag != slot) {
1112 trace_process_ncq_command_mismatch(s, port, tag, slot);
1113 }
1114
1115 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) {
1116 trace_process_ncq_command_aux(s, port, tag);
1117 }
1118 if (ncq_fis->prio || ncq_fis->icc) {
1119 trace_process_ncq_command_prioicc(s, port, tag);
1120 }
1121 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) {
1122 trace_process_ncq_command_fua(s, port, tag);
1123 }
1124 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) {
1125 trace_process_ncq_command_rarc(s, port, tag);
1126 }
1127
1128 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) |
1129 ncq_fis->sector_count_low);
1130 if (!ncq_tfs->sector_count) {
1131 ncq_tfs->sector_count = 0x10000;
1132 }
1133 size = ncq_tfs->sector_count * 512;
1134 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0);
1135
1136 if (ncq_tfs->sglist.size < size) {
1137 error_report("ahci: PRDT length for NCQ command (0x%zx) "
1138 "is smaller than the requested size (0x%zx)",
1139 ncq_tfs->sglist.size, size);
1140 ncq_err(ncq_tfs);
1141 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);
1142 return;
1143 } else if (ncq_tfs->sglist.size != size) {
1144 trace_process_ncq_command_large(s, port, tag,
1145 ncq_tfs->sglist.size, size);
1146 }
1147
1148 trace_process_ncq_command(s, port, tag,
1149 ncq_fis->command,
1150 ncq_tfs->lba,
1151 ncq_tfs->lba + ncq_tfs->sector_count - 1);
1152 execute_ncq_command(ncq_tfs);
1153 }
1154
1155 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot)
1156 {
1157 if (port >= s->ports || slot >= AHCI_MAX_CMDS) {
1158 return NULL;
1159 }
1160
1161 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL;
1162 }
1163
1164 static void handle_reg_h2d_fis(AHCIState *s, int port,
1165 uint8_t slot, uint8_t *cmd_fis)
1166 {
1167 IDEState *ide_state = &s->dev[port].port.ifs[0];
1168 AHCICmdHdr *cmd = get_cmd_header(s, port, slot);
1169 uint16_t opts = le16_to_cpu(cmd->opts);
1170
1171 if (cmd_fis[1] & 0x0F) {
1172 trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1],
1173 cmd_fis[2], cmd_fis[3]);
1174 return;
1175 }
1176
1177 if (cmd_fis[1] & 0x70) {
1178 trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1],
1179 cmd_fis[2], cmd_fis[3]);
1180 return;
1181 }
1182
1183 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) {
1184 switch (s->dev[port].port_state) {
1185 case STATE_RUN:
1186 if (cmd_fis[15] & ATA_SRST) {
1187 s->dev[port].port_state = STATE_RESET;
1188 }
1189 break;
1190 case STATE_RESET:
1191 if (!(cmd_fis[15] & ATA_SRST)) {
1192 ahci_reset_port(s, port);
1193 }
1194 break;
1195 }
1196 return;
1197 }
1198
1199 /* Check for NCQ command */
1200 if (is_ncq(cmd_fis[2])) {
1201 process_ncq_command(s, port, cmd_fis, slot);
1202 return;
1203 }
1204
1205 /* Decompose the FIS:
1206 * AHCI does not interpret FIS packets, it only forwards them.
1207 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1208 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1209 *
1210 * ATA4 describes sector number for LBA28/CHS commands.
1211 * ATA6 describes sector number for LBA48 commands.
1212 * ATA8 deprecates CHS fully, describing only LBA28/48.
1213 *
1214 * We dutifully convert the FIS into IDE registers, and allow the
1215 * core layer to interpret them as needed. */
1216 ide_state->feature = cmd_fis[3];
1217 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */
1218 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */
1219 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */
1220 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */
1221 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */
1222 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */
1223 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */
1224 ide_state->hob_feature = cmd_fis[11];
1225 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
1226 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1227 /* 15: Only valid when UPDATE_COMMAND not set. */
1228
1229 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1230 * table to ide_state->io_buffer */
1231 if (opts & AHCI_CMD_ATAPI) {
1232 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
1233 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) {
1234 char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10);
1235 trace_handle_reg_h2d_fis_dump(s, port, pretty_fis);
1236 g_free(pretty_fis);
1237 }
1238 s->dev[port].done_atapi_packet = false;
1239 /* XXX send PIO setup FIS */
1240 }
1241
1242 ide_state->error = 0;
1243
1244 /* Reset transferred byte counter */
1245 cmd->status = 0;
1246
1247 /* We're ready to process the command in FIS byte 2. */
1248 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
1249 }
1250
1251 static int handle_cmd(AHCIState *s, int port, uint8_t slot)
1252 {
1253 IDEState *ide_state;
1254 uint64_t tbl_addr;
1255 AHCICmdHdr *cmd;
1256 uint8_t *cmd_fis;
1257 dma_addr_t cmd_len;
1258
1259 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1260 /* Engine currently busy, try again later */
1261 trace_handle_cmd_busy(s, port);
1262 return -1;
1263 }
1264
1265 if (!s->dev[port].lst) {
1266 trace_handle_cmd_nolist(s, port);
1267 return -1;
1268 }
1269 cmd = get_cmd_header(s, port, slot);
1270 /* remember current slot handle for later */
1271 s->dev[port].cur_cmd = cmd;
1272
1273 /* The device we are working for */
1274 ide_state = &s->dev[port].port.ifs[0];
1275 if (!ide_state->blk) {
1276 trace_handle_cmd_badport(s, port);
1277 return -1;
1278 }
1279
1280 tbl_addr = le64_to_cpu(cmd->tbl_addr);
1281 cmd_len = 0x80;
1282 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,
1283 DMA_DIRECTION_FROM_DEVICE);
1284 if (!cmd_fis) {
1285 trace_handle_cmd_badfis(s, port);
1286 return -1;
1287 } else if (cmd_len != 0x80) {
1288 ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS);
1289 trace_handle_cmd_badmap(s, port, cmd_len);
1290 goto out;
1291 }
1292 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) {
1293 char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80);
1294 trace_handle_cmd_fis_dump(s, port, pretty_fis);
1295 g_free(pretty_fis);
1296 }
1297 switch (cmd_fis[0]) {
1298 case SATA_FIS_TYPE_REGISTER_H2D:
1299 handle_reg_h2d_fis(s, port, slot, cmd_fis);
1300 break;
1301 default:
1302 trace_handle_cmd_unhandled_fis(s, port,
1303 cmd_fis[0], cmd_fis[1], cmd_fis[2]);
1304 break;
1305 }
1306
1307 out:
1308 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE,
1309 cmd_len);
1310
1311 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1312 /* async command, complete later */
1313 s->dev[port].busy_slot = slot;
1314 return -1;
1315 }
1316
1317 /* done handling the command */
1318 return 0;
1319 }
1320
1321 /* DMA dev <-> ram */
1322 static void ahci_start_transfer(IDEDMA *dma)
1323 {
1324 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1325 IDEState *s = &ad->port.ifs[0];
1326 uint32_t size = (uint32_t)(s->data_end - s->data_ptr);
1327 /* write == ram -> device */
1328 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts);
1329 int is_write = opts & AHCI_CMD_WRITE;
1330 int is_atapi = opts & AHCI_CMD_ATAPI;
1331 int has_sglist = 0;
1332
1333 if (is_atapi && !ad->done_atapi_packet) {
1334 /* already prepopulated iobuffer */
1335 ad->done_atapi_packet = true;
1336 size = 0;
1337 goto out;
1338 }
1339
1340 if (ahci_dma_prepare_buf(dma, size)) {
1341 has_sglist = 1;
1342 }
1343
1344 trace_ahci_start_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read",
1345 size, is_atapi ? "atapi" : "ata",
1346 has_sglist ? "" : "o");
1347
1348 if (has_sglist && size) {
1349 if (is_write) {
1350 dma_buf_write(s->data_ptr, size, &s->sg);
1351 } else {
1352 dma_buf_read(s->data_ptr, size, &s->sg);
1353 }
1354 }
1355
1356 out:
1357 /* declare that we processed everything */
1358 s->data_ptr = s->data_end;
1359
1360 /* Update number of transferred bytes, destroy sglist */
1361 dma_buf_commit(s, size);
1362
1363 s->end_transfer_func(s);
1364
1365 if (!(s->status & DRQ_STAT)) {
1366 /* done with PIO send/receive */
1367 ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status));
1368 }
1369 }
1370
1371 static void ahci_start_dma(IDEDMA *dma, IDEState *s,
1372 BlockCompletionFunc *dma_cb)
1373 {
1374 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1375 trace_ahci_start_dma(ad->hba, ad->port_no);
1376 s->io_buffer_offset = 0;
1377 dma_cb(s, 0);
1378 }
1379
1380 static void ahci_restart_dma(IDEDMA *dma)
1381 {
1382 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1383 }
1384
1385 /**
1386 * IDE/PIO restarts are handled by the core layer, but NCQ commands
1387 * need an extra kick from the AHCI HBA.
1388 */
1389 static void ahci_restart(IDEDMA *dma)
1390 {
1391 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1392 int i;
1393
1394 for (i = 0; i < AHCI_MAX_CMDS; i++) {
1395 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i];
1396 if (ncq_tfs->halt) {
1397 execute_ncq_command(ncq_tfs);
1398 }
1399 }
1400 }
1401
1402 /**
1403 * Called in DMA and PIO R/W chains to read the PRDT.
1404 * Not shared with NCQ pathways.
1405 */
1406 static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)
1407 {
1408 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1409 IDEState *s = &ad->port.ifs[0];
1410
1411 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd,
1412 limit, s->io_buffer_offset) == -1) {
1413 trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no);
1414 return -1;
1415 }
1416 s->io_buffer_size = s->sg.size;
1417
1418 trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size);
1419 return s->io_buffer_size;
1420 }
1421
1422 /**
1423 * Updates the command header with a bytes-read value.
1424 * Called via dma_buf_commit, for both DMA and PIO paths.
1425 * sglist destruction is handled within dma_buf_commit.
1426 */
1427 static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
1428 {
1429 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1430
1431 tx_bytes += le32_to_cpu(ad->cur_cmd->status);
1432 ad->cur_cmd->status = cpu_to_le32(tx_bytes);
1433 }
1434
1435 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write)
1436 {
1437 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1438 IDEState *s = &ad->port.ifs[0];
1439 uint8_t *p = s->io_buffer + s->io_buffer_index;
1440 int l = s->io_buffer_size - s->io_buffer_index;
1441
1442 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) {
1443 return 0;
1444 }
1445
1446 if (is_write) {
1447 dma_buf_read(p, l, &s->sg);
1448 } else {
1449 dma_buf_write(p, l, &s->sg);
1450 }
1451
1452 /* free sglist, update byte count */
1453 dma_buf_commit(s, l);
1454 s->io_buffer_index += l;
1455
1456 trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l);
1457 return 1;
1458 }
1459
1460 static void ahci_cmd_done(IDEDMA *dma)
1461 {
1462 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1463
1464 trace_ahci_cmd_done(ad->hba, ad->port_no);
1465
1466 /* no longer busy */
1467 if (ad->busy_slot != -1) {
1468 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
1469 ad->busy_slot = -1;
1470 }
1471
1472 /* update d2h status */
1473 ahci_write_fis_d2h(ad);
1474
1475 if (ad->port_regs.cmd_issue && !ad->check_bh) {
1476 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad);
1477 qemu_bh_schedule(ad->check_bh);
1478 }
1479 }
1480
1481 static void ahci_irq_set(void *opaque, int n, int level)
1482 {
1483 }
1484
1485 static const IDEDMAOps ahci_dma_ops = {
1486 .start_dma = ahci_start_dma,
1487 .restart = ahci_restart,
1488 .restart_dma = ahci_restart_dma,
1489 .start_transfer = ahci_start_transfer,
1490 .prepare_buf = ahci_dma_prepare_buf,
1491 .commit_buf = ahci_commit_buf,
1492 .rw_buf = ahci_dma_rw_buf,
1493 .cmd_done = ahci_cmd_done,
1494 };
1495
1496 void ahci_init(AHCIState *s, DeviceState *qdev)
1497 {
1498 s->container = qdev;
1499 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1500 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
1501 "ahci", AHCI_MEM_BAR_SIZE);
1502 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
1503 "ahci-idp", 32);
1504 }
1505
1506 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
1507 {
1508 qemu_irq *irqs;
1509 int i;
1510
1511 s->as = as;
1512 s->ports = ports;
1513 s->dev = g_new0(AHCIDevice, ports);
1514 ahci_reg_init(s);
1515 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1516 for (i = 0; i < s->ports; i++) {
1517 AHCIDevice *ad = &s->dev[i];
1518
1519 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1);
1520 ide_init2(&ad->port, irqs[i]);
1521
1522 ad->hba = s;
1523 ad->port_no = i;
1524 ad->port.dma = &ad->dma;
1525 ad->port.dma->ops = &ahci_dma_ops;
1526 ide_register_restart_cb(&ad->port);
1527 }
1528 g_free(irqs);
1529 }
1530
1531 void ahci_uninit(AHCIState *s)
1532 {
1533 int i, j;
1534
1535 for (i = 0; i < s->ports; i++) {
1536 AHCIDevice *ad = &s->dev[i];
1537
1538 for (j = 0; j < 2; j++) {
1539 IDEState *s = &ad->port.ifs[j];
1540
1541 ide_exit(s);
1542 }
1543 object_unparent(OBJECT(&ad->port));
1544 }
1545
1546 g_free(s->dev);
1547 }
1548
1549 void ahci_reset(AHCIState *s)
1550 {
1551 AHCIPortRegs *pr;
1552 int i;
1553
1554 trace_ahci_reset(s);
1555
1556 s->control_regs.irqstatus = 0;
1557 /* AHCI Enable (AE)
1558 * The implementation of this bit is dependent upon the value of the
1559 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1560 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1561 * read-only and shall have a reset value of '1'.
1562 *
1563 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1564 */
1565 s->control_regs.ghc = HOST_CTL_AHCI_EN;
1566
1567 for (i = 0; i < s->ports; i++) {
1568 pr = &s->dev[i].port_regs;
1569 pr->irq_stat = 0;
1570 pr->irq_mask = 0;
1571 pr->scr_ctl = 0;
1572 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
1573 ahci_reset_port(s, i);
1574 }
1575 }
1576
1577 static const VMStateDescription vmstate_ncq_tfs = {
1578 .name = "ncq state",
1579 .version_id = 1,
1580 .fields = (VMStateField[]) {
1581 VMSTATE_UINT32(sector_count, NCQTransferState),
1582 VMSTATE_UINT64(lba, NCQTransferState),
1583 VMSTATE_UINT8(tag, NCQTransferState),
1584 VMSTATE_UINT8(cmd, NCQTransferState),
1585 VMSTATE_UINT8(slot, NCQTransferState),
1586 VMSTATE_BOOL(used, NCQTransferState),
1587 VMSTATE_BOOL(halt, NCQTransferState),
1588 VMSTATE_END_OF_LIST()
1589 },
1590 };
1591
1592 static const VMStateDescription vmstate_ahci_device = {
1593 .name = "ahci port",
1594 .version_id = 1,
1595 .fields = (VMStateField[]) {
1596 VMSTATE_IDE_BUS(port, AHCIDevice),
1597 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice),
1598 VMSTATE_UINT32(port_state, AHCIDevice),
1599 VMSTATE_UINT32(finished, AHCIDevice),
1600 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice),
1601 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice),
1602 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice),
1603 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice),
1604 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice),
1605 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice),
1606 VMSTATE_UINT32(port_regs.cmd, AHCIDevice),
1607 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice),
1608 VMSTATE_UINT32(port_regs.sig, AHCIDevice),
1609 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice),
1610 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice),
1611 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
1612 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
1613 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
1614 VMSTATE_BOOL(done_atapi_packet, AHCIDevice),
1615 VMSTATE_INT32(busy_slot, AHCIDevice),
1616 VMSTATE_BOOL(init_d2h_sent, AHCIDevice),
1617 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS,
1618 1, vmstate_ncq_tfs, NCQTransferState),
1619 VMSTATE_END_OF_LIST()
1620 },
1621 };
1622
1623 static int ahci_state_post_load(void *opaque, int version_id)
1624 {
1625 int i, j;
1626 struct AHCIDevice *ad;
1627 NCQTransferState *ncq_tfs;
1628 AHCIPortRegs *pr;
1629 AHCIState *s = opaque;
1630
1631 for (i = 0; i < s->ports; i++) {
1632 ad = &s->dev[i];
1633 pr = &ad->port_regs;
1634
1635 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) {
1636 error_report("AHCI: DMA engine should be off, but status bit "
1637 "indicates it is still running.");
1638 return -1;
1639 }
1640 if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) {
1641 error_report("AHCI: FIS RX engine should be off, but status bit "
1642 "indicates it is still running.");
1643 return -1;
1644 }
1645
1646 /* After a migrate, the DMA/FIS engines are "off" and
1647 * need to be conditionally restarted */
1648 pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
1649 if (ahci_cond_start_engines(ad) != 0) {
1650 return -1;
1651 }
1652
1653 for (j = 0; j < AHCI_MAX_CMDS; j++) {
1654 ncq_tfs = &ad->ncq_tfs[j];
1655 ncq_tfs->drive = ad;
1656
1657 if (ncq_tfs->used != ncq_tfs->halt) {
1658 return -1;
1659 }
1660 if (!ncq_tfs->halt) {
1661 continue;
1662 }
1663 if (!is_ncq(ncq_tfs->cmd)) {
1664 return -1;
1665 }
1666 if (ncq_tfs->slot != ncq_tfs->tag) {
1667 return -1;
1668 }
1669 /* If ncq_tfs->halt is justly set, the engine should be engaged,
1670 * and the command list buffer should be mapped. */
1671 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot);
1672 if (!ncq_tfs->cmdh) {
1673 return -1;
1674 }
1675 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist,
1676 ncq_tfs->cmdh, ncq_tfs->sector_count * 512,
1677 0);
1678 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) {
1679 return -1;
1680 }
1681 }
1682
1683
1684 /*
1685 * If an error is present, ad->busy_slot will be valid and not -1.
1686 * In this case, an operation is waiting to resume and will re-check
1687 * for additional AHCI commands to execute upon completion.
1688 *
1689 * In the case where no error was present, busy_slot will be -1,
1690 * and we should check to see if there are additional commands waiting.
1691 */
1692 if (ad->busy_slot == -1) {
1693 check_cmd(s, i);
1694 } else {
1695 /* We are in the middle of a command, and may need to access
1696 * the command header in guest memory again. */
1697 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) {
1698 return -1;
1699 }
1700 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot);
1701 }
1702 }
1703
1704 return 0;
1705 }
1706
1707 const VMStateDescription vmstate_ahci = {
1708 .name = "ahci",
1709 .version_id = 1,
1710 .post_load = ahci_state_post_load,
1711 .fields = (VMStateField[]) {
1712 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
1713 vmstate_ahci_device, AHCIDevice),
1714 VMSTATE_UINT32(control_regs.cap, AHCIState),
1715 VMSTATE_UINT32(control_regs.ghc, AHCIState),
1716 VMSTATE_UINT32(control_regs.irqstatus, AHCIState),
1717 VMSTATE_UINT32(control_regs.impl, AHCIState),
1718 VMSTATE_UINT32(control_regs.version, AHCIState),
1719 VMSTATE_UINT32(idp_index, AHCIState),
1720 VMSTATE_INT32_EQUAL(ports, AHCIState, NULL),
1721 VMSTATE_END_OF_LIST()
1722 },
1723 };
1724
1725 static const VMStateDescription vmstate_sysbus_ahci = {
1726 .name = "sysbus-ahci",
1727 .fields = (VMStateField[]) {
1728 VMSTATE_AHCI(ahci, SysbusAHCIState),
1729 VMSTATE_END_OF_LIST()
1730 },
1731 };
1732
1733 static void sysbus_ahci_reset(DeviceState *dev)
1734 {
1735 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1736
1737 ahci_reset(&s->ahci);
1738 }
1739
1740 static void sysbus_ahci_init(Object *obj)
1741 {
1742 SysbusAHCIState *s = SYSBUS_AHCI(obj);
1743 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1744
1745 ahci_init(&s->ahci, DEVICE(obj));
1746
1747 sysbus_init_mmio(sbd, &s->ahci.mem);
1748 sysbus_init_irq(sbd, &s->ahci.irq);
1749 }
1750
1751 static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
1752 {
1753 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1754
1755 ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
1756 }
1757
1758 static Property sysbus_ahci_properties[] = {
1759 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
1760 DEFINE_PROP_END_OF_LIST(),
1761 };
1762
1763 static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
1764 {
1765 DeviceClass *dc = DEVICE_CLASS(klass);
1766
1767 dc->realize = sysbus_ahci_realize;
1768 dc->vmsd = &vmstate_sysbus_ahci;
1769 dc->props = sysbus_ahci_properties;
1770 dc->reset = sysbus_ahci_reset;
1771 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1772 }
1773
1774 static const TypeInfo sysbus_ahci_info = {
1775 .name = TYPE_SYSBUS_AHCI,
1776 .parent = TYPE_SYS_BUS_DEVICE,
1777 .instance_size = sizeof(SysbusAHCIState),
1778 .instance_init = sysbus_ahci_init,
1779 .class_init = sysbus_ahci_class_init,
1780 };
1781
1782 static void sysbus_ahci_register_types(void)
1783 {
1784 type_register_static(&sysbus_ahci_info);
1785 }
1786
1787 type_init(sysbus_ahci_register_types)
1788
1789 int32_t ahci_get_num_ports(PCIDevice *dev)
1790 {
1791 AHCIPCIState *d = ICH_AHCI(dev);
1792 AHCIState *ahci = &d->ahci;
1793
1794 return ahci->ports;
1795 }
1796
1797 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
1798 {
1799 AHCIPCIState *d = ICH_AHCI(dev);
1800 AHCIState *ahci = &d->ahci;
1801 int i;
1802
1803 for (i = 0; i < ahci->ports; i++) {
1804 if (hd[i] == NULL) {
1805 continue;
1806 }
1807 ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
1808 }
1809
1810 }
AR7 emulation for QEMU