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hw: vfio: drop TYPE_FOO MACRO in VMStateDescription
[qemu/ar7.git] / hw / arm / virt-acpi-build.c
blobe7c96d658e3339bdafa1fcfb1095e40444064bb2
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu-common.h"
32 #include "qemu/bitmap.h"
33 #include "trace.h"
34 #include "qom/cpu.h"
35 #include "target/arm/cpu.h"
36 #include "hw/acpi/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/hw.h"
42 #include "hw/acpi/aml-build.h"
43 #include "hw/acpi/pci.h"
44 #include "hw/pci/pcie_host.h"
45 #include "hw/pci/pci.h"
46 #include "hw/arm/virt.h"
47 #include "sysemu/numa.h"
48 #include "kvm_arm.h"
49
50 #define ARM_SPI_BASE 32
51 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
52
53 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
54 {
55 uint16_t i;
56
57 for (i = 0; i < smp_cpus; i++) {
58 Aml *dev = aml_device("C%.03X", i);
59 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
60 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
61 aml_append(scope, dev);
62 }
63 }
64
65 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
66 uint32_t uart_irq)
67 {
68 Aml *dev = aml_device("COM0");
69 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
70 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
71
72 Aml *crs = aml_resource_template();
73 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
74 uart_memmap->size, AML_READ_WRITE));
75 aml_append(crs,
76 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
77 AML_EXCLUSIVE, &uart_irq, 1));
78 aml_append(dev, aml_name_decl("_CRS", crs));
79
80 /* The _ADR entry is used to link this device to the UART described
81 * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
82 */
83 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
84
85 aml_append(scope, dev);
86 }
87
88 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
89 {
90 Aml *dev = aml_device("FWCF");
91 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
92 /* device present, functioning, decoding, not shown in UI */
93 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
94 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
95
96 Aml *crs = aml_resource_template();
97 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
98 fw_cfg_memmap->size, AML_READ_WRITE));
99 aml_append(dev, aml_name_decl("_CRS", crs));
100 aml_append(scope, dev);
101 }
102
103 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
104 {
105 Aml *dev, *crs;
106 hwaddr base = flash_memmap->base;
107 hwaddr size = flash_memmap->size / 2;
108
109 dev = aml_device("FLS0");
110 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
111 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
112
113 crs = aml_resource_template();
114 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
115 aml_append(dev, aml_name_decl("_CRS", crs));
116 aml_append(scope, dev);
117
118 dev = aml_device("FLS1");
119 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
120 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
121 crs = aml_resource_template();
122 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
123 aml_append(dev, aml_name_decl("_CRS", crs));
124 aml_append(scope, dev);
125 }
126
127 static void acpi_dsdt_add_virtio(Aml *scope,
128 const MemMapEntry *virtio_mmio_memmap,
129 uint32_t mmio_irq, int num)
130 {
131 hwaddr base = virtio_mmio_memmap->base;
132 hwaddr size = virtio_mmio_memmap->size;
133 int i;
134
135 for (i = 0; i < num; i++) {
136 uint32_t irq = mmio_irq + i;
137 Aml *dev = aml_device("VR%02u", i);
138 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
139 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
140 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
141
142 Aml *crs = aml_resource_template();
143 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
144 aml_append(crs,
145 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
146 AML_EXCLUSIVE, &irq, 1));
147 aml_append(dev, aml_name_decl("_CRS", crs));
148 aml_append(scope, dev);
149 base += size;
150 }
151 }
152
153 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
154 uint32_t irq, bool use_highmem, bool highmem_ecam)
155 {
156 int ecam_id = VIRT_ECAM_ID(highmem_ecam);
157 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
158 int i, bus_no;
159 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
160 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
161 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
162 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
163 hwaddr base_ecam = memmap[ecam_id].base;
164 hwaddr size_ecam = memmap[ecam_id].size;
165 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
166
167 Aml *dev = aml_device("%s", "PCI0");
168 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
169 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
170 aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
171 aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
172 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
173 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
174 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
175 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
176
177 /* Declare the PCI Routing Table. */
178 Aml *rt_pkg = aml_varpackage(nr_pcie_buses * PCI_NUM_PINS);
179 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
180 for (i = 0; i < PCI_NUM_PINS; i++) {
181 int gsi = (i + bus_no) % PCI_NUM_PINS;
182 Aml *pkg = aml_package(4);
183 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
184 aml_append(pkg, aml_int(i));
185 aml_append(pkg, aml_name("GSI%d", gsi));
186 aml_append(pkg, aml_int(0));
187 aml_append(rt_pkg, pkg);
188 }
189 }
190 aml_append(dev, aml_name_decl("_PRT", rt_pkg));
191
192 /* Create GSI link device */
193 for (i = 0; i < PCI_NUM_PINS; i++) {
194 uint32_t irqs = irq + i;
195 Aml *dev_gsi = aml_device("GSI%d", i);
196 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
197 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
198 crs = aml_resource_template();
199 aml_append(crs,
200 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
201 AML_EXCLUSIVE, &irqs, 1));
202 aml_append(dev_gsi, aml_name_decl("_PRS", crs));
203 crs = aml_resource_template();
204 aml_append(crs,
205 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
206 AML_EXCLUSIVE, &irqs, 1));
207 aml_append(dev_gsi, aml_name_decl("_CRS", crs));
208 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
209 aml_append(dev_gsi, method);
210 aml_append(dev, dev_gsi);
211 }
212
213 method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
214 aml_append(method, aml_return(aml_int(base_ecam)));
215 aml_append(dev, method);
216
217 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
218 Aml *rbuf = aml_resource_template();
219 aml_append(rbuf,
220 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
221 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
222 nr_pcie_buses));
223 aml_append(rbuf,
224 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
225 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
226 base_mmio + size_mmio - 1, 0x0000, size_mmio));
227 aml_append(rbuf,
228 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
229 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
230 size_pio));
231
232 if (use_highmem) {
233 hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
234 hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
235
236 aml_append(rbuf,
237 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
238 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
239 base_mmio_high,
240 base_mmio_high + size_mmio_high - 1, 0x0000,
241 size_mmio_high));
242 }
243
244 aml_append(method, aml_name_decl("RBUF", rbuf));
245 aml_append(method, aml_return(rbuf));
246 aml_append(dev, method);
247
248 /* Declare an _OSC (OS Control Handoff) method */
249 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
250 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
251 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
252 aml_append(method,
253 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
254
255 /* PCI Firmware Specification 3.0
256 * 4.5.1. _OSC Interface for PCI Host Bridge Devices
257 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
258 * identified by the Universal Unique IDentifier (UUID)
259 * 33DB4D5B-1FF7-401C-9657-7441C03DD766
260 */
261 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
262 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
263 aml_append(ifctx,
264 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
265 aml_append(ifctx,
266 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
267 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
268 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
269 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
270 aml_name("CTRL")));
271
272 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
273 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
274 aml_name("CDW1")));
275 aml_append(ifctx, ifctx1);
276
277 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
278 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
279 aml_name("CDW1")));
280 aml_append(ifctx, ifctx1);
281
282 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
283 aml_append(ifctx, aml_return(aml_arg(3)));
284 aml_append(method, ifctx);
285
286 elsectx = aml_else();
287 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
288 aml_name("CDW1")));
289 aml_append(elsectx, aml_return(aml_arg(3)));
290 aml_append(method, elsectx);
291 aml_append(dev, method);
292
293 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
294
295 /* PCI Firmware Specification 3.0
296 * 4.6.1. _DSM for PCI Express Slot Information
297 * The UUID in _DSM in this context is
298 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
299 */
300 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
301 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
302 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
303 uint8_t byte_list[1] = {1};
304 buf = aml_buffer(1, byte_list);
305 aml_append(ifctx1, aml_return(buf));
306 aml_append(ifctx, ifctx1);
307 aml_append(method, ifctx);
308
309 byte_list[0] = 0;
310 buf = aml_buffer(1, byte_list);
311 aml_append(method, aml_return(buf));
312 aml_append(dev, method);
313
314 Aml *dev_rp0 = aml_device("%s", "RP0");
315 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
316 aml_append(dev, dev_rp0);
317
318 Aml *dev_res0 = aml_device("%s", "RES0");
319 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
320 crs = aml_resource_template();
321 aml_append(crs,
322 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
323 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
324 base_ecam + size_ecam - 1, 0x0000, size_ecam));
325 aml_append(dev_res0, aml_name_decl("_CRS", crs));
326 aml_append(dev, dev_res0);
327 aml_append(scope, dev);
328 }
329
330 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
331 uint32_t gpio_irq)
332 {
333 Aml *dev = aml_device("GPO0");
334 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
335 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
336 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
337
338 Aml *crs = aml_resource_template();
339 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
340 AML_READ_WRITE));
341 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
342 AML_EXCLUSIVE, &gpio_irq, 1));
343 aml_append(dev, aml_name_decl("_CRS", crs));
344
345 Aml *aei = aml_resource_template();
346 /* Pin 3 for power button */
347 const uint32_t pin_list[1] = {3};
348 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
349 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
350 "GPO0", NULL, 0));
351 aml_append(dev, aml_name_decl("_AEI", aei));
352
353 /* _E03 is handle for power button */
354 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
355 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
356 aml_int(0x80)));
357 aml_append(dev, method);
358 aml_append(scope, dev);
359 }
360
361 static void acpi_dsdt_add_power_button(Aml *scope)
362 {
363 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
364 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
365 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
366 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
367 aml_append(scope, dev);
368 }
369
370 static void
371 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
372 {
373 int nb_nodes, iort_start = table_data->len;
374 AcpiIortIdMapping *idmap;
375 AcpiIortItsGroup *its;
376 AcpiIortTable *iort;
377 AcpiIortSmmu3 *smmu;
378 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
379 AcpiIortRC *rc;
380
381 iort = acpi_data_push(table_data, sizeof(*iort));
382
383 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
384 nb_nodes = 3; /* RC, ITS, SMMUv3 */
385 } else {
386 nb_nodes = 2; /* RC, ITS */
387 }
388
389 iort_length = sizeof(*iort);
390 iort->node_count = cpu_to_le32(nb_nodes);
391 /*
392 * Use a copy in case table_data->data moves during acpi_data_push
393 * operations.
394 */
395 iort_node_offset = sizeof(*iort);
396 iort->node_offset = cpu_to_le32(iort_node_offset);
397
398 /* ITS group node */
399 node_size = sizeof(*its) + sizeof(uint32_t);
400 iort_length += node_size;
401 its = acpi_data_push(table_data, node_size);
402
403 its->type = ACPI_IORT_NODE_ITS_GROUP;
404 its->length = cpu_to_le16(node_size);
405 its->its_count = cpu_to_le32(1);
406 its->identifiers[0] = 0; /* MADT translation_id */
407
408 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
409 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
410
411 /* SMMUv3 node */
412 smmu_offset = iort_node_offset + node_size;
413 node_size = sizeof(*smmu) + sizeof(*idmap);
414 iort_length += node_size;
415 smmu = acpi_data_push(table_data, node_size);
416
417 smmu->type = ACPI_IORT_NODE_SMMU_V3;
418 smmu->length = cpu_to_le16(node_size);
419 smmu->mapping_count = cpu_to_le32(1);
420 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
421 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
422 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
423 smmu->event_gsiv = cpu_to_le32(irq);
424 smmu->pri_gsiv = cpu_to_le32(irq + 1);
425 smmu->gerr_gsiv = cpu_to_le32(irq + 2);
426 smmu->sync_gsiv = cpu_to_le32(irq + 3);
427
428 /* Identity RID mapping covering the whole input RID range */
429 idmap = &smmu->id_mapping_array[0];
430 idmap->input_base = 0;
431 idmap->id_count = cpu_to_le32(0xFFFF);
432 idmap->output_base = 0;
433 /* output IORT node is the ITS group node (the first node) */
434 idmap->output_reference = cpu_to_le32(iort_node_offset);
435 }
436
437 /* Root Complex Node */
438 node_size = sizeof(*rc) + sizeof(*idmap);
439 iort_length += node_size;
440 rc = acpi_data_push(table_data, node_size);
441
442 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
443 rc->length = cpu_to_le16(node_size);
444 rc->mapping_count = cpu_to_le32(1);
445 rc->mapping_offset = cpu_to_le32(sizeof(*rc));
446
447 /* fully coherent device */
448 rc->memory_properties.cache_coherency = cpu_to_le32(1);
449 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
450 rc->pci_segment_number = 0; /* MCFG pci_segment */
451
452 /* Identity RID mapping covering the whole input RID range */
453 idmap = &rc->id_mapping_array[0];
454 idmap->input_base = 0;
455 idmap->id_count = cpu_to_le32(0xFFFF);
456 idmap->output_base = 0;
457
458 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
459 /* output IORT node is the smmuv3 node */
460 idmap->output_reference = cpu_to_le32(smmu_offset);
461 } else {
462 /* output IORT node is the ITS group node (the first node) */
463 idmap->output_reference = cpu_to_le32(iort_node_offset);
464 }
465
466 /*
467 * Update the pointer address in case table_data->data moves during above
468 * acpi_data_push operations.
469 */
470 iort = (AcpiIortTable *)(table_data->data + iort_start);
471 iort->length = cpu_to_le32(iort_length);
472
473 build_header(linker, table_data, (void *)(table_data->data + iort_start),
474 "IORT", table_data->len - iort_start, 0, NULL, NULL);
475 }
476
477 static void
478 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
479 {
480 AcpiSerialPortConsoleRedirection *spcr;
481 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
482 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
483 int spcr_start = table_data->len;
484
485 spcr = acpi_data_push(table_data, sizeof(*spcr));
486
487 spcr->interface_type = 0x3; /* ARM PL011 UART */
488
489 spcr->base_address.space_id = AML_SYSTEM_MEMORY;
490 spcr->base_address.bit_width = 8;
491 spcr->base_address.bit_offset = 0;
492 spcr->base_address.access_width = 1;
493 spcr->base_address.address = cpu_to_le64(uart_memmap->base);
494
495 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
496 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
497
498 spcr->baud = 3; /* Baud Rate: 3 = 9600 */
499 spcr->parity = 0; /* No Parity */
500 spcr->stopbits = 1; /* 1 Stop bit */
501 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
502 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
503
504 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
505 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
506
507 build_header(linker, table_data, (void *)(table_data->data + spcr_start),
508 "SPCR", table_data->len - spcr_start, 2, NULL, NULL);
509 }
510
511 static void
512 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
513 {
514 AcpiSystemResourceAffinityTable *srat;
515 AcpiSratProcessorGiccAffinity *core;
516 AcpiSratMemoryAffinity *numamem;
517 int i, srat_start;
518 uint64_t mem_base;
519 MachineClass *mc = MACHINE_GET_CLASS(vms);
520 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(MACHINE(vms));
521
522 srat_start = table_data->len;
523 srat = acpi_data_push(table_data, sizeof(*srat));
524 srat->reserved1 = cpu_to_le32(1);
525
526 for (i = 0; i < cpu_list->len; ++i) {
527 core = acpi_data_push(table_data, sizeof(*core));
528 core->type = ACPI_SRAT_PROCESSOR_GICC;
529 core->length = sizeof(*core);
530 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
531 core->acpi_processor_uid = cpu_to_le32(i);
532 core->flags = cpu_to_le32(1);
533 }
534
535 mem_base = vms->memmap[VIRT_MEM].base;
536 for (i = 0; i < nb_numa_nodes; ++i) {
537 if (numa_info[i].node_mem > 0) {
538 numamem = acpi_data_push(table_data, sizeof(*numamem));
539 build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
540 MEM_AFFINITY_ENABLED);
541 mem_base += numa_info[i].node_mem;
542 }
543 }
544
545 build_header(linker, table_data, (void *)(table_data->data + srat_start),
546 "SRAT", table_data->len - srat_start, 3, NULL, NULL);
547 }
548
549 static void
550 build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
551 {
552 AcpiTableMcfg *mcfg;
553 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
554
555 mcfg = acpi_data_push(table_data, len);
556 mcfg->allocation[0].address = cpu_to_le64(info->base);
557
558 /* Only a single allocation so no need to play with segments */
559 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
560 mcfg->allocation[0].start_bus_number = 0;
561 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->size - 1);
562
563 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL);
564 }
565
566 /* GTDT */
567 static void
568 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
569 {
570 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
571 int gtdt_start = table_data->len;
572 AcpiGenericTimerTable *gtdt;
573 uint32_t irqflags;
574
575 if (vmc->claim_edge_triggered_timers) {
576 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
577 } else {
578 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
579 }
580
581 gtdt = acpi_data_push(table_data, sizeof *gtdt);
582 /* The interrupt values are the same with the device tree when adding 16 */
583 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
584 gtdt->secure_el1_flags = cpu_to_le32(irqflags);
585
586 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
587 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
588 ACPI_GTDT_CAP_ALWAYS_ON);
589
590 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
591 gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
592
593 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
594 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
595
596 build_header(linker, table_data,
597 (void *)(table_data->data + gtdt_start), "GTDT",
598 table_data->len - gtdt_start, 2, NULL, NULL);
599 }
600
601 /* MADT */
602 static void
603 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
604 {
605 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
606 int madt_start = table_data->len;
607 const MemMapEntry *memmap = vms->memmap;
608 const int *irqmap = vms->irqmap;
609 AcpiMultipleApicTable *madt;
610 AcpiMadtGenericDistributor *gicd;
611 AcpiMadtGenericMsiFrame *gic_msi;
612 int i;
613
614 madt = acpi_data_push(table_data, sizeof *madt);
615
616 gicd = acpi_data_push(table_data, sizeof *gicd);
617 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
618 gicd->length = sizeof(*gicd);
619 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
620 gicd->version = vms->gic_version;
621
622 for (i = 0; i < vms->smp_cpus; i++) {
623 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
624 sizeof(*gicc));
625 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
626
627 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
628 gicc->length = sizeof(*gicc);
629 if (vms->gic_version == 2) {
630 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
631 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
632 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
633 }
634 gicc->cpu_interface_number = cpu_to_le32(i);
635 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
636 gicc->uid = cpu_to_le32(i);
637 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
638
639 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
640 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
641 }
642 if (vms->virt) {
643 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
644 }
645 }
646
647 if (vms->gic_version == 3) {
648 AcpiMadtGenericTranslator *gic_its;
649 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
650 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
651 sizeof *gicr);
652
653 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
654 gicr->length = sizeof(*gicr);
655 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
656 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
657
658 if (nb_redist_regions == 2) {
659 gicr = acpi_data_push(table_data, sizeof(*gicr));
660 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
661 gicr->length = sizeof(*gicr);
662 gicr->base_address =
663 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base);
664 gicr->range_length =
665 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size);
666 }
667
668 if (its_class_name() && !vmc->no_its) {
669 gic_its = acpi_data_push(table_data, sizeof *gic_its);
670 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
671 gic_its->length = sizeof(*gic_its);
672 gic_its->translation_id = 0;
673 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
674 }
675 } else {
676 gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
677 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
678 gic_msi->length = sizeof(*gic_msi);
679 gic_msi->gic_msi_frame_id = 0;
680 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
681 gic_msi->flags = cpu_to_le32(1);
682 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
683 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
684 }
685
686 build_header(linker, table_data,
687 (void *)(table_data->data + madt_start), "APIC",
688 table_data->len - madt_start, 3, NULL, NULL);
689 }
690
691 /* FADT */
692 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
693 VirtMachineState *vms, unsigned dsdt_tbl_offset)
694 {
695 /* ACPI v5.1 */
696 AcpiFadtData fadt = {
697 .rev = 5,
698 .minor_ver = 1,
699 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
700 .xdsdt_tbl_offset = &dsdt_tbl_offset,
701 };
702
703 switch (vms->psci_conduit) {
704 case QEMU_PSCI_CONDUIT_DISABLED:
705 fadt.arm_boot_arch = 0;
706 break;
707 case QEMU_PSCI_CONDUIT_HVC:
708 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
709 ACPI_FADT_ARM_PSCI_USE_HVC;
710 break;
711 case QEMU_PSCI_CONDUIT_SMC:
712 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
713 break;
714 default:
715 g_assert_not_reached();
716 }
717
718 build_fadt(table_data, linker, &fadt, NULL, NULL);
719 }
720
721 /* DSDT */
722 static void
723 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
724 {
725 Aml *scope, *dsdt;
726 const MemMapEntry *memmap = vms->memmap;
727 const int *irqmap = vms->irqmap;
728
729 dsdt = init_aml_allocator();
730 /* Reserve space for header */
731 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
732
733 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
734 * While UEFI can use libfdt to disable the RTC device node in the DTB that
735 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
736 * the RTC ACPI device at all when using UEFI.
737 */
738 scope = aml_scope("\\_SB");
739 acpi_dsdt_add_cpus(scope, vms->smp_cpus);
740 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
741 (irqmap[VIRT_UART] + ARM_SPI_BASE));
742 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
743 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
744 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
745 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
746 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
747 vms->highmem, vms->highmem_ecam);
748 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
749 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
750 acpi_dsdt_add_power_button(scope);
751
752 aml_append(dsdt, scope);
753
754 /* copy AML table into ACPI tables blob and patch header there */
755 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
756 build_header(linker, table_data,
757 (void *)(table_data->data + table_data->len - dsdt->buf->len),
758 "DSDT", dsdt->buf->len, 2, NULL, NULL);
759 free_aml_allocator();
760 }
761
762 typedef
763 struct AcpiBuildState {
764 /* Copy of table in RAM (for patching). */
765 MemoryRegion *table_mr;
766 MemoryRegion *rsdp_mr;
767 MemoryRegion *linker_mr;
768 /* Is table patched? */
769 bool patched;
770 } AcpiBuildState;
771
772 static
773 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
774 {
775 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
776 GArray *table_offsets;
777 unsigned dsdt, xsdt;
778 GArray *tables_blob = tables->table_data;
779
780 table_offsets = g_array_new(false, true /* clear */,
781 sizeof(uint32_t));
782
783 bios_linker_loader_alloc(tables->linker,
784 ACPI_BUILD_TABLE_FILE, tables_blob,
785 64, false /* high memory */);
786
787 /* DSDT is pointed to by FADT */
788 dsdt = tables_blob->len;
789 build_dsdt(tables_blob, tables->linker, vms);
790
791 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
792 acpi_add_table(table_offsets, tables_blob);
793 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
794
795 acpi_add_table(table_offsets, tables_blob);
796 build_madt(tables_blob, tables->linker, vms);
797
798 acpi_add_table(table_offsets, tables_blob);
799 build_gtdt(tables_blob, tables->linker, vms);
800
801 acpi_add_table(table_offsets, tables_blob);
802 {
803 AcpiMcfgInfo mcfg = {
804 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
805 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
806 };
807 build_mcfg(tables_blob, tables->linker, &mcfg);
808 }
809
810 acpi_add_table(table_offsets, tables_blob);
811 build_spcr(tables_blob, tables->linker, vms);
812
813 if (nb_numa_nodes > 0) {
814 acpi_add_table(table_offsets, tables_blob);
815 build_srat(tables_blob, tables->linker, vms);
816 if (have_numa_distance) {
817 acpi_add_table(table_offsets, tables_blob);
818 build_slit(tables_blob, tables->linker);
819 }
820 }
821
822 if (its_class_name() && !vmc->no_its) {
823 acpi_add_table(table_offsets, tables_blob);
824 build_iort(tables_blob, tables->linker, vms);
825 }
826
827 /* XSDT is pointed to by RSDP */
828 xsdt = tables_blob->len;
829 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
830
831 /* RSDP is in FSEG memory, so allocate it separately */
832 {
833 AcpiRsdpData rsdp_data = {
834 .revision = 2,
835 .oem_id = ACPI_BUILD_APPNAME6,
836 .xsdt_tbl_offset = &xsdt,
837 .rsdt_tbl_offset = NULL,
838 };
839 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
840 }
841
842 /* Cleanup memory that's no longer used. */
843 g_array_free(table_offsets, true);
844 }
845
846 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
847 {
848 uint32_t size = acpi_data_len(data);
849
850 /* Make sure RAM size is correct - in case it got changed
851 * e.g. by migration */
852 memory_region_ram_resize(mr, size, &error_abort);
853
854 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
855 memory_region_set_dirty(mr, 0, size);
856 }
857
858 static void virt_acpi_build_update(void *build_opaque)
859 {
860 AcpiBuildState *build_state = build_opaque;
861 AcpiBuildTables tables;
862
863 /* No state to update or already patched? Nothing to do. */
864 if (!build_state || build_state->patched) {
865 return;
866 }
867 build_state->patched = true;
868
869 acpi_build_tables_init(&tables);
870
871 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
872
873 acpi_ram_update(build_state->table_mr, tables.table_data);
874 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
875 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
876
877 acpi_build_tables_cleanup(&tables, true);
878 }
879
880 static void virt_acpi_build_reset(void *build_opaque)
881 {
882 AcpiBuildState *build_state = build_opaque;
883 build_state->patched = false;
884 }
885
886 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
887 GArray *blob, const char *name,
888 uint64_t max_size)
889 {
890 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
891 name, virt_acpi_build_update, build_state, NULL, true);
892 }
893
894 static const VMStateDescription vmstate_virt_acpi_build = {
895 .name = "virt_acpi_build",
896 .version_id = 1,
897 .minimum_version_id = 1,
898 .fields = (VMStateField[]) {
899 VMSTATE_BOOL(patched, AcpiBuildState),
900 VMSTATE_END_OF_LIST()
901 },
902 };
903
904 void virt_acpi_setup(VirtMachineState *vms)
905 {
906 AcpiBuildTables tables;
907 AcpiBuildState *build_state;
908
909 if (!vms->fw_cfg) {
910 trace_virt_acpi_setup();
911 return;
912 }
913
914 if (!acpi_enabled) {
915 trace_virt_acpi_setup();
916 return;
917 }
918
919 build_state = g_malloc0(sizeof *build_state);
920
921 acpi_build_tables_init(&tables);
922 virt_acpi_build(vms, &tables);
923
924 /* Now expose it all to Guest */
925 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
926 ACPI_BUILD_TABLE_FILE,
927 ACPI_BUILD_TABLE_MAX_SIZE);
928 assert(build_state->table_mr != NULL);
929
930 build_state->linker_mr =
931 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
932 "etc/table-loader", 0);
933
934 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
935 acpi_data_len(tables.tcpalog));
936
937 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
938 ACPI_BUILD_RSDP_FILE, 0);
939
940 qemu_register_reset(virt_acpi_build_reset, build_state);
941 virt_acpi_build_reset(build_state);
942 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
943
944 /* Cleanup tables but don't free the memory: we track it
945 * in build_state.
946 */
947 acpi_build_tables_cleanup(&tables, false);
948 }
AR7 emulation for QEMU