hw/arm/mainstone.c

   1 /*
   2  * PXA270-based Intel Mainstone platforms.
   3  *
   4  * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
   5  *                                    <akuster@mvista.com>
   6  *
   7  * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * This code is licensed under the GNU GPL v2.
  10  *
  11  * Contributions after 2012-01-13 are licensed under the terms of the
  12  * GNU GPL, version 2 or (at your option) any later version.
  13  */
  14 #include "qemu/osdep.h"
  15 #include "qemu/error-report.h"
  16 #include "qapi/error.h"
  17 #include "hw/hw.h"
  18 #include "hw/arm/pxa.h"
  19 #include "hw/arm/arm.h"
  20 #include "net/net.h"
  21 #include "hw/net/smc91c111.h"
  22 #include "hw/boards.h"
  23 #include "hw/block/flash.h"
  24 #include "hw/sysbus.h"
  25 #include "exec/address-spaces.h"
  26 #include "sysemu/qtest.h"
  27 #include "cpu.h"
  28
  29 /* Device addresses */
  30 #define MST_FPGA_PHYS   0x08000000
  31 #define MST_ETH_PHYS    0x10000300
  32 #define MST_FLASH_0             0x00000000
  33 #define MST_FLASH_1             0x04000000
  34
  35 /* IRQ definitions */
  36 #define MMC_IRQ       0
  37 #define USIM_IRQ      1
  38 #define USBC_IRQ      2
  39 #define ETHERNET_IRQ  3
  40 #define AC97_IRQ      4
  41 #define PEN_IRQ       5
  42 #define MSINS_IRQ     6
  43 #define EXBRD_IRQ     7
  44 #define S0_CD_IRQ     9
  45 #define S0_STSCHG_IRQ 10
  46 #define S0_IRQ        11
  47 #define S1_CD_IRQ     13
  48 #define S1_STSCHG_IRQ 14
  49 #define S1_IRQ        15
  50
  51 static const struct keymap map[0xE0] = {
  52     [0 ... 0xDF] = { -1, -1 },
  53     [0x1e] = {0,0}, /* a */
  54     [0x30] = {0,1}, /* b */
  55     [0x2e] = {0,2}, /* c */
  56     [0x20] = {0,3}, /* d */
  57     [0x12] = {0,4}, /* e */
  58     [0x21] = {0,5}, /* f */
  59     [0x22] = {1,0}, /* g */
  60     [0x23] = {1,1}, /* h */
  61     [0x17] = {1,2}, /* i */
  62     [0x24] = {1,3}, /* j */
  63     [0x25] = {1,4}, /* k */
  64     [0x26] = {1,5}, /* l */
  65     [0x32] = {2,0}, /* m */
  66     [0x31] = {2,1}, /* n */
  67     [0x18] = {2,2}, /* o */
  68     [0x19] = {2,3}, /* p */
  69     [0x10] = {2,4}, /* q */
  70     [0x13] = {2,5}, /* r */
  71     [0x1f] = {3,0}, /* s */
  72     [0x14] = {3,1}, /* t */
  73     [0x16] = {3,2}, /* u */
  74     [0x2f] = {3,3}, /* v */
  75     [0x11] = {3,4}, /* w */
  76     [0x2d] = {3,5}, /* x */
  77     [0x34] = {4,0}, /* . */
  78     [0x15] = {4,2}, /* y */
  79     [0x2c] = {4,3}, /* z */
  80     [0x35] = {4,4}, /* / */
  81     [0xc7] = {5,0}, /* Home */
  82     [0x2a] = {5,1}, /* shift */
  83     /*
  84      * There are two matrix positions which map to space,
  85      * but QEMU can only use one of them for the reverse
  86      * mapping, so simply use the second one.
  87      */
  88     /* [0x39] = {5,2}, space */
  89     [0x39] = {5,3}, /* space */
  90     /*
  91      * Matrix position {5,4} and other keys are missing here.
  92      * TODO: Compare with Linux code and test real hardware.
  93      */
  94     [0x1c] = {5,4}, /* enter */
  95     [0x0e] = {5,5}, /* backspace */
  96     [0xc8] = {6,0}, /* up */
  97     [0xd0] = {6,1}, /* down */
  98     [0xcb] = {6,2}, /* left */
  99     [0xcd] = {6,3}, /* right */
 100 };
 101
 102 enum mainstone_model_e { mainstone };
 103
 104 #define MAINSTONE_RAM   0x04000000
 105 #define MAINSTONE_ROM   0x00800000
 106 #define MAINSTONE_FLASH 0x02000000
 107
 108 static struct arm_boot_info mainstone_binfo = {
 109     .loader_start = PXA2XX_SDRAM_BASE,
 110     .ram_size = 0x04000000,
 111 };
 112
 113 static void mainstone_common_init(MemoryRegion *address_space_mem,
 114                                   MachineState *machine,
 115                                   enum mainstone_model_e model, int arm_id)
 116 {
 117     uint32_t sector_len = 256 * 1024;
 118     hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
 119     PXA2xxState *mpu;
 120     DeviceState *mst_irq;
 121     DriveInfo *dinfo;
 122     int i;
 123     int be;
 124     MemoryRegion *rom = g_new(MemoryRegion, 1);
 125
 126     /* Setup CPU & memory */
 127     mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
 128                       machine->cpu_type);
 129     memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
 130                            &error_fatal);
 131     memory_region_set_readonly(rom, true);
 132     memory_region_add_subregion(address_space_mem, 0, rom);
 133
 134 #ifdef TARGET_WORDS_BIGENDIAN
 135     be = 1;
 136 #else
 137     be = 0;
 138 #endif
 139     /* There are two 32MiB flash devices on the board */
 140     for (i = 0; i < 2; i ++) {
 141         dinfo = drive_get(IF_PFLASH, 0, i);
 142         if (!dinfo) {
 143             if (qtest_enabled()) {
 144                 break;
 145             }
 146             error_report("Two flash images must be given with the "
 147                          "'pflash' parameter");
 148             exit(1);
 149         }
 150
 151         if (!pflash_cfi01_register(mainstone_flash_base[i],
 152                                    i ? "mainstone.flash1" : "mainstone.flash0",
 153                                    MAINSTONE_FLASH,
 154                                    blk_by_legacy_dinfo(dinfo),
 155                                    sector_len, 4, 0, 0, 0, 0, be)) {
 156             error_report("Error registering flash memory");
 157             exit(1);
 158         }
 159     }
 160
 161     mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
 162                     qdev_get_gpio_in(mpu->gpio, 0));
 163
 164     /* setup keypad */
 165     pxa27x_register_keypad(mpu->kp, map, 0xe0);
 166
 167     /* MMC/SD host */
 168     pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
 169
 170     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
 171             qdev_get_gpio_in(mst_irq, S0_IRQ),
 172             qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
 173     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
 174             qdev_get_gpio_in(mst_irq, S1_IRQ),
 175             qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
 176
 177     smc91c111_init(&nd_table[0], MST_ETH_PHYS,
 178                     qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
 179
 180     mainstone_binfo.kernel_filename = machine->kernel_filename;
 181     mainstone_binfo.kernel_cmdline = machine->kernel_cmdline;
 182     mainstone_binfo.initrd_filename = machine->initrd_filename;
 183     mainstone_binfo.board_id = arm_id;
 184     arm_load_kernel(mpu->cpu, &mainstone_binfo);
 185 }
 186
 187 static void mainstone_init(MachineState *machine)
 188 {
 189     mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
 190 }
 191
 192 static void mainstone2_machine_init(MachineClass *mc)
 193 {
 194     mc->desc = "Mainstone II (PXA27x)";
 195     mc->init = mainstone_init;
 196     mc->ignore_memory_transaction_failures = true;
 197     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
 198 }
 199
 200 DEFINE_MACHINE("mainstone", mainstone2_machine_init)