include/qemu/osdep.h: Don't include qapi/error.h
[qemu/ar7.git] / hw / nvram / spapr_nvram.c
blob2ca427b5865394976eea24b3c900b0997b212b90
1 /*
2 * QEMU sPAPR NVRAM emulation
4 * Copyright (C) 2012 David Gibson, IBM Corporation.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include <libfdt.h>
29 #include "sysemu/block-backend.h"
30 #include "sysemu/device_tree.h"
31 #include "hw/sysbus.h"
32 #include "hw/ppc/spapr.h"
33 #include "hw/ppc/spapr_vio.h"
35 typedef struct sPAPRNVRAM {
36 VIOsPAPRDevice sdev;
37 uint32_t size;
38 uint8_t *buf;
39 BlockBackend *blk;
40 } sPAPRNVRAM;
42 #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
43 #define VIO_SPAPR_NVRAM(obj) \
44 OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM)
46 #define MIN_NVRAM_SIZE 8192
47 #define DEFAULT_NVRAM_SIZE 65536
48 #define MAX_NVRAM_SIZE 1048576
50 static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr,
51 uint32_t token, uint32_t nargs,
52 target_ulong args,
53 uint32_t nret, target_ulong rets)
55 sPAPRNVRAM *nvram = spapr->nvram;
56 hwaddr offset, buffer, len;
57 void *membuf;
59 if ((nargs != 3) || (nret != 2)) {
60 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
61 return;
64 if (!nvram) {
65 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
66 rtas_st(rets, 1, 0);
67 return;
70 offset = rtas_ld(args, 0);
71 buffer = rtas_ld(args, 1);
72 len = rtas_ld(args, 2);
74 if (((offset + len) < offset)
75 || ((offset + len) > nvram->size)) {
76 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
77 rtas_st(rets, 1, 0);
78 return;
81 assert(nvram->buf);
83 membuf = cpu_physical_memory_map(buffer, &len, 1);
84 memcpy(membuf, nvram->buf + offset, len);
85 cpu_physical_memory_unmap(membuf, len, 1, len);
87 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
88 rtas_st(rets, 1, len);
91 static void rtas_nvram_store(PowerPCCPU *cpu, sPAPRMachineState *spapr,
92 uint32_t token, uint32_t nargs,
93 target_ulong args,
94 uint32_t nret, target_ulong rets)
96 sPAPRNVRAM *nvram = spapr->nvram;
97 hwaddr offset, buffer, len;
98 int alen;
99 void *membuf;
101 if ((nargs != 3) || (nret != 2)) {
102 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
103 return;
106 if (!nvram) {
107 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
108 return;
111 offset = rtas_ld(args, 0);
112 buffer = rtas_ld(args, 1);
113 len = rtas_ld(args, 2);
115 if (((offset + len) < offset)
116 || ((offset + len) > nvram->size)) {
117 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
118 return;
121 membuf = cpu_physical_memory_map(buffer, &len, 0);
123 alen = len;
124 if (nvram->blk) {
125 alen = blk_pwrite(nvram->blk, offset, membuf, len);
128 assert(nvram->buf);
129 memcpy(nvram->buf + offset, membuf, len);
131 cpu_physical_memory_unmap(membuf, len, 0, len);
133 rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS);
134 rtas_st(rets, 1, (alen < 0) ? 0 : alen);
137 static void spapr_nvram_realize(VIOsPAPRDevice *dev, Error **errp)
139 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
141 if (nvram->blk) {
142 nvram->size = blk_getlength(nvram->blk);
143 } else {
144 nvram->size = DEFAULT_NVRAM_SIZE;
147 nvram->buf = g_malloc0(nvram->size);
149 if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
150 error_setg(errp, "spapr-nvram must be between %d and %d bytes in size",
151 MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
152 return;
155 if (nvram->blk) {
156 int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size);
158 if (alen != nvram->size) {
159 error_setg(errp, "can't read spapr-nvram contents");
160 return;
164 spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch);
165 spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store);
168 static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
170 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
172 return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
175 static int spapr_nvram_pre_load(void *opaque)
177 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
179 g_free(nvram->buf);
180 nvram->buf = NULL;
181 nvram->size = 0;
183 return 0;
186 static int spapr_nvram_post_load(void *opaque, int version_id)
188 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
190 if (nvram->blk) {
191 int alen = blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size);
193 if (alen < 0) {
194 return alen;
196 if (alen != nvram->size) {
197 return -1;
201 return 0;
204 static const VMStateDescription vmstate_spapr_nvram = {
205 .name = "spapr_nvram",
206 .version_id = 1,
207 .minimum_version_id = 1,
208 .pre_load = spapr_nvram_pre_load,
209 .post_load = spapr_nvram_post_load,
210 .fields = (VMStateField[]) {
211 VMSTATE_UINT32(size, sPAPRNVRAM),
212 VMSTATE_VBUFFER_ALLOC_UINT32(buf, sPAPRNVRAM, 1, NULL, 0, size),
213 VMSTATE_END_OF_LIST()
217 static Property spapr_nvram_properties[] = {
218 DEFINE_SPAPR_PROPERTIES(sPAPRNVRAM, sdev),
219 DEFINE_PROP_DRIVE("drive", sPAPRNVRAM, blk),
220 DEFINE_PROP_END_OF_LIST(),
223 static void spapr_nvram_class_init(ObjectClass *klass, void *data)
225 DeviceClass *dc = DEVICE_CLASS(klass);
226 VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
228 k->realize = spapr_nvram_realize;
229 k->devnode = spapr_nvram_devnode;
230 k->dt_name = "nvram";
231 k->dt_type = "nvram";
232 k->dt_compatible = "qemu,spapr-nvram";
233 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
234 dc->props = spapr_nvram_properties;
235 dc->vmsd = &vmstate_spapr_nvram;
238 static const TypeInfo spapr_nvram_type_info = {
239 .name = TYPE_VIO_SPAPR_NVRAM,
240 .parent = TYPE_VIO_SPAPR_DEVICE,
241 .instance_size = sizeof(sPAPRNVRAM),
242 .class_init = spapr_nvram_class_init,
245 static void spapr_nvram_register_types(void)
247 type_register_static(&spapr_nvram_type_info);
250 type_init(spapr_nvram_register_types)