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include/qemu/osdep.h: Don't include qapi/error.h
[qemu/ar7.git] / hw / intc / openpic.c
blob2d3769310fbbe235aef9e40be5f45b2f39014a1f
1 /*
2 * OpenPIC emulation
3 *
4 * Copyright (c) 2004 Jocelyn Mayer
5 * 2011 Alexander Graf
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 *
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
32 *
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
34 *
35 */
36 #include "qemu/osdep.h"
37 #include "hw/hw.h"
38 #include "hw/ppc/mac.h"
39 #include "hw/pci/pci.h"
40 #include "hw/ppc/openpic.h"
41 #include "hw/ppc/ppc_e500.h"
42 #include "hw/sysbus.h"
43 #include "hw/pci/msi.h"
44 #include "qapi/error.h"
45 #include "qemu/bitops.h"
46 #include "qapi/qmp/qerror.h"
47
48 //#define DEBUG_OPENPIC
49
50 #ifdef DEBUG_OPENPIC
51 static const int debug_openpic = 1;
52 #else
53 static const int debug_openpic = 0;
54 #endif
55
56 #define DPRINTF(fmt, ...) do { \
57 if (debug_openpic) { \
58 printf(fmt , ## __VA_ARGS__); \
59 } \
60 } while (0)
61
62 #define MAX_CPU 32
63 #define MAX_MSI 8
64 #define VID 0x03 /* MPIC version ID */
65
66 /* OpenPIC capability flags */
67 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
68 #define OPENPIC_FLAG_ILR (2 << 0)
69
70 /* OpenPIC address map */
71 #define OPENPIC_GLB_REG_START 0x0
72 #define OPENPIC_GLB_REG_SIZE 0x10F0
73 #define OPENPIC_TMR_REG_START 0x10F0
74 #define OPENPIC_TMR_REG_SIZE 0x220
75 #define OPENPIC_MSI_REG_START 0x1600
76 #define OPENPIC_MSI_REG_SIZE 0x200
77 #define OPENPIC_SUMMARY_REG_START 0x3800
78 #define OPENPIC_SUMMARY_REG_SIZE 0x800
79 #define OPENPIC_SRC_REG_START 0x10000
80 #define OPENPIC_SRC_REG_SIZE (OPENPIC_MAX_SRC * 0x20)
81 #define OPENPIC_CPU_REG_START 0x20000
82 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
83
84 /* Raven */
85 #define RAVEN_MAX_CPU 2
86 #define RAVEN_MAX_EXT 48
87 #define RAVEN_MAX_IRQ 64
88 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR
89 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI
90
91 /* Interrupt definitions */
92 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
93 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
94 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
95 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
96 /* First doorbell IRQ */
97 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
98
99 typedef struct FslMpicInfo {
100 int max_ext;
101 } FslMpicInfo;
102
103 static FslMpicInfo fsl_mpic_20 = {
104 .max_ext = 12,
105 };
106
107 static FslMpicInfo fsl_mpic_42 = {
108 .max_ext = 12,
109 };
110
111 #define FRR_NIRQ_SHIFT 16
112 #define FRR_NCPU_SHIFT 8
113 #define FRR_VID_SHIFT 0
114
115 #define VID_REVISION_1_2 2
116 #define VID_REVISION_1_3 3
117
118 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
119
120 #define GCR_RESET 0x80000000
121 #define GCR_MODE_PASS 0x00000000
122 #define GCR_MODE_MIXED 0x20000000
123 #define GCR_MODE_PROXY 0x60000000
124
125 #define TBCR_CI 0x80000000 /* count inhibit */
126 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
127
128 #define IDR_EP_SHIFT 31
129 #define IDR_EP_MASK (1U << IDR_EP_SHIFT)
130 #define IDR_CI0_SHIFT 30
131 #define IDR_CI1_SHIFT 29
132 #define IDR_P1_SHIFT 1
133 #define IDR_P0_SHIFT 0
134
135 #define ILR_INTTGT_MASK 0x000000ff
136 #define ILR_INTTGT_INT 0x00
137 #define ILR_INTTGT_CINT 0x01 /* critical */
138 #define ILR_INTTGT_MCP 0x02 /* machine check */
139
140 /* The currently supported INTTGT values happen to be the same as QEMU's
141 * openpic output codes, but don't depend on this. The output codes
142 * could change (unlikely, but...) or support could be added for
143 * more INTTGT values.
144 */
145 static const int inttgt_output[][2] = {
146 { ILR_INTTGT_INT, OPENPIC_OUTPUT_INT },
147 { ILR_INTTGT_CINT, OPENPIC_OUTPUT_CINT },
148 { ILR_INTTGT_MCP, OPENPIC_OUTPUT_MCK },
149 };
150
151 static int inttgt_to_output(int inttgt)
152 {
153 int i;
154
155 for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
156 if (inttgt_output[i][0] == inttgt) {
157 return inttgt_output[i][1];
158 }
159 }
160
161 fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt);
162 return OPENPIC_OUTPUT_INT;
163 }
164
165 static int output_to_inttgt(int output)
166 {
167 int i;
168
169 for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
170 if (inttgt_output[i][1] == output) {
171 return inttgt_output[i][0];
172 }
173 }
174
175 abort();
176 }
177
178 #define MSIIR_OFFSET 0x140
179 #define MSIIR_SRS_SHIFT 29
180 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
181 #define MSIIR_IBS_SHIFT 24
182 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
183
184 static int get_current_cpu(void)
185 {
186 if (!current_cpu) {
187 return -1;
188 }
189
190 return current_cpu->cpu_index;
191 }
192
193 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
194 int idx);
195 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
196 uint32_t val, int idx);
197 static void openpic_reset(DeviceState *d);
198
199 typedef enum IRQType {
200 IRQ_TYPE_NORMAL = 0,
201 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
202 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
203 } IRQType;
204
205 /* Round up to the nearest 64 IRQs so that the queue length
206 * won't change when moving between 32 and 64 bit hosts.
207 */
208 #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
209
210 typedef struct IRQQueue {
211 unsigned long *queue;
212 int32_t queue_size; /* Only used for VMSTATE_BITMAP */
213 int next;
214 int priority;
215 } IRQQueue;
216
217 typedef struct IRQSource {
218 uint32_t ivpr; /* IRQ vector/priority register */
219 uint32_t idr; /* IRQ destination register */
220 uint32_t destmask; /* bitmap of CPU destinations */
221 int last_cpu;
222 int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
223 int pending; /* TRUE if IRQ is pending */
224 IRQType type;
225 bool level:1; /* level-triggered */
226 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
227 } IRQSource;
228
229 #define IVPR_MASK_SHIFT 31
230 #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
231 #define IVPR_ACTIVITY_SHIFT 30
232 #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
233 #define IVPR_MODE_SHIFT 29
234 #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
235 #define IVPR_POLARITY_SHIFT 23
236 #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
237 #define IVPR_SENSE_SHIFT 22
238 #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
239
240 #define IVPR_PRIORITY_MASK (0xFU << 16)
241 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
242 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
243
244 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
245 #define IDR_EP 0x80000000 /* external pin */
246 #define IDR_CI 0x40000000 /* critical interrupt */
247
248 typedef struct OpenPICTimer {
249 uint32_t tccr; /* Global timer current count register */
250 uint32_t tbcr; /* Global timer base count register */
251 } OpenPICTimer;
252
253 typedef struct OpenPICMSI {
254 uint32_t msir; /* Shared Message Signaled Interrupt Register */
255 } OpenPICMSI;
256
257 typedef struct IRQDest {
258 int32_t ctpr; /* CPU current task priority */
259 IRQQueue raised;
260 IRQQueue servicing;
261 qemu_irq *irqs;
262
263 /* Count of IRQ sources asserting on non-INT outputs */
264 uint32_t outputs_active[OPENPIC_OUTPUT_NB];
265 } IRQDest;
266
267 #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC)
268
269 typedef struct OpenPICState {
270 /*< private >*/
271 SysBusDevice parent_obj;
272 /*< public >*/
273
274 MemoryRegion mem;
275
276 /* Behavior control */
277 FslMpicInfo *fsl;
278 uint32_t model;
279 uint32_t flags;
280 uint32_t nb_irqs;
281 uint32_t vid;
282 uint32_t vir; /* Vendor identification register */
283 uint32_t vector_mask;
284 uint32_t tfrr_reset;
285 uint32_t ivpr_reset;
286 uint32_t idr_reset;
287 uint32_t brr1;
288 uint32_t mpic_mode_mask;
289
290 /* Sub-regions */
291 MemoryRegion sub_io_mem[6];
292
293 /* Global registers */
294 uint32_t frr; /* Feature reporting register */
295 uint32_t gcr; /* Global configuration register */
296 uint32_t pir; /* Processor initialization register */
297 uint32_t spve; /* Spurious vector register */
298 uint32_t tfrr; /* Timer frequency reporting register */
299 /* Source registers */
300 IRQSource src[OPENPIC_MAX_IRQ];
301 /* Local registers per output pin */
302 IRQDest dst[MAX_CPU];
303 uint32_t nb_cpus;
304 /* Timer registers */
305 OpenPICTimer timers[OPENPIC_MAX_TMR];
306 /* Shared MSI registers */
307 OpenPICMSI msi[MAX_MSI];
308 uint32_t max_irq;
309 uint32_t irq_ipi0;
310 uint32_t irq_tim0;
311 uint32_t irq_msi;
312 } OpenPICState;
313
314 static inline void IRQ_setbit(IRQQueue *q, int n_IRQ)
315 {
316 set_bit(n_IRQ, q->queue);
317 }
318
319 static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ)
320 {
321 clear_bit(n_IRQ, q->queue);
322 }
323
324 static void IRQ_check(OpenPICState *opp, IRQQueue *q)
325 {
326 int irq = -1;
327 int next = -1;
328 int priority = -1;
329
330 for (;;) {
331 irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
332 if (irq == opp->max_irq) {
333 break;
334 }
335
336 DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
337 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
338
339 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
340 next = irq;
341 priority = IVPR_PRIORITY(opp->src[irq].ivpr);
342 }
343 }
344
345 q->next = next;
346 q->priority = priority;
347 }
348
349 static int IRQ_get_next(OpenPICState *opp, IRQQueue *q)
350 {
351 /* XXX: optimize */
352 IRQ_check(opp, q);
353
354 return q->next;
355 }
356
357 static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
358 bool active, bool was_active)
359 {
360 IRQDest *dst;
361 IRQSource *src;
362 int priority;
363
364 dst = &opp->dst[n_CPU];
365 src = &opp->src[n_IRQ];
366
367 DPRINTF("%s: IRQ %d active %d was %d\n",
368 __func__, n_IRQ, active, was_active);
369
370 if (src->output != OPENPIC_OUTPUT_INT) {
371 DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
372 __func__, src->output, n_IRQ, active, was_active,
373 dst->outputs_active[src->output]);
374
375 /* On Freescale MPIC, critical interrupts ignore priority,
376 * IACK, EOI, etc. Before MPIC v4.1 they also ignore
377 * masking.
378 */
379 if (active) {
380 if (!was_active && dst->outputs_active[src->output]++ == 0) {
381 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
382 __func__, src->output, n_CPU, n_IRQ);
383 qemu_irq_raise(dst->irqs[src->output]);
384 }
385 } else {
386 if (was_active && --dst->outputs_active[src->output] == 0) {
387 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
388 __func__, src->output, n_CPU, n_IRQ);
389 qemu_irq_lower(dst->irqs[src->output]);
390 }
391 }
392
393 return;
394 }
395
396 priority = IVPR_PRIORITY(src->ivpr);
397
398 /* Even if the interrupt doesn't have enough priority,
399 * it is still raised, in case ctpr is lowered later.
400 */
401 if (active) {
402 IRQ_setbit(&dst->raised, n_IRQ);
403 } else {
404 IRQ_resetbit(&dst->raised, n_IRQ);
405 }
406
407 IRQ_check(opp, &dst->raised);
408
409 if (active && priority <= dst->ctpr) {
410 DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
411 __func__, n_IRQ, priority, dst->ctpr, n_CPU);
412 active = 0;
413 }
414
415 if (active) {
416 if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
417 priority <= dst->servicing.priority) {
418 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
419 __func__, n_IRQ, dst->servicing.next, n_CPU);
420 } else {
421 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
422 __func__, n_CPU, n_IRQ, dst->raised.next);
423 qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
424 }
425 } else {
426 IRQ_get_next(opp, &dst->servicing);
427 if (dst->raised.priority > dst->ctpr &&
428 dst->raised.priority > dst->servicing.priority) {
429 DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
430 __func__, n_IRQ, dst->raised.next, dst->raised.priority,
431 dst->ctpr, dst->servicing.priority, n_CPU);
432 /* IRQ line stays asserted */
433 } else {
434 DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
435 __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU);
436 qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
437 }
438 }
439 }
440
441 /* update pic state because registers for n_IRQ have changed value */
442 static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
443 {
444 IRQSource *src;
445 bool active, was_active;
446 int i;
447
448 src = &opp->src[n_IRQ];
449 active = src->pending;
450
451 if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
452 /* Interrupt source is disabled */
453 DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
454 active = false;
455 }
456
457 was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK);
458
459 /*
460 * We don't have a similar check for already-active because
461 * ctpr may have changed and we need to withdraw the interrupt.
462 */
463 if (!active && !was_active) {
464 DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
465 return;
466 }
467
468 if (active) {
469 src->ivpr |= IVPR_ACTIVITY_MASK;
470 } else {
471 src->ivpr &= ~IVPR_ACTIVITY_MASK;
472 }
473
474 if (src->destmask == 0) {
475 /* No target */
476 DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
477 return;
478 }
479
480 if (src->destmask == (1 << src->last_cpu)) {
481 /* Only one CPU is allowed to receive this IRQ */
482 IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
483 } else if (!(src->ivpr & IVPR_MODE_MASK)) {
484 /* Directed delivery mode */
485 for (i = 0; i < opp->nb_cpus; i++) {
486 if (src->destmask & (1 << i)) {
487 IRQ_local_pipe(opp, i, n_IRQ, active, was_active);
488 }
489 }
490 } else {
491 /* Distributed delivery mode */
492 for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
493 if (i == opp->nb_cpus) {
494 i = 0;
495 }
496 if (src->destmask & (1 << i)) {
497 IRQ_local_pipe(opp, i, n_IRQ, active, was_active);
498 src->last_cpu = i;
499 break;
500 }
501 }
502 }
503 }
504
505 static void openpic_set_irq(void *opaque, int n_IRQ, int level)
506 {
507 OpenPICState *opp = opaque;
508 IRQSource *src;
509
510 if (n_IRQ >= OPENPIC_MAX_IRQ) {
511 fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ);
512 abort();
513 }
514
515 src = &opp->src[n_IRQ];
516 DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
517 n_IRQ, level, src->ivpr);
518 if (src->level) {
519 /* level-sensitive irq */
520 src->pending = level;
521 openpic_update_irq(opp, n_IRQ);
522 } else {
523 /* edge-sensitive irq */
524 if (level) {
525 src->pending = 1;
526 openpic_update_irq(opp, n_IRQ);
527 }
528
529 if (src->output != OPENPIC_OUTPUT_INT) {
530 /* Edge-triggered interrupts shouldn't be used
531 * with non-INT delivery, but just in case,
532 * try to make it do something sane rather than
533 * cause an interrupt storm. This is close to
534 * what you'd probably see happen in real hardware.
535 */
536 src->pending = 0;
537 openpic_update_irq(opp, n_IRQ);
538 }
539 }
540 }
541
542 static inline uint32_t read_IRQreg_idr(OpenPICState *opp, int n_IRQ)
543 {
544 return opp->src[n_IRQ].idr;
545 }
546
547 static inline uint32_t read_IRQreg_ilr(OpenPICState *opp, int n_IRQ)
548 {
549 if (opp->flags & OPENPIC_FLAG_ILR) {
550 return output_to_inttgt(opp->src[n_IRQ].output);
551 }
552
553 return 0xffffffff;
554 }
555
556 static inline uint32_t read_IRQreg_ivpr(OpenPICState *opp, int n_IRQ)
557 {
558 return opp->src[n_IRQ].ivpr;
559 }
560
561 static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val)
562 {
563 IRQSource *src = &opp->src[n_IRQ];
564 uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;
565 uint32_t crit_mask = 0;
566 uint32_t mask = normal_mask;
567 int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
568 int i;
569
570 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
571 crit_mask = mask << crit_shift;
572 mask |= crit_mask | IDR_EP;
573 }
574
575 src->idr = val & mask;
576 DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
577
578 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
579 if (src->idr & crit_mask) {
580 if (src->idr & normal_mask) {
581 DPRINTF("%s: IRQ configured for multiple output types, using "
582 "critical\n", __func__);
583 }
584
585 src->output = OPENPIC_OUTPUT_CINT;
586 src->nomask = true;
587 src->destmask = 0;
588
589 for (i = 0; i < opp->nb_cpus; i++) {
590 int n_ci = IDR_CI0_SHIFT - i;
591
592 if (src->idr & (1UL << n_ci)) {
593 src->destmask |= 1UL << i;
594 }
595 }
596 } else {
597 src->output = OPENPIC_OUTPUT_INT;
598 src->nomask = false;
599 src->destmask = src->idr & normal_mask;
600 }
601 } else {
602 src->destmask = src->idr;
603 }
604 }
605
606 static inline void write_IRQreg_ilr(OpenPICState *opp, int n_IRQ, uint32_t val)
607 {
608 if (opp->flags & OPENPIC_FLAG_ILR) {
609 IRQSource *src = &opp->src[n_IRQ];
610
611 src->output = inttgt_to_output(val & ILR_INTTGT_MASK);
612 DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
613 src->output);
614
615 /* TODO: on MPIC v4.0 only, set nomask for non-INT */
616 }
617 }
618
619 static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
620 {
621 uint32_t mask;
622
623 /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
624 * the polarity bit is read-only on internal interrupts.
625 */
626 mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
627 IVPR_POLARITY_MASK | opp->vector_mask;
628
629 /* ACTIVITY bit is read-only */
630 opp->src[n_IRQ].ivpr =
631 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
632
633 /* For FSL internal interrupts, The sense bit is reserved and zero,
634 * and the interrupt is always level-triggered. Timers and IPIs
635 * have no sense or polarity bits, and are edge-triggered.
636 */
637 switch (opp->src[n_IRQ].type) {
638 case IRQ_TYPE_NORMAL:
639 opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
640 break;
641
642 case IRQ_TYPE_FSLINT:
643 opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
644 break;
645
646 case IRQ_TYPE_FSLSPECIAL:
647 opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
648 break;
649 }
650
651 openpic_update_irq(opp, n_IRQ);
652 DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
653 opp->src[n_IRQ].ivpr);
654 }
655
656 static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
657 {
658 bool mpic_proxy = false;
659
660 if (val & GCR_RESET) {
661 openpic_reset(DEVICE(opp));
662 return;
663 }
664
665 opp->gcr &= ~opp->mpic_mode_mask;
666 opp->gcr |= val & opp->mpic_mode_mask;
667
668 /* Set external proxy mode */
669 if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
670 mpic_proxy = true;
671 }
672
673 ppce500_set_mpic_proxy(mpic_proxy);
674 }
675
676 static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
677 unsigned len)
678 {
679 OpenPICState *opp = opaque;
680 IRQDest *dst;
681 int idx;
682
683 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
684 __func__, addr, val);
685 if (addr & 0xF) {
686 return;
687 }
688 switch (addr) {
689 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
690 break;
691 case 0x40:
692 case 0x50:
693 case 0x60:
694 case 0x70:
695 case 0x80:
696 case 0x90:
697 case 0xA0:
698 case 0xB0:
699 openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
700 break;
701 case 0x1000: /* FRR */
702 break;
703 case 0x1020: /* GCR */
704 openpic_gcr_write(opp, val);
705 break;
706 case 0x1080: /* VIR */
707 break;
708 case 0x1090: /* PIR */
709 for (idx = 0; idx < opp->nb_cpus; idx++) {
710 if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
711 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
712 dst = &opp->dst[idx];
713 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
714 } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
715 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
716 dst = &opp->dst[idx];
717 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
718 }
719 }
720 opp->pir = val;
721 break;
722 case 0x10A0: /* IPI_IVPR */
723 case 0x10B0:
724 case 0x10C0:
725 case 0x10D0:
726 {
727 int idx;
728 idx = (addr - 0x10A0) >> 4;
729 write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
730 }
731 break;
732 case 0x10E0: /* SPVE */
733 opp->spve = val & opp->vector_mask;
734 break;
735 default:
736 break;
737 }
738 }
739
740 static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
741 {
742 OpenPICState *opp = opaque;
743 uint32_t retval;
744
745 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
746 retval = 0xFFFFFFFF;
747 if (addr & 0xF) {
748 return retval;
749 }
750 switch (addr) {
751 case 0x1000: /* FRR */
752 retval = opp->frr;
753 break;
754 case 0x1020: /* GCR */
755 retval = opp->gcr;
756 break;
757 case 0x1080: /* VIR */
758 retval = opp->vir;
759 break;
760 case 0x1090: /* PIR */
761 retval = 0x00000000;
762 break;
763 case 0x00: /* Block Revision Register1 (BRR1) */
764 retval = opp->brr1;
765 break;
766 case 0x40:
767 case 0x50:
768 case 0x60:
769 case 0x70:
770 case 0x80:
771 case 0x90:
772 case 0xA0:
773 case 0xB0:
774 retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
775 break;
776 case 0x10A0: /* IPI_IVPR */
777 case 0x10B0:
778 case 0x10C0:
779 case 0x10D0:
780 {
781 int idx;
782 idx = (addr - 0x10A0) >> 4;
783 retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
784 }
785 break;
786 case 0x10E0: /* SPVE */
787 retval = opp->spve;
788 break;
789 default:
790 break;
791 }
792 DPRINTF("%s: => 0x%08x\n", __func__, retval);
793
794 return retval;
795 }
796
797 static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
798 unsigned len)
799 {
800 OpenPICState *opp = opaque;
801 int idx;
802
803 addr += 0x10f0;
804
805 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
806 __func__, addr, val);
807 if (addr & 0xF) {
808 return;
809 }
810
811 if (addr == 0x10f0) {
812 /* TFRR */
813 opp->tfrr = val;
814 return;
815 }
816
817 idx = (addr >> 6) & 0x3;
818 addr = addr & 0x30;
819
820 switch (addr & 0x30) {
821 case 0x00: /* TCCR */
822 break;
823 case 0x10: /* TBCR */
824 if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&
825 (val & TBCR_CI) == 0 &&
826 (opp->timers[idx].tbcr & TBCR_CI) != 0) {
827 opp->timers[idx].tccr &= ~TCCR_TOG;
828 }
829 opp->timers[idx].tbcr = val;
830 break;
831 case 0x20: /* TVPR */
832 write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
833 break;
834 case 0x30: /* TDR */
835 write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
836 break;
837 }
838 }
839
840 static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
841 {
842 OpenPICState *opp = opaque;
843 uint32_t retval = -1;
844 int idx;
845
846 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
847 if (addr & 0xF) {
848 goto out;
849 }
850 idx = (addr >> 6) & 0x3;
851 if (addr == 0x0) {
852 /* TFRR */
853 retval = opp->tfrr;
854 goto out;
855 }
856 switch (addr & 0x30) {
857 case 0x00: /* TCCR */
858 retval = opp->timers[idx].tccr;
859 break;
860 case 0x10: /* TBCR */
861 retval = opp->timers[idx].tbcr;
862 break;
863 case 0x20: /* TIPV */
864 retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
865 break;
866 case 0x30: /* TIDE (TIDR) */
867 retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
868 break;
869 }
870
871 out:
872 DPRINTF("%s: => 0x%08x\n", __func__, retval);
873
874 return retval;
875 }
876
877 static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
878 unsigned len)
879 {
880 OpenPICState *opp = opaque;
881 int idx;
882
883 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
884 __func__, addr, val);
885
886 addr = addr & 0xffff;
887 idx = addr >> 5;
888
889 switch (addr & 0x1f) {
890 case 0x00:
891 write_IRQreg_ivpr(opp, idx, val);
892 break;
893 case 0x10:
894 write_IRQreg_idr(opp, idx, val);
895 break;
896 case 0x18:
897 write_IRQreg_ilr(opp, idx, val);
898 break;
899 }
900 }
901
902 static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
903 {
904 OpenPICState *opp = opaque;
905 uint32_t retval;
906 int idx;
907
908 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
909 retval = 0xFFFFFFFF;
910
911 addr = addr & 0xffff;
912 idx = addr >> 5;
913
914 switch (addr & 0x1f) {
915 case 0x00:
916 retval = read_IRQreg_ivpr(opp, idx);
917 break;
918 case 0x10:
919 retval = read_IRQreg_idr(opp, idx);
920 break;
921 case 0x18:
922 retval = read_IRQreg_ilr(opp, idx);
923 break;
924 }
925
926 DPRINTF("%s: => 0x%08x\n", __func__, retval);
927 return retval;
928 }
929
930 static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val,
931 unsigned size)
932 {
933 OpenPICState *opp = opaque;
934 int idx = opp->irq_msi;
935 int srs, ibs;
936
937 DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n",
938 __func__, addr, val);
939 if (addr & 0xF) {
940 return;
941 }
942
943 switch (addr) {
944 case MSIIR_OFFSET:
945 srs = val >> MSIIR_SRS_SHIFT;
946 idx += srs;
947 ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
948 opp->msi[srs].msir |= 1 << ibs;
949 openpic_set_irq(opp, idx, 1);
950 break;
951 default:
952 /* most registers are read-only, thus ignored */
953 break;
954 }
955 }
956
957 static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
958 {
959 OpenPICState *opp = opaque;
960 uint64_t r = 0;
961 int i, srs;
962
963 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
964 if (addr & 0xF) {
965 return -1;
966 }
967
968 srs = addr >> 4;
969
970 switch (addr) {
971 case 0x00:
972 case 0x10:
973 case 0x20:
974 case 0x30:
975 case 0x40:
976 case 0x50:
977 case 0x60:
978 case 0x70: /* MSIRs */
979 r = opp->msi[srs].msir;
980 /* Clear on read */
981 opp->msi[srs].msir = 0;
982 openpic_set_irq(opp, opp->irq_msi + srs, 0);
983 break;
984 case 0x120: /* MSISR */
985 for (i = 0; i < MAX_MSI; i++) {
986 r |= (opp->msi[i].msir ? 1 : 0) << i;
987 }
988 break;
989 }
990
991 return r;
992 }
993
994 static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size)
995 {
996 uint64_t r = 0;
997
998 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
999
1000 /* TODO: EISR/EIMR */
1001
1002 return r;
1003 }
1004
1005 static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val,
1006 unsigned size)
1007 {
1008 DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n",
1009 __func__, addr, val);
1010
1011 /* TODO: EISR/EIMR */
1012 }
1013
1014 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
1015 uint32_t val, int idx)
1016 {
1017 OpenPICState *opp = opaque;
1018 IRQSource *src;
1019 IRQDest *dst;
1020 int s_IRQ, n_IRQ;
1021
1022 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx,
1023 addr, val);
1024
1025 if (idx < 0 || idx >= opp->nb_cpus) {
1026 return;
1027 }
1028
1029 if (addr & 0xF) {
1030 return;
1031 }
1032 dst = &opp->dst[idx];
1033 addr &= 0xFF0;
1034 switch (addr) {
1035 case 0x40: /* IPIDR */
1036 case 0x50:
1037 case 0x60:
1038 case 0x70:
1039 idx = (addr - 0x40) >> 4;
1040 /* we use IDE as mask which CPUs to deliver the IPI to still. */
1041 opp->src[opp->irq_ipi0 + idx].destmask |= val;
1042 openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
1043 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
1044 break;
1045 case 0x80: /* CTPR */
1046 dst->ctpr = val & 0x0000000F;
1047
1048 DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1049 __func__, idx, dst->ctpr, dst->raised.priority,
1050 dst->servicing.priority);
1051
1052 if (dst->raised.priority <= dst->ctpr) {
1053 DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1054 __func__, idx);
1055 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
1056 } else if (dst->raised.priority > dst->servicing.priority) {
1057 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1058 __func__, idx, dst->raised.next);
1059 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]);
1060 }
1061
1062 break;
1063 case 0x90: /* WHOAMI */
1064 /* Read-only register */
1065 break;
1066 case 0xA0: /* IACK */
1067 /* Read-only register */
1068 break;
1069 case 0xB0: /* EOI */
1070 DPRINTF("EOI\n");
1071 s_IRQ = IRQ_get_next(opp, &dst->servicing);
1072
1073 if (s_IRQ < 0) {
1074 DPRINTF("%s: EOI with no interrupt in service\n", __func__);
1075 break;
1076 }
1077
1078 IRQ_resetbit(&dst->servicing, s_IRQ);
1079 /* Set up next servicing IRQ */
1080 s_IRQ = IRQ_get_next(opp, &dst->servicing);
1081 /* Check queued interrupts. */
1082 n_IRQ = IRQ_get_next(opp, &dst->raised);
1083 src = &opp->src[n_IRQ];
1084 if (n_IRQ != -1 &&
1085 (s_IRQ == -1 ||
1086 IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
1087 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
1088 idx, n_IRQ);
1089 qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]);
1090 }
1091 break;
1092 default:
1093 break;
1094 }
1095 }
1096
1097 static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
1098 unsigned len)
1099 {
1100 openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
1101 }
1102
1103
1104 static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu)
1105 {
1106 IRQSource *src;
1107 int retval, irq;
1108
1109 DPRINTF("Lower OpenPIC INT output\n");
1110 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
1111
1112 irq = IRQ_get_next(opp, &dst->raised);
1113 DPRINTF("IACK: irq=%d\n", irq);
1114
1115 if (irq == -1) {
1116 /* No more interrupt pending */
1117 return opp->spve;
1118 }
1119
1120 src = &opp->src[irq];
1121 if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
1122 !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) {
1123 fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1124 __func__, irq, dst->ctpr, src->ivpr);
1125 openpic_update_irq(opp, irq);
1126 retval = opp->spve;
1127 } else {
1128 /* IRQ enter servicing state */
1129 IRQ_setbit(&dst->servicing, irq);
1130 retval = IVPR_VECTOR(opp, src->ivpr);
1131 }
1132
1133 if (!src->level) {
1134 /* edge-sensitive IRQ */
1135 src->ivpr &= ~IVPR_ACTIVITY_MASK;
1136 src->pending = 0;
1137 IRQ_resetbit(&dst->raised, irq);
1138 }
1139
1140 if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + OPENPIC_MAX_IPI))) {
1141 src->destmask &= ~(1 << cpu);
1142 if (src->destmask && !src->level) {
1143 /* trigger on CPUs that didn't know about it yet */
1144 openpic_set_irq(opp, irq, 1);
1145 openpic_set_irq(opp, irq, 0);
1146 /* if all CPUs knew about it, set active bit again */
1147 src->ivpr |= IVPR_ACTIVITY_MASK;
1148 }
1149 }
1150
1151 return retval;
1152 }
1153
1154 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
1155 int idx)
1156 {
1157 OpenPICState *opp = opaque;
1158 IRQDest *dst;
1159 uint32_t retval;
1160
1161 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr);
1162 retval = 0xFFFFFFFF;
1163
1164 if (idx < 0 || idx >= opp->nb_cpus) {
1165 return retval;
1166 }
1167
1168 if (addr & 0xF) {
1169 return retval;
1170 }
1171 dst = &opp->dst[idx];
1172 addr &= 0xFF0;
1173 switch (addr) {
1174 case 0x80: /* CTPR */
1175 retval = dst->ctpr;
1176 break;
1177 case 0x90: /* WHOAMI */
1178 retval = idx;
1179 break;
1180 case 0xA0: /* IACK */
1181 retval = openpic_iack(opp, dst, idx);
1182 break;
1183 case 0xB0: /* EOI */
1184 retval = 0;
1185 break;
1186 default:
1187 break;
1188 }
1189 DPRINTF("%s: => 0x%08x\n", __func__, retval);
1190
1191 return retval;
1192 }
1193
1194 static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
1195 {
1196 return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
1197 }
1198
1199 static const MemoryRegionOps openpic_glb_ops_le = {
1200 .write = openpic_gbl_write,
1201 .read = openpic_gbl_read,
1202 .endianness = DEVICE_LITTLE_ENDIAN,
1203 .impl = {
1204 .min_access_size = 4,
1205 .max_access_size = 4,
1206 },
1207 };
1208
1209 static const MemoryRegionOps openpic_glb_ops_be = {
1210 .write = openpic_gbl_write,
1211 .read = openpic_gbl_read,
1212 .endianness = DEVICE_BIG_ENDIAN,
1213 .impl = {
1214 .min_access_size = 4,
1215 .max_access_size = 4,
1216 },
1217 };
1218
1219 static const MemoryRegionOps openpic_tmr_ops_le = {
1220 .write = openpic_tmr_write,
1221 .read = openpic_tmr_read,
1222 .endianness = DEVICE_LITTLE_ENDIAN,
1223 .impl = {
1224 .min_access_size = 4,
1225 .max_access_size = 4,
1226 },
1227 };
1228
1229 static const MemoryRegionOps openpic_tmr_ops_be = {
1230 .write = openpic_tmr_write,
1231 .read = openpic_tmr_read,
1232 .endianness = DEVICE_BIG_ENDIAN,
1233 .impl = {
1234 .min_access_size = 4,
1235 .max_access_size = 4,
1236 },
1237 };
1238
1239 static const MemoryRegionOps openpic_cpu_ops_le = {
1240 .write = openpic_cpu_write,
1241 .read = openpic_cpu_read,
1242 .endianness = DEVICE_LITTLE_ENDIAN,
1243 .impl = {
1244 .min_access_size = 4,
1245 .max_access_size = 4,
1246 },
1247 };
1248
1249 static const MemoryRegionOps openpic_cpu_ops_be = {
1250 .write = openpic_cpu_write,
1251 .read = openpic_cpu_read,
1252 .endianness = DEVICE_BIG_ENDIAN,
1253 .impl = {
1254 .min_access_size = 4,
1255 .max_access_size = 4,
1256 },
1257 };
1258
1259 static const MemoryRegionOps openpic_src_ops_le = {
1260 .write = openpic_src_write,
1261 .read = openpic_src_read,
1262 .endianness = DEVICE_LITTLE_ENDIAN,
1263 .impl = {
1264 .min_access_size = 4,
1265 .max_access_size = 4,
1266 },
1267 };
1268
1269 static const MemoryRegionOps openpic_src_ops_be = {
1270 .write = openpic_src_write,
1271 .read = openpic_src_read,
1272 .endianness = DEVICE_BIG_ENDIAN,
1273 .impl = {
1274 .min_access_size = 4,
1275 .max_access_size = 4,
1276 },
1277 };
1278
1279 static const MemoryRegionOps openpic_msi_ops_be = {
1280 .read = openpic_msi_read,
1281 .write = openpic_msi_write,
1282 .endianness = DEVICE_BIG_ENDIAN,
1283 .impl = {
1284 .min_access_size = 4,
1285 .max_access_size = 4,
1286 },
1287 };
1288
1289 static const MemoryRegionOps openpic_summary_ops_be = {
1290 .read = openpic_summary_read,
1291 .write = openpic_summary_write,
1292 .endianness = DEVICE_BIG_ENDIAN,
1293 .impl = {
1294 .min_access_size = 4,
1295 .max_access_size = 4,
1296 },
1297 };
1298
1299 static void openpic_reset(DeviceState *d)
1300 {
1301 OpenPICState *opp = OPENPIC(d);
1302 int i;
1303
1304 opp->gcr = GCR_RESET;
1305 /* Initialise controller registers */
1306 opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
1307 ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) |
1308 (opp->vid << FRR_VID_SHIFT);
1309
1310 opp->pir = 0;
1311 opp->spve = -1 & opp->vector_mask;
1312 opp->tfrr = opp->tfrr_reset;
1313 /* Initialise IRQ sources */
1314 for (i = 0; i < opp->max_irq; i++) {
1315 opp->src[i].ivpr = opp->ivpr_reset;
1316 switch (opp->src[i].type) {
1317 case IRQ_TYPE_NORMAL:
1318 opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK);
1319 break;
1320
1321 case IRQ_TYPE_FSLINT:
1322 opp->src[i].ivpr |= IVPR_POLARITY_MASK;
1323 break;
1324
1325 case IRQ_TYPE_FSLSPECIAL:
1326 break;
1327 }
1328
1329 write_IRQreg_idr(opp, i, opp->idr_reset);
1330 }
1331 /* Initialise IRQ destinations */
1332 for (i = 0; i < opp->nb_cpus; i++) {
1333 opp->dst[i].ctpr = 15;
1334 opp->dst[i].raised.next = -1;
1335 opp->dst[i].raised.priority = 0;
1336 bitmap_clear(opp->dst[i].raised.queue, 0, IRQQUEUE_SIZE_BITS);
1337 opp->dst[i].servicing.next = -1;
1338 opp->dst[i].servicing.priority = 0;
1339 bitmap_clear(opp->dst[i].servicing.queue, 0, IRQQUEUE_SIZE_BITS);
1340 }
1341 /* Initialise timers */
1342 for (i = 0; i < OPENPIC_MAX_TMR; i++) {
1343 opp->timers[i].tccr = 0;
1344 opp->timers[i].tbcr = TBCR_CI;
1345 }
1346 /* Go out of RESET state */
1347 opp->gcr = 0;
1348 }
1349
1350 typedef struct MemReg {
1351 const char *name;
1352 MemoryRegionOps const *ops;
1353 hwaddr start_addr;
1354 ram_addr_t size;
1355 } MemReg;
1356
1357 static void fsl_common_init(OpenPICState *opp)
1358 {
1359 int i;
1360 int virq = OPENPIC_MAX_SRC;
1361
1362 opp->vid = VID_REVISION_1_2;
1363 opp->vir = VIR_GENERIC;
1364 opp->vector_mask = 0xFFFF;
1365 opp->tfrr_reset = 0;
1366 opp->ivpr_reset = IVPR_MASK_MASK;
1367 opp->idr_reset = 1 << 0;
1368 opp->max_irq = OPENPIC_MAX_IRQ;
1369
1370 opp->irq_ipi0 = virq;
1371 virq += OPENPIC_MAX_IPI;
1372 opp->irq_tim0 = virq;
1373 virq += OPENPIC_MAX_TMR;
1374
1375 assert(virq <= OPENPIC_MAX_IRQ);
1376
1377 opp->irq_msi = 224;
1378
1379 msi_nonbroken = true;
1380 for (i = 0; i < opp->fsl->max_ext; i++) {
1381 opp->src[i].level = false;
1382 }
1383
1384 /* Internal interrupts, including message and MSI */
1385 for (i = 16; i < OPENPIC_MAX_SRC; i++) {
1386 opp->src[i].type = IRQ_TYPE_FSLINT;
1387 opp->src[i].level = true;
1388 }
1389
1390 /* timers and IPIs */
1391 for (i = OPENPIC_MAX_SRC; i < virq; i++) {
1392 opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
1393 opp->src[i].level = false;
1394 }
1395 }
1396
1397 static void map_list(OpenPICState *opp, const MemReg *list, int *count)
1398 {
1399 while (list->name) {
1400 assert(*count < ARRAY_SIZE(opp->sub_io_mem));
1401
1402 memory_region_init_io(&opp->sub_io_mem[*count], OBJECT(opp), list->ops,
1403 opp, list->name, list->size);
1404
1405 memory_region_add_subregion(&opp->mem, list->start_addr,
1406 &opp->sub_io_mem[*count]);
1407
1408 (*count)++;
1409 list++;
1410 }
1411 }
1412
1413 static const VMStateDescription vmstate_openpic_irq_queue = {
1414 .name = "openpic_irq_queue",
1415 .version_id = 0,
1416 .minimum_version_id = 0,
1417 .fields = (VMStateField[]) {
1418 VMSTATE_BITMAP(queue, IRQQueue, 0, queue_size),
1419 VMSTATE_INT32(next, IRQQueue),
1420 VMSTATE_INT32(priority, IRQQueue),
1421 VMSTATE_END_OF_LIST()
1422 }
1423 };
1424
1425 static const VMStateDescription vmstate_openpic_irqdest = {
1426 .name = "openpic_irqdest",
1427 .version_id = 0,
1428 .minimum_version_id = 0,
1429 .fields = (VMStateField[]) {
1430 VMSTATE_INT32(ctpr, IRQDest),
1431 VMSTATE_STRUCT(raised, IRQDest, 0, vmstate_openpic_irq_queue,
1432 IRQQueue),
1433 VMSTATE_STRUCT(servicing, IRQDest, 0, vmstate_openpic_irq_queue,
1434 IRQQueue),
1435 VMSTATE_UINT32_ARRAY(outputs_active, IRQDest, OPENPIC_OUTPUT_NB),
1436 VMSTATE_END_OF_LIST()
1437 }
1438 };
1439
1440 static const VMStateDescription vmstate_openpic_irqsource = {
1441 .name = "openpic_irqsource",
1442 .version_id = 0,
1443 .minimum_version_id = 0,
1444 .fields = (VMStateField[]) {
1445 VMSTATE_UINT32(ivpr, IRQSource),
1446 VMSTATE_UINT32(idr, IRQSource),
1447 VMSTATE_UINT32(destmask, IRQSource),
1448 VMSTATE_INT32(last_cpu, IRQSource),
1449 VMSTATE_INT32(pending, IRQSource),
1450 VMSTATE_END_OF_LIST()
1451 }
1452 };
1453
1454 static const VMStateDescription vmstate_openpic_timer = {
1455 .name = "openpic_timer",
1456 .version_id = 0,
1457 .minimum_version_id = 0,
1458 .fields = (VMStateField[]) {
1459 VMSTATE_UINT32(tccr, OpenPICTimer),
1460 VMSTATE_UINT32(tbcr, OpenPICTimer),
1461 VMSTATE_END_OF_LIST()
1462 }
1463 };
1464
1465 static const VMStateDescription vmstate_openpic_msi = {
1466 .name = "openpic_msi",
1467 .version_id = 0,
1468 .minimum_version_id = 0,
1469 .fields = (VMStateField[]) {
1470 VMSTATE_UINT32(msir, OpenPICMSI),
1471 VMSTATE_END_OF_LIST()
1472 }
1473 };
1474
1475 static int openpic_post_load(void *opaque, int version_id)
1476 {
1477 OpenPICState *opp = (OpenPICState *)opaque;
1478 int i;
1479
1480 /* Update internal ivpr and idr variables */
1481 for (i = 0; i < opp->max_irq; i++) {
1482 write_IRQreg_idr(opp, i, opp->src[i].idr);
1483 write_IRQreg_ivpr(opp, i, opp->src[i].ivpr);
1484 }
1485
1486 return 0;
1487 }
1488
1489 static const VMStateDescription vmstate_openpic = {
1490 .name = "openpic",
1491 .version_id = 3,
1492 .minimum_version_id = 3,
1493 .post_load = openpic_post_load,
1494 .fields = (VMStateField[]) {
1495 VMSTATE_UINT32(gcr, OpenPICState),
1496 VMSTATE_UINT32(vir, OpenPICState),
1497 VMSTATE_UINT32(pir, OpenPICState),
1498 VMSTATE_UINT32(spve, OpenPICState),
1499 VMSTATE_UINT32(tfrr, OpenPICState),
1500 VMSTATE_UINT32(max_irq, OpenPICState),
1501 VMSTATE_STRUCT_VARRAY_UINT32(src, OpenPICState, max_irq, 0,
1502 vmstate_openpic_irqsource, IRQSource),
1503 VMSTATE_UINT32_EQUAL(nb_cpus, OpenPICState),
1504 VMSTATE_STRUCT_VARRAY_UINT32(dst, OpenPICState, nb_cpus, 0,
1505 vmstate_openpic_irqdest, IRQDest),
1506 VMSTATE_STRUCT_ARRAY(timers, OpenPICState, OPENPIC_MAX_TMR, 0,
1507 vmstate_openpic_timer, OpenPICTimer),
1508 VMSTATE_STRUCT_ARRAY(msi, OpenPICState, MAX_MSI, 0,
1509 vmstate_openpic_msi, OpenPICMSI),
1510 VMSTATE_UINT32(irq_ipi0, OpenPICState),
1511 VMSTATE_UINT32(irq_tim0, OpenPICState),
1512 VMSTATE_UINT32(irq_msi, OpenPICState),
1513 VMSTATE_END_OF_LIST()
1514 }
1515 };
1516
1517 static void openpic_init(Object *obj)
1518 {
1519 OpenPICState *opp = OPENPIC(obj);
1520
1521 memory_region_init(&opp->mem, obj, "openpic", 0x40000);
1522 }
1523
1524 static void openpic_realize(DeviceState *dev, Error **errp)
1525 {
1526 SysBusDevice *d = SYS_BUS_DEVICE(dev);
1527 OpenPICState *opp = OPENPIC(dev);
1528 int i, j;
1529 int list_count = 0;
1530 static const MemReg list_le[] = {
1531 {"glb", &openpic_glb_ops_le,
1532 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1533 {"tmr", &openpic_tmr_ops_le,
1534 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1535 {"src", &openpic_src_ops_le,
1536 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1537 {"cpu", &openpic_cpu_ops_le,
1538 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1539 {NULL}
1540 };
1541 static const MemReg list_be[] = {
1542 {"glb", &openpic_glb_ops_be,
1543 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1544 {"tmr", &openpic_tmr_ops_be,
1545 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1546 {"src", &openpic_src_ops_be,
1547 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1548 {"cpu", &openpic_cpu_ops_be,
1549 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1550 {NULL}
1551 };
1552 static const MemReg list_fsl[] = {
1553 {"msi", &openpic_msi_ops_be,
1554 OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
1555 {"summary", &openpic_summary_ops_be,
1556 OPENPIC_SUMMARY_REG_START, OPENPIC_SUMMARY_REG_SIZE},
1557 {NULL}
1558 };
1559
1560 if (opp->nb_cpus > MAX_CPU) {
1561 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
1562 TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
1563 (uint64_t)0, (uint64_t)MAX_CPU);
1564 return;
1565 }
1566
1567 switch (opp->model) {
1568 case OPENPIC_MODEL_FSL_MPIC_20:
1569 default:
1570 opp->fsl = &fsl_mpic_20;
1571 opp->brr1 = 0x00400200;
1572 opp->flags |= OPENPIC_FLAG_IDR_CRIT;
1573 opp->nb_irqs = 80;
1574 opp->mpic_mode_mask = GCR_MODE_MIXED;
1575
1576 fsl_common_init(opp);
1577 map_list(opp, list_be, &list_count);
1578 map_list(opp, list_fsl, &list_count);
1579
1580 break;
1581
1582 case OPENPIC_MODEL_FSL_MPIC_42:
1583 opp->fsl = &fsl_mpic_42;
1584 opp->brr1 = 0x00400402;
1585 opp->flags |= OPENPIC_FLAG_ILR;
1586 opp->nb_irqs = 196;
1587 opp->mpic_mode_mask = GCR_MODE_PROXY;
1588
1589 fsl_common_init(opp);
1590 map_list(opp, list_be, &list_count);
1591 map_list(opp, list_fsl, &list_count);
1592
1593 break;
1594
1595 case OPENPIC_MODEL_RAVEN:
1596 opp->nb_irqs = RAVEN_MAX_EXT;
1597 opp->vid = VID_REVISION_1_3;
1598 opp->vir = VIR_GENERIC;
1599 opp->vector_mask = 0xFF;
1600 opp->tfrr_reset = 4160000;
1601 opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK;
1602 opp->idr_reset = 0;
1603 opp->max_irq = RAVEN_MAX_IRQ;
1604 opp->irq_ipi0 = RAVEN_IPI_IRQ;
1605 opp->irq_tim0 = RAVEN_TMR_IRQ;
1606 opp->brr1 = -1;
1607 opp->mpic_mode_mask = GCR_MODE_MIXED;
1608
1609 if (opp->nb_cpus != 1) {
1610 error_setg(errp, "Only UP supported today");
1611 return;
1612 }
1613
1614 map_list(opp, list_le, &list_count);
1615 break;
1616 }
1617
1618 for (i = 0; i < opp->nb_cpus; i++) {
1619 opp->dst[i].irqs = g_new0(qemu_irq, OPENPIC_OUTPUT_NB);
1620 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
1621 sysbus_init_irq(d, &opp->dst[i].irqs[j]);
1622 }
1623
1624 opp->dst[i].raised.queue_size = IRQQUEUE_SIZE_BITS;
1625 opp->dst[i].raised.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
1626 opp->dst[i].servicing.queue_size = IRQQUEUE_SIZE_BITS;
1627 opp->dst[i].servicing.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
1628 }
1629
1630 sysbus_init_mmio(d, &opp->mem);
1631 qdev_init_gpio_in(dev, openpic_set_irq, opp->max_irq);
1632 }
1633
1634 static Property openpic_properties[] = {
1635 DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20),
1636 DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1),
1637 DEFINE_PROP_END_OF_LIST(),
1638 };
1639
1640 static void openpic_class_init(ObjectClass *oc, void *data)
1641 {
1642 DeviceClass *dc = DEVICE_CLASS(oc);
1643
1644 dc->realize = openpic_realize;
1645 dc->props = openpic_properties;
1646 dc->reset = openpic_reset;
1647 dc->vmsd = &vmstate_openpic;
1648 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
1649 }
1650
1651 static const TypeInfo openpic_info = {
1652 .name = TYPE_OPENPIC,
1653 .parent = TYPE_SYS_BUS_DEVICE,
1654 .instance_size = sizeof(OpenPICState),
1655 .instance_init = openpic_init,
1656 .class_init = openpic_class_init,
1657 };
1658
1659 static void openpic_register_types(void)
1660 {
1661 type_register_static(&openpic_info);
1662 }
1663
1664 type_init(openpic_register_types)
AR7 emulation for QEMU