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include/qemu/osdep.h: Don't include qapi/error.h
[qemu/ar7.git] / hw / display / tc6393xb.c
blobda3ceceb0a83b5b825b8e0289930163ee51ce0d4
1 /*
2 * Toshiba TC6393XB I/O Controller.
3 * Found in Sharp Zaurus SL-6000 (tosa) or some
4 * Toshiba e-Series PDAs.
5 *
6 * Most features are currently unsupported!!!
7 *
8 * This code is licensed under the GNU GPL v2.
9 *
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
12 */
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/hw.h"
16 #include "hw/devices.h"
17 #include "hw/block/flash.h"
18 #include "ui/console.h"
19 #include "ui/pixel_ops.h"
20 #include "sysemu/block-backend.h"
21 #include "sysemu/blockdev.h"
22
23 #define IRQ_TC6393_NAND 0
24 #define IRQ_TC6393_MMC 1
25 #define IRQ_TC6393_OHCI 2
26 #define IRQ_TC6393_SERIAL 3
27 #define IRQ_TC6393_FB 4
28
29 #define TC6393XB_NR_IRQS 8
30
31 #define TC6393XB_GPIOS 16
32
33 #define SCR_REVID 0x08 /* b Revision ID */
34 #define SCR_ISR 0x50 /* b Interrupt Status */
35 #define SCR_IMR 0x52 /* b Interrupt Mask */
36 #define SCR_IRR 0x54 /* b Interrupt Routing */
37 #define SCR_GPER 0x60 /* w GP Enable */
38 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
39 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
40 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
41 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
42 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
43 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
44 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
45 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
46 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
47 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
48 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
49 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
50 #define SCR_CCR 0x98 /* w Clock Control */
51 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
52 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
53 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
54 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
55 #define SCR_FER 0xe0 /* b Function Enable */
56 #define SCR_MCR 0xe4 /* w Mode Control */
57 #define SCR_CONFIG 0xfc /* b Configuration Control */
58 #define SCR_DEBUG 0xff /* b Debug */
59
60 #define NAND_CFG_COMMAND 0x04 /* w Command */
61 #define NAND_CFG_BASE 0x10 /* l Control Base Address */
62 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
63 #define NAND_CFG_INTE 0x48 /* b Int Enable */
64 #define NAND_CFG_EC 0x4a /* b Event Control */
65 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
66 #define NAND_CFG_ECCC 0x5b /* b ECC Control */
67 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
68 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
69 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
70 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
71
72 #define NAND_DATA 0x00 /* l Data */
73 #define NAND_MODE 0x04 /* b Mode */
74 #define NAND_STATUS 0x05 /* b Status */
75 #define NAND_ISR 0x06 /* b Interrupt Status */
76 #define NAND_IMR 0x07 /* b Interrupt Mask */
77
78 #define NAND_MODE_WP 0x80
79 #define NAND_MODE_CE 0x10
80 #define NAND_MODE_ALE 0x02
81 #define NAND_MODE_CLE 0x01
82 #define NAND_MODE_ECC_MASK 0x60
83 #define NAND_MODE_ECC_EN 0x20
84 #define NAND_MODE_ECC_READ 0x40
85 #define NAND_MODE_ECC_RST 0x60
86
87 struct TC6393xbState {
88 MemoryRegion iomem;
89 qemu_irq irq;
90 qemu_irq *sub_irqs;
91 struct {
92 uint8_t ISR;
93 uint8_t IMR;
94 uint8_t IRR;
95 uint16_t GPER;
96 uint8_t GPI_SR[3];
97 uint8_t GPI_IMR[3];
98 uint8_t GPI_EDER[3];
99 uint8_t GPI_LIR[3];
100 uint8_t GP_IARCR[3];
101 uint8_t GP_IARLCR[3];
102 uint8_t GPI_BCR[3];
103 uint16_t GPA_IARCR;
104 uint16_t GPA_IARLCR;
105 uint16_t CCR;
106 uint16_t PLL2CR;
107 uint32_t PLL1CR;
108 uint8_t DIARCR;
109 uint8_t DBOCR;
110 uint8_t FER;
111 uint16_t MCR;
112 uint8_t CONFIG;
113 uint8_t DEBUG;
114 } scr;
115 uint32_t gpio_dir;
116 uint32_t gpio_level;
117 uint32_t prev_level;
118 qemu_irq handler[TC6393XB_GPIOS];
119 qemu_irq *gpio_in;
120
121 struct {
122 uint8_t mode;
123 uint8_t isr;
124 uint8_t imr;
125 } nand;
126 int nand_enable;
127 uint32_t nand_phys;
128 DeviceState *flash;
129 ECCState ecc;
130
131 QemuConsole *con;
132 MemoryRegion vram;
133 uint16_t *vram_ptr;
134 uint32_t scr_width, scr_height; /* in pixels */
135 qemu_irq l3v;
136 unsigned blank : 1,
137 blanked : 1;
138 };
139
140 qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
141 {
142 return s->gpio_in;
143 }
144
145 static void tc6393xb_gpio_set(void *opaque, int line, int level)
146 {
147 // TC6393xbState *s = opaque;
148
149 if (line > TC6393XB_GPIOS) {
150 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
151 return;
152 }
153
154 // FIXME: how does the chip reflect the GPIO input level change?
155 }
156
157 void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
158 qemu_irq handler)
159 {
160 if (line >= TC6393XB_GPIOS) {
161 fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
162 return;
163 }
164
165 s->handler[line] = handler;
166 }
167
168 static void tc6393xb_gpio_handler_update(TC6393xbState *s)
169 {
170 uint32_t level, diff;
171 int bit;
172
173 level = s->gpio_level & s->gpio_dir;
174
175 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
176 bit = ctz32(diff);
177 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
178 }
179
180 s->prev_level = level;
181 }
182
183 qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
184 {
185 return s->l3v;
186 }
187
188 static void tc6393xb_l3v(void *opaque, int line, int level)
189 {
190 TC6393xbState *s = opaque;
191 s->blank = !level;
192 fprintf(stderr, "L3V: %d\n", level);
193 }
194
195 static void tc6393xb_sub_irq(void *opaque, int line, int level) {
196 TC6393xbState *s = opaque;
197 uint8_t isr = s->scr.ISR;
198 if (level)
199 isr |= 1 << line;
200 else
201 isr &= ~(1 << line);
202 s->scr.ISR = isr;
203 qemu_set_irq(s->irq, isr & s->scr.IMR);
204 }
205
206 #define SCR_REG_B(N) \
207 case SCR_ ##N: return s->scr.N
208 #define SCR_REG_W(N) \
209 case SCR_ ##N: return s->scr.N; \
210 case SCR_ ##N + 1: return s->scr.N >> 8;
211 #define SCR_REG_L(N) \
212 case SCR_ ##N: return s->scr.N; \
213 case SCR_ ##N + 1: return s->scr.N >> 8; \
214 case SCR_ ##N + 2: return s->scr.N >> 16; \
215 case SCR_ ##N + 3: return s->scr.N >> 24;
216 #define SCR_REG_A(N) \
217 case SCR_ ##N(0): return s->scr.N[0]; \
218 case SCR_ ##N(1): return s->scr.N[1]; \
219 case SCR_ ##N(2): return s->scr.N[2]
220
221 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
222 {
223 switch (addr) {
224 case SCR_REVID:
225 return 3;
226 case SCR_REVID+1:
227 return 0;
228 SCR_REG_B(ISR);
229 SCR_REG_B(IMR);
230 SCR_REG_B(IRR);
231 SCR_REG_W(GPER);
232 SCR_REG_A(GPI_SR);
233 SCR_REG_A(GPI_IMR);
234 SCR_REG_A(GPI_EDER);
235 SCR_REG_A(GPI_LIR);
236 case SCR_GPO_DSR(0):
237 case SCR_GPO_DSR(1):
238 case SCR_GPO_DSR(2):
239 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
240 case SCR_GPO_DOECR(0):
241 case SCR_GPO_DOECR(1):
242 case SCR_GPO_DOECR(2):
243 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
244 SCR_REG_A(GP_IARCR);
245 SCR_REG_A(GP_IARLCR);
246 SCR_REG_A(GPI_BCR);
247 SCR_REG_W(GPA_IARCR);
248 SCR_REG_W(GPA_IARLCR);
249 SCR_REG_W(CCR);
250 SCR_REG_W(PLL2CR);
251 SCR_REG_L(PLL1CR);
252 SCR_REG_B(DIARCR);
253 SCR_REG_B(DBOCR);
254 SCR_REG_B(FER);
255 SCR_REG_W(MCR);
256 SCR_REG_B(CONFIG);
257 SCR_REG_B(DEBUG);
258 }
259 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
260 return 0;
261 }
262 #undef SCR_REG_B
263 #undef SCR_REG_W
264 #undef SCR_REG_L
265 #undef SCR_REG_A
266
267 #define SCR_REG_B(N) \
268 case SCR_ ##N: s->scr.N = value; return;
269 #define SCR_REG_W(N) \
270 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
271 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
272 #define SCR_REG_L(N) \
273 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
274 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \
275 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \
276 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
277 #define SCR_REG_A(N) \
278 case SCR_ ##N(0): s->scr.N[0] = value; return; \
279 case SCR_ ##N(1): s->scr.N[1] = value; return; \
280 case SCR_ ##N(2): s->scr.N[2] = value; return
281
282 static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
283 {
284 switch (addr) {
285 SCR_REG_B(ISR);
286 SCR_REG_B(IMR);
287 SCR_REG_B(IRR);
288 SCR_REG_W(GPER);
289 SCR_REG_A(GPI_SR);
290 SCR_REG_A(GPI_IMR);
291 SCR_REG_A(GPI_EDER);
292 SCR_REG_A(GPI_LIR);
293 case SCR_GPO_DSR(0):
294 case SCR_GPO_DSR(1):
295 case SCR_GPO_DSR(2):
296 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
297 tc6393xb_gpio_handler_update(s);
298 return;
299 case SCR_GPO_DOECR(0):
300 case SCR_GPO_DOECR(1):
301 case SCR_GPO_DOECR(2):
302 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
303 tc6393xb_gpio_handler_update(s);
304 return;
305 SCR_REG_A(GP_IARCR);
306 SCR_REG_A(GP_IARLCR);
307 SCR_REG_A(GPI_BCR);
308 SCR_REG_W(GPA_IARCR);
309 SCR_REG_W(GPA_IARLCR);
310 SCR_REG_W(CCR);
311 SCR_REG_W(PLL2CR);
312 SCR_REG_L(PLL1CR);
313 SCR_REG_B(DIARCR);
314 SCR_REG_B(DBOCR);
315 SCR_REG_B(FER);
316 SCR_REG_W(MCR);
317 SCR_REG_B(CONFIG);
318 SCR_REG_B(DEBUG);
319 }
320 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
321 (uint32_t) addr, value & 0xff);
322 }
323 #undef SCR_REG_B
324 #undef SCR_REG_W
325 #undef SCR_REG_L
326 #undef SCR_REG_A
327
328 static void tc6393xb_nand_irq(TC6393xbState *s) {
329 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
330 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
331 }
332
333 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
334 switch (addr) {
335 case NAND_CFG_COMMAND:
336 return s->nand_enable ? 2 : 0;
337 case NAND_CFG_BASE:
338 case NAND_CFG_BASE + 1:
339 case NAND_CFG_BASE + 2:
340 case NAND_CFG_BASE + 3:
341 return s->nand_phys >> (addr - NAND_CFG_BASE);
342 }
343 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
344 return 0;
345 }
346 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
347 switch (addr) {
348 case NAND_CFG_COMMAND:
349 s->nand_enable = (value & 0x2);
350 return;
351 case NAND_CFG_BASE:
352 case NAND_CFG_BASE + 1:
353 case NAND_CFG_BASE + 2:
354 case NAND_CFG_BASE + 3:
355 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
356 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
357 return;
358 }
359 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
360 (uint32_t) addr, value & 0xff);
361 }
362
363 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
364 switch (addr) {
365 case NAND_DATA + 0:
366 case NAND_DATA + 1:
367 case NAND_DATA + 2:
368 case NAND_DATA + 3:
369 return nand_getio(s->flash);
370 case NAND_MODE:
371 return s->nand.mode;
372 case NAND_STATUS:
373 return 0x14;
374 case NAND_ISR:
375 return s->nand.isr;
376 case NAND_IMR:
377 return s->nand.imr;
378 }
379 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
380 return 0;
381 }
382 static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
383 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
384 // (uint32_t) addr, value & 0xff);
385 switch (addr) {
386 case NAND_DATA + 0:
387 case NAND_DATA + 1:
388 case NAND_DATA + 2:
389 case NAND_DATA + 3:
390 nand_setio(s->flash, value);
391 s->nand.isr |= 1;
392 tc6393xb_nand_irq(s);
393 return;
394 case NAND_MODE:
395 s->nand.mode = value;
396 nand_setpins(s->flash,
397 value & NAND_MODE_CLE,
398 value & NAND_MODE_ALE,
399 !(value & NAND_MODE_CE),
400 value & NAND_MODE_WP,
401 0); // FIXME: gnd
402 switch (value & NAND_MODE_ECC_MASK) {
403 case NAND_MODE_ECC_RST:
404 ecc_reset(&s->ecc);
405 break;
406 case NAND_MODE_ECC_READ:
407 // FIXME
408 break;
409 case NAND_MODE_ECC_EN:
410 ecc_reset(&s->ecc);
411 }
412 return;
413 case NAND_ISR:
414 s->nand.isr = value;
415 tc6393xb_nand_irq(s);
416 return;
417 case NAND_IMR:
418 s->nand.imr = value;
419 tc6393xb_nand_irq(s);
420 return;
421 }
422 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
423 (uint32_t) addr, value & 0xff);
424 }
425
426 #define BITS 8
427 #include "tc6393xb_template.h"
428 #define BITS 15
429 #include "tc6393xb_template.h"
430 #define BITS 16
431 #include "tc6393xb_template.h"
432 #define BITS 24
433 #include "tc6393xb_template.h"
434 #define BITS 32
435 #include "tc6393xb_template.h"
436
437 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
438 {
439 DisplaySurface *surface = qemu_console_surface(s->con);
440
441 switch (surface_bits_per_pixel(surface)) {
442 case 8:
443 tc6393xb_draw_graphic8(s);
444 break;
445 case 15:
446 tc6393xb_draw_graphic15(s);
447 break;
448 case 16:
449 tc6393xb_draw_graphic16(s);
450 break;
451 case 24:
452 tc6393xb_draw_graphic24(s);
453 break;
454 case 32:
455 tc6393xb_draw_graphic32(s);
456 break;
457 default:
458 printf("tc6393xb: unknown depth %d\n",
459 surface_bits_per_pixel(surface));
460 return;
461 }
462
463 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
464 }
465
466 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
467 {
468 DisplaySurface *surface = qemu_console_surface(s->con);
469 int i, w;
470 uint8_t *d;
471
472 if (!full_update)
473 return;
474
475 w = s->scr_width * surface_bytes_per_pixel(surface);
476 d = surface_data(surface);
477 for(i = 0; i < s->scr_height; i++) {
478 memset(d, 0, w);
479 d += surface_stride(surface);
480 }
481
482 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
483 }
484
485 static void tc6393xb_update_display(void *opaque)
486 {
487 TC6393xbState *s = opaque;
488 DisplaySurface *surface = qemu_console_surface(s->con);
489 int full_update;
490
491 if (s->scr_width == 0 || s->scr_height == 0)
492 return;
493
494 full_update = 0;
495 if (s->blanked != s->blank) {
496 s->blanked = s->blank;
497 full_update = 1;
498 }
499 if (s->scr_width != surface_width(surface) ||
500 s->scr_height != surface_height(surface)) {
501 qemu_console_resize(s->con, s->scr_width, s->scr_height);
502 full_update = 1;
503 }
504 if (s->blanked)
505 tc6393xb_draw_blank(s, full_update);
506 else
507 tc6393xb_draw_graphic(s, full_update);
508 }
509
510
511 static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
512 unsigned size)
513 {
514 TC6393xbState *s = opaque;
515
516 switch (addr >> 8) {
517 case 0:
518 return tc6393xb_scr_readb(s, addr & 0xff);
519 case 1:
520 return tc6393xb_nand_cfg_readb(s, addr & 0xff);
521 };
522
523 if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
524 // return tc6393xb_nand_readb(s, addr & 0xff);
525 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
526 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
527 return d;
528 }
529
530 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
531 return 0;
532 }
533
534 static void tc6393xb_writeb(void *opaque, hwaddr addr,
535 uint64_t value, unsigned size) {
536 TC6393xbState *s = opaque;
537
538 switch (addr >> 8) {
539 case 0:
540 tc6393xb_scr_writeb(s, addr & 0xff, value);
541 return;
542 case 1:
543 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
544 return;
545 };
546
547 if ((addr &~0xff) == s->nand_phys && s->nand_enable)
548 tc6393xb_nand_writeb(s, addr & 0xff, value);
549 else
550 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
551 (uint32_t) addr, (int)value & 0xff);
552 }
553
554 static const GraphicHwOps tc6393xb_gfx_ops = {
555 .gfx_update = tc6393xb_update_display,
556 };
557
558 TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
559 {
560 TC6393xbState *s;
561 DriveInfo *nand;
562 static const MemoryRegionOps tc6393xb_ops = {
563 .read = tc6393xb_readb,
564 .write = tc6393xb_writeb,
565 .endianness = DEVICE_NATIVE_ENDIAN,
566 .impl = {
567 .min_access_size = 1,
568 .max_access_size = 1,
569 },
570 };
571
572 s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
573 s->irq = irq;
574 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
575
576 s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0);
577 s->blanked = 1;
578
579 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
580
581 nand = drive_get(IF_MTD, 0, 0);
582 s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
583 NAND_MFR_TOSHIBA, 0x76);
584
585 memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
586 memory_region_add_subregion(sysmem, base, &s->iomem);
587
588 memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000,
589 &error_fatal);
590 vmstate_register_ram_global(&s->vram);
591 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
592 memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
593 s->scr_width = 480;
594 s->scr_height = 640;
595 s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s);
596
597 return s;
598 }
AR7 emulation for QEMU