4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
28 #include "hw/char/serial.h"
29 #include "ui/console.h"
30 #include "hw/devices.h"
31 #include "hw/sysbus.h"
32 #include "qemu/range.h"
33 #include "ui/pixel_ops.h"
34 #include "exec/address-spaces.h"
38 * - Minimum implementation for Linux console : mmio regs and CRT layer.
39 * - 2D grapihcs acceleration partially supported : only fill rectangle.
43 * - Touch panel support
46 * - More 2D graphics engine support
47 * - Performance tuning
51 //#define DEBUG_BITBLT
54 #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
56 #define SM501_DPRINTF(fmt, ...) do {} while(0)
60 #define MMIO_BASE_OFFSET 0x3e00000
62 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
64 /* System Configuration area */
65 /* System config base */
66 #define SM501_SYS_CONFIG (0x000000)
69 #define SM501_SYSTEM_CONTROL (0x000000)
71 #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
72 #define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
73 #define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
75 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
76 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
77 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
78 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
79 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
81 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
82 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
83 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
84 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
86 /* miscellaneous control */
88 #define SM501_MISC_CONTROL (0x000004)
90 #define SM501_MISC_BUS_SH (0x0)
91 #define SM501_MISC_BUS_PCI (0x1)
92 #define SM501_MISC_BUS_XSCALE (0x2)
93 #define SM501_MISC_BUS_NEC (0x6)
94 #define SM501_MISC_BUS_MASK (0x7)
96 #define SM501_MISC_VR_62MB (1<<3)
97 #define SM501_MISC_CDR_RESET (1<<7)
98 #define SM501_MISC_USB_LB (1<<8)
99 #define SM501_MISC_USB_SLAVE (1<<9)
100 #define SM501_MISC_BL_1 (1<<10)
101 #define SM501_MISC_MC (1<<11)
102 #define SM501_MISC_DAC_POWER (1<<12)
103 #define SM501_MISC_IRQ_INVERT (1<<16)
104 #define SM501_MISC_SH (1<<17)
106 #define SM501_MISC_HOLD_EMPTY (0<<18)
107 #define SM501_MISC_HOLD_8 (1<<18)
108 #define SM501_MISC_HOLD_16 (2<<18)
109 #define SM501_MISC_HOLD_24 (3<<18)
110 #define SM501_MISC_HOLD_32 (4<<18)
111 #define SM501_MISC_HOLD_MASK (7<<18)
113 #define SM501_MISC_FREQ_12 (1<<24)
114 #define SM501_MISC_PNL_24BIT (1<<25)
115 #define SM501_MISC_8051_LE (1<<26)
119 #define SM501_GPIO31_0_CONTROL (0x000008)
120 #define SM501_GPIO63_32_CONTROL (0x00000C)
121 #define SM501_DRAM_CONTROL (0x000010)
124 #define SM501_ARBTRTN_CONTROL (0x000014)
127 #define SM501_COMMAND_LIST_STATUS (0x000024)
129 /* interrupt debug */
130 #define SM501_RAW_IRQ_STATUS (0x000028)
131 #define SM501_RAW_IRQ_CLEAR (0x000028)
132 #define SM501_IRQ_STATUS (0x00002C)
133 #define SM501_IRQ_MASK (0x000030)
134 #define SM501_DEBUG_CONTROL (0x000034)
136 /* power management */
137 #define SM501_POWERMODE_P2X_SRC (1<<29)
138 #define SM501_POWERMODE_V2X_SRC (1<<20)
139 #define SM501_POWERMODE_M_SRC (1<<12)
140 #define SM501_POWERMODE_M1_SRC (1<<4)
142 #define SM501_CURRENT_GATE (0x000038)
143 #define SM501_CURRENT_CLOCK (0x00003C)
144 #define SM501_POWER_MODE_0_GATE (0x000040)
145 #define SM501_POWER_MODE_0_CLOCK (0x000044)
146 #define SM501_POWER_MODE_1_GATE (0x000048)
147 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
148 #define SM501_SLEEP_MODE_GATE (0x000050)
149 #define SM501_POWER_MODE_CONTROL (0x000054)
151 /* power gates for units within the 501 */
152 #define SM501_GATE_HOST (0)
153 #define SM501_GATE_MEMORY (1)
154 #define SM501_GATE_DISPLAY (2)
155 #define SM501_GATE_2D_ENGINE (3)
156 #define SM501_GATE_CSC (4)
157 #define SM501_GATE_ZVPORT (5)
158 #define SM501_GATE_GPIO (6)
159 #define SM501_GATE_UART0 (7)
160 #define SM501_GATE_UART1 (8)
161 #define SM501_GATE_SSP (10)
162 #define SM501_GATE_USB_HOST (11)
163 #define SM501_GATE_USB_GADGET (12)
164 #define SM501_GATE_UCONTROLLER (17)
165 #define SM501_GATE_AC97 (18)
168 #define SM501_CLOCK_P2XCLK (24)
170 #define SM501_CLOCK_V2XCLK (16)
172 #define SM501_CLOCK_MCLK (8)
173 /* SDRAM controller clock */
174 #define SM501_CLOCK_M1XCLK (0)
177 #define SM501_PCI_MASTER_BASE (0x000058)
178 #define SM501_ENDIAN_CONTROL (0x00005C)
179 #define SM501_DEVICEID (0x000060)
182 #define SM501_DEVICEID_SM501 (0x05010000)
183 #define SM501_DEVICEID_IDMASK (0xffff0000)
184 #define SM501_DEVICEID_REVMASK (0x000000ff)
186 #define SM501_PLLCLOCK_COUNT (0x000064)
187 #define SM501_MISC_TIMING (0x000068)
188 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
190 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
193 #define SM501_GPIO (0x010000)
194 #define SM501_GPIO_DATA_LOW (0x00)
195 #define SM501_GPIO_DATA_HIGH (0x04)
196 #define SM501_GPIO_DDR_LOW (0x08)
197 #define SM501_GPIO_DDR_HIGH (0x0C)
198 #define SM501_GPIO_IRQ_SETUP (0x10)
199 #define SM501_GPIO_IRQ_STATUS (0x14)
200 #define SM501_GPIO_IRQ_RESET (0x14)
202 /* I2C controller base */
203 #define SM501_I2C (0x010040)
204 #define SM501_I2C_BYTE_COUNT (0x00)
205 #define SM501_I2C_CONTROL (0x01)
206 #define SM501_I2C_STATUS (0x02)
207 #define SM501_I2C_RESET (0x02)
208 #define SM501_I2C_SLAVE_ADDRESS (0x03)
209 #define SM501_I2C_DATA (0x04)
212 #define SM501_SSP (0x020000)
215 #define SM501_UART0 (0x030000)
218 #define SM501_UART1 (0x030020)
220 /* USB host port base */
221 #define SM501_USB_HOST (0x040000)
223 /* USB slave/gadget base */
224 #define SM501_USB_GADGET (0x060000)
226 /* USB slave/gadget data port base */
227 #define SM501_USB_GADGET_DATA (0x070000)
229 /* Display controller/video engine base */
230 #define SM501_DC (0x080000)
232 /* common defines for the SM501 address registers */
233 #define SM501_ADDR_FLIP (1<<31)
234 #define SM501_ADDR_EXT (1<<27)
235 #define SM501_ADDR_CS1 (1<<26)
236 #define SM501_ADDR_MASK (0x3f << 26)
238 #define SM501_FIFO_MASK (0x3 << 16)
239 #define SM501_FIFO_1 (0x0 << 16)
240 #define SM501_FIFO_3 (0x1 << 16)
241 #define SM501_FIFO_7 (0x2 << 16)
242 #define SM501_FIFO_11 (0x3 << 16)
244 /* common registers for panel and the crt */
245 #define SM501_OFF_DC_H_TOT (0x000)
246 #define SM501_OFF_DC_V_TOT (0x008)
247 #define SM501_OFF_DC_H_SYNC (0x004)
248 #define SM501_OFF_DC_V_SYNC (0x00C)
250 #define SM501_DC_PANEL_CONTROL (0x000)
252 #define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
253 #define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
254 #define SM501_DC_PANEL_CONTROL_DATA (1<<25)
255 #define SM501_DC_PANEL_CONTROL_VDD (1<<24)
256 #define SM501_DC_PANEL_CONTROL_DP (1<<23)
258 #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
259 #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
260 #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
262 #define SM501_DC_PANEL_CONTROL_DE (1<<20)
264 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
265 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
266 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
268 #define SM501_DC_PANEL_CONTROL_CP (1<<14)
269 #define SM501_DC_PANEL_CONTROL_VSP (1<<13)
270 #define SM501_DC_PANEL_CONTROL_HSP (1<<12)
271 #define SM501_DC_PANEL_CONTROL_CK (1<<9)
272 #define SM501_DC_PANEL_CONTROL_TE (1<<8)
273 #define SM501_DC_PANEL_CONTROL_VPD (1<<7)
274 #define SM501_DC_PANEL_CONTROL_VP (1<<6)
275 #define SM501_DC_PANEL_CONTROL_HPD (1<<5)
276 #define SM501_DC_PANEL_CONTROL_HP (1<<4)
277 #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
278 #define SM501_DC_PANEL_CONTROL_EN (1<<2)
280 #define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
281 #define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
282 #define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
285 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
286 #define SM501_DC_PANEL_COLOR_KEY (0x008)
287 #define SM501_DC_PANEL_FB_ADDR (0x00C)
288 #define SM501_DC_PANEL_FB_OFFSET (0x010)
289 #define SM501_DC_PANEL_FB_WIDTH (0x014)
290 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
291 #define SM501_DC_PANEL_TL_LOC (0x01C)
292 #define SM501_DC_PANEL_BR_LOC (0x020)
293 #define SM501_DC_PANEL_H_TOT (0x024)
294 #define SM501_DC_PANEL_H_SYNC (0x028)
295 #define SM501_DC_PANEL_V_TOT (0x02C)
296 #define SM501_DC_PANEL_V_SYNC (0x030)
297 #define SM501_DC_PANEL_CUR_LINE (0x034)
299 #define SM501_DC_VIDEO_CONTROL (0x040)
300 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
301 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
302 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
303 #define SM501_DC_VIDEO_TL_LOC (0x050)
304 #define SM501_DC_VIDEO_BR_LOC (0x054)
305 #define SM501_DC_VIDEO_SCALE (0x058)
306 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
307 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
308 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
309 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
311 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
312 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
313 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
314 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
315 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
316 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
317 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
318 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
319 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
320 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
322 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
323 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
324 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
325 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
326 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
328 #define SM501_HWC_EN (1<<31)
330 #define SM501_OFF_HWC_ADDR (0x00)
331 #define SM501_OFF_HWC_LOC (0x04)
332 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
333 #define SM501_OFF_HWC_COLOR_3 (0x0C)
335 #define SM501_DC_ALPHA_CONTROL (0x100)
336 #define SM501_DC_ALPHA_FB_ADDR (0x104)
337 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
338 #define SM501_DC_ALPHA_TL_LOC (0x10C)
339 #define SM501_DC_ALPHA_BR_LOC (0x110)
340 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
341 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
343 #define SM501_DC_CRT_CONTROL (0x200)
345 #define SM501_DC_CRT_CONTROL_TVP (1<<15)
346 #define SM501_DC_CRT_CONTROL_CP (1<<14)
347 #define SM501_DC_CRT_CONTROL_VSP (1<<13)
348 #define SM501_DC_CRT_CONTROL_HSP (1<<12)
349 #define SM501_DC_CRT_CONTROL_VS (1<<11)
350 #define SM501_DC_CRT_CONTROL_BLANK (1<<10)
351 #define SM501_DC_CRT_CONTROL_SEL (1<<9)
352 #define SM501_DC_CRT_CONTROL_TE (1<<8)
353 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
354 #define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
355 #define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
357 #define SM501_DC_CRT_CONTROL_8BPP (0<<0)
358 #define SM501_DC_CRT_CONTROL_16BPP (1<<0)
359 #define SM501_DC_CRT_CONTROL_32BPP (2<<0)
361 #define SM501_DC_CRT_FB_ADDR (0x204)
362 #define SM501_DC_CRT_FB_OFFSET (0x208)
363 #define SM501_DC_CRT_H_TOT (0x20C)
364 #define SM501_DC_CRT_H_SYNC (0x210)
365 #define SM501_DC_CRT_V_TOT (0x214)
366 #define SM501_DC_CRT_V_SYNC (0x218)
367 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
368 #define SM501_DC_CRT_CUR_LINE (0x220)
369 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
371 #define SM501_DC_CRT_HWC_BASE (0x230)
372 #define SM501_DC_CRT_HWC_ADDR (0x230)
373 #define SM501_DC_CRT_HWC_LOC (0x234)
374 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
375 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
377 #define SM501_DC_PANEL_PALETTE (0x400)
379 #define SM501_DC_VIDEO_PALETTE (0x800)
381 #define SM501_DC_CRT_PALETTE (0xC00)
383 /* Zoom Video port base */
384 #define SM501_ZVPORT (0x090000)
387 #define SM501_AC97 (0x0A0000)
389 /* 8051 micro controller base */
390 #define SM501_UCONTROLLER (0x0B0000)
392 /* 8051 micro controller SRAM base */
393 #define SM501_UCONTROLLER_SRAM (0x0C0000)
396 #define SM501_DMA (0x0D0000)
399 #define SM501_2D_ENGINE (0x100000)
400 #define SM501_2D_SOURCE (0x00)
401 #define SM501_2D_DESTINATION (0x04)
402 #define SM501_2D_DIMENSION (0x08)
403 #define SM501_2D_CONTROL (0x0C)
404 #define SM501_2D_PITCH (0x10)
405 #define SM501_2D_FOREGROUND (0x14)
406 #define SM501_2D_BACKGROUND (0x18)
407 #define SM501_2D_STRETCH (0x1C)
408 #define SM501_2D_COLOR_COMPARE (0x20)
409 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
410 #define SM501_2D_MASK (0x28)
411 #define SM501_2D_CLIP_TL (0x2C)
412 #define SM501_2D_CLIP_BR (0x30)
413 #define SM501_2D_MONO_PATTERN_LOW (0x34)
414 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
415 #define SM501_2D_WINDOW_WIDTH (0x3C)
416 #define SM501_2D_SOURCE_BASE (0x40)
417 #define SM501_2D_DESTINATION_BASE (0x44)
418 #define SM501_2D_ALPHA (0x48)
419 #define SM501_2D_WRAP (0x4C)
420 #define SM501_2D_STATUS (0x50)
422 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
423 #define SM501_CSC_CONSTANTS (0xCC)
424 #define SM501_CSC_Y_SOURCE_X (0xD0)
425 #define SM501_CSC_Y_SOURCE_Y (0xD4)
426 #define SM501_CSC_U_SOURCE_BASE (0xD8)
427 #define SM501_CSC_V_SOURCE_BASE (0xDC)
428 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
429 #define SM501_CSC_SOURCE_PITCH (0xE4)
430 #define SM501_CSC_DESTINATION (0xE8)
431 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
432 #define SM501_CSC_DESTINATION_PITCH (0xF0)
433 #define SM501_CSC_SCALE_FACTOR (0xF4)
434 #define SM501_CSC_DESTINATION_BASE (0xF8)
435 #define SM501_CSC_CONTROL (0xFC)
437 /* 2d engine data port base */
438 #define SM501_2D_ENGINE_DATA (0x110000)
440 /* end of register definitions */
442 #define SM501_HWC_WIDTH (64)
443 #define SM501_HWC_HEIGHT (64)
445 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
446 static const uint32_t sm501_mem_local_size
[] = {
454 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
456 typedef struct SM501State
{
457 /* graphic console status */
460 /* status & internal resources */
462 uint32_t local_mem_size_index
;
464 MemoryRegion local_mem_region
;
466 uint32_t last_height
;
469 uint32_t system_control
;
470 uint32_t misc_control
;
471 uint32_t gpio_31_0_control
;
472 uint32_t gpio_63_32_control
;
473 uint32_t dram_control
;
475 uint32_t misc_timing
;
476 uint32_t power_mode_control
;
483 uint8_t dc_palette
[0x400 * 3];
485 uint32_t dc_panel_control
;
486 uint32_t dc_panel_panning_control
;
487 uint32_t dc_panel_fb_addr
;
488 uint32_t dc_panel_fb_offset
;
489 uint32_t dc_panel_fb_width
;
490 uint32_t dc_panel_fb_height
;
491 uint32_t dc_panel_tl_location
;
492 uint32_t dc_panel_br_location
;
493 uint32_t dc_panel_h_total
;
494 uint32_t dc_panel_h_sync
;
495 uint32_t dc_panel_v_total
;
496 uint32_t dc_panel_v_sync
;
498 uint32_t dc_panel_hwc_addr
;
499 uint32_t dc_panel_hwc_location
;
500 uint32_t dc_panel_hwc_color_1_2
;
501 uint32_t dc_panel_hwc_color_3
;
503 uint32_t dc_crt_control
;
504 uint32_t dc_crt_fb_addr
;
505 uint32_t dc_crt_fb_offset
;
506 uint32_t dc_crt_h_total
;
507 uint32_t dc_crt_h_sync
;
508 uint32_t dc_crt_v_total
;
509 uint32_t dc_crt_v_sync
;
511 uint32_t dc_crt_hwc_addr
;
512 uint32_t dc_crt_hwc_location
;
513 uint32_t dc_crt_hwc_color_1_2
;
514 uint32_t dc_crt_hwc_color_3
;
516 uint32_t twoD_source
;
517 uint32_t twoD_destination
;
518 uint32_t twoD_dimension
;
519 uint32_t twoD_control
;
521 uint32_t twoD_foreground
;
522 uint32_t twoD_stretch
;
523 uint32_t twoD_color_compare_mask
;
525 uint32_t twoD_window_width
;
526 uint32_t twoD_source_base
;
527 uint32_t twoD_destination_base
;
531 static uint32_t get_local_mem_size_index(uint32_t size
)
533 uint32_t norm_size
= 0;
536 for (i
= 0; i
< ARRAY_SIZE(sm501_mem_local_size
); i
++) {
537 uint32_t new_size
= sm501_mem_local_size
[i
];
538 if (new_size
>= size
) {
539 if (norm_size
== 0 || norm_size
> new_size
) {
540 norm_size
= new_size
;
550 * Check the availability of hardware cursor.
551 * @param crt 0 for PANEL, 1 for CRT.
553 static inline int is_hwc_enabled(SM501State
*state
, int crt
)
555 uint32_t addr
= crt
? state
->dc_crt_hwc_addr
: state
->dc_panel_hwc_addr
;
556 return addr
& 0x80000000;
560 * Get the address which holds cursor pattern data.
561 * @param crt 0 for PANEL, 1 for CRT.
563 static inline uint32_t get_hwc_address(SM501State
*state
, int crt
)
565 uint32_t addr
= crt
? state
->dc_crt_hwc_addr
: state
->dc_panel_hwc_addr
;
566 return (addr
& 0x03FFFFF0)/* >> 4*/;
570 * Get the cursor position in y coordinate.
571 * @param crt 0 for PANEL, 1 for CRT.
573 static inline uint32_t get_hwc_y(SM501State
*state
, int crt
)
575 uint32_t location
= crt
? state
->dc_crt_hwc_location
576 : state
->dc_panel_hwc_location
;
577 return (location
& 0x07FF0000) >> 16;
581 * Get the cursor position in x coordinate.
582 * @param crt 0 for PANEL, 1 for CRT.
584 static inline uint32_t get_hwc_x(SM501State
*state
, int crt
)
586 uint32_t location
= crt
? state
->dc_crt_hwc_location
587 : state
->dc_panel_hwc_location
;
588 return location
& 0x000007FF;
592 * Get the cursor position in x coordinate.
593 * @param crt 0 for PANEL, 1 for CRT.
594 * @param index 0, 1, 2 or 3 which specifies color of corsor dot.
596 static inline uint16_t get_hwc_color(SM501State
*state
, int crt
, int index
)
598 uint32_t color_reg
= 0;
599 uint16_t color_565
= 0;
608 color_reg
= crt
? state
->dc_crt_hwc_color_1_2
609 : state
->dc_panel_hwc_color_1_2
;
612 color_reg
= crt
? state
->dc_crt_hwc_color_3
613 : state
->dc_panel_hwc_color_3
;
616 printf("invalid hw cursor color.\n");
623 color_565
= (uint16_t)(color_reg
& 0xFFFF);
626 color_565
= (uint16_t)((color_reg
>> 16) & 0xFFFF);
632 static int within_hwc_y_range(SM501State
*state
, int y
, int crt
)
634 int hwc_y
= get_hwc_y(state
, crt
);
635 return (hwc_y
<= y
&& y
< hwc_y
+ SM501_HWC_HEIGHT
);
638 static void sm501_2d_operation(SM501State
* s
)
640 /* obtain operation parameters */
641 int operation
= (s
->twoD_control
>> 16) & 0x1f;
642 int rtl
= s
->twoD_control
& 0x8000000;
643 int src_x
= (s
->twoD_source
>> 16) & 0x01FFF;
644 int src_y
= s
->twoD_source
& 0xFFFF;
645 int dst_x
= (s
->twoD_destination
>> 16) & 0x01FFF;
646 int dst_y
= s
->twoD_destination
& 0xFFFF;
647 int operation_width
= (s
->twoD_dimension
>> 16) & 0x1FFF;
648 int operation_height
= s
->twoD_dimension
& 0xFFFF;
649 uint32_t color
= s
->twoD_foreground
;
650 int format_flags
= (s
->twoD_stretch
>> 20) & 0x3;
651 int addressing
= (s
->twoD_stretch
>> 16) & 0xF;
653 /* get frame buffer info */
654 uint8_t * src
= s
->local_mem
+ (s
->twoD_source_base
& 0x03FFFFFF);
655 uint8_t * dst
= s
->local_mem
+ (s
->twoD_destination_base
& 0x03FFFFFF);
656 int src_width
= (s
->dc_crt_h_total
& 0x00000FFF) + 1;
657 int dst_width
= (s
->dc_crt_h_total
& 0x00000FFF) + 1;
659 if (addressing
!= 0x0) {
660 printf("%s: only XY addressing is supported.\n", __func__
);
664 if ((s
->twoD_source_base
& 0x08000000) ||
665 (s
->twoD_destination_base
& 0x08000000)) {
666 printf("%s: only local memory is supported.\n", __func__
);
671 case 0x00: /* copy area */
672 #define COPY_AREA(_bpp, _pixel_type, rtl) { \
673 int y, x, index_d, index_s; \
674 for (y = 0; y < operation_height; y++) { \
675 for (x = 0; x < operation_width; x++) { \
677 index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
678 index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
680 index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
681 index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
683 *(_pixel_type*)&dst[index_d] = *(_pixel_type*)&src[index_s];\
687 switch (format_flags
) {
689 COPY_AREA(1, uint8_t, rtl
);
692 COPY_AREA(2, uint16_t, rtl
);
695 COPY_AREA(4, uint32_t, rtl
);
700 case 0x01: /* fill rectangle */
701 #define FILL_RECT(_bpp, _pixel_type) { \
703 for (y = 0; y < operation_height; y++) { \
704 for (x = 0; x < operation_width; x++) { \
705 int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
706 *(_pixel_type*)&dst[index] = (_pixel_type)color; \
711 switch (format_flags
) {
713 FILL_RECT(1, uint8_t);
716 FILL_RECT(2, uint16_t);
719 FILL_RECT(4, uint32_t);
725 printf("non-implemented SM501 2D operation. %d\n", operation
);
731 static uint64_t sm501_system_config_read(void *opaque
, hwaddr addr
,
734 SM501State
* s
= (SM501State
*)opaque
;
736 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr
);
739 case SM501_SYSTEM_CONTROL
:
740 ret
= s
->system_control
;
742 case SM501_MISC_CONTROL
:
743 ret
= s
->misc_control
;
745 case SM501_GPIO31_0_CONTROL
:
746 ret
= s
->gpio_31_0_control
;
748 case SM501_GPIO63_32_CONTROL
:
749 ret
= s
->gpio_63_32_control
;
754 case SM501_DRAM_CONTROL
:
755 ret
= (s
->dram_control
& 0x07F107C0) | s
->local_mem_size_index
<< 13;
760 case SM501_MISC_TIMING
:
761 /* TODO : simulate gate control */
762 ret
= s
->misc_timing
;
764 case SM501_CURRENT_GATE
:
765 /* TODO : simulate gate control */
768 case SM501_CURRENT_CLOCK
:
771 case SM501_POWER_MODE_CONTROL
:
772 ret
= s
->power_mode_control
;
776 printf("sm501 system config : not implemented register read."
777 " addr=%x\n", (int)addr
);
784 static void sm501_system_config_write(void *opaque
, hwaddr addr
,
785 uint64_t value
, unsigned size
)
787 SM501State
* s
= (SM501State
*)opaque
;
788 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
789 (uint32_t)addr
, (uint32_t)value
);
792 case SM501_SYSTEM_CONTROL
:
793 s
->system_control
= value
& 0xE300B8F7;
795 case SM501_MISC_CONTROL
:
796 s
->misc_control
= value
& 0xFF7FFF20;
798 case SM501_GPIO31_0_CONTROL
:
799 s
->gpio_31_0_control
= value
;
801 case SM501_GPIO63_32_CONTROL
:
802 s
->gpio_63_32_control
= value
;
804 case SM501_DRAM_CONTROL
:
805 s
->local_mem_size_index
= (value
>> 13) & 0x7;
806 /* rODO : check validity of size change */
807 s
->dram_control
|= value
& 0x7FFFFFC3;
812 case SM501_MISC_TIMING
:
813 s
->misc_timing
= value
& 0xF31F1FFF;
815 case SM501_POWER_MODE_0_GATE
:
816 case SM501_POWER_MODE_1_GATE
:
817 case SM501_POWER_MODE_0_CLOCK
:
818 case SM501_POWER_MODE_1_CLOCK
:
819 /* TODO : simulate gate & clock control */
821 case SM501_POWER_MODE_CONTROL
:
822 s
->power_mode_control
= value
& 0x00000003;
826 printf("sm501 system config : not implemented register write."
827 " addr=%x, val=%x\n", (int)addr
, (uint32_t)value
);
832 static const MemoryRegionOps sm501_system_config_ops
= {
833 .read
= sm501_system_config_read
,
834 .write
= sm501_system_config_write
,
836 .min_access_size
= 4,
837 .max_access_size
= 4,
839 .endianness
= DEVICE_NATIVE_ENDIAN
,
842 static uint32_t sm501_palette_read(void *opaque
, hwaddr addr
)
844 SM501State
* s
= (SM501State
*)opaque
;
845 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr
);
847 /* TODO : consider BYTE/WORD access */
848 /* TODO : consider endian */
850 assert(range_covers_byte(0, 0x400 * 3, addr
));
851 return *(uint32_t*)&s
->dc_palette
[addr
];
854 static void sm501_palette_write(void *opaque
,
855 hwaddr addr
, uint32_t value
)
857 SM501State
* s
= (SM501State
*)opaque
;
858 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
861 /* TODO : consider BYTE/WORD access */
862 /* TODO : consider endian */
864 assert(range_covers_byte(0, 0x400 * 3, addr
));
865 *(uint32_t*)&s
->dc_palette
[addr
] = value
;
868 static uint64_t sm501_disp_ctrl_read(void *opaque
, hwaddr addr
,
871 SM501State
* s
= (SM501State
*)opaque
;
873 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr
);
877 case SM501_DC_PANEL_CONTROL
:
878 ret
= s
->dc_panel_control
;
880 case SM501_DC_PANEL_PANNING_CONTROL
:
881 ret
= s
->dc_panel_panning_control
;
883 case SM501_DC_PANEL_FB_ADDR
:
884 ret
= s
->dc_panel_fb_addr
;
886 case SM501_DC_PANEL_FB_OFFSET
:
887 ret
= s
->dc_panel_fb_offset
;
889 case SM501_DC_PANEL_FB_WIDTH
:
890 ret
= s
->dc_panel_fb_width
;
892 case SM501_DC_PANEL_FB_HEIGHT
:
893 ret
= s
->dc_panel_fb_height
;
895 case SM501_DC_PANEL_TL_LOC
:
896 ret
= s
->dc_panel_tl_location
;
898 case SM501_DC_PANEL_BR_LOC
:
899 ret
= s
->dc_panel_br_location
;
902 case SM501_DC_PANEL_H_TOT
:
903 ret
= s
->dc_panel_h_total
;
905 case SM501_DC_PANEL_H_SYNC
:
906 ret
= s
->dc_panel_h_sync
;
908 case SM501_DC_PANEL_V_TOT
:
909 ret
= s
->dc_panel_v_total
;
911 case SM501_DC_PANEL_V_SYNC
:
912 ret
= s
->dc_panel_v_sync
;
915 case SM501_DC_CRT_CONTROL
:
916 ret
= s
->dc_crt_control
;
918 case SM501_DC_CRT_FB_ADDR
:
919 ret
= s
->dc_crt_fb_addr
;
921 case SM501_DC_CRT_FB_OFFSET
:
922 ret
= s
->dc_crt_fb_offset
;
924 case SM501_DC_CRT_H_TOT
:
925 ret
= s
->dc_crt_h_total
;
927 case SM501_DC_CRT_H_SYNC
:
928 ret
= s
->dc_crt_h_sync
;
930 case SM501_DC_CRT_V_TOT
:
931 ret
= s
->dc_crt_v_total
;
933 case SM501_DC_CRT_V_SYNC
:
934 ret
= s
->dc_crt_v_sync
;
937 case SM501_DC_CRT_HWC_ADDR
:
938 ret
= s
->dc_crt_hwc_addr
;
940 case SM501_DC_CRT_HWC_LOC
:
941 ret
= s
->dc_crt_hwc_location
;
943 case SM501_DC_CRT_HWC_COLOR_1_2
:
944 ret
= s
->dc_crt_hwc_color_1_2
;
946 case SM501_DC_CRT_HWC_COLOR_3
:
947 ret
= s
->dc_crt_hwc_color_3
;
950 case SM501_DC_PANEL_PALETTE
... SM501_DC_PANEL_PALETTE
+ 0x400*3 - 4:
951 ret
= sm501_palette_read(opaque
, addr
- SM501_DC_PANEL_PALETTE
);
955 printf("sm501 disp ctrl : not implemented register read."
956 " addr=%x\n", (int)addr
);
963 static void sm501_disp_ctrl_write(void *opaque
, hwaddr addr
,
964 uint64_t value
, unsigned size
)
966 SM501State
* s
= (SM501State
*)opaque
;
967 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
968 (unsigned)addr
, (unsigned)value
);
971 case SM501_DC_PANEL_CONTROL
:
972 s
->dc_panel_control
= value
& 0x0FFF73FF;
974 case SM501_DC_PANEL_PANNING_CONTROL
:
975 s
->dc_panel_panning_control
= value
& 0xFF3FFF3F;
977 case SM501_DC_PANEL_FB_ADDR
:
978 s
->dc_panel_fb_addr
= value
& 0x8FFFFFF0;
980 case SM501_DC_PANEL_FB_OFFSET
:
981 s
->dc_panel_fb_offset
= value
& 0x3FF03FF0;
983 case SM501_DC_PANEL_FB_WIDTH
:
984 s
->dc_panel_fb_width
= value
& 0x0FFF0FFF;
986 case SM501_DC_PANEL_FB_HEIGHT
:
987 s
->dc_panel_fb_height
= value
& 0x0FFF0FFF;
989 case SM501_DC_PANEL_TL_LOC
:
990 s
->dc_panel_tl_location
= value
& 0x07FF07FF;
992 case SM501_DC_PANEL_BR_LOC
:
993 s
->dc_panel_br_location
= value
& 0x07FF07FF;
996 case SM501_DC_PANEL_H_TOT
:
997 s
->dc_panel_h_total
= value
& 0x0FFF0FFF;
999 case SM501_DC_PANEL_H_SYNC
:
1000 s
->dc_panel_h_sync
= value
& 0x00FF0FFF;
1002 case SM501_DC_PANEL_V_TOT
:
1003 s
->dc_panel_v_total
= value
& 0x0FFF0FFF;
1005 case SM501_DC_PANEL_V_SYNC
:
1006 s
->dc_panel_v_sync
= value
& 0x003F0FFF;
1009 case SM501_DC_PANEL_HWC_ADDR
:
1010 s
->dc_panel_hwc_addr
= value
& 0x8FFFFFF0;
1012 case SM501_DC_PANEL_HWC_LOC
:
1013 s
->dc_panel_hwc_location
= value
& 0x0FFF0FFF;
1015 case SM501_DC_PANEL_HWC_COLOR_1_2
:
1016 s
->dc_panel_hwc_color_1_2
= value
;
1018 case SM501_DC_PANEL_HWC_COLOR_3
:
1019 s
->dc_panel_hwc_color_3
= value
& 0x0000FFFF;
1022 case SM501_DC_CRT_CONTROL
:
1023 s
->dc_crt_control
= value
& 0x0003FFFF;
1025 case SM501_DC_CRT_FB_ADDR
:
1026 s
->dc_crt_fb_addr
= value
& 0x8FFFFFF0;
1028 case SM501_DC_CRT_FB_OFFSET
:
1029 s
->dc_crt_fb_offset
= value
& 0x3FF03FF0;
1031 case SM501_DC_CRT_H_TOT
:
1032 s
->dc_crt_h_total
= value
& 0x0FFF0FFF;
1034 case SM501_DC_CRT_H_SYNC
:
1035 s
->dc_crt_h_sync
= value
& 0x00FF0FFF;
1037 case SM501_DC_CRT_V_TOT
:
1038 s
->dc_crt_v_total
= value
& 0x0FFF0FFF;
1040 case SM501_DC_CRT_V_SYNC
:
1041 s
->dc_crt_v_sync
= value
& 0x003F0FFF;
1044 case SM501_DC_CRT_HWC_ADDR
:
1045 s
->dc_crt_hwc_addr
= value
& 0x8FFFFFF0;
1047 case SM501_DC_CRT_HWC_LOC
:
1048 s
->dc_crt_hwc_location
= value
& 0x0FFF0FFF;
1050 case SM501_DC_CRT_HWC_COLOR_1_2
:
1051 s
->dc_crt_hwc_color_1_2
= value
;
1053 case SM501_DC_CRT_HWC_COLOR_3
:
1054 s
->dc_crt_hwc_color_3
= value
& 0x0000FFFF;
1057 case SM501_DC_PANEL_PALETTE
... SM501_DC_PANEL_PALETTE
+ 0x400*3 - 4:
1058 sm501_palette_write(opaque
, addr
- SM501_DC_PANEL_PALETTE
, value
);
1062 printf("sm501 disp ctrl : not implemented register write."
1063 " addr=%x, val=%x\n", (int)addr
, (unsigned)value
);
1068 static const MemoryRegionOps sm501_disp_ctrl_ops
= {
1069 .read
= sm501_disp_ctrl_read
,
1070 .write
= sm501_disp_ctrl_write
,
1072 .min_access_size
= 4,
1073 .max_access_size
= 4,
1075 .endianness
= DEVICE_NATIVE_ENDIAN
,
1078 static uint64_t sm501_2d_engine_read(void *opaque
, hwaddr addr
,
1081 SM501State
* s
= (SM501State
*)opaque
;
1083 SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr
);
1086 case SM501_2D_SOURCE_BASE
:
1087 ret
= s
->twoD_source_base
;
1090 printf("sm501 disp ctrl : not implemented register read."
1091 " addr=%x\n", (int)addr
);
1098 static void sm501_2d_engine_write(void *opaque
, hwaddr addr
,
1099 uint64_t value
, unsigned size
)
1101 SM501State
* s
= (SM501State
*)opaque
;
1102 SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
1103 (unsigned)addr
, (unsigned)value
);
1106 case SM501_2D_SOURCE
:
1107 s
->twoD_source
= value
;
1109 case SM501_2D_DESTINATION
:
1110 s
->twoD_destination
= value
;
1112 case SM501_2D_DIMENSION
:
1113 s
->twoD_dimension
= value
;
1115 case SM501_2D_CONTROL
:
1116 s
->twoD_control
= value
;
1118 /* do 2d operation if start flag is set. */
1119 if (value
& 0x80000000) {
1120 sm501_2d_operation(s
);
1121 s
->twoD_control
&= ~0x80000000; /* start flag down */
1125 case SM501_2D_PITCH
:
1126 s
->twoD_pitch
= value
;
1128 case SM501_2D_FOREGROUND
:
1129 s
->twoD_foreground
= value
;
1131 case SM501_2D_STRETCH
:
1132 s
->twoD_stretch
= value
;
1134 case SM501_2D_COLOR_COMPARE_MASK
:
1135 s
->twoD_color_compare_mask
= value
;
1138 s
->twoD_mask
= value
;
1140 case SM501_2D_WINDOW_WIDTH
:
1141 s
->twoD_window_width
= value
;
1143 case SM501_2D_SOURCE_BASE
:
1144 s
->twoD_source_base
= value
;
1146 case SM501_2D_DESTINATION_BASE
:
1147 s
->twoD_destination_base
= value
;
1150 printf("sm501 2d engine : not implemented register write."
1151 " addr=%x, val=%x\n", (int)addr
, (unsigned)value
);
1156 static const MemoryRegionOps sm501_2d_engine_ops
= {
1157 .read
= sm501_2d_engine_read
,
1158 .write
= sm501_2d_engine_write
,
1160 .min_access_size
= 4,
1161 .max_access_size
= 4,
1163 .endianness
= DEVICE_NATIVE_ENDIAN
,
1166 /* draw line functions for all console modes */
1168 typedef void draw_line_func(uint8_t *d
, const uint8_t *s
,
1169 int width
, const uint32_t *pal
);
1171 typedef void draw_hwc_line_func(SM501State
* s
, int crt
, uint8_t * palette
,
1172 int c_y
, uint8_t *d
, int width
);
1175 #include "sm501_template.h"
1178 #include "sm501_template.h"
1182 #include "sm501_template.h"
1185 #include "sm501_template.h"
1189 #include "sm501_template.h"
1192 #include "sm501_template.h"
1196 #include "sm501_template.h"
1198 static draw_line_func
* draw_line8_funcs
[] = {
1208 static draw_line_func
* draw_line16_funcs
[] = {
1218 static draw_line_func
* draw_line32_funcs
[] = {
1228 static draw_hwc_line_func
* draw_hwc_line_funcs
[] = {
1233 draw_hwc_line_32bgr
,
1234 draw_hwc_line_15bgr
,
1235 draw_hwc_line_16bgr
,
1238 static inline int get_depth_index(DisplaySurface
*surface
)
1240 switch (surface_bits_per_pixel(surface
)) {
1249 if (is_surface_bgr(surface
)) {
1257 static void sm501_draw_crt(SM501State
* s
)
1259 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1261 int width
= (s
->dc_crt_h_total
& 0x00000FFF) + 1;
1262 int height
= (s
->dc_crt_v_total
& 0x00000FFF) + 1;
1264 uint8_t * src
= s
->local_mem
;
1266 int dst_bpp
= surface_bytes_per_pixel(surface
);
1267 uint32_t * palette
= (uint32_t *)&s
->dc_palette
[SM501_DC_CRT_PALETTE
1268 - SM501_DC_PANEL_PALETTE
];
1269 uint8_t hwc_palette
[3 * 3];
1270 int ds_depth_index
= get_depth_index(surface
);
1271 draw_line_func
* draw_line
= NULL
;
1272 draw_hwc_line_func
* draw_hwc_line
= NULL
;
1273 int full_update
= 0;
1275 ram_addr_t page_min
= ~0l;
1276 ram_addr_t page_max
= 0l;
1277 ram_addr_t offset
= 0;
1279 /* choose draw_line function */
1280 switch (s
->dc_crt_control
& 3) {
1281 case SM501_DC_CRT_CONTROL_8BPP
:
1283 draw_line
= draw_line8_funcs
[ds_depth_index
];
1285 case SM501_DC_CRT_CONTROL_16BPP
:
1287 draw_line
= draw_line16_funcs
[ds_depth_index
];
1289 case SM501_DC_CRT_CONTROL_32BPP
:
1291 draw_line
= draw_line32_funcs
[ds_depth_index
];
1294 printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
1300 /* set up to draw hardware cursor */
1301 if (is_hwc_enabled(s
, 1)) {
1304 /* get cursor palette */
1305 for (i
= 0; i
< 3; i
++) {
1306 uint16_t rgb565
= get_hwc_color(s
, 1, i
+ 1);
1307 hwc_palette
[i
* 3 + 0] = (rgb565
& 0xf800) >> 8; /* red */
1308 hwc_palette
[i
* 3 + 1] = (rgb565
& 0x07e0) >> 3; /* green */
1309 hwc_palette
[i
* 3 + 2] = (rgb565
& 0x001f) << 3; /* blue */
1312 /* choose cursor draw line function */
1313 draw_hwc_line
= draw_hwc_line_funcs
[ds_depth_index
];
1316 /* adjust console size */
1317 if (s
->last_width
!= width
|| s
->last_height
!= height
) {
1318 qemu_console_resize(s
->con
, width
, height
);
1319 surface
= qemu_console_surface(s
->con
);
1320 s
->last_width
= width
;
1321 s
->last_height
= height
;
1325 /* draw each line according to conditions */
1326 memory_region_sync_dirty_bitmap(&s
->local_mem_region
);
1327 for (y
= 0; y
< height
; y
++) {
1328 int update_hwc
= draw_hwc_line
? within_hwc_y_range(s
, y
, 1) : 0;
1329 int update
= full_update
|| update_hwc
;
1330 ram_addr_t page0
= offset
;
1331 ram_addr_t page1
= offset
+ width
* src_bpp
- 1;
1333 /* check dirty flags for each line */
1334 update
= memory_region_get_dirty(&s
->local_mem_region
, page0
,
1335 page1
- page0
, DIRTY_MEMORY_VGA
);
1337 /* draw line and change status */
1339 uint8_t *d
= surface_data(surface
);
1340 d
+= y
* width
* dst_bpp
;
1342 /* draw graphics layer */
1343 draw_line(d
, src
, width
, palette
);
1345 /* draw haredware cursor */
1347 draw_hwc_line(s
, 1, hwc_palette
, y
- get_hwc_y(s
, 1), d
, width
);
1352 if (page0
< page_min
)
1354 if (page1
> page_max
)
1358 /* flush to display */
1359 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
1364 src
+= width
* src_bpp
;
1365 offset
+= width
* src_bpp
;
1368 /* complete flush to display */
1370 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
1372 /* clear dirty flags */
1373 if (page_min
!= ~0l) {
1374 memory_region_reset_dirty(&s
->local_mem_region
,
1375 page_min
, page_max
+ TARGET_PAGE_SIZE
,
1380 static void sm501_update_display(void *opaque
)
1382 SM501State
* s
= (SM501State
*)opaque
;
1384 if (s
->dc_crt_control
& SM501_DC_CRT_CONTROL_ENABLE
)
1388 static const GraphicHwOps sm501_ops
= {
1389 .gfx_update
= sm501_update_display
,
1392 void sm501_init(MemoryRegion
*address_space_mem
, uint32_t base
,
1393 uint32_t local_mem_bytes
, qemu_irq irq
, CharDriverState
*chr
)
1397 MemoryRegion
*sm501_system_config
= g_new(MemoryRegion
, 1);
1398 MemoryRegion
*sm501_disp_ctrl
= g_new(MemoryRegion
, 1);
1399 MemoryRegion
*sm501_2d_engine
= g_new(MemoryRegion
, 1);
1401 /* allocate management data region */
1402 s
= (SM501State
*)g_malloc0(sizeof(SM501State
));
1404 s
->local_mem_size_index
1405 = get_local_mem_size_index(local_mem_bytes
);
1406 SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s
),
1407 s
->local_mem_size_index
);
1408 s
->system_control
= 0x00100000;
1409 s
->misc_control
= 0x00001000; /* assumes SH, active=low */
1410 s
->dc_panel_control
= 0x00010000;
1411 s
->dc_crt_control
= 0x00010000;
1413 /* allocate local memory */
1414 memory_region_init_ram(&s
->local_mem_region
, NULL
, "sm501.local",
1415 local_mem_bytes
, &error_fatal
);
1416 vmstate_register_ram_global(&s
->local_mem_region
);
1417 memory_region_set_log(&s
->local_mem_region
, true, DIRTY_MEMORY_VGA
);
1418 s
->local_mem
= memory_region_get_ram_ptr(&s
->local_mem_region
);
1419 memory_region_add_subregion(address_space_mem
, base
, &s
->local_mem_region
);
1422 memory_region_init_io(sm501_system_config
, NULL
, &sm501_system_config_ops
, s
,
1423 "sm501-system-config", 0x6c);
1424 memory_region_add_subregion(address_space_mem
, base
+ MMIO_BASE_OFFSET
,
1425 sm501_system_config
);
1426 memory_region_init_io(sm501_disp_ctrl
, NULL
, &sm501_disp_ctrl_ops
, s
,
1427 "sm501-disp-ctrl", 0x1000);
1428 memory_region_add_subregion(address_space_mem
,
1429 base
+ MMIO_BASE_OFFSET
+ SM501_DC
,
1431 memory_region_init_io(sm501_2d_engine
, NULL
, &sm501_2d_engine_ops
, s
,
1432 "sm501-2d-engine", 0x54);
1433 memory_region_add_subregion(address_space_mem
,
1434 base
+ MMIO_BASE_OFFSET
+ SM501_2D_ENGINE
,
1437 /* bridge to usb host emulation module */
1438 dev
= qdev_create(NULL
, "sysbus-ohci");
1439 qdev_prop_set_uint32(dev
, "num-ports", 2);
1440 qdev_prop_set_uint64(dev
, "dma-offset", base
);
1441 qdev_init_nofail(dev
);
1442 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1443 base
+ MMIO_BASE_OFFSET
+ SM501_USB_HOST
);
1444 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, irq
);
1446 /* bridge to serial emulation module */
1448 serial_mm_init(address_space_mem
,
1449 base
+ MMIO_BASE_OFFSET
+ SM501_UART0
, 2,
1450 NULL
, /* TODO : chain irq to IRL */
1451 115200, chr
, DEVICE_NATIVE_ENDIAN
);
1454 /* create qemu graphic console */
1455 s
->con
= graphic_console_init(DEVICE(dev
), 0, &sm501_ops
, s
);