hw/char/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/char/serial.h"
  28 #include "sysemu/char.h"
  29 #include "qapi/error.h"
  30 #include "qemu/timer.h"
  31 #include "exec/address-spaces.h"
  32 #include "qemu/error-report.h"
  33
  34 //#define DEBUG_SERIAL
  35
  36 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  37
  38 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  39 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  40 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  41 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  42
  43 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  44 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  45
  46 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  47 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  48 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  49 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  50 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  51
  52 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  53 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  54
  55 /*
  56  * These are the definitions for the Modem Control Register
  57  */
  58 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  59 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  60 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  61 #define UART_MCR_RTS    0x02    /* RTS complement */
  62 #define UART_MCR_DTR    0x01    /* DTR complement */
  63
  64 /*
  65  * These are the definitions for the Modem Status Register
  66  */
  67 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  68 #define UART_MSR_RI     0x40    /* Ring Indicator */
  69 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  70 #define UART_MSR_CTS    0x10    /* Clear to Send */
  71 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  72 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  73 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  74 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  75 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  76
  77 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  78 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  79 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  80 #define UART_LSR_FE     0x08    /* Frame error indicator */
  81 #define UART_LSR_PE     0x04    /* Parity error indicator */
  82 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  83 #define UART_LSR_DR     0x01    /* Receiver data ready */
  84 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  85
  86 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  87
  88 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  89 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  90 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  91 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  92
  93 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  94 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  95 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  96 #define UART_FCR_FE         0x01    /* FIFO Enable */
  97
  98 #define MAX_XMIT_RETRY      4
  99
 100 #ifdef DEBUG_SERIAL
 101 #define DPRINTF(fmt, ...) \
 102 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 103 #else
 104 #define DPRINTF(fmt, ...) \
 105 do {} while (0)
 106 #endif
 107
 108 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 109
 110 static inline void recv_fifo_put(SerialState *s, uint8_t chr)
 111 {
 112     /* Receive overruns do not overwrite FIFO contents. */
 113     if (!fifo8_is_full(&s->recv_fifo)) {
 114         fifo8_push(&s->recv_fifo, chr);
 115     } else {
 116         s->lsr |= UART_LSR_OE;
 117     }
 118 }
 119
 120 static void serial_update_irq(SerialState *s)
 121 {
 122     uint8_t tmp_iir = UART_IIR_NO_INT;
 123
 124     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 125         tmp_iir = UART_IIR_RLSI;
 126     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 127         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 128          * this is not in the specification but is observed on existing
 129          * hardware.  */
 130         tmp_iir = UART_IIR_CTI;
 131     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 132                (!(s->fcr & UART_FCR_FE) ||
 133                 s->recv_fifo.num >= s->recv_fifo_itl)) {
 134         tmp_iir = UART_IIR_RDI;
 135     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 136         tmp_iir = UART_IIR_THRI;
 137     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 138         tmp_iir = UART_IIR_MSI;
 139     }
 140
 141     s->iir = tmp_iir | (s->iir & 0xF0);
 142
 143     if (tmp_iir != UART_IIR_NO_INT) {
 144         qemu_irq_raise(s->irq);
 145     } else {
 146         qemu_irq_lower(s->irq);
 147     }
 148 }
 149
 150 static void serial_update_parameters(SerialState *s)
 151 {
 152     int speed, parity, data_bits, stop_bits, frame_size;
 153     QEMUSerialSetParams ssp;
 154
 155     if (s->divider == 0)
 156         return;
 157
 158     /* Start bit. */
 159     frame_size = 1;
 160     if (s->lcr & 0x08) {
 161         /* Parity bit. */
 162         frame_size++;
 163         if (s->lcr & 0x10)
 164             parity = 'E';
 165         else
 166             parity = 'O';
 167     } else {
 168             parity = 'N';
 169     }
 170     if (s->lcr & 0x04)
 171         stop_bits = 2;
 172     else
 173         stop_bits = 1;
 174
 175     data_bits = (s->lcr & 0x03) + 5;
 176     frame_size += data_bits + stop_bits;
 177     speed = s->baudbase / s->divider;
 178     ssp.speed = speed;
 179     ssp.parity = parity;
 180     ssp.data_bits = data_bits;
 181     ssp.stop_bits = stop_bits;
 182     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 183     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 184
 185     DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
 186            speed, parity, data_bits, stop_bits);
 187 }
 188
 189 static void serial_update_msl(SerialState *s)
 190 {
 191     uint8_t omsr;
 192     int flags;
 193
 194     timer_del(s->modem_status_poll);
 195
 196     if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 197         s->poll_msl = -1;
 198         return;
 199     }
 200
 201     omsr = s->msr;
 202
 203     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 204     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 205     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 206     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 207
 208     if (s->msr != omsr) {
 209          /* Set delta bits */
 210          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 211          /* UART_MSR_TERI only if change was from 1 -> 0 */
 212          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 213              s->msr &= ~UART_MSR_TERI;
 214          serial_update_irq(s);
 215     }
 216
 217     /* The real 16550A apparently has a 250ns response latency to line status changes.
 218        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 219
 220     if (s->poll_msl)
 221         timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 100);
 222 }
 223
 224 static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
 225 {
 226     SerialState *s = opaque;
 227
 228     do {
 229         assert(!(s->lsr & UART_LSR_TEMT));
 230         if (s->tsr_retry <= 0) {
 231             assert(!(s->lsr & UART_LSR_THRE));
 232
 233             if (s->fcr & UART_FCR_FE) {
 234                 assert(!fifo8_is_empty(&s->xmit_fifo));
 235                 s->tsr = fifo8_pop(&s->xmit_fifo);
 236                 if (!s->xmit_fifo.num) {
 237                     s->lsr |= UART_LSR_THRE;
 238                 }
 239             } else {
 240                 s->tsr = s->thr;
 241                 s->lsr |= UART_LSR_THRE;
 242             }
 243             if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
 244                 s->thr_ipending = 1;
 245                 serial_update_irq(s);
 246             }
 247         }
 248
 249         if (s->mcr & UART_MCR_LOOP) {
 250             /* in loopback mode, say that we just received a char */
 251             serial_receive1(s, &s->tsr, 1);
 252         } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
 253             if (s->tsr_retry >= 0 && s->tsr_retry < MAX_XMIT_RETRY &&
 254                 qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
 255                                       serial_xmit, s) > 0) {
 256                 s->tsr_retry++;
 257                 return FALSE;
 258             }
 259             s->tsr_retry = 0;
 260         } else {
 261             s->tsr_retry = 0;
 262         }
 263
 264         /* Transmit another byte if it is already available. It is only
 265            possible when FIFO is enabled and not empty. */
 266     } while (!(s->lsr & UART_LSR_THRE));
 267
 268     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 269     s->lsr |= UART_LSR_TEMT;
 270
 271     return FALSE;
 272 }
 273
 274
 275 /* Setter for FCR.
 276    is_load flag means, that value is set while loading VM state
 277    and interrupt should not be invoked */
 278 static void serial_write_fcr(SerialState *s, uint8_t val)
 279 {
 280     /* Set fcr - val only has the bits that are supposed to "stick" */
 281     s->fcr = val;
 282
 283     if (val & UART_FCR_FE) {
 284         s->iir |= UART_IIR_FE;
 285         /* Set recv_fifo trigger Level */
 286         switch (val & 0xC0) {
 287         case UART_FCR_ITL_1:
 288             s->recv_fifo_itl = 1;
 289             break;
 290         case UART_FCR_ITL_2:
 291             s->recv_fifo_itl = 4;
 292             break;
 293         case UART_FCR_ITL_3:
 294             s->recv_fifo_itl = 8;
 295             break;
 296         case UART_FCR_ITL_4:
 297             s->recv_fifo_itl = 14;
 298             break;
 299         }
 300     } else {
 301         s->iir &= ~UART_IIR_FE;
 302     }
 303 }
 304
 305 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 306                                 unsigned size)
 307 {
 308     SerialState *s = opaque;
 309
 310     addr &= 7;
 311     DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
 312     switch(addr) {
 313     default:
 314     case 0:
 315         if (s->lcr & UART_LCR_DLAB) {
 316             s->divider = (s->divider & 0xff00) | val;
 317             serial_update_parameters(s);
 318         } else {
 319             s->thr = (uint8_t) val;
 320             if(s->fcr & UART_FCR_FE) {
 321                 /* xmit overruns overwrite data, so make space if needed */
 322                 if (fifo8_is_full(&s->xmit_fifo)) {
 323                     fifo8_pop(&s->xmit_fifo);
 324                 }
 325                 fifo8_push(&s->xmit_fifo, s->thr);
 326             }
 327             s->thr_ipending = 0;
 328             s->lsr &= ~UART_LSR_THRE;
 329             s->lsr &= ~UART_LSR_TEMT;
 330             serial_update_irq(s);
 331             if (s->tsr_retry <= 0) {
 332                 serial_xmit(NULL, G_IO_OUT, s);
 333             }
 334         }
 335         break;
 336     case 1:
 337         if (s->lcr & UART_LCR_DLAB) {
 338             s->divider = (s->divider & 0x00ff) | (val << 8);
 339             serial_update_parameters(s);
 340         } else {
 341             uint8_t changed = (s->ier ^ val) & 0x0f;
 342             s->ier = val & 0x0f;
 343             /* If the backend device is a real serial port, turn polling of the modem
 344              * status lines on physical port on or off depending on UART_IER_MSI state.
 345              */
 346             if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
 347                 if (s->ier & UART_IER_MSI) {
 348                      s->poll_msl = 1;
 349                      serial_update_msl(s);
 350                 } else {
 351                      timer_del(s->modem_status_poll);
 352                      s->poll_msl = 0;
 353                 }
 354             }
 355
 356             /* Turning on the THRE interrupt on IER can trigger the interrupt
 357              * if LSR.THRE=1, even if it had been masked before by reading IIR.
 358              * This is not in the datasheet, but Windows relies on it.  It is
 359              * unclear if THRE has to be resampled every time THRI becomes
 360              * 1, or only on the rising edge.  Bochs does the latter, and Windows
 361              * always toggles IER to all zeroes and back to all ones, so do the
 362              * same.
 363              *
 364              * If IER.THRI is zero, thr_ipending is not used.  Set it to zero
 365              * so that the thr_ipending subsection is not migrated.
 366              */
 367             if (changed & UART_IER_THRI) {
 368                 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
 369                     s->thr_ipending = 1;
 370                 } else {
 371                     s->thr_ipending = 0;
 372                 }
 373             }
 374
 375             if (changed) {
 376                 serial_update_irq(s);
 377             }
 378         }
 379         break;
 380     case 2:
 381         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 382         if ((val ^ s->fcr) & UART_FCR_FE) {
 383             val |= UART_FCR_XFR | UART_FCR_RFR;
 384         }
 385
 386         /* FIFO clear */
 387
 388         if (val & UART_FCR_RFR) {
 389             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 390             timer_del(s->fifo_timeout_timer);
 391             s->timeout_ipending = 0;
 392             fifo8_reset(&s->recv_fifo);
 393         }
 394
 395         if (val & UART_FCR_XFR) {
 396             s->lsr |= UART_LSR_THRE;
 397             s->thr_ipending = 1;
 398             fifo8_reset(&s->xmit_fifo);
 399         }
 400
 401         serial_write_fcr(s, val & 0xC9);
 402         serial_update_irq(s);
 403         break;
 404     case 3:
 405         {
 406             int break_enable;
 407             s->lcr = val;
 408             serial_update_parameters(s);
 409             break_enable = (val >> 6) & 1;
 410             if (break_enable != s->last_break_enable) {
 411                 s->last_break_enable = break_enable;
 412                 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 413                                &break_enable);
 414             }
 415         }
 416         break;
 417     case 4:
 418         {
 419             int flags;
 420             int old_mcr = s->mcr;
 421             s->mcr = val & 0x1f;
 422             if (val & UART_MCR_LOOP)
 423                 break;
 424
 425             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 426
 427                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 428
 429                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 430
 431                 if (val & UART_MCR_RTS)
 432                     flags |= CHR_TIOCM_RTS;
 433                 if (val & UART_MCR_DTR)
 434                     flags |= CHR_TIOCM_DTR;
 435
 436                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 437                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 438                    from the device/computer at the other end of the serial line */
 439                 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
 440             }
 441         }
 442         break;
 443     case 5:
 444         break;
 445     case 6:
 446         break;
 447     case 7:
 448         s->scr = val;
 449         break;
 450     }
 451 }
 452
 453 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
 454 {
 455     SerialState *s = opaque;
 456     uint32_t ret;
 457
 458     addr &= 7;
 459     switch(addr) {
 460     default:
 461     case 0:
 462         if (s->lcr & UART_LCR_DLAB) {
 463             ret = s->divider & 0xff;
 464         } else {
 465             if(s->fcr & UART_FCR_FE) {
 466                 ret = fifo8_is_empty(&s->recv_fifo) ?
 467                             0 : fifo8_pop(&s->recv_fifo);
 468                 if (s->recv_fifo.num == 0) {
 469                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 470                 } else {
 471                     timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 472                 }
 473                 s->timeout_ipending = 0;
 474             } else {
 475                 ret = s->rbr;
 476                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 477             }
 478             serial_update_irq(s);
 479             if (!(s->mcr & UART_MCR_LOOP)) {
 480                 /* in loopback mode, don't receive any data */
 481                 qemu_chr_accept_input(s->chr);
 482             }
 483         }
 484         break;
 485     case 1:
 486         if (s->lcr & UART_LCR_DLAB) {
 487             ret = (s->divider >> 8) & 0xff;
 488         } else {
 489             ret = s->ier;
 490         }
 491         break;
 492     case 2:
 493         ret = s->iir;
 494         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 495             s->thr_ipending = 0;
 496             serial_update_irq(s);
 497         }
 498         break;
 499     case 3:
 500         ret = s->lcr;
 501         break;
 502     case 4:
 503         ret = s->mcr;
 504         break;
 505     case 5:
 506         ret = s->lsr;
 507         /* Clear break and overrun interrupts */
 508         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 509             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 510             serial_update_irq(s);
 511         }
 512         break;
 513     case 6:
 514         if (s->mcr & UART_MCR_LOOP) {
 515             /* in loopback, the modem output pins are connected to the
 516                inputs */
 517             ret = (s->mcr & 0x0c) << 4;
 518             ret |= (s->mcr & 0x02) << 3;
 519             ret |= (s->mcr & 0x01) << 5;
 520         } else {
 521             if (s->poll_msl >= 0)
 522                 serial_update_msl(s);
 523             ret = s->msr;
 524             /* Clear delta bits & msr int after read, if they were set */
 525             if (s->msr & UART_MSR_ANY_DELTA) {
 526                 s->msr &= 0xF0;
 527                 serial_update_irq(s);
 528             }
 529         }
 530         break;
 531     case 7:
 532         ret = s->scr;
 533         break;
 534     }
 535     DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
 536     return ret;
 537 }
 538
 539 static int serial_can_receive(SerialState *s)
 540 {
 541     if(s->fcr & UART_FCR_FE) {
 542         if (s->recv_fifo.num < UART_FIFO_LENGTH) {
 543             /*
 544              * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
 545              * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
 546              * effect will be to almost always fill the fifo completely before
 547              * the guest has a chance to respond, effectively overriding the ITL
 548              * that the guest has set.
 549              */
 550             return (s->recv_fifo.num <= s->recv_fifo_itl) ?
 551                         s->recv_fifo_itl - s->recv_fifo.num : 1;
 552         } else {
 553             return 0;
 554         }
 555     } else {
 556         return !(s->lsr & UART_LSR_DR);
 557     }
 558 }
 559
 560 static void serial_receive_break(SerialState *s)
 561 {
 562     s->rbr = 0;
 563     /* When the LSR_DR is set a null byte is pushed into the fifo */
 564     recv_fifo_put(s, '\0');
 565     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 566     serial_update_irq(s);
 567 }
 568
 569 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 570 static void fifo_timeout_int (void *opaque) {
 571     SerialState *s = opaque;
 572     if (s->recv_fifo.num) {
 573         s->timeout_ipending = 1;
 574         serial_update_irq(s);
 575     }
 576 }
 577
 578 static int serial_can_receive1(void *opaque)
 579 {
 580     SerialState *s = opaque;
 581     return serial_can_receive(s);
 582 }
 583
 584 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 585 {
 586     SerialState *s = opaque;
 587
 588     if (s->wakeup) {
 589         qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
 590     }
 591     if(s->fcr & UART_FCR_FE) {
 592         int i;
 593         for (i = 0; i < size; i++) {
 594             recv_fifo_put(s, buf[i]);
 595         }
 596         s->lsr |= UART_LSR_DR;
 597         /* call the timeout receive callback in 4 char transmit time */
 598         timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 599     } else {
 600         if (s->lsr & UART_LSR_DR)
 601             s->lsr |= UART_LSR_OE;
 602         s->rbr = buf[0];
 603         s->lsr |= UART_LSR_DR;
 604     }
 605     serial_update_irq(s);
 606 }
 607
 608 static void serial_event(void *opaque, int event)
 609 {
 610     SerialState *s = opaque;
 611     DPRINTF("event %x\n", event);
 612     if (event == CHR_EVENT_BREAK)
 613         serial_receive_break(s);
 614 }
 615
 616 static void serial_pre_save(void *opaque)
 617 {
 618     SerialState *s = opaque;
 619     s->fcr_vmstate = s->fcr;
 620 }
 621
 622 static int serial_pre_load(void *opaque)
 623 {
 624     SerialState *s = opaque;
 625     s->thr_ipending = -1;
 626     s->poll_msl = -1;
 627     return 0;
 628 }
 629
 630 static int serial_post_load(void *opaque, int version_id)
 631 {
 632     SerialState *s = opaque;
 633
 634     if (version_id < 3) {
 635         s->fcr_vmstate = 0;
 636     }
 637     if (s->thr_ipending == -1) {
 638         s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 639     }
 640     s->last_break_enable = (s->lcr >> 6) & 1;
 641     /* Initialize fcr via setter to perform essential side-effects */
 642     serial_write_fcr(s, s->fcr_vmstate);
 643     serial_update_parameters(s);
 644     return 0;
 645 }
 646
 647 static bool serial_thr_ipending_needed(void *opaque)
 648 {
 649     SerialState *s = opaque;
 650
 651     if (s->ier & UART_IER_THRI) {
 652         bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 653         return s->thr_ipending != expected_value;
 654     } else {
 655         /* LSR.THRE will be sampled again when the interrupt is
 656          * enabled.  thr_ipending is not used in this case, do
 657          * not migrate it.
 658          */
 659         return false;
 660     }
 661 }
 662
 663 static const VMStateDescription vmstate_serial_thr_ipending = {
 664     .name = "serial/thr_ipending",
 665     .version_id = 1,
 666     .minimum_version_id = 1,
 667     .needed = serial_thr_ipending_needed,
 668     .fields = (VMStateField[]) {
 669         VMSTATE_INT32(thr_ipending, SerialState),
 670         VMSTATE_END_OF_LIST()
 671     }
 672 };
 673
 674 static bool serial_tsr_needed(void *opaque)
 675 {
 676     SerialState *s = (SerialState *)opaque;
 677     return s->tsr_retry != 0;
 678 }
 679
 680 static const VMStateDescription vmstate_serial_tsr = {
 681     .name = "serial/tsr",
 682     .version_id = 1,
 683     .minimum_version_id = 1,
 684     .needed = serial_tsr_needed,
 685     .fields = (VMStateField[]) {
 686         VMSTATE_INT32(tsr_retry, SerialState),
 687         VMSTATE_UINT8(thr, SerialState),
 688         VMSTATE_UINT8(tsr, SerialState),
 689         VMSTATE_END_OF_LIST()
 690     }
 691 };
 692
 693 static bool serial_recv_fifo_needed(void *opaque)
 694 {
 695     SerialState *s = (SerialState *)opaque;
 696     return !fifo8_is_empty(&s->recv_fifo);
 697
 698 }
 699
 700 static const VMStateDescription vmstate_serial_recv_fifo = {
 701     .name = "serial/recv_fifo",
 702     .version_id = 1,
 703     .minimum_version_id = 1,
 704     .needed = serial_recv_fifo_needed,
 705     .fields = (VMStateField[]) {
 706         VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 707         VMSTATE_END_OF_LIST()
 708     }
 709 };
 710
 711 static bool serial_xmit_fifo_needed(void *opaque)
 712 {
 713     SerialState *s = (SerialState *)opaque;
 714     return !fifo8_is_empty(&s->xmit_fifo);
 715 }
 716
 717 static const VMStateDescription vmstate_serial_xmit_fifo = {
 718     .name = "serial/xmit_fifo",
 719     .version_id = 1,
 720     .minimum_version_id = 1,
 721     .needed = serial_xmit_fifo_needed,
 722     .fields = (VMStateField[]) {
 723         VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 724         VMSTATE_END_OF_LIST()
 725     }
 726 };
 727
 728 static bool serial_fifo_timeout_timer_needed(void *opaque)
 729 {
 730     SerialState *s = (SerialState *)opaque;
 731     return timer_pending(s->fifo_timeout_timer);
 732 }
 733
 734 static const VMStateDescription vmstate_serial_fifo_timeout_timer = {
 735     .name = "serial/fifo_timeout_timer",
 736     .version_id = 1,
 737     .minimum_version_id = 1,
 738     .needed = serial_fifo_timeout_timer_needed,
 739     .fields = (VMStateField[]) {
 740         VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
 741         VMSTATE_END_OF_LIST()
 742     }
 743 };
 744
 745 static bool serial_timeout_ipending_needed(void *opaque)
 746 {
 747     SerialState *s = (SerialState *)opaque;
 748     return s->timeout_ipending != 0;
 749 }
 750
 751 static const VMStateDescription vmstate_serial_timeout_ipending = {
 752     .name = "serial/timeout_ipending",
 753     .version_id = 1,
 754     .minimum_version_id = 1,
 755     .needed = serial_timeout_ipending_needed,
 756     .fields = (VMStateField[]) {
 757         VMSTATE_INT32(timeout_ipending, SerialState),
 758         VMSTATE_END_OF_LIST()
 759     }
 760 };
 761
 762 static bool serial_poll_needed(void *opaque)
 763 {
 764     SerialState *s = (SerialState *)opaque;
 765     return s->poll_msl >= 0;
 766 }
 767
 768 static const VMStateDescription vmstate_serial_poll = {
 769     .name = "serial/poll",
 770     .version_id = 1,
 771     .needed = serial_poll_needed,
 772     .minimum_version_id = 1,
 773     .fields = (VMStateField[]) {
 774         VMSTATE_INT32(poll_msl, SerialState),
 775         VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
 776         VMSTATE_END_OF_LIST()
 777     }
 778 };
 779
 780 const VMStateDescription vmstate_serial = {
 781     .name = "serial",
 782     .version_id = 3,
 783     .minimum_version_id = 2,
 784     .pre_save = serial_pre_save,
 785     .pre_load = serial_pre_load,
 786     .post_load = serial_post_load,
 787     .fields = (VMStateField[]) {
 788         VMSTATE_UINT16_V(divider, SerialState, 2),
 789         VMSTATE_UINT8(rbr, SerialState),
 790         VMSTATE_UINT8(ier, SerialState),
 791         VMSTATE_UINT8(iir, SerialState),
 792         VMSTATE_UINT8(lcr, SerialState),
 793         VMSTATE_UINT8(mcr, SerialState),
 794         VMSTATE_UINT8(lsr, SerialState),
 795         VMSTATE_UINT8(msr, SerialState),
 796         VMSTATE_UINT8(scr, SerialState),
 797         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 798         VMSTATE_END_OF_LIST()
 799     },
 800     .subsections = (const VMStateDescription*[]) {
 801         &vmstate_serial_thr_ipending,
 802         &vmstate_serial_tsr,
 803         &vmstate_serial_recv_fifo,
 804         &vmstate_serial_xmit_fifo,
 805         &vmstate_serial_fifo_timeout_timer,
 806         &vmstate_serial_timeout_ipending,
 807         &vmstate_serial_poll,
 808         NULL
 809     }
 810 };
 811
 812 static void serial_reset(void *opaque)
 813 {
 814     SerialState *s = opaque;
 815
 816     s->rbr = 0;
 817     s->ier = 0;
 818     s->iir = UART_IIR_NO_INT;
 819     s->lcr = 0;
 820     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 821     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 822     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 823     s->divider = 0x0C;
 824     s->mcr = UART_MCR_OUT2;
 825     s->scr = 0;
 826     s->tsr_retry = 0;
 827     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
 828     s->poll_msl = 0;
 829
 830     s->timeout_ipending = 0;
 831     timer_del(s->fifo_timeout_timer);
 832     timer_del(s->modem_status_poll);
 833
 834     fifo8_reset(&s->recv_fifo);
 835     fifo8_reset(&s->xmit_fifo);
 836
 837     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 838
 839     s->thr_ipending = 0;
 840     s->last_break_enable = 0;
 841     qemu_irq_lower(s->irq);
 842
 843     serial_update_msl(s);
 844     s->msr &= ~UART_MSR_ANY_DELTA;
 845 }
 846
 847 void serial_realize_core(SerialState *s, Error **errp)
 848 {
 849     if (!s->chr) {
 850         error_setg(errp, "Can't create serial device, empty char device");
 851         return;
 852     }
 853
 854     s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
 855
 856     s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
 857     qemu_register_reset(serial_reset, s);
 858
 859     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 860                           serial_event, s);
 861     fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
 862     fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
 863     serial_reset(s);
 864 }
 865
 866 void serial_exit_core(SerialState *s)
 867 {
 868     qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL);
 869     qemu_unregister_reset(serial_reset, s);
 870 }
 871
 872 /* Change the main reference oscillator frequency. */
 873 void serial_set_frequency(SerialState *s, uint32_t frequency)
 874 {
 875     s->baudbase = frequency;
 876     serial_update_parameters(s);
 877 }
 878
 879 const MemoryRegionOps serial_io_ops = {
 880     .read = serial_ioport_read,
 881     .write = serial_ioport_write,
 882     .impl = {
 883         .min_access_size = 1,
 884         .max_access_size = 1,
 885     },
 886     .endianness = DEVICE_LITTLE_ENDIAN,
 887 };
 888
 889 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 890                          CharDriverState *chr, MemoryRegion *system_io)
 891 {
 892     SerialState *s;
 893
 894     s = g_malloc0(sizeof(SerialState));
 895
 896     s->irq = irq;
 897     s->baudbase = baudbase;
 898     s->chr = chr;
 899     serial_realize_core(s, &error_fatal);
 900
 901     vmstate_register(NULL, base, &vmstate_serial, s);
 902
 903     memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
 904     memory_region_add_subregion(system_io, base, &s->io);
 905
 906     return s;
 907 }
 908
 909 /* Memory mapped interface */
 910 static uint64_t serial_mm_read(void *opaque, hwaddr addr,
 911                                unsigned size)
 912 {
 913     SerialState *s = opaque;
 914     return serial_ioport_read(s, addr >> s->it_shift, 1);
 915 }
 916
 917 static void serial_mm_write(void *opaque, hwaddr addr,
 918                             uint64_t value, unsigned size)
 919 {
 920     SerialState *s = opaque;
 921     value &= ~0u >> (32 - (size * 8));
 922     serial_ioport_write(s, addr >> s->it_shift, value, 1);
 923 }
 924
 925 static const MemoryRegionOps serial_mm_ops[3] = {
 926     [DEVICE_NATIVE_ENDIAN] = {
 927         .read = serial_mm_read,
 928         .write = serial_mm_write,
 929         .endianness = DEVICE_NATIVE_ENDIAN,
 930     },
 931     [DEVICE_LITTLE_ENDIAN] = {
 932         .read = serial_mm_read,
 933         .write = serial_mm_write,
 934         .endianness = DEVICE_LITTLE_ENDIAN,
 935     },
 936     [DEVICE_BIG_ENDIAN] = {
 937         .read = serial_mm_read,
 938         .write = serial_mm_write,
 939         .endianness = DEVICE_BIG_ENDIAN,
 940     },
 941 };
 942
 943 SerialState *serial_mm_init(MemoryRegion *address_space,
 944                             hwaddr base, int it_shift,
 945                             qemu_irq irq, int baudbase,
 946                             CharDriverState *chr, enum device_endian end)
 947 {
 948     SerialState *s;
 949
 950     s = g_malloc0(sizeof(SerialState));
 951
 952     s->it_shift = it_shift;
 953     s->irq = irq;
 954     s->baudbase = baudbase;
 955     s->chr = chr;
 956
 957     serial_realize_core(s, &error_fatal);
 958     vmstate_register(NULL, base, &vmstate_serial, s);
 959
 960     memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
 961                           "serial", 8 << it_shift);
 962     memory_region_add_subregion(address_space, base, &s->io);
 963     return s;
 964 }