include/qemu/osdep.h: Don't include qapi/error.h
[qemu/ar7.git] / hw / arm / pxa2xx.c
blob24109091bff9d9ec8b0735d7b3ae5602f1907743
1 /*
2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPL.
8 */
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "hw/arm/pxa.h"
14 #include "sysemu/sysemu.h"
15 #include "hw/char/serial.h"
16 #include "hw/i2c/i2c.h"
17 #include "hw/ssi/ssi.h"
18 #include "sysemu/char.h"
19 #include "sysemu/block-backend.h"
20 #include "sysemu/blockdev.h"
22 static struct {
23 hwaddr io_base;
24 int irqn;
25 } pxa255_serial[] = {
26 { 0x40100000, PXA2XX_PIC_FFUART },
27 { 0x40200000, PXA2XX_PIC_BTUART },
28 { 0x40700000, PXA2XX_PIC_STUART },
29 { 0x41600000, PXA25X_PIC_HWUART },
30 { 0, 0 }
31 }, pxa270_serial[] = {
32 { 0x40100000, PXA2XX_PIC_FFUART },
33 { 0x40200000, PXA2XX_PIC_BTUART },
34 { 0x40700000, PXA2XX_PIC_STUART },
35 { 0, 0 }
38 typedef struct PXASSPDef {
39 hwaddr io_base;
40 int irqn;
41 } PXASSPDef;
43 #if 0
44 static PXASSPDef pxa250_ssp[] = {
45 { 0x41000000, PXA2XX_PIC_SSP },
46 { 0, 0 }
48 #endif
50 static PXASSPDef pxa255_ssp[] = {
51 { 0x41000000, PXA2XX_PIC_SSP },
52 { 0x41400000, PXA25X_PIC_NSSP },
53 { 0, 0 }
56 #if 0
57 static PXASSPDef pxa26x_ssp[] = {
58 { 0x41000000, PXA2XX_PIC_SSP },
59 { 0x41400000, PXA25X_PIC_NSSP },
60 { 0x41500000, PXA26X_PIC_ASSP },
61 { 0, 0 }
63 #endif
65 static PXASSPDef pxa27x_ssp[] = {
66 { 0x41000000, PXA2XX_PIC_SSP },
67 { 0x41700000, PXA27X_PIC_SSP2 },
68 { 0x41900000, PXA2XX_PIC_SSP3 },
69 { 0, 0 }
72 #define PMCR 0x00 /* Power Manager Control register */
73 #define PSSR 0x04 /* Power Manager Sleep Status register */
74 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
75 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
76 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
77 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
78 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
79 #define PCFR 0x1c /* Power Manager General Configuration register */
80 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
81 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
82 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
83 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
84 #define RCSR 0x30 /* Reset Controller Status register */
85 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
86 #define PTSR 0x38 /* Power Manager Standby Configuration register */
87 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
88 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
89 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
90 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
91 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
92 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
94 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
95 unsigned size)
97 PXA2xxState *s = (PXA2xxState *) opaque;
99 switch (addr) {
100 case PMCR ... PCMD31:
101 if (addr & 3)
102 goto fail;
104 return s->pm_regs[addr >> 2];
105 default:
106 fail:
107 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
108 break;
110 return 0;
113 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
114 uint64_t value, unsigned size)
116 PXA2xxState *s = (PXA2xxState *) opaque;
118 switch (addr) {
119 case PMCR:
120 /* Clear the write-one-to-clear bits... */
121 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
122 /* ...and set the plain r/w bits */
123 s->pm_regs[addr >> 2] &= ~0x15;
124 s->pm_regs[addr >> 2] |= value & 0x15;
125 break;
127 case PSSR: /* Read-clean registers */
128 case RCSR:
129 case PKSR:
130 s->pm_regs[addr >> 2] &= ~value;
131 break;
133 default: /* Read-write registers */
134 if (!(addr & 3)) {
135 s->pm_regs[addr >> 2] = value;
136 break;
139 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
140 break;
144 static const MemoryRegionOps pxa2xx_pm_ops = {
145 .read = pxa2xx_pm_read,
146 .write = pxa2xx_pm_write,
147 .endianness = DEVICE_NATIVE_ENDIAN,
150 static const VMStateDescription vmstate_pxa2xx_pm = {
151 .name = "pxa2xx_pm",
152 .version_id = 0,
153 .minimum_version_id = 0,
154 .fields = (VMStateField[]) {
155 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
156 VMSTATE_END_OF_LIST()
160 #define CCCR 0x00 /* Core Clock Configuration register */
161 #define CKEN 0x04 /* Clock Enable register */
162 #define OSCC 0x08 /* Oscillator Configuration register */
163 #define CCSR 0x0c /* Core Clock Status register */
165 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
166 unsigned size)
168 PXA2xxState *s = (PXA2xxState *) opaque;
170 switch (addr) {
171 case CCCR:
172 case CKEN:
173 case OSCC:
174 return s->cm_regs[addr >> 2];
176 case CCSR:
177 return s->cm_regs[CCCR >> 2] | (3 << 28);
179 default:
180 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
181 break;
183 return 0;
186 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
187 uint64_t value, unsigned size)
189 PXA2xxState *s = (PXA2xxState *) opaque;
191 switch (addr) {
192 case CCCR:
193 case CKEN:
194 s->cm_regs[addr >> 2] = value;
195 break;
197 case OSCC:
198 s->cm_regs[addr >> 2] &= ~0x6c;
199 s->cm_regs[addr >> 2] |= value & 0x6e;
200 if ((value >> 1) & 1) /* OON */
201 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
202 break;
204 default:
205 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
206 break;
210 static const MemoryRegionOps pxa2xx_cm_ops = {
211 .read = pxa2xx_cm_read,
212 .write = pxa2xx_cm_write,
213 .endianness = DEVICE_NATIVE_ENDIAN,
216 static const VMStateDescription vmstate_pxa2xx_cm = {
217 .name = "pxa2xx_cm",
218 .version_id = 0,
219 .minimum_version_id = 0,
220 .fields = (VMStateField[]) {
221 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
222 VMSTATE_UINT32(clkcfg, PXA2xxState),
223 VMSTATE_UINT32(pmnc, PXA2xxState),
224 VMSTATE_END_OF_LIST()
228 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
230 PXA2xxState *s = (PXA2xxState *)ri->opaque;
231 return s->clkcfg;
234 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
235 uint64_t value)
237 PXA2xxState *s = (PXA2xxState *)ri->opaque;
238 s->clkcfg = value & 0xf;
239 if (value & 2) {
240 printf("%s: CPU frequency change attempt\n", __func__);
244 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
245 uint64_t value)
247 PXA2xxState *s = (PXA2xxState *)ri->opaque;
248 static const char *pwrmode[8] = {
249 "Normal", "Idle", "Deep-idle", "Standby",
250 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
253 if (value & 8) {
254 printf("%s: CPU voltage change attempt\n", __func__);
256 switch (value & 7) {
257 case 0:
258 /* Do nothing */
259 break;
261 case 1:
262 /* Idle */
263 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
264 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
265 break;
267 /* Fall through. */
269 case 2:
270 /* Deep-Idle */
271 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
272 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
273 goto message;
275 case 3:
276 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
277 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
278 s->cpu->env.cp15.sctlr_ns = 0;
279 s->cpu->env.cp15.cpacr_el1 = 0;
280 s->cpu->env.cp15.ttbr0_el[1] = 0;
281 s->cpu->env.cp15.dacr_ns = 0;
282 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
283 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
286 * The scratch-pad register is almost universally used
287 * for storing the return address on suspend. For the
288 * lack of a resuming bootloader, perform a jump
289 * directly to that address.
291 memset(s->cpu->env.regs, 0, 4 * 15);
292 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
294 #if 0
295 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
296 cpu_physical_memory_write(0, &buffer, 4);
297 buffer = s->pm_regs[PSPR >> 2];
298 cpu_physical_memory_write(8, &buffer, 4);
299 #endif
301 /* Suspend */
302 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
304 goto message;
306 default:
307 message:
308 printf("%s: machine entered %s mode\n", __func__,
309 pwrmode[value & 7]);
313 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
315 PXA2xxState *s = (PXA2xxState *)ri->opaque;
316 return s->pmnc;
319 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
320 uint64_t value)
322 PXA2xxState *s = (PXA2xxState *)ri->opaque;
323 s->pmnc = value;
326 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
328 PXA2xxState *s = (PXA2xxState *)ri->opaque;
329 if (s->pmnc & 1) {
330 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
331 } else {
332 return 0;
336 static const ARMCPRegInfo pxa_cp_reginfo[] = {
337 /* cp14 crm==1: perf registers */
338 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
339 .access = PL1_RW, .type = ARM_CP_IO,
340 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
341 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
342 .access = PL1_RW, .type = ARM_CP_IO,
343 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
344 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
345 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
346 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
347 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
348 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
349 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
350 /* cp14 crm==2: performance count registers */
351 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
352 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
353 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
354 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
355 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
356 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
357 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
358 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
359 /* cp14 crn==6: CLKCFG */
360 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
361 .access = PL1_RW, .type = ARM_CP_IO,
362 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
363 /* cp14 crn==7: PWRMODE */
364 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
365 .access = PL1_RW, .type = ARM_CP_IO,
366 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
367 REGINFO_SENTINEL
370 static void pxa2xx_setup_cp14(PXA2xxState *s)
372 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
375 #define MDCNFG 0x00 /* SDRAM Configuration register */
376 #define MDREFR 0x04 /* SDRAM Refresh Control register */
377 #define MSC0 0x08 /* Static Memory Control register 0 */
378 #define MSC1 0x0c /* Static Memory Control register 1 */
379 #define MSC2 0x10 /* Static Memory Control register 2 */
380 #define MECR 0x14 /* Expansion Memory Bus Config register */
381 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
382 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
383 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
384 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
385 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
386 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
387 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
388 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
389 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
390 #define ARB_CNTL 0x48 /* Arbiter Control register */
391 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
392 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
393 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
394 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
395 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
396 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
397 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
399 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
400 unsigned size)
402 PXA2xxState *s = (PXA2xxState *) opaque;
404 switch (addr) {
405 case MDCNFG ... SA1110:
406 if ((addr & 3) == 0)
407 return s->mm_regs[addr >> 2];
409 default:
410 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
411 break;
413 return 0;
416 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
417 uint64_t value, unsigned size)
419 PXA2xxState *s = (PXA2xxState *) opaque;
421 switch (addr) {
422 case MDCNFG ... SA1110:
423 if ((addr & 3) == 0) {
424 s->mm_regs[addr >> 2] = value;
425 break;
428 default:
429 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
430 break;
434 static const MemoryRegionOps pxa2xx_mm_ops = {
435 .read = pxa2xx_mm_read,
436 .write = pxa2xx_mm_write,
437 .endianness = DEVICE_NATIVE_ENDIAN,
440 static const VMStateDescription vmstate_pxa2xx_mm = {
441 .name = "pxa2xx_mm",
442 .version_id = 0,
443 .minimum_version_id = 0,
444 .fields = (VMStateField[]) {
445 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
446 VMSTATE_END_OF_LIST()
450 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
451 #define PXA2XX_SSP(obj) \
452 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
454 /* Synchronous Serial Ports */
455 typedef struct {
456 /*< private >*/
457 SysBusDevice parent_obj;
458 /*< public >*/
460 MemoryRegion iomem;
461 qemu_irq irq;
462 uint32_t enable;
463 SSIBus *bus;
465 uint32_t sscr[2];
466 uint32_t sspsp;
467 uint32_t ssto;
468 uint32_t ssitr;
469 uint32_t sssr;
470 uint8_t sstsa;
471 uint8_t ssrsa;
472 uint8_t ssacd;
474 uint32_t rx_fifo[16];
475 uint32_t rx_level;
476 uint32_t rx_start;
477 } PXA2xxSSPState;
479 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id)
481 PXA2xxSSPState *s = opaque;
483 return s->rx_start < sizeof(s->rx_fifo);
486 static const VMStateDescription vmstate_pxa2xx_ssp = {
487 .name = "pxa2xx-ssp",
488 .version_id = 1,
489 .minimum_version_id = 1,
490 .fields = (VMStateField[]) {
491 VMSTATE_UINT32(enable, PXA2xxSSPState),
492 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2),
493 VMSTATE_UINT32(sspsp, PXA2xxSSPState),
494 VMSTATE_UINT32(ssto, PXA2xxSSPState),
495 VMSTATE_UINT32(ssitr, PXA2xxSSPState),
496 VMSTATE_UINT32(sssr, PXA2xxSSPState),
497 VMSTATE_UINT8(sstsa, PXA2xxSSPState),
498 VMSTATE_UINT8(ssrsa, PXA2xxSSPState),
499 VMSTATE_UINT8(ssacd, PXA2xxSSPState),
500 VMSTATE_UINT32(rx_level, PXA2xxSSPState),
501 VMSTATE_UINT32(rx_start, PXA2xxSSPState),
502 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate),
503 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16),
504 VMSTATE_END_OF_LIST()
508 #define SSCR0 0x00 /* SSP Control register 0 */
509 #define SSCR1 0x04 /* SSP Control register 1 */
510 #define SSSR 0x08 /* SSP Status register */
511 #define SSITR 0x0c /* SSP Interrupt Test register */
512 #define SSDR 0x10 /* SSP Data register */
513 #define SSTO 0x28 /* SSP Time-Out register */
514 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
515 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
516 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
517 #define SSTSS 0x38 /* SSP Time Slot Status register */
518 #define SSACD 0x3c /* SSP Audio Clock Divider register */
520 /* Bitfields for above registers */
521 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
522 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
523 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
524 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
525 #define SSCR0_SSE (1 << 7)
526 #define SSCR0_RIM (1 << 22)
527 #define SSCR0_TIM (1 << 23)
528 #define SSCR0_MOD (1U << 31)
529 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
530 #define SSCR1_RIE (1 << 0)
531 #define SSCR1_TIE (1 << 1)
532 #define SSCR1_LBM (1 << 2)
533 #define SSCR1_MWDS (1 << 5)
534 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
535 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
536 #define SSCR1_EFWR (1 << 14)
537 #define SSCR1_PINTE (1 << 18)
538 #define SSCR1_TINTE (1 << 19)
539 #define SSCR1_RSRE (1 << 20)
540 #define SSCR1_TSRE (1 << 21)
541 #define SSCR1_EBCEI (1 << 29)
542 #define SSITR_INT (7 << 5)
543 #define SSSR_TNF (1 << 2)
544 #define SSSR_RNE (1 << 3)
545 #define SSSR_TFS (1 << 5)
546 #define SSSR_RFS (1 << 6)
547 #define SSSR_ROR (1 << 7)
548 #define SSSR_PINT (1 << 18)
549 #define SSSR_TINT (1 << 19)
550 #define SSSR_EOC (1 << 20)
551 #define SSSR_TUR (1 << 21)
552 #define SSSR_BCE (1 << 23)
553 #define SSSR_RW 0x00bc0080
555 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
557 int level = 0;
559 level |= s->ssitr & SSITR_INT;
560 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
561 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
562 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
563 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
564 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
565 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
566 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
567 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
568 qemu_set_irq(s->irq, !!level);
571 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
573 s->sssr &= ~(0xf << 12); /* Clear RFL */
574 s->sssr &= ~(0xf << 8); /* Clear TFL */
575 s->sssr &= ~SSSR_TFS;
576 s->sssr &= ~SSSR_TNF;
577 if (s->enable) {
578 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
579 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
580 s->sssr |= SSSR_RFS;
581 else
582 s->sssr &= ~SSSR_RFS;
583 if (s->rx_level)
584 s->sssr |= SSSR_RNE;
585 else
586 s->sssr &= ~SSSR_RNE;
587 /* TX FIFO is never filled, so it is always in underrun
588 condition if SSP is enabled */
589 s->sssr |= SSSR_TFS;
590 s->sssr |= SSSR_TNF;
593 pxa2xx_ssp_int_update(s);
596 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
597 unsigned size)
599 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
600 uint32_t retval;
602 switch (addr) {
603 case SSCR0:
604 return s->sscr[0];
605 case SSCR1:
606 return s->sscr[1];
607 case SSPSP:
608 return s->sspsp;
609 case SSTO:
610 return s->ssto;
611 case SSITR:
612 return s->ssitr;
613 case SSSR:
614 return s->sssr | s->ssitr;
615 case SSDR:
616 if (!s->enable)
617 return 0xffffffff;
618 if (s->rx_level < 1) {
619 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
620 return 0xffffffff;
622 s->rx_level --;
623 retval = s->rx_fifo[s->rx_start ++];
624 s->rx_start &= 0xf;
625 pxa2xx_ssp_fifo_update(s);
626 return retval;
627 case SSTSA:
628 return s->sstsa;
629 case SSRSA:
630 return s->ssrsa;
631 case SSTSS:
632 return 0;
633 case SSACD:
634 return s->ssacd;
635 default:
636 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
637 break;
639 return 0;
642 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
643 uint64_t value64, unsigned size)
645 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
646 uint32_t value = value64;
648 switch (addr) {
649 case SSCR0:
650 s->sscr[0] = value & 0xc7ffffff;
651 s->enable = value & SSCR0_SSE;
652 if (value & SSCR0_MOD)
653 printf("%s: Attempt to use network mode\n", __FUNCTION__);
654 if (s->enable && SSCR0_DSS(value) < 4)
655 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
656 SSCR0_DSS(value));
657 if (!(value & SSCR0_SSE)) {
658 s->sssr = 0;
659 s->ssitr = 0;
660 s->rx_level = 0;
662 pxa2xx_ssp_fifo_update(s);
663 break;
665 case SSCR1:
666 s->sscr[1] = value;
667 if (value & (SSCR1_LBM | SSCR1_EFWR))
668 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
669 pxa2xx_ssp_fifo_update(s);
670 break;
672 case SSPSP:
673 s->sspsp = value;
674 break;
676 case SSTO:
677 s->ssto = value;
678 break;
680 case SSITR:
681 s->ssitr = value & SSITR_INT;
682 pxa2xx_ssp_int_update(s);
683 break;
685 case SSSR:
686 s->sssr &= ~(value & SSSR_RW);
687 pxa2xx_ssp_int_update(s);
688 break;
690 case SSDR:
691 if (SSCR0_UWIRE(s->sscr[0])) {
692 if (s->sscr[1] & SSCR1_MWDS)
693 value &= 0xffff;
694 else
695 value &= 0xff;
696 } else
697 /* Note how 32bits overflow does no harm here */
698 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
700 /* Data goes from here to the Tx FIFO and is shifted out from
701 * there directly to the slave, no need to buffer it.
703 if (s->enable) {
704 uint32_t readval;
705 readval = ssi_transfer(s->bus, value);
706 if (s->rx_level < 0x10) {
707 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
708 } else {
709 s->sssr |= SSSR_ROR;
712 pxa2xx_ssp_fifo_update(s);
713 break;
715 case SSTSA:
716 s->sstsa = value;
717 break;
719 case SSRSA:
720 s->ssrsa = value;
721 break;
723 case SSACD:
724 s->ssacd = value;
725 break;
727 default:
728 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
729 break;
733 static const MemoryRegionOps pxa2xx_ssp_ops = {
734 .read = pxa2xx_ssp_read,
735 .write = pxa2xx_ssp_write,
736 .endianness = DEVICE_NATIVE_ENDIAN,
739 static void pxa2xx_ssp_reset(DeviceState *d)
741 PXA2xxSSPState *s = PXA2XX_SSP(d);
743 s->enable = 0;
744 s->sscr[0] = s->sscr[1] = 0;
745 s->sspsp = 0;
746 s->ssto = 0;
747 s->ssitr = 0;
748 s->sssr = 0;
749 s->sstsa = 0;
750 s->ssrsa = 0;
751 s->ssacd = 0;
752 s->rx_start = s->rx_level = 0;
755 static int pxa2xx_ssp_init(SysBusDevice *sbd)
757 DeviceState *dev = DEVICE(sbd);
758 PXA2xxSSPState *s = PXA2XX_SSP(dev);
760 sysbus_init_irq(sbd, &s->irq);
762 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
763 "pxa2xx-ssp", 0x1000);
764 sysbus_init_mmio(sbd, &s->iomem);
766 s->bus = ssi_create_bus(dev, "ssi");
767 return 0;
770 /* Real-Time Clock */
771 #define RCNR 0x00 /* RTC Counter register */
772 #define RTAR 0x04 /* RTC Alarm register */
773 #define RTSR 0x08 /* RTC Status register */
774 #define RTTR 0x0c /* RTC Timer Trim register */
775 #define RDCR 0x10 /* RTC Day Counter register */
776 #define RYCR 0x14 /* RTC Year Counter register */
777 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
778 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
779 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
780 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
781 #define SWCR 0x28 /* RTC Stopwatch Counter register */
782 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
783 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
784 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
785 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
787 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
788 #define PXA2XX_RTC(obj) \
789 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
791 typedef struct {
792 /*< private >*/
793 SysBusDevice parent_obj;
794 /*< public >*/
796 MemoryRegion iomem;
797 uint32_t rttr;
798 uint32_t rtsr;
799 uint32_t rtar;
800 uint32_t rdar1;
801 uint32_t rdar2;
802 uint32_t ryar1;
803 uint32_t ryar2;
804 uint32_t swar1;
805 uint32_t swar2;
806 uint32_t piar;
807 uint32_t last_rcnr;
808 uint32_t last_rdcr;
809 uint32_t last_rycr;
810 uint32_t last_swcr;
811 uint32_t last_rtcpicr;
812 int64_t last_hz;
813 int64_t last_sw;
814 int64_t last_pi;
815 QEMUTimer *rtc_hz;
816 QEMUTimer *rtc_rdal1;
817 QEMUTimer *rtc_rdal2;
818 QEMUTimer *rtc_swal1;
819 QEMUTimer *rtc_swal2;
820 QEMUTimer *rtc_pi;
821 qemu_irq rtc_irq;
822 } PXA2xxRTCState;
824 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
826 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
829 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
831 int64_t rt = qemu_clock_get_ms(rtc_clock);
832 s->last_rcnr += ((rt - s->last_hz) << 15) /
833 (1000 * ((s->rttr & 0xffff) + 1));
834 s->last_rdcr += ((rt - s->last_hz) << 15) /
835 (1000 * ((s->rttr & 0xffff) + 1));
836 s->last_hz = rt;
839 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
841 int64_t rt = qemu_clock_get_ms(rtc_clock);
842 if (s->rtsr & (1 << 12))
843 s->last_swcr += (rt - s->last_sw) / 10;
844 s->last_sw = rt;
847 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
849 int64_t rt = qemu_clock_get_ms(rtc_clock);
850 if (s->rtsr & (1 << 15))
851 s->last_swcr += rt - s->last_pi;
852 s->last_pi = rt;
855 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
856 uint32_t rtsr)
858 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
859 timer_mod(s->rtc_hz, s->last_hz +
860 (((s->rtar - s->last_rcnr) * 1000 *
861 ((s->rttr & 0xffff) + 1)) >> 15));
862 else
863 timer_del(s->rtc_hz);
865 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
866 timer_mod(s->rtc_rdal1, s->last_hz +
867 (((s->rdar1 - s->last_rdcr) * 1000 *
868 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
869 else
870 timer_del(s->rtc_rdal1);
872 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
873 timer_mod(s->rtc_rdal2, s->last_hz +
874 (((s->rdar2 - s->last_rdcr) * 1000 *
875 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
876 else
877 timer_del(s->rtc_rdal2);
879 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
880 timer_mod(s->rtc_swal1, s->last_sw +
881 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
882 else
883 timer_del(s->rtc_swal1);
885 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
886 timer_mod(s->rtc_swal2, s->last_sw +
887 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
888 else
889 timer_del(s->rtc_swal2);
891 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
892 timer_mod(s->rtc_pi, s->last_pi +
893 (s->piar & 0xffff) - s->last_rtcpicr);
894 else
895 timer_del(s->rtc_pi);
898 static inline void pxa2xx_rtc_hz_tick(void *opaque)
900 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
901 s->rtsr |= (1 << 0);
902 pxa2xx_rtc_alarm_update(s, s->rtsr);
903 pxa2xx_rtc_int_update(s);
906 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
908 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
909 s->rtsr |= (1 << 4);
910 pxa2xx_rtc_alarm_update(s, s->rtsr);
911 pxa2xx_rtc_int_update(s);
914 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
916 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
917 s->rtsr |= (1 << 6);
918 pxa2xx_rtc_alarm_update(s, s->rtsr);
919 pxa2xx_rtc_int_update(s);
922 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
924 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
925 s->rtsr |= (1 << 8);
926 pxa2xx_rtc_alarm_update(s, s->rtsr);
927 pxa2xx_rtc_int_update(s);
930 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
932 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
933 s->rtsr |= (1 << 10);
934 pxa2xx_rtc_alarm_update(s, s->rtsr);
935 pxa2xx_rtc_int_update(s);
938 static inline void pxa2xx_rtc_pi_tick(void *opaque)
940 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
941 s->rtsr |= (1 << 13);
942 pxa2xx_rtc_piupdate(s);
943 s->last_rtcpicr = 0;
944 pxa2xx_rtc_alarm_update(s, s->rtsr);
945 pxa2xx_rtc_int_update(s);
948 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
949 unsigned size)
951 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
953 switch (addr) {
954 case RTTR:
955 return s->rttr;
956 case RTSR:
957 return s->rtsr;
958 case RTAR:
959 return s->rtar;
960 case RDAR1:
961 return s->rdar1;
962 case RDAR2:
963 return s->rdar2;
964 case RYAR1:
965 return s->ryar1;
966 case RYAR2:
967 return s->ryar2;
968 case SWAR1:
969 return s->swar1;
970 case SWAR2:
971 return s->swar2;
972 case PIAR:
973 return s->piar;
974 case RCNR:
975 return s->last_rcnr +
976 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
977 (1000 * ((s->rttr & 0xffff) + 1));
978 case RDCR:
979 return s->last_rdcr +
980 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
981 (1000 * ((s->rttr & 0xffff) + 1));
982 case RYCR:
983 return s->last_rycr;
984 case SWCR:
985 if (s->rtsr & (1 << 12))
986 return s->last_swcr +
987 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
988 else
989 return s->last_swcr;
990 default:
991 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
992 break;
994 return 0;
997 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
998 uint64_t value64, unsigned size)
1000 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1001 uint32_t value = value64;
1003 switch (addr) {
1004 case RTTR:
1005 if (!(s->rttr & (1U << 31))) {
1006 pxa2xx_rtc_hzupdate(s);
1007 s->rttr = value;
1008 pxa2xx_rtc_alarm_update(s, s->rtsr);
1010 break;
1012 case RTSR:
1013 if ((s->rtsr ^ value) & (1 << 15))
1014 pxa2xx_rtc_piupdate(s);
1016 if ((s->rtsr ^ value) & (1 << 12))
1017 pxa2xx_rtc_swupdate(s);
1019 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1020 pxa2xx_rtc_alarm_update(s, value);
1022 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1023 pxa2xx_rtc_int_update(s);
1024 break;
1026 case RTAR:
1027 s->rtar = value;
1028 pxa2xx_rtc_alarm_update(s, s->rtsr);
1029 break;
1031 case RDAR1:
1032 s->rdar1 = value;
1033 pxa2xx_rtc_alarm_update(s, s->rtsr);
1034 break;
1036 case RDAR2:
1037 s->rdar2 = value;
1038 pxa2xx_rtc_alarm_update(s, s->rtsr);
1039 break;
1041 case RYAR1:
1042 s->ryar1 = value;
1043 pxa2xx_rtc_alarm_update(s, s->rtsr);
1044 break;
1046 case RYAR2:
1047 s->ryar2 = value;
1048 pxa2xx_rtc_alarm_update(s, s->rtsr);
1049 break;
1051 case SWAR1:
1052 pxa2xx_rtc_swupdate(s);
1053 s->swar1 = value;
1054 s->last_swcr = 0;
1055 pxa2xx_rtc_alarm_update(s, s->rtsr);
1056 break;
1058 case SWAR2:
1059 s->swar2 = value;
1060 pxa2xx_rtc_alarm_update(s, s->rtsr);
1061 break;
1063 case PIAR:
1064 s->piar = value;
1065 pxa2xx_rtc_alarm_update(s, s->rtsr);
1066 break;
1068 case RCNR:
1069 pxa2xx_rtc_hzupdate(s);
1070 s->last_rcnr = value;
1071 pxa2xx_rtc_alarm_update(s, s->rtsr);
1072 break;
1074 case RDCR:
1075 pxa2xx_rtc_hzupdate(s);
1076 s->last_rdcr = value;
1077 pxa2xx_rtc_alarm_update(s, s->rtsr);
1078 break;
1080 case RYCR:
1081 s->last_rycr = value;
1082 break;
1084 case SWCR:
1085 pxa2xx_rtc_swupdate(s);
1086 s->last_swcr = value;
1087 pxa2xx_rtc_alarm_update(s, s->rtsr);
1088 break;
1090 case RTCPICR:
1091 pxa2xx_rtc_piupdate(s);
1092 s->last_rtcpicr = value & 0xffff;
1093 pxa2xx_rtc_alarm_update(s, s->rtsr);
1094 break;
1096 default:
1097 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1101 static const MemoryRegionOps pxa2xx_rtc_ops = {
1102 .read = pxa2xx_rtc_read,
1103 .write = pxa2xx_rtc_write,
1104 .endianness = DEVICE_NATIVE_ENDIAN,
1107 static int pxa2xx_rtc_init(SysBusDevice *dev)
1109 PXA2xxRTCState *s = PXA2XX_RTC(dev);
1110 struct tm tm;
1111 int wom;
1113 s->rttr = 0x7fff;
1114 s->rtsr = 0;
1116 qemu_get_timedate(&tm, 0);
1117 wom = ((tm.tm_mday - 1) / 7) + 1;
1119 s->last_rcnr = (uint32_t) mktimegm(&tm);
1120 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1121 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1122 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1123 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1124 s->last_swcr = (tm.tm_hour << 19) |
1125 (tm.tm_min << 13) | (tm.tm_sec << 7);
1126 s->last_rtcpicr = 0;
1127 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1129 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1130 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1131 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1132 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1133 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1134 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1136 sysbus_init_irq(dev, &s->rtc_irq);
1138 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s,
1139 "pxa2xx-rtc", 0x10000);
1140 sysbus_init_mmio(dev, &s->iomem);
1142 return 0;
1145 static void pxa2xx_rtc_pre_save(void *opaque)
1147 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1149 pxa2xx_rtc_hzupdate(s);
1150 pxa2xx_rtc_piupdate(s);
1151 pxa2xx_rtc_swupdate(s);
1154 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1156 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1158 pxa2xx_rtc_alarm_update(s, s->rtsr);
1160 return 0;
1163 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1164 .name = "pxa2xx_rtc",
1165 .version_id = 0,
1166 .minimum_version_id = 0,
1167 .pre_save = pxa2xx_rtc_pre_save,
1168 .post_load = pxa2xx_rtc_post_load,
1169 .fields = (VMStateField[]) {
1170 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1171 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1172 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1173 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1174 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1175 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1176 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1177 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1178 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1179 VMSTATE_UINT32(piar, PXA2xxRTCState),
1180 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1181 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1182 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1183 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1184 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1185 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1186 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1187 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1188 VMSTATE_END_OF_LIST(),
1192 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1194 DeviceClass *dc = DEVICE_CLASS(klass);
1195 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1197 k->init = pxa2xx_rtc_init;
1198 dc->desc = "PXA2xx RTC Controller";
1199 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1202 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1203 .name = TYPE_PXA2XX_RTC,
1204 .parent = TYPE_SYS_BUS_DEVICE,
1205 .instance_size = sizeof(PXA2xxRTCState),
1206 .class_init = pxa2xx_rtc_sysbus_class_init,
1209 /* I2C Interface */
1211 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1212 #define PXA2XX_I2C_SLAVE(obj) \
1213 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1215 typedef struct PXA2xxI2CSlaveState {
1216 I2CSlave parent_obj;
1218 PXA2xxI2CState *host;
1219 } PXA2xxI2CSlaveState;
1221 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1222 #define PXA2XX_I2C(obj) \
1223 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1225 struct PXA2xxI2CState {
1226 /*< private >*/
1227 SysBusDevice parent_obj;
1228 /*< public >*/
1230 MemoryRegion iomem;
1231 PXA2xxI2CSlaveState *slave;
1232 I2CBus *bus;
1233 qemu_irq irq;
1234 uint32_t offset;
1235 uint32_t region_size;
1237 uint16_t control;
1238 uint16_t status;
1239 uint8_t ibmr;
1240 uint8_t data;
1243 #define IBMR 0x80 /* I2C Bus Monitor register */
1244 #define IDBR 0x88 /* I2C Data Buffer register */
1245 #define ICR 0x90 /* I2C Control register */
1246 #define ISR 0x98 /* I2C Status register */
1247 #define ISAR 0xa0 /* I2C Slave Address register */
1249 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1251 uint16_t level = 0;
1252 level |= s->status & s->control & (1 << 10); /* BED */
1253 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1254 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1255 level |= s->status & (1 << 9); /* SAD */
1256 qemu_set_irq(s->irq, !!level);
1259 /* These are only stubs now. */
1260 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1262 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1263 PXA2xxI2CState *s = slave->host;
1265 switch (event) {
1266 case I2C_START_SEND:
1267 s->status |= (1 << 9); /* set SAD */
1268 s->status &= ~(1 << 0); /* clear RWM */
1269 break;
1270 case I2C_START_RECV:
1271 s->status |= (1 << 9); /* set SAD */
1272 s->status |= 1 << 0; /* set RWM */
1273 break;
1274 case I2C_FINISH:
1275 s->status |= (1 << 4); /* set SSD */
1276 break;
1277 case I2C_NACK:
1278 s->status |= 1 << 1; /* set ACKNAK */
1279 break;
1281 pxa2xx_i2c_update(s);
1284 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1286 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1287 PXA2xxI2CState *s = slave->host;
1289 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1290 return 0;
1293 if (s->status & (1 << 0)) { /* RWM */
1294 s->status |= 1 << 6; /* set ITE */
1296 pxa2xx_i2c_update(s);
1298 return s->data;
1301 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1303 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1304 PXA2xxI2CState *s = slave->host;
1306 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1307 return 1;
1310 if (!(s->status & (1 << 0))) { /* RWM */
1311 s->status |= 1 << 7; /* set IRF */
1312 s->data = data;
1314 pxa2xx_i2c_update(s);
1316 return 1;
1319 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1320 unsigned size)
1322 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1323 I2CSlave *slave;
1325 addr -= s->offset;
1326 switch (addr) {
1327 case ICR:
1328 return s->control;
1329 case ISR:
1330 return s->status | (i2c_bus_busy(s->bus) << 2);
1331 case ISAR:
1332 slave = I2C_SLAVE(s->slave);
1333 return slave->address;
1334 case IDBR:
1335 return s->data;
1336 case IBMR:
1337 if (s->status & (1 << 2))
1338 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1339 else
1340 s->ibmr = 0;
1341 return s->ibmr;
1342 default:
1343 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1344 break;
1346 return 0;
1349 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1350 uint64_t value64, unsigned size)
1352 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1353 uint32_t value = value64;
1354 int ack;
1356 addr -= s->offset;
1357 switch (addr) {
1358 case ICR:
1359 s->control = value & 0xfff7;
1360 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1361 /* TODO: slave mode */
1362 if (value & (1 << 0)) { /* START condition */
1363 if (s->data & 1)
1364 s->status |= 1 << 0; /* set RWM */
1365 else
1366 s->status &= ~(1 << 0); /* clear RWM */
1367 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1368 } else {
1369 if (s->status & (1 << 0)) { /* RWM */
1370 s->data = i2c_recv(s->bus);
1371 if (value & (1 << 2)) /* ACKNAK */
1372 i2c_nack(s->bus);
1373 ack = 1;
1374 } else
1375 ack = !i2c_send(s->bus, s->data);
1378 if (value & (1 << 1)) /* STOP condition */
1379 i2c_end_transfer(s->bus);
1381 if (ack) {
1382 if (value & (1 << 0)) /* START condition */
1383 s->status |= 1 << 6; /* set ITE */
1384 else
1385 if (s->status & (1 << 0)) /* RWM */
1386 s->status |= 1 << 7; /* set IRF */
1387 else
1388 s->status |= 1 << 6; /* set ITE */
1389 s->status &= ~(1 << 1); /* clear ACKNAK */
1390 } else {
1391 s->status |= 1 << 6; /* set ITE */
1392 s->status |= 1 << 10; /* set BED */
1393 s->status |= 1 << 1; /* set ACKNAK */
1396 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1397 if (value & (1 << 4)) /* MA */
1398 i2c_end_transfer(s->bus);
1399 pxa2xx_i2c_update(s);
1400 break;
1402 case ISR:
1403 s->status &= ~(value & 0x07f0);
1404 pxa2xx_i2c_update(s);
1405 break;
1407 case ISAR:
1408 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f);
1409 break;
1411 case IDBR:
1412 s->data = value & 0xff;
1413 break;
1415 default:
1416 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1420 static const MemoryRegionOps pxa2xx_i2c_ops = {
1421 .read = pxa2xx_i2c_read,
1422 .write = pxa2xx_i2c_write,
1423 .endianness = DEVICE_NATIVE_ENDIAN,
1426 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1427 .name = "pxa2xx_i2c_slave",
1428 .version_id = 1,
1429 .minimum_version_id = 1,
1430 .fields = (VMStateField[]) {
1431 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1432 VMSTATE_END_OF_LIST()
1436 static const VMStateDescription vmstate_pxa2xx_i2c = {
1437 .name = "pxa2xx_i2c",
1438 .version_id = 1,
1439 .minimum_version_id = 1,
1440 .fields = (VMStateField[]) {
1441 VMSTATE_UINT16(control, PXA2xxI2CState),
1442 VMSTATE_UINT16(status, PXA2xxI2CState),
1443 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1444 VMSTATE_UINT8(data, PXA2xxI2CState),
1445 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1446 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1447 VMSTATE_END_OF_LIST()
1451 static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
1453 /* Nothing to do. */
1454 return 0;
1457 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1459 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1461 k->init = pxa2xx_i2c_slave_init;
1462 k->event = pxa2xx_i2c_event;
1463 k->recv = pxa2xx_i2c_rx;
1464 k->send = pxa2xx_i2c_tx;
1467 static const TypeInfo pxa2xx_i2c_slave_info = {
1468 .name = TYPE_PXA2XX_I2C_SLAVE,
1469 .parent = TYPE_I2C_SLAVE,
1470 .instance_size = sizeof(PXA2xxI2CSlaveState),
1471 .class_init = pxa2xx_i2c_slave_class_init,
1474 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1475 qemu_irq irq, uint32_t region_size)
1477 DeviceState *dev;
1478 SysBusDevice *i2c_dev;
1479 PXA2xxI2CState *s;
1480 I2CBus *i2cbus;
1482 dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1483 qdev_prop_set_uint32(dev, "size", region_size + 1);
1484 qdev_prop_set_uint32(dev, "offset", base & region_size);
1485 qdev_init_nofail(dev);
1487 i2c_dev = SYS_BUS_DEVICE(dev);
1488 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1489 sysbus_connect_irq(i2c_dev, 0, irq);
1491 s = PXA2XX_I2C(i2c_dev);
1492 /* FIXME: Should the slave device really be on a separate bus? */
1493 i2cbus = i2c_init_bus(dev, "dummy");
1494 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0);
1495 s->slave = PXA2XX_I2C_SLAVE(dev);
1496 s->slave->host = s;
1498 return s;
1501 static int pxa2xx_i2c_initfn(SysBusDevice *sbd)
1503 DeviceState *dev = DEVICE(sbd);
1504 PXA2xxI2CState *s = PXA2XX_I2C(dev);
1506 s->bus = i2c_init_bus(dev, "i2c");
1508 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
1509 "pxa2xx-i2c", s->region_size);
1510 sysbus_init_mmio(sbd, &s->iomem);
1511 sysbus_init_irq(sbd, &s->irq);
1513 return 0;
1516 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1518 return s->bus;
1521 static Property pxa2xx_i2c_properties[] = {
1522 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1523 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1524 DEFINE_PROP_END_OF_LIST(),
1527 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1529 DeviceClass *dc = DEVICE_CLASS(klass);
1530 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1532 k->init = pxa2xx_i2c_initfn;
1533 dc->desc = "PXA2xx I2C Bus Controller";
1534 dc->vmsd = &vmstate_pxa2xx_i2c;
1535 dc->props = pxa2xx_i2c_properties;
1538 static const TypeInfo pxa2xx_i2c_info = {
1539 .name = TYPE_PXA2XX_I2C,
1540 .parent = TYPE_SYS_BUS_DEVICE,
1541 .instance_size = sizeof(PXA2xxI2CState),
1542 .class_init = pxa2xx_i2c_class_init,
1545 /* PXA Inter-IC Sound Controller */
1546 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1548 i2s->rx_len = 0;
1549 i2s->tx_len = 0;
1550 i2s->fifo_len = 0;
1551 i2s->clk = 0x1a;
1552 i2s->control[0] = 0x00;
1553 i2s->control[1] = 0x00;
1554 i2s->status = 0x00;
1555 i2s->mask = 0x00;
1558 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1559 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1560 #define SACR_DREC(val) (val & (1 << 3))
1561 #define SACR_DPRL(val) (val & (1 << 4))
1563 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1565 int rfs, tfs;
1566 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1567 !SACR_DREC(i2s->control[1]);
1568 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1569 i2s->enable && !SACR_DPRL(i2s->control[1]);
1571 qemu_set_irq(i2s->rx_dma, rfs);
1572 qemu_set_irq(i2s->tx_dma, tfs);
1574 i2s->status &= 0xe0;
1575 if (i2s->fifo_len < 16 || !i2s->enable)
1576 i2s->status |= 1 << 0; /* TNF */
1577 if (i2s->rx_len)
1578 i2s->status |= 1 << 1; /* RNE */
1579 if (i2s->enable)
1580 i2s->status |= 1 << 2; /* BSY */
1581 if (tfs)
1582 i2s->status |= 1 << 3; /* TFS */
1583 if (rfs)
1584 i2s->status |= 1 << 4; /* RFS */
1585 if (!(i2s->tx_len && i2s->enable))
1586 i2s->status |= i2s->fifo_len << 8; /* TFL */
1587 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1589 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1592 #define SACR0 0x00 /* Serial Audio Global Control register */
1593 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1594 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1595 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1596 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1597 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1598 #define SADR 0x80 /* Serial Audio Data register */
1600 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1601 unsigned size)
1603 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1605 switch (addr) {
1606 case SACR0:
1607 return s->control[0];
1608 case SACR1:
1609 return s->control[1];
1610 case SASR0:
1611 return s->status;
1612 case SAIMR:
1613 return s->mask;
1614 case SAICR:
1615 return 0;
1616 case SADIV:
1617 return s->clk;
1618 case SADR:
1619 if (s->rx_len > 0) {
1620 s->rx_len --;
1621 pxa2xx_i2s_update(s);
1622 return s->codec_in(s->opaque);
1624 return 0;
1625 default:
1626 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1627 break;
1629 return 0;
1632 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1633 uint64_t value, unsigned size)
1635 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1636 uint32_t *sample;
1638 switch (addr) {
1639 case SACR0:
1640 if (value & (1 << 3)) /* RST */
1641 pxa2xx_i2s_reset(s);
1642 s->control[0] = value & 0xff3d;
1643 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1644 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1645 s->codec_out(s->opaque, *sample);
1646 s->status &= ~(1 << 7); /* I2SOFF */
1648 if (value & (1 << 4)) /* EFWR */
1649 printf("%s: Attempt to use special function\n", __FUNCTION__);
1650 s->enable = (value & 9) == 1; /* ENB && !RST*/
1651 pxa2xx_i2s_update(s);
1652 break;
1653 case SACR1:
1654 s->control[1] = value & 0x0039;
1655 if (value & (1 << 5)) /* ENLBF */
1656 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1657 if (value & (1 << 4)) /* DPRL */
1658 s->fifo_len = 0;
1659 pxa2xx_i2s_update(s);
1660 break;
1661 case SAIMR:
1662 s->mask = value & 0x0078;
1663 pxa2xx_i2s_update(s);
1664 break;
1665 case SAICR:
1666 s->status &= ~(value & (3 << 5));
1667 pxa2xx_i2s_update(s);
1668 break;
1669 case SADIV:
1670 s->clk = value & 0x007f;
1671 break;
1672 case SADR:
1673 if (s->tx_len && s->enable) {
1674 s->tx_len --;
1675 pxa2xx_i2s_update(s);
1676 s->codec_out(s->opaque, value);
1677 } else if (s->fifo_len < 16) {
1678 s->fifo[s->fifo_len ++] = value;
1679 pxa2xx_i2s_update(s);
1681 break;
1682 default:
1683 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1687 static const MemoryRegionOps pxa2xx_i2s_ops = {
1688 .read = pxa2xx_i2s_read,
1689 .write = pxa2xx_i2s_write,
1690 .endianness = DEVICE_NATIVE_ENDIAN,
1693 static const VMStateDescription vmstate_pxa2xx_i2s = {
1694 .name = "pxa2xx_i2s",
1695 .version_id = 0,
1696 .minimum_version_id = 0,
1697 .fields = (VMStateField[]) {
1698 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1699 VMSTATE_UINT32(status, PXA2xxI2SState),
1700 VMSTATE_UINT32(mask, PXA2xxI2SState),
1701 VMSTATE_UINT32(clk, PXA2xxI2SState),
1702 VMSTATE_INT32(enable, PXA2xxI2SState),
1703 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1704 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1705 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1706 VMSTATE_END_OF_LIST()
1710 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1712 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1713 uint32_t *sample;
1715 /* Signal FIFO errors */
1716 if (s->enable && s->tx_len)
1717 s->status |= 1 << 5; /* TUR */
1718 if (s->enable && s->rx_len)
1719 s->status |= 1 << 6; /* ROR */
1721 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1722 * handle the cases where it makes a difference. */
1723 s->tx_len = tx - s->fifo_len;
1724 s->rx_len = rx;
1725 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1726 if (s->enable)
1727 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1728 s->codec_out(s->opaque, *sample);
1729 pxa2xx_i2s_update(s);
1732 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1733 hwaddr base,
1734 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1736 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1);
1738 s->irq = irq;
1739 s->rx_dma = rx_dma;
1740 s->tx_dma = tx_dma;
1741 s->data_req = pxa2xx_i2s_data_req;
1743 pxa2xx_i2s_reset(s);
1745 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1746 "pxa2xx-i2s", 0x100000);
1747 memory_region_add_subregion(sysmem, base, &s->iomem);
1749 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1751 return s;
1754 /* PXA Fast Infra-red Communications Port */
1755 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
1756 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
1758 struct PXA2xxFIrState {
1759 /*< private >*/
1760 SysBusDevice parent_obj;
1761 /*< public >*/
1763 MemoryRegion iomem;
1764 qemu_irq irq;
1765 qemu_irq rx_dma;
1766 qemu_irq tx_dma;
1767 uint32_t enable;
1768 CharDriverState *chr;
1770 uint8_t control[3];
1771 uint8_t status[2];
1773 uint32_t rx_len;
1774 uint32_t rx_start;
1775 uint8_t rx_fifo[64];
1778 static void pxa2xx_fir_reset(DeviceState *d)
1780 PXA2xxFIrState *s = PXA2XX_FIR(d);
1782 s->control[0] = 0x00;
1783 s->control[1] = 0x00;
1784 s->control[2] = 0x00;
1785 s->status[0] = 0x00;
1786 s->status[1] = 0x00;
1787 s->enable = 0;
1790 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1792 static const int tresh[4] = { 8, 16, 32, 0 };
1793 int intr = 0;
1794 if ((s->control[0] & (1 << 4)) && /* RXE */
1795 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1796 s->status[0] |= 1 << 4; /* RFS */
1797 else
1798 s->status[0] &= ~(1 << 4); /* RFS */
1799 if (s->control[0] & (1 << 3)) /* TXE */
1800 s->status[0] |= 1 << 3; /* TFS */
1801 else
1802 s->status[0] &= ~(1 << 3); /* TFS */
1803 if (s->rx_len)
1804 s->status[1] |= 1 << 2; /* RNE */
1805 else
1806 s->status[1] &= ~(1 << 2); /* RNE */
1807 if (s->control[0] & (1 << 4)) /* RXE */
1808 s->status[1] |= 1 << 0; /* RSY */
1809 else
1810 s->status[1] &= ~(1 << 0); /* RSY */
1812 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1813 (s->status[0] & (1 << 4)); /* RFS */
1814 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1815 (s->status[0] & (1 << 3)); /* TFS */
1816 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1817 (s->status[0] & (1 << 6)); /* EOC */
1818 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1819 (s->status[0] & (1 << 1)); /* TUR */
1820 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1822 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1823 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1825 qemu_set_irq(s->irq, intr && s->enable);
1828 #define ICCR0 0x00 /* FICP Control register 0 */
1829 #define ICCR1 0x04 /* FICP Control register 1 */
1830 #define ICCR2 0x08 /* FICP Control register 2 */
1831 #define ICDR 0x0c /* FICP Data register */
1832 #define ICSR0 0x14 /* FICP Status register 0 */
1833 #define ICSR1 0x18 /* FICP Status register 1 */
1834 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1836 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1837 unsigned size)
1839 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1840 uint8_t ret;
1842 switch (addr) {
1843 case ICCR0:
1844 return s->control[0];
1845 case ICCR1:
1846 return s->control[1];
1847 case ICCR2:
1848 return s->control[2];
1849 case ICDR:
1850 s->status[0] &= ~0x01;
1851 s->status[1] &= ~0x72;
1852 if (s->rx_len) {
1853 s->rx_len --;
1854 ret = s->rx_fifo[s->rx_start ++];
1855 s->rx_start &= 63;
1856 pxa2xx_fir_update(s);
1857 return ret;
1859 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1860 break;
1861 case ICSR0:
1862 return s->status[0];
1863 case ICSR1:
1864 return s->status[1] | (1 << 3); /* TNF */
1865 case ICFOR:
1866 return s->rx_len;
1867 default:
1868 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1869 break;
1871 return 0;
1874 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1875 uint64_t value64, unsigned size)
1877 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1878 uint32_t value = value64;
1879 uint8_t ch;
1881 switch (addr) {
1882 case ICCR0:
1883 s->control[0] = value;
1884 if (!(value & (1 << 4))) /* RXE */
1885 s->rx_len = s->rx_start = 0;
1886 if (!(value & (1 << 3))) { /* TXE */
1887 /* Nop */
1889 s->enable = value & 1; /* ITR */
1890 if (!s->enable)
1891 s->status[0] = 0;
1892 pxa2xx_fir_update(s);
1893 break;
1894 case ICCR1:
1895 s->control[1] = value;
1896 break;
1897 case ICCR2:
1898 s->control[2] = value & 0x3f;
1899 pxa2xx_fir_update(s);
1900 break;
1901 case ICDR:
1902 if (s->control[2] & (1 << 2)) /* TXP */
1903 ch = value;
1904 else
1905 ch = ~value;
1906 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1907 qemu_chr_fe_write(s->chr, &ch, 1);
1908 break;
1909 case ICSR0:
1910 s->status[0] &= ~(value & 0x66);
1911 pxa2xx_fir_update(s);
1912 break;
1913 case ICFOR:
1914 break;
1915 default:
1916 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1920 static const MemoryRegionOps pxa2xx_fir_ops = {
1921 .read = pxa2xx_fir_read,
1922 .write = pxa2xx_fir_write,
1923 .endianness = DEVICE_NATIVE_ENDIAN,
1926 static int pxa2xx_fir_is_empty(void *opaque)
1928 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1929 return (s->rx_len < 64);
1932 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1934 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1935 if (!(s->control[0] & (1 << 4))) /* RXE */
1936 return;
1938 while (size --) {
1939 s->status[1] |= 1 << 4; /* EOF */
1940 if (s->rx_len >= 64) {
1941 s->status[1] |= 1 << 6; /* ROR */
1942 break;
1945 if (s->control[2] & (1 << 3)) /* RXP */
1946 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1947 else
1948 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1951 pxa2xx_fir_update(s);
1954 static void pxa2xx_fir_event(void *opaque, int event)
1958 static void pxa2xx_fir_instance_init(Object *obj)
1960 PXA2xxFIrState *s = PXA2XX_FIR(obj);
1961 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1963 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s,
1964 "pxa2xx-fir", 0x1000);
1965 sysbus_init_mmio(sbd, &s->iomem);
1966 sysbus_init_irq(sbd, &s->irq);
1967 sysbus_init_irq(sbd, &s->rx_dma);
1968 sysbus_init_irq(sbd, &s->tx_dma);
1971 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
1973 PXA2xxFIrState *s = PXA2XX_FIR(dev);
1975 if (s->chr) {
1976 qemu_chr_fe_claim_no_fail(s->chr);
1977 qemu_chr_add_handlers(s->chr, pxa2xx_fir_is_empty,
1978 pxa2xx_fir_rx, pxa2xx_fir_event, s);
1982 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
1984 PXA2xxFIrState *s = opaque;
1986 return s->rx_start < ARRAY_SIZE(s->rx_fifo);
1989 static const VMStateDescription pxa2xx_fir_vmsd = {
1990 .name = "pxa2xx-fir",
1991 .version_id = 1,
1992 .minimum_version_id = 1,
1993 .fields = (VMStateField[]) {
1994 VMSTATE_UINT32(enable, PXA2xxFIrState),
1995 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3),
1996 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2),
1997 VMSTATE_UINT32(rx_len, PXA2xxFIrState),
1998 VMSTATE_UINT32(rx_start, PXA2xxFIrState),
1999 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate),
2000 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64),
2001 VMSTATE_END_OF_LIST()
2005 static Property pxa2xx_fir_properties[] = {
2006 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr),
2007 DEFINE_PROP_END_OF_LIST(),
2010 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data)
2012 DeviceClass *dc = DEVICE_CLASS(klass);
2014 dc->realize = pxa2xx_fir_realize;
2015 dc->vmsd = &pxa2xx_fir_vmsd;
2016 dc->props = pxa2xx_fir_properties;
2017 dc->reset = pxa2xx_fir_reset;
2020 static const TypeInfo pxa2xx_fir_info = {
2021 .name = TYPE_PXA2XX_FIR,
2022 .parent = TYPE_SYS_BUS_DEVICE,
2023 .instance_size = sizeof(PXA2xxFIrState),
2024 .class_init = pxa2xx_fir_class_init,
2025 .instance_init = pxa2xx_fir_instance_init,
2028 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2029 hwaddr base,
2030 qemu_irq irq, qemu_irq rx_dma,
2031 qemu_irq tx_dma,
2032 CharDriverState *chr)
2034 DeviceState *dev;
2035 SysBusDevice *sbd;
2037 dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
2038 qdev_prop_set_chr(dev, "chardev", chr);
2039 qdev_init_nofail(dev);
2040 sbd = SYS_BUS_DEVICE(dev);
2041 sysbus_mmio_map(sbd, 0, base);
2042 sysbus_connect_irq(sbd, 0, irq);
2043 sysbus_connect_irq(sbd, 1, rx_dma);
2044 sysbus_connect_irq(sbd, 2, tx_dma);
2045 return PXA2XX_FIR(dev);
2048 static void pxa2xx_reset(void *opaque, int line, int level)
2050 PXA2xxState *s = (PXA2xxState *) opaque;
2052 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2053 cpu_reset(CPU(s->cpu));
2054 /* TODO: reset peripherals */
2058 /* Initialise a PXA270 integrated chip (ARM based core). */
2059 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2060 unsigned int sdram_size, const char *revision)
2062 PXA2xxState *s;
2063 int i;
2064 DriveInfo *dinfo;
2065 s = g_new0(PXA2xxState, 1);
2067 if (revision && strncmp(revision, "pxa27", 5)) {
2068 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2069 exit(1);
2071 if (!revision)
2072 revision = "pxa270";
2074 s->cpu = cpu_arm_init(revision);
2075 if (s->cpu == NULL) {
2076 fprintf(stderr, "Unable to find CPU definition\n");
2077 exit(1);
2079 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2081 /* SDRAM & Internal Memory Storage */
2082 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size,
2083 &error_fatal);
2084 vmstate_register_ram_global(&s->sdram);
2085 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2086 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000,
2087 &error_fatal);
2088 vmstate_register_ram_global(&s->internal);
2089 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2090 &s->internal);
2092 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2094 s->dma = pxa27x_dma_init(0x40000000,
2095 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2097 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2098 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2099 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2100 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2101 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2102 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2103 NULL);
2105 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2107 dinfo = drive_get(IF_SD, 0, 0);
2108 if (!dinfo) {
2109 fprintf(stderr, "qemu: missing SecureDigital device\n");
2110 exit(1);
2112 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2113 blk_by_legacy_dinfo(dinfo),
2114 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2115 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2116 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2118 for (i = 0; pxa270_serial[i].io_base; i++) {
2119 if (serial_hds[i]) {
2120 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2121 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2122 14857000 / 16, serial_hds[i],
2123 DEVICE_NATIVE_ENDIAN);
2124 } else {
2125 break;
2128 if (serial_hds[i])
2129 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2130 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2131 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2132 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2133 serial_hds[i]);
2135 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2136 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2138 s->cm_base = 0x41300000;
2139 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2140 s->clkcfg = 0x00000009; /* Turbo mode active */
2141 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2142 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2143 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2145 pxa2xx_setup_cp14(s);
2147 s->mm_base = 0x48000000;
2148 s->mm_regs[MDMRS >> 2] = 0x00020002;
2149 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2150 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2151 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2152 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2153 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2155 s->pm_base = 0x40f00000;
2156 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2157 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2158 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2160 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2161 s->ssp = g_new0(SSIBus *, i);
2162 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2163 DeviceState *dev;
2164 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2165 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2166 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2169 if (usb_enabled()) {
2170 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2171 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2174 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2175 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2177 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2178 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2180 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2181 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2182 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2183 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2185 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2186 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2187 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2188 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2190 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2191 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2193 /* GPIO1 resets the processor */
2194 /* The handler can be overridden by board-specific code */
2195 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2196 return s;
2199 /* Initialise a PXA255 integrated chip (ARM based core). */
2200 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2202 PXA2xxState *s;
2203 int i;
2204 DriveInfo *dinfo;
2206 s = g_new0(PXA2xxState, 1);
2208 s->cpu = cpu_arm_init("pxa255");
2209 if (s->cpu == NULL) {
2210 fprintf(stderr, "Unable to find CPU definition\n");
2211 exit(1);
2213 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2215 /* SDRAM & Internal Memory Storage */
2216 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size,
2217 &error_fatal);
2218 vmstate_register_ram_global(&s->sdram);
2219 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2220 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2221 PXA2XX_INTERNAL_SIZE, &error_fatal);
2222 vmstate_register_ram_global(&s->internal);
2223 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2224 &s->internal);
2226 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2228 s->dma = pxa255_dma_init(0x40000000,
2229 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2231 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2232 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2233 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2234 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2235 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2236 NULL);
2238 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2240 dinfo = drive_get(IF_SD, 0, 0);
2241 if (!dinfo) {
2242 fprintf(stderr, "qemu: missing SecureDigital device\n");
2243 exit(1);
2245 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2246 blk_by_legacy_dinfo(dinfo),
2247 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2248 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2249 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2251 for (i = 0; pxa255_serial[i].io_base; i++) {
2252 if (serial_hds[i]) {
2253 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2254 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2255 14745600 / 16, serial_hds[i],
2256 DEVICE_NATIVE_ENDIAN);
2257 } else {
2258 break;
2261 if (serial_hds[i])
2262 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2263 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2264 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2265 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2266 serial_hds[i]);
2268 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2269 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2271 s->cm_base = 0x41300000;
2272 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2273 s->clkcfg = 0x00000009; /* Turbo mode active */
2274 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2275 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2276 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2278 pxa2xx_setup_cp14(s);
2280 s->mm_base = 0x48000000;
2281 s->mm_regs[MDMRS >> 2] = 0x00020002;
2282 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2283 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2284 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2285 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2286 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2288 s->pm_base = 0x40f00000;
2289 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2290 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2291 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2293 for (i = 0; pxa255_ssp[i].io_base; i ++);
2294 s->ssp = g_new0(SSIBus *, i);
2295 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2296 DeviceState *dev;
2297 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2298 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2299 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2302 if (usb_enabled()) {
2303 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2304 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2307 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2308 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2310 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2311 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2313 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2314 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2315 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2316 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2318 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2319 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2320 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2321 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2323 /* GPIO1 resets the processor */
2324 /* The handler can be overridden by board-specific code */
2325 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2326 return s;
2329 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2331 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
2332 DeviceClass *dc = DEVICE_CLASS(klass);
2334 sdc->init = pxa2xx_ssp_init;
2335 dc->reset = pxa2xx_ssp_reset;
2336 dc->vmsd = &vmstate_pxa2xx_ssp;
2339 static const TypeInfo pxa2xx_ssp_info = {
2340 .name = TYPE_PXA2XX_SSP,
2341 .parent = TYPE_SYS_BUS_DEVICE,
2342 .instance_size = sizeof(PXA2xxSSPState),
2343 .class_init = pxa2xx_ssp_class_init,
2346 static void pxa2xx_register_types(void)
2348 type_register_static(&pxa2xx_i2c_slave_info);
2349 type_register_static(&pxa2xx_ssp_info);
2350 type_register_static(&pxa2xx_i2c_info);
2351 type_register_static(&pxa2xx_rtc_sysbus_info);
2352 type_register_static(&pxa2xx_fir_info);
2355 type_init(pxa2xx_register_types)