hw/arm/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "hw/sysbus.h"
  19 #include "hw/arm/arm.h"
  20 #include "net/net.h"
  21 #include "exec/address-spaces.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/boards.h"
  24 #include "hw/block/flash.h"
  25 #include "sysemu/block-backend.h"
  26 #include "hw/loader.h"
  27 #include "hw/misc/zynq-xadc.h"
  28 #include "hw/ssi.h"
  29 #include "qemu/error-report.h"
  30
  31 #define NUM_SPI_FLASHES 4
  32 #define NUM_QSPI_FLASHES 2
  33 #define NUM_QSPI_BUSSES 2
  34
  35 #define FLASH_SIZE (64 * 1024 * 1024)
  36 #define FLASH_SECTOR_SIZE (128 * 1024)
  37
  38 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  39
  40 #define MPCORE_PERIPHBASE 0xF8F00000
  41 #define ZYNQ_BOARD_MIDR 0x413FC090
  42
  43 static const int dma_irqs[8] = {
  44     46, 47, 48, 49, 72, 73, 74, 75
  45 };
  46
  47 #define BOARD_SETUP_ADDR        0x100
  48
  49 #define SLCR_LOCK_OFFSET        0x004
  50 #define SLCR_UNLOCK_OFFSET      0x008
  51 #define SLCR_ARM_PLL_OFFSET     0x100
  52
  53 #define SLCR_XILINX_UNLOCK_KEY  0xdf0d
  54 #define SLCR_XILINX_LOCK_KEY    0x767b
  55
  56 #define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
  57                         extract32((x), 12,  4) << 16)
  58
  59 /* Write immediate val to address r0 + addr. r0 should contain base offset
  60  * of the SLCR block. Clobbers r1.
  61  */
  62
  63 #define SLCR_WRITE(addr, val) \
  64     0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
  65     0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
  66     0xe5801000 + (addr)
  67
  68 static void zynq_write_board_setup(ARMCPU *cpu,
  69                                    const struct arm_boot_info *info)
  70 {
  71     int n;
  72     uint32_t board_setup_blob[] = {
  73         0xe3a004f8, /* mov r0, #0xf8000000 */
  74         SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
  75         SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
  76         SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
  77         0xe12fff1e, /* bx lr */
  78     };
  79     for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
  80         board_setup_blob[n] = tswap32(board_setup_blob[n]);
  81     }
  82     rom_add_blob_fixed("board-setup", board_setup_blob,
  83                        sizeof(board_setup_blob), BOARD_SETUP_ADDR);
  84 }
  85
  86 static struct arm_boot_info zynq_binfo = {};
  87
  88 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  89 {
  90     DeviceState *dev;
  91     SysBusDevice *s;
  92
  93     dev = qdev_create(NULL, "cadence_gem");
  94     if (nd->used) {
  95         qemu_check_nic_model(nd, "cadence_gem");
  96         qdev_set_nic_properties(dev, nd);
  97     }
  98     qdev_init_nofail(dev);
  99     s = SYS_BUS_DEVICE(dev);
 100     sysbus_mmio_map(s, 0, base);
 101     sysbus_connect_irq(s, 0, irq);
 102 }
 103
 104 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
 105                                          bool is_qspi)
 106 {
 107     DeviceState *dev;
 108     SysBusDevice *busdev;
 109     SSIBus *spi;
 110     DeviceState *flash_dev;
 111     int i, j;
 112     int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
 113     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
 114
 115     dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
 116     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
 117     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
 118     qdev_prop_set_uint8(dev, "num-busses", num_busses);
 119     qdev_init_nofail(dev);
 120     busdev = SYS_BUS_DEVICE(dev);
 121     sysbus_mmio_map(busdev, 0, base_addr);
 122     if (is_qspi) {
 123         sysbus_mmio_map(busdev, 1, 0xFC000000);
 124     }
 125     sysbus_connect_irq(busdev, 0, irq);
 126
 127     for (i = 0; i < num_busses; ++i) {
 128         char bus_name[16];
 129         qemu_irq cs_line;
 130
 131         snprintf(bus_name, 16, "spi%d", i);
 132         spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
 133
 134         for (j = 0; j < num_ss; ++j) {
 135             flash_dev = ssi_create_slave(spi, "n25q128");
 136
 137             cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 138             sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
 139         }
 140     }
 141
 142 }
 143
 144 static void zynq_init(MachineState *machine)
 145 {
 146     ram_addr_t ram_size = machine->ram_size;
 147     const char *cpu_model = machine->cpu_model;
 148     const char *kernel_filename = machine->kernel_filename;
 149     const char *kernel_cmdline = machine->kernel_cmdline;
 150     const char *initrd_filename = machine->initrd_filename;
 151     ObjectClass *cpu_oc;
 152     ARMCPU *cpu;
 153     MemoryRegion *address_space_mem = get_system_memory();
 154     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
 155     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
 156     DeviceState *dev;
 157     SysBusDevice *busdev;
 158     qemu_irq pic[64];
 159     int n;
 160
 161     if (!cpu_model) {
 162         cpu_model = "cortex-a9";
 163     }
 164     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 165
 166     cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
 167
 168     /* By default A9 CPUs have EL3 enabled.  This board does not
 169      * currently support EL3 so the CPU EL3 property is disabled before
 170      * realization.
 171      */
 172     if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
 173         object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
 174     }
 175
 176     object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
 177                             &error_fatal);
 178     object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
 179                             &error_fatal);
 180     object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
 181
 182     /* max 2GB ram */
 183     if (ram_size > 0x80000000) {
 184         ram_size = 0x80000000;
 185     }
 186
 187     /* DDR remapped to address zero.  */
 188     memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
 189                                          ram_size);
 190     memory_region_add_subregion(address_space_mem, 0, ext_ram);
 191
 192     /* 256K of on-chip memory */
 193     memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
 194                            &error_fatal);
 195     vmstate_register_ram_global(ocm_ram);
 196     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
 197
 198     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 199
 200     /* AMD */
 201     pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
 202                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 203                           FLASH_SECTOR_SIZE,
 204                           FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
 205                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
 206                               0);
 207
 208     dev = qdev_create(NULL, "xilinx,zynq_slcr");
 209     qdev_init_nofail(dev);
 210     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
 211
 212     dev = qdev_create(NULL, "a9mpcore_priv");
 213     qdev_prop_set_uint32(dev, "num-cpu", 1);
 214     qdev_init_nofail(dev);
 215     busdev = SYS_BUS_DEVICE(dev);
 216     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 217     sysbus_connect_irq(busdev, 0,
 218                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 219
 220     for (n = 0; n < 64; n++) {
 221         pic[n] = qdev_get_gpio_in(dev, n);
 222     }
 223
 224     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
 225     zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
 226     zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
 227
 228     sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
 229     sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
 230
 231     sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
 232     sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
 233
 234     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 235             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 236     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 237             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 238
 239     gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
 240     gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
 241
 242     dev = qdev_create(NULL, "generic-sdhci");
 243     qdev_init_nofail(dev);
 244     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
 245     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
 246
 247     dev = qdev_create(NULL, "generic-sdhci");
 248     qdev_init_nofail(dev);
 249     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
 250     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
 251
 252     dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
 253     qdev_init_nofail(dev);
 254     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
 255     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
 256
 257     dev = qdev_create(NULL, "pl330");
 258     qdev_prop_set_uint8(dev, "num_chnls",  8);
 259     qdev_prop_set_uint8(dev, "num_periph_req",  4);
 260     qdev_prop_set_uint8(dev, "num_events",  16);
 261
 262     qdev_prop_set_uint8(dev, "data_width",  64);
 263     qdev_prop_set_uint8(dev, "wr_cap",  8);
 264     qdev_prop_set_uint8(dev, "wr_q_dep",  16);
 265     qdev_prop_set_uint8(dev, "rd_cap",  8);
 266     qdev_prop_set_uint8(dev, "rd_q_dep",  16);
 267     qdev_prop_set_uint16(dev, "data_buffer_dep",  256);
 268
 269     qdev_init_nofail(dev);
 270     busdev = SYS_BUS_DEVICE(dev);
 271     sysbus_mmio_map(busdev, 0, 0xF8003000);
 272     sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
 273     for (n = 0; n < 8; ++n) { /* event irqs */
 274         sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
 275     }
 276
 277     zynq_binfo.ram_size = ram_size;
 278     zynq_binfo.kernel_filename = kernel_filename;
 279     zynq_binfo.kernel_cmdline = kernel_cmdline;
 280     zynq_binfo.initrd_filename = initrd_filename;
 281     zynq_binfo.nb_cpus = 1;
 282     zynq_binfo.board_id = 0xd32;
 283     zynq_binfo.loader_start = 0;
 284     zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 285     zynq_binfo.write_board_setup = zynq_write_board_setup;
 286
 287     arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
 288 }
 289
 290 static void zynq_machine_init(MachineClass *mc)
 291 {
 292     mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
 293     mc->init = zynq_init;
 294     mc->block_default_type = IF_SCSI;
 295     mc->max_cpus = 1;
 296     mc->no_sdcard = 1;
 297 }
 298
 299 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)