hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/i386/pc.h"
  24 #include "hw/southbridge/piix.h"
  25 #include "hw/irq.h"
  26 #include "hw/isa/apm.h"
  27 #include "hw/i2c/pm_smbus.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/acpi/acpi.h"
  31 #include "sysemu/runstate.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/xen.h"
  34 #include "qapi/error.h"
  35 #include "qemu/range.h"
  36 #include "exec/address-spaces.h"
  37 #include "hw/acpi/pcihp.h"
  38 #include "hw/acpi/cpu_hotplug.h"
  39 #include "hw/acpi/cpu.h"
  40 #include "hw/hotplug.h"
  41 #include "hw/mem/pc-dimm.h"
  42 #include "hw/mem/nvdimm.h"
  43 #include "hw/acpi/memory_hotplug.h"
  44 #include "hw/acpi/acpi_dev_interface.h"
  45 #include "migration/vmstate.h"
  46 #include "hw/core/cpu.h"
  47 #include "trace.h"
  48
  49 #define GPE_BASE 0xafe0
  50 #define GPE_LEN 4
  51
  52 struct pci_status {
  53     uint32_t up; /* deprecated, maintained for migration compatibility */
  54     uint32_t down;
  55 };
  56
  57 typedef struct PIIX4PMState {
  58     /*< private >*/
  59     PCIDevice parent_obj;
  60     /*< public >*/
  61
  62     MemoryRegion io;
  63     uint32_t io_base;
  64
  65     MemoryRegion io_gpe;
  66     ACPIREGS ar;
  67
  68     APMState apm;
  69
  70     PMSMBus smb;
  71     uint32_t smb_io_base;
  72
  73     qemu_irq irq;
  74     qemu_irq smi_irq;
  75     int smm_enabled;
  76     Notifier machine_ready;
  77     Notifier powerdown_notifier;
  78
  79     AcpiPciHpState acpi_pci_hotplug;
  80     bool use_acpi_pci_hotplug;
  81
  82     uint8_t disable_s3;
  83     uint8_t disable_s4;
  84     uint8_t s4_val;
  85
  86     bool cpu_hotplug_legacy;
  87     AcpiCpuHotplug gpe_cpu;
  88     CPUHotplugState cpuhp_state;
  89
  90     MemHotplugState acpi_memory_hotplug;
  91 } PIIX4PMState;
  92
  93 #define PIIX4_PM(obj) \
  94     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
  95
  96 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  97                                            PCIBus *bus, PIIX4PMState *s);
  98
  99 #define ACPI_ENABLE 0xf1
 100 #define ACPI_DISABLE 0xf0
 101
 102 static void pm_tmr_timer(ACPIREGS *ar)
 103 {
 104     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 105     acpi_update_sci(&s->ar, s->irq);
 106 }
 107
 108 static void apm_ctrl_changed(uint32_t val, void *arg)
 109 {
 110     PIIX4PMState *s = arg;
 111     PCIDevice *d = PCI_DEVICE(s);
 112
 113     /* ACPI specs 3.0, 4.7.2.5 */
 114     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 115     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 116         return;
 117     }
 118
 119     if (d->config[0x5b] & (1 << 1)) {
 120         if (s->smi_irq) {
 121             qemu_irq_raise(s->smi_irq);
 122         }
 123     }
 124 }
 125
 126 static void pm_io_space_update(PIIX4PMState *s)
 127 {
 128     PCIDevice *d = PCI_DEVICE(s);
 129
 130     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 131     s->io_base &= 0xffc0;
 132
 133     memory_region_transaction_begin();
 134     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 135     memory_region_set_address(&s->io, s->io_base);
 136     memory_region_transaction_commit();
 137 }
 138
 139 static void smbus_io_space_update(PIIX4PMState *s)
 140 {
 141     PCIDevice *d = PCI_DEVICE(s);
 142
 143     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 144     s->smb_io_base &= 0xffc0;
 145
 146     memory_region_transaction_begin();
 147     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 148     memory_region_set_address(&s->smb.io, s->smb_io_base);
 149     memory_region_transaction_commit();
 150 }
 151
 152 static void pm_write_config(PCIDevice *d,
 153                             uint32_t address, uint32_t val, int len)
 154 {
 155     pci_default_write_config(d, address, val, len);
 156     if (range_covers_byte(address, len, 0x80) ||
 157         ranges_overlap(address, len, 0x40, 4)) {
 158         pm_io_space_update((PIIX4PMState *)d);
 159     }
 160     if (range_covers_byte(address, len, 0xd2) ||
 161         ranges_overlap(address, len, 0x90, 4)) {
 162         smbus_io_space_update((PIIX4PMState *)d);
 163     }
 164 }
 165
 166 static int vmstate_acpi_post_load(void *opaque, int version_id)
 167 {
 168     PIIX4PMState *s = opaque;
 169
 170     pm_io_space_update(s);
 171     smbus_io_space_update(s);
 172     return 0;
 173 }
 174
 175 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 176  {                                                                   \
 177      .name       = (stringify(_field)),                              \
 178      .version_id = 0,                                                \
 179      .info       = &vmstate_info_uint16,                             \
 180      .size       = sizeof(uint16_t),                                 \
 181      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 182      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 183  }
 184
 185 static const VMStateDescription vmstate_gpe = {
 186     .name = "gpe",
 187     .version_id = 1,
 188     .minimum_version_id = 1,
 189     .fields = (VMStateField[]) {
 190         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 191         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 192         VMSTATE_END_OF_LIST()
 193     }
 194 };
 195
 196 static const VMStateDescription vmstate_pci_status = {
 197     .name = "pci_status",
 198     .version_id = 1,
 199     .minimum_version_id = 1,
 200     .fields = (VMStateField[]) {
 201         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 202         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 203         VMSTATE_END_OF_LIST()
 204     }
 205 };
 206
 207 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 208 {
 209     PIIX4PMState *s = opaque;
 210     return s->use_acpi_pci_hotplug;
 211 }
 212
 213 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 214 {
 215     PIIX4PMState *s = opaque;
 216     return !s->use_acpi_pci_hotplug;
 217 }
 218
 219 static bool vmstate_test_use_memhp(void *opaque)
 220 {
 221     PIIX4PMState *s = opaque;
 222     return s->acpi_memory_hotplug.is_enabled;
 223 }
 224
 225 static const VMStateDescription vmstate_memhp_state = {
 226     .name = "piix4_pm/memhp",
 227     .version_id = 1,
 228     .minimum_version_id = 1,
 229     .minimum_version_id_old = 1,
 230     .needed = vmstate_test_use_memhp,
 231     .fields      = (VMStateField[]) {
 232         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 233         VMSTATE_END_OF_LIST()
 234     }
 235 };
 236
 237 static bool vmstate_test_use_cpuhp(void *opaque)
 238 {
 239     PIIX4PMState *s = opaque;
 240     return !s->cpu_hotplug_legacy;
 241 }
 242
 243 static int vmstate_cpuhp_pre_load(void *opaque)
 244 {
 245     Object *obj = OBJECT(opaque);
 246     object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort);
 247     return 0;
 248 }
 249
 250 static const VMStateDescription vmstate_cpuhp_state = {
 251     .name = "piix4_pm/cpuhp",
 252     .version_id = 1,
 253     .minimum_version_id = 1,
 254     .minimum_version_id_old = 1,
 255     .needed = vmstate_test_use_cpuhp,
 256     .pre_load = vmstate_cpuhp_pre_load,
 257     .fields      = (VMStateField[]) {
 258         VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
 259         VMSTATE_END_OF_LIST()
 260     }
 261 };
 262
 263 static bool piix4_vmstate_need_smbus(void *opaque, int version_id)
 264 {
 265     return pm_smbus_vmstate_needed();
 266 }
 267
 268 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 269  * To support incoming qemu-kvm 1.2 migration, change version_id
 270  * and minimum_version_id to 2 below (which breaks migration from
 271  * qemu 1.2).
 272  *
 273  */
 274 static const VMStateDescription vmstate_acpi = {
 275     .name = "piix4_pm",
 276     .version_id = 3,
 277     .minimum_version_id = 3,
 278     .post_load = vmstate_acpi_post_load,
 279     .fields = (VMStateField[]) {
 280         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 281         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 282         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 283         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 284         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 285         VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3,
 286                             pmsmb_vmstate, PMSMBus),
 287         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 288         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 289         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 290         VMSTATE_STRUCT_TEST(
 291             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 292             PIIX4PMState,
 293             vmstate_test_no_use_acpi_pci_hotplug,
 294             2, vmstate_pci_status,
 295             struct AcpiPciHpPciStatus),
 296         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 297                             vmstate_test_use_acpi_pci_hotplug),
 298         VMSTATE_END_OF_LIST()
 299     },
 300     .subsections = (const VMStateDescription*[]) {
 301          &vmstate_memhp_state,
 302          &vmstate_cpuhp_state,
 303          NULL
 304     }
 305 };
 306
 307 static void piix4_pm_reset(DeviceState *dev)
 308 {
 309     PIIX4PMState *s = PIIX4_PM(dev);
 310     PCIDevice *d = PCI_DEVICE(s);
 311     uint8_t *pci_conf = d->config;
 312
 313     pci_conf[0x58] = 0;
 314     pci_conf[0x59] = 0;
 315     pci_conf[0x5a] = 0;
 316     pci_conf[0x5b] = 0;
 317
 318     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 319     pci_conf[0x80] = 0;
 320
 321     if (!s->smm_enabled) {
 322         /* Mark SMM as already inited (until KVM supports SMM). */
 323         pci_conf[0x5B] = 0x02;
 324     }
 325     pm_io_space_update(s);
 326     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 327 }
 328
 329 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 330 {
 331     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 332
 333     assert(s != NULL);
 334     acpi_pm1_evt_power_down(&s->ar);
 335 }
 336
 337 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev,
 338                                     DeviceState *dev, Error **errp)
 339 {
 340     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 341
 342     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 343         acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
 344     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 345         if (!s->acpi_memory_hotplug.is_enabled) {
 346             error_setg(errp,
 347                 "memory hotplug is not enabled: %s.memory-hotplug-support "
 348                 "is not set", object_get_typename(OBJECT(s)));
 349         }
 350     } else if (
 351                !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 352         error_setg(errp, "acpi: device pre plug request for not supported"
 353                    " device type: %s", object_get_typename(OBJECT(dev)));
 354     }
 355 }
 356
 357 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 358                                  DeviceState *dev, Error **errp)
 359 {
 360     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 361
 362     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 363         if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
 364             nvdimm_acpi_plug_cb(hotplug_dev, dev);
 365         } else {
 366             acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
 367                                 dev, errp);
 368         }
 369     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 370         acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
 371     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 372         if (s->cpu_hotplug_legacy) {
 373             legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
 374         } else {
 375             acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 376         }
 377     } else {
 378         g_assert_not_reached();
 379     }
 380 }
 381
 382 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 383                                            DeviceState *dev, Error **errp)
 384 {
 385     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 386
 387     if (s->acpi_memory_hotplug.is_enabled &&
 388         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 389         acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
 390                                       dev, errp);
 391     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 392         acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug,
 393                                             dev, errp);
 394     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 395                !s->cpu_hotplug_legacy) {
 396         acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 397     } else {
 398         error_setg(errp, "acpi: device unplug request for not supported device"
 399                    " type: %s", object_get_typename(OBJECT(dev)));
 400     }
 401 }
 402
 403 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 404                                    DeviceState *dev, Error **errp)
 405 {
 406     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 407
 408     if (s->acpi_memory_hotplug.is_enabled &&
 409         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 410         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 411     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 412         acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
 413                                     errp);
 414     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 415                !s->cpu_hotplug_legacy) {
 416         acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
 417     } else {
 418         error_setg(errp, "acpi: device unplug for not supported device"
 419                    " type: %s", object_get_typename(OBJECT(dev)));
 420     }
 421 }
 422
 423 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 424 {
 425     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 426     PCIDevice *d = PCI_DEVICE(s);
 427     MemoryRegion *io_as = pci_address_space_io(d);
 428     uint8_t *pci_conf;
 429
 430     pci_conf = d->config;
 431     pci_conf[0x5f] = 0x10 |
 432         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 433     pci_conf[0x63] = 0x60;
 434     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 435         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 436 }
 437
 438 static void piix4_pm_add_propeties(PIIX4PMState *s)
 439 {
 440     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 441     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 442     static const uint32_t gpe0_blk = GPE_BASE;
 443     static const uint32_t gpe0_blk_len = GPE_LEN;
 444     static const uint16_t sci_int = 9;
 445
 446     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 447                                   &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
 448     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 449                                   &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
 450     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 451                                   &gpe0_blk, OBJ_PROP_FLAG_READ);
 452     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 453                                   &gpe0_blk_len, OBJ_PROP_FLAG_READ);
 454     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 455                                   &sci_int, OBJ_PROP_FLAG_READ);
 456     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 457                                   &s->io_base, OBJ_PROP_FLAG_READ);
 458 }
 459
 460 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 461 {
 462     PIIX4PMState *s = PIIX4_PM(dev);
 463     uint8_t *pci_conf;
 464
 465     pci_conf = dev->config;
 466     pci_conf[0x06] = 0x80;
 467     pci_conf[0x07] = 0x02;
 468     pci_conf[0x09] = 0x00;
 469     pci_conf[0x3d] = 0x01; // interrupt pin 1
 470
 471     /* APM */
 472     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 473
 474     if (!s->smm_enabled) {
 475         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 476          * support SMM mode. */
 477         pci_conf[0x5B] = 0x02;
 478     }
 479
 480     /* XXX: which specification is used ? The i82731AB has different
 481        mappings */
 482     pci_conf[0x90] = s->smb_io_base | 1;
 483     pci_conf[0x91] = s->smb_io_base >> 8;
 484     pci_conf[0xd2] = 0x09;
 485     pm_smbus_init(DEVICE(dev), &s->smb, true);
 486     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 487     memory_region_add_subregion(pci_address_space_io(dev),
 488                                 s->smb_io_base, &s->smb.io);
 489
 490     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 491     memory_region_set_enabled(&s->io, false);
 492     memory_region_add_subregion(pci_address_space_io(dev),
 493                                 0, &s->io);
 494
 495     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 496     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 497     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
 498     acpi_gpe_init(&s->ar, GPE_LEN);
 499
 500     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 501     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 502
 503     s->machine_ready.notify = piix4_pm_machine_ready;
 504     qemu_add_machine_init_done_notifier(&s->machine_ready);
 505
 506     piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
 507                                    pci_get_bus(dev), s);
 508     qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort);
 509
 510     piix4_pm_add_propeties(s);
 511 }
 512
 513 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 514                       qemu_irq sci_irq, qemu_irq smi_irq,
 515                       int smm_enabled, DeviceState **piix4_pm)
 516 {
 517     DeviceState *dev;
 518     PIIX4PMState *s;
 519
 520     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 521     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 522     if (piix4_pm) {
 523         *piix4_pm = dev;
 524     }
 525
 526     s = PIIX4_PM(dev);
 527     s->irq = sci_irq;
 528     s->smi_irq = smi_irq;
 529     s->smm_enabled = smm_enabled;
 530     if (xen_enabled()) {
 531         s->use_acpi_pci_hotplug = false;
 532     }
 533
 534     qdev_init_nofail(dev);
 535
 536     return s->smb.smbus;
 537 }
 538
 539 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 540 {
 541     PIIX4PMState *s = opaque;
 542     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 543
 544     trace_piix4_gpe_readb(addr, width, val);
 545     return val;
 546 }
 547
 548 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 549                        unsigned width)
 550 {
 551     PIIX4PMState *s = opaque;
 552
 553     trace_piix4_gpe_writeb(addr, width, val);
 554     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 555     acpi_update_sci(&s->ar, s->irq);
 556 }
 557
 558 static const MemoryRegionOps piix4_gpe_ops = {
 559     .read = gpe_readb,
 560     .write = gpe_writeb,
 561     .valid.min_access_size = 1,
 562     .valid.max_access_size = 4,
 563     .impl.min_access_size = 1,
 564     .impl.max_access_size = 1,
 565     .endianness = DEVICE_LITTLE_ENDIAN,
 566 };
 567
 568
 569 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
 570 {
 571     PIIX4PMState *s = PIIX4_PM(obj);
 572
 573     return s->cpu_hotplug_legacy;
 574 }
 575
 576 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
 577 {
 578     PIIX4PMState *s = PIIX4_PM(obj);
 579
 580     assert(!value);
 581     if (s->cpu_hotplug_legacy && value == false) {
 582         acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
 583                                    PIIX4_CPU_HOTPLUG_IO_BASE);
 584     }
 585     s->cpu_hotplug_legacy = value;
 586 }
 587
 588 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 589                                            PCIBus *bus, PIIX4PMState *s)
 590 {
 591     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 592                           "acpi-gpe0", GPE_LEN);
 593     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 594
 595     acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 596                     s->use_acpi_pci_hotplug);
 597
 598     s->cpu_hotplug_legacy = true;
 599     object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
 600                              piix4_get_cpu_hotplug_legacy,
 601                              piix4_set_cpu_hotplug_legacy);
 602     legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 603                                  PIIX4_CPU_HOTPLUG_IO_BASE);
 604
 605     if (s->acpi_memory_hotplug.is_enabled) {
 606         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
 607                                  ACPI_MEMORY_HOTPLUG_BASE);
 608     }
 609 }
 610
 611 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 612 {
 613     PIIX4PMState *s = PIIX4_PM(adev);
 614
 615     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 616     if (!s->cpu_hotplug_legacy) {
 617         acpi_cpu_ospm_status(&s->cpuhp_state, list);
 618     }
 619 }
 620
 621 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 622 {
 623     PIIX4PMState *s = PIIX4_PM(adev);
 624
 625     acpi_send_gpe_event(&s->ar, s->irq, ev);
 626 }
 627
 628 static Property piix4_pm_properties[] = {
 629     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 630     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 631     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 632     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 633     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 634                      use_acpi_pci_hotplug, true),
 635     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 636                      acpi_memory_hotplug.is_enabled, true),
 637     DEFINE_PROP_END_OF_LIST(),
 638 };
 639
 640 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 641 {
 642     DeviceClass *dc = DEVICE_CLASS(klass);
 643     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 644     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 645     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 646
 647     k->realize = piix4_pm_realize;
 648     k->config_write = pm_write_config;
 649     k->vendor_id = PCI_VENDOR_ID_INTEL;
 650     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 651     k->revision = 0x03;
 652     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 653     dc->reset = piix4_pm_reset;
 654     dc->desc = "PM";
 655     dc->vmsd = &vmstate_acpi;
 656     device_class_set_props(dc, piix4_pm_properties);
 657     /*
 658      * Reason: part of PIIX4 southbridge, needs to be wired up,
 659      * e.g. by mips_malta_init()
 660      */
 661     dc->user_creatable = false;
 662     dc->hotpluggable = false;
 663     hc->pre_plug = piix4_device_pre_plug_cb;
 664     hc->plug = piix4_device_plug_cb;
 665     hc->unplug_request = piix4_device_unplug_request_cb;
 666     hc->unplug = piix4_device_unplug_cb;
 667     adevc->ospm_status = piix4_ospm_status;
 668     adevc->send_event = piix4_send_gpe;
 669     adevc->madt_cpu = pc_madt_cpu_entry;
 670 }
 671
 672 static const TypeInfo piix4_pm_info = {
 673     .name          = TYPE_PIIX4_PM,
 674     .parent        = TYPE_PCI_DEVICE,
 675     .instance_size = sizeof(PIIX4PMState),
 676     .class_init    = piix4_pm_class_init,
 677     .interfaces = (InterfaceInfo[]) {
 678         { TYPE_HOTPLUG_HANDLER },
 679         { TYPE_ACPI_DEVICE_IF },
 680         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 681         { }
 682     }
 683 };
 684
 685 static void piix4_pm_register_types(void)
 686 {
 687     type_register_static(&piix4_pm_info);
 688 }
 689
 690 type_init(piix4_pm_register_types)