hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn
[qemu/ar7.git] / cpu-target.c
blob5af120e8aa1dadb6041baed4c3fce179df6b1c1c
1 /*
2 * Target-specific parts of the CPU object
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "exec/target_page.h"
24 #include "exec/page-protection.h"
25 #include "hw/qdev-core.h"
26 #include "hw/qdev-properties.h"
27 #include "qemu/error-report.h"
28 #include "qemu/qemu-print.h"
29 #include "migration/vmstate.h"
30 #ifdef CONFIG_USER_ONLY
31 #include "qemu.h"
32 #else
33 #include "hw/core/sysemu-cpu-ops.h"
34 #include "exec/address-spaces.h"
35 #include "exec/memory.h"
36 #endif
37 #include "sysemu/cpus.h"
38 #include "sysemu/tcg.h"
39 #include "exec/tswap.h"
40 #include "exec/replay-core.h"
41 #include "exec/cpu-common.h"
42 #include "exec/exec-all.h"
43 #include "exec/tb-flush.h"
44 #include "exec/translate-all.h"
45 #include "exec/log.h"
46 #include "hw/core/accel-cpu.h"
47 #include "trace/trace-root.h"
48 #include "qemu/accel.h"
50 #ifndef CONFIG_USER_ONLY
51 static int cpu_common_post_load(void *opaque, int version_id)
53 CPUState *cpu = opaque;
55 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
56 version_id is increased. */
57 cpu->interrupt_request &= ~0x01;
58 tlb_flush(cpu);
60 /* loadvm has just updated the content of RAM, bypassing the
61 * usual mechanisms that ensure we flush TBs for writes to
62 * memory we've translated code from. So we must flush all TBs,
63 * which will now be stale.
65 tb_flush(cpu);
67 return 0;
70 static int cpu_common_pre_load(void *opaque)
72 CPUState *cpu = opaque;
74 cpu->exception_index = -1;
76 return 0;
79 static bool cpu_common_exception_index_needed(void *opaque)
81 CPUState *cpu = opaque;
83 return tcg_enabled() && cpu->exception_index != -1;
86 static const VMStateDescription vmstate_cpu_common_exception_index = {
87 .name = "cpu_common/exception_index",
88 .version_id = 1,
89 .minimum_version_id = 1,
90 .needed = cpu_common_exception_index_needed,
91 .fields = (const VMStateField[]) {
92 VMSTATE_INT32(exception_index, CPUState),
93 VMSTATE_END_OF_LIST()
97 static bool cpu_common_crash_occurred_needed(void *opaque)
99 CPUState *cpu = opaque;
101 return cpu->crash_occurred;
104 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
105 .name = "cpu_common/crash_occurred",
106 .version_id = 1,
107 .minimum_version_id = 1,
108 .needed = cpu_common_crash_occurred_needed,
109 .fields = (const VMStateField[]) {
110 VMSTATE_BOOL(crash_occurred, CPUState),
111 VMSTATE_END_OF_LIST()
115 const VMStateDescription vmstate_cpu_common = {
116 .name = "cpu_common",
117 .version_id = 1,
118 .minimum_version_id = 1,
119 .pre_load = cpu_common_pre_load,
120 .post_load = cpu_common_post_load,
121 .fields = (const VMStateField[]) {
122 VMSTATE_UINT32(halted, CPUState),
123 VMSTATE_UINT32(interrupt_request, CPUState),
124 VMSTATE_END_OF_LIST()
126 .subsections = (const VMStateDescription * const []) {
127 &vmstate_cpu_common_exception_index,
128 &vmstate_cpu_common_crash_occurred,
129 NULL
132 #endif
134 bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
136 /* cache the cpu class for the hotpath */
137 cpu->cc = CPU_GET_CLASS(cpu);
139 if (!accel_cpu_common_realize(cpu, errp)) {
140 return false;
143 /* Wait until cpu initialization complete before exposing cpu. */
144 cpu_list_add(cpu);
146 #ifdef CONFIG_USER_ONLY
147 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
148 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
149 #else
150 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
151 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
153 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
154 vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
156 #endif /* CONFIG_USER_ONLY */
158 return true;
161 void cpu_exec_unrealizefn(CPUState *cpu)
163 #ifndef CONFIG_USER_ONLY
164 CPUClass *cc = CPU_GET_CLASS(cpu);
166 if (cc->sysemu_ops->legacy_vmsd != NULL) {
167 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
169 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
170 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
172 #endif
174 cpu_list_remove(cpu);
176 * Now that the vCPU has been removed from the RCU list, we can call
177 * accel_cpu_common_unrealize, which may free fields using call_rcu.
179 accel_cpu_common_unrealize(cpu);
183 * This can't go in hw/core/cpu.c because that file is compiled only
184 * once for both user-mode and system builds.
186 static Property cpu_common_props[] = {
187 #ifdef CONFIG_USER_ONLY
189 * Create a property for the user-only object, so users can
190 * adjust prctl(PR_SET_UNALIGN) from the command-line.
191 * Has no effect if the target does not support the feature.
193 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
194 prctl_unalign_sigbus, false),
195 #else
197 * Create a memory property for system CPU object, so users can
198 * wire up its memory. The default if no link is set up is to use
199 * the system address space.
201 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
202 MemoryRegion *),
203 #endif
204 DEFINE_PROP_END_OF_LIST(),
207 #ifndef CONFIG_USER_ONLY
208 static bool cpu_get_start_powered_off(Object *obj, Error **errp)
210 CPUState *cpu = CPU(obj);
211 return cpu->start_powered_off;
214 static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
216 CPUState *cpu = CPU(obj);
217 cpu->start_powered_off = value;
219 #endif
221 void cpu_class_init_props(DeviceClass *dc)
223 #ifndef CONFIG_USER_ONLY
224 ObjectClass *oc = OBJECT_CLASS(dc);
227 * We can't use DEFINE_PROP_BOOL in the Property array for this
228 * property, because we want this to be settable after realize.
230 object_class_property_add_bool(oc, "start-powered-off",
231 cpu_get_start_powered_off,
232 cpu_set_start_powered_off);
233 #endif
235 device_class_set_props(dc, cpu_common_props);
238 void cpu_exec_initfn(CPUState *cpu)
240 cpu->as = NULL;
241 cpu->num_ases = 0;
243 #ifndef CONFIG_USER_ONLY
244 cpu->thread_id = qemu_get_thread_id();
245 cpu->memory = get_system_memory();
246 object_ref(OBJECT(cpu->memory));
247 #endif
250 char *cpu_model_from_type(const char *typename)
252 const char *suffix = "-" CPU_RESOLVING_TYPE;
254 if (!object_class_by_name(typename)) {
255 return NULL;
258 if (g_str_has_suffix(typename, suffix)) {
259 return g_strndup(typename, strlen(typename) - strlen(suffix));
262 return g_strdup(typename);
265 const char *parse_cpu_option(const char *cpu_option)
267 ObjectClass *oc;
268 CPUClass *cc;
269 gchar **model_pieces;
270 const char *cpu_type;
272 model_pieces = g_strsplit(cpu_option, ",", 2);
273 if (!model_pieces[0]) {
274 error_report("-cpu option cannot be empty");
275 exit(1);
278 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
279 if (oc == NULL) {
280 error_report("unable to find CPU model '%s'", model_pieces[0]);
281 g_strfreev(model_pieces);
282 exit(EXIT_FAILURE);
285 cpu_type = object_class_get_name(oc);
286 cc = CPU_CLASS(oc);
287 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
288 g_strfreev(model_pieces);
289 return cpu_type;
292 #ifndef cpu_list
293 static void cpu_list_entry(gpointer data, gpointer user_data)
295 CPUClass *cc = CPU_CLASS(OBJECT_CLASS(data));
296 const char *typename = object_class_get_name(OBJECT_CLASS(data));
297 g_autofree char *model = cpu_model_from_type(typename);
299 if (cc->deprecation_note) {
300 qemu_printf(" %s (deprecated)\n", model);
301 } else {
302 qemu_printf(" %s\n", model);
306 static void cpu_list(void)
308 GSList *list;
310 list = object_class_get_list_sorted(TYPE_CPU, false);
311 qemu_printf("Available CPUs:\n");
312 g_slist_foreach(list, cpu_list_entry, NULL);
313 g_slist_free(list);
315 #endif
317 void list_cpus(void)
319 cpu_list();
322 /* enable or disable single step mode. EXCP_DEBUG is returned by the
323 CPU loop after each instruction */
324 void cpu_single_step(CPUState *cpu, int enabled)
326 if (cpu->singlestep_enabled != enabled) {
327 cpu->singlestep_enabled = enabled;
329 #if !defined(CONFIG_USER_ONLY)
330 const AccelOpsClass *ops = cpus_get_accel();
331 if (ops->update_guest_debug) {
332 ops->update_guest_debug(cpu);
334 #endif
336 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
340 void cpu_abort(CPUState *cpu, const char *fmt, ...)
342 va_list ap;
343 va_list ap2;
345 va_start(ap, fmt);
346 va_copy(ap2, ap);
347 fprintf(stderr, "qemu: fatal: ");
348 vfprintf(stderr, fmt, ap);
349 fprintf(stderr, "\n");
350 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
351 if (qemu_log_separate()) {
352 FILE *logfile = qemu_log_trylock();
353 if (logfile) {
354 fprintf(logfile, "qemu: fatal: ");
355 vfprintf(logfile, fmt, ap2);
356 fprintf(logfile, "\n");
357 cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
358 qemu_log_unlock(logfile);
361 va_end(ap2);
362 va_end(ap);
363 replay_finish();
364 #if defined(CONFIG_USER_ONLY)
366 struct sigaction act;
367 sigfillset(&act.sa_mask);
368 act.sa_handler = SIG_DFL;
369 act.sa_flags = 0;
370 sigaction(SIGABRT, &act, NULL);
372 #endif
373 abort();
376 /* physical memory access (slow version, mainly for debug) */
377 #if defined(CONFIG_USER_ONLY)
378 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
379 void *ptr, size_t len, bool is_write)
381 int flags;
382 vaddr l, page;
383 void * p;
384 uint8_t *buf = ptr;
385 ssize_t written;
386 int ret = -1;
387 int fd = -1;
389 while (len > 0) {
390 page = addr & TARGET_PAGE_MASK;
391 l = (page + TARGET_PAGE_SIZE) - addr;
392 if (l > len)
393 l = len;
394 flags = page_get_flags(page);
395 if (!(flags & PAGE_VALID)) {
396 goto out_close;
398 if (is_write) {
399 if (flags & PAGE_WRITE) {
400 /* XXX: this code should not depend on lock_user */
401 p = lock_user(VERIFY_WRITE, addr, l, 0);
402 if (!p) {
403 goto out_close;
405 memcpy(p, buf, l);
406 unlock_user(p, addr, l);
407 } else {
408 /* Bypass the host page protection using ptrace. */
409 if (fd == -1) {
410 fd = open("/proc/self/mem", O_WRONLY);
411 if (fd == -1) {
412 goto out;
416 * If there is a TranslationBlock and we weren't bypassing the
417 * host page protection, the memcpy() above would SEGV,
418 * ultimately leading to page_unprotect(). So invalidate the
419 * translations manually. Both invalidation and pwrite() must
420 * be under mmap_lock() in order to prevent the creation of
421 * another TranslationBlock in between.
423 mmap_lock();
424 tb_invalidate_phys_range(addr, addr + l - 1);
425 written = pwrite(fd, buf, l,
426 (off_t)(uintptr_t)g2h_untagged(addr));
427 mmap_unlock();
428 if (written != l) {
429 goto out_close;
432 } else if (flags & PAGE_READ) {
433 /* XXX: this code should not depend on lock_user */
434 p = lock_user(VERIFY_READ, addr, l, 1);
435 if (!p) {
436 goto out_close;
438 memcpy(buf, p, l);
439 unlock_user(p, addr, 0);
440 } else {
441 /* Bypass the host page protection using ptrace. */
442 if (fd == -1) {
443 fd = open("/proc/self/mem", O_RDONLY);
444 if (fd == -1) {
445 goto out;
448 if (pread(fd, buf, l,
449 (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
450 goto out_close;
453 len -= l;
454 buf += l;
455 addr += l;
457 ret = 0;
458 out_close:
459 if (fd != -1) {
460 close(fd);
462 out:
463 return ret;
465 #endif
467 bool target_words_bigendian(void)
469 return TARGET_BIG_ENDIAN;
472 const char *target_name(void)
474 return TARGET_NAME;