1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/erst.h"
47 #include "hw/acpi/piix4.h"
48 #include "sysemu/tpm_backend.h"
49 #include "hw/rtc/mc146818rtc_regs.h"
50 #include "migration/vmstate.h"
51 #include "hw/mem/memory-device.h"
52 #include "hw/mem/nvdimm.h"
53 #include "sysemu/numa.h"
54 #include "sysemu/reset.h"
55 #include "hw/hyperv/vmbus-bridge.h"
57 /* Supported chipsets: */
58 #include "hw/southbridge/ich9.h"
59 #include "hw/acpi/pcihp.h"
60 #include "hw/i386/fw_cfg.h"
61 #include "hw/i386/pc.h"
62 #include "hw/pci/pci_bus.h"
63 #include "hw/pci-host/i440fx.h"
64 #include "hw/pci-host/q35.h"
65 #include "hw/i386/x86-iommu.h"
67 #include "hw/acpi/aml-build.h"
68 #include "hw/acpi/utils.h"
69 #include "hw/acpi/pci.h"
70 #include "hw/acpi/cxl.h"
72 #include "qom/qom-qobject.h"
73 #include "hw/i386/amd_iommu.h"
74 #include "hw/i386/intel_iommu.h"
75 #include "hw/virtio/virtio-iommu.h"
77 #include "hw/acpi/hmat.h"
78 #include "hw/acpi/viot.h"
80 #include CONFIG_DEVICES
82 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
84 * a little bit, there should be plenty of free space since the DSDT
85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
87 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
88 #define ACPI_BUILD_ALIGN_SIZE 0x1000
90 #define ACPI_BUILD_TABLE_SIZE 0x20000
92 /* #define DEBUG_ACPI_BUILD */
93 #ifdef DEBUG_ACPI_BUILD
94 #define ACPI_BUILD_DPRINTF(fmt, ...) \
95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
97 #define ACPI_BUILD_DPRINTF(fmt, ...)
100 typedef struct AcpiPmInfo
{
103 bool pcihp_bridge_en
;
105 bool smi_on_cpu_unplug
;
109 uint16_t cpu_hp_io_base
;
110 uint16_t pcihp_io_base
;
111 uint16_t pcihp_io_len
;
114 typedef struct AcpiMiscInfo
{
117 TPMVersion tpm_version
;
121 typedef struct FwCfgTPMConfig
{
122 uint32_t tpmppi_address
;
124 uint8_t tpmppi_version
;
125 } QEMU_PACKED FwCfgTPMConfig
;
127 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
);
129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio
= {
130 .space_id
= AML_AS_SYSTEM_IO
,
131 .address
= NVDIMM_ACPI_IO_BASE
,
132 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
135 static void init_common_fadt_data(MachineState
*ms
, Object
*o
,
138 X86MachineState
*x86ms
= X86_MACHINE(ms
);
140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
141 * behavior for compatibility irrelevant to smm_enabled, which doesn't
142 * comforms to ACPI spec.
144 bool smm_enabled
= object_property_get_bool(o
, "smm-compat", NULL
) ?
145 true : x86_machine_is_smm_enabled(x86ms
);
146 uint32_t io
= object_property_get_uint(o
, ACPI_PM_PROP_PM_IO_BASE
, NULL
);
147 AmlAddressSpace as
= AML_AS_SYSTEM_IO
;
148 AcpiFadtData fadt
= {
151 (1 << ACPI_FADT_F_WBINVD
) |
152 (1 << ACPI_FADT_F_PROC_C1
) |
153 (1 << ACPI_FADT_F_SLP_BUTTON
) |
154 (1 << ACPI_FADT_F_RTC_S4
) |
155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
) |
156 /* APIC destination mode ("Flat Logical") has an upper limit of 8
157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
160 ((ms
->smp
.max_cpus
> 8) ?
161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
) : 0),
162 .int_model
= 1 /* Multiple APIC */,
163 .rtc_century
= RTC_CENTURY
,
164 .plvl2_lat
= 0xfff /* C2 state not supported */,
165 .plvl3_lat
= 0xfff /* C3 state not supported */,
166 .smi_cmd
= smm_enabled
? ACPI_PORT_SMI_CMD
: 0,
167 .sci_int
= object_property_get_uint(o
, ACPI_PM_PROP_SCI_INT
, NULL
),
170 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_ENABLE_CMD
, NULL
) :
174 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_DISABLE_CMD
, NULL
) :
176 .pm1a_evt
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
},
177 .pm1a_cnt
= { .space_id
= as
, .bit_width
= 2 * 8,
178 .address
= io
+ 0x04 },
179 .pm_tmr
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
+ 0x08 },
180 .gpe0_blk
= { .space_id
= as
, .bit_width
=
181 object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK_LEN
, NULL
) * 8,
182 .address
= object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK
, NULL
)
187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
188 * Flags, bit offset 1 - 8042.
190 fadt
.iapc_boot_arch
= iapc_boot_arch_8042();
195 static Object
*object_resolve_type_unambiguous(const char *typename
)
198 Object
*o
= object_resolve_path_type("", typename
, &ambig
);
206 static void acpi_get_pm_info(MachineState
*machine
, AcpiPmInfo
*pm
)
208 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
209 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
210 Object
*obj
= piix
? piix
: lpc
;
212 pm
->cpu_hp_io_base
= 0;
213 pm
->pcihp_io_base
= 0;
214 pm
->pcihp_io_len
= 0;
215 pm
->smi_on_cpuhp
= false;
216 pm
->smi_on_cpu_unplug
= false;
219 init_common_fadt_data(machine
, obj
, &pm
->fadt
);
221 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
223 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
226 uint64_t smi_features
= object_property_get_uint(lpc
,
227 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP
, NULL
);
228 struct AcpiGenericAddress r
= { .space_id
= AML_AS_SYSTEM_IO
,
229 .bit_width
= 8, .address
= ICH9_RST_CNT_IOPORT
};
230 pm
->fadt
.reset_reg
= r
;
231 pm
->fadt
.reset_val
= 0xf;
232 pm
->fadt
.flags
|= 1 << ACPI_FADT_F_RESET_REG_SUP
;
233 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
235 !!(smi_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
));
236 pm
->smi_on_cpu_unplug
=
237 !!(smi_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
));
240 object_property_get_uint(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
242 object_property_get_uint(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
244 /* Fill in optional s3/s4 related properties */
245 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
247 pm
->s3_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
249 pm
->s3_disabled
= false;
252 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
254 pm
->s4_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
256 pm
->s4_disabled
= false;
259 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
261 pm
->s4_val
= qnum_get_uint(qobject_to(QNum
, o
));
267 pm
->pcihp_bridge_en
=
268 object_property_get_bool(obj
, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE
,
271 object_property_get_bool(obj
, ACPI_PM_PROP_ACPI_PCI_ROOTHP
,
275 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
277 info
->has_hpet
= hpet_find();
279 info
->tpm_version
= tpm_get_version(tpm_find());
284 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
285 * On i386 arch we only have two pci hosts, so we can look only for them.
287 Object
*acpi_get_i386_pci_host(void)
291 host
= PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL
));
293 host
= PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL
));
299 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
303 pci_host
= acpi_get_i386_pci_host();
309 range_set_bounds1(hole
,
310 object_property_get_uint(pci_host
,
311 PCI_HOST_PROP_PCI_HOLE_START
,
313 object_property_get_uint(pci_host
,
314 PCI_HOST_PROP_PCI_HOLE_END
,
316 range_set_bounds1(hole64
,
317 object_property_get_uint(pci_host
,
318 PCI_HOST_PROP_PCI_HOLE64_START
,
320 object_property_get_uint(pci_host
,
321 PCI_HOST_PROP_PCI_HOLE64_END
,
325 static void acpi_align_size(GArray
*blob
, unsigned align
)
327 /* Align size to multiple of given size. This reduces the chance
328 * we need to change size in the future (breaking cross version migration).
330 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
335 * 5.2.6 Firmware ACPI Control Structure
338 build_facs(GArray
*table_data
)
340 const char *sig
= "FACS";
341 const uint8_t reserved
[40] = {};
343 g_array_append_vals(table_data
, sig
, 4); /* Signature */
344 build_append_int_noprefix(table_data
, 64, 4); /* Length */
345 build_append_int_noprefix(table_data
, 0, 4); /* Hardware Signature */
346 build_append_int_noprefix(table_data
, 0, 4); /* Firmware Waking Vector */
347 build_append_int_noprefix(table_data
, 0, 4); /* Global Lock */
348 build_append_int_noprefix(table_data
, 0, 4); /* Flags */
349 g_array_append_vals(table_data
, reserved
, 40); /* Reserved */
352 Aml
*aml_pci_device_dsm(void)
356 method
= aml_method("_DSM", 4, AML_SERIALIZED
);
358 Aml
*params
= aml_local(0);
359 Aml
*pkg
= aml_package(2);
360 aml_append(pkg
, aml_int(0));
361 aml_append(pkg
, aml_int(0));
362 aml_append(method
, aml_store(pkg
, params
));
364 aml_store(aml_name("BSEL"), aml_index(params
, aml_int(0))));
366 aml_store(aml_name("ASUN"), aml_index(params
, aml_int(1))));
368 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
369 aml_arg(2), aml_arg(3), params
))
375 static void build_append_pci_dsm_func0_common(Aml
*ctx
, Aml
*retvar
)
378 uint8_t byte_list
[1] = { 0 }; /* nothing supported yet */
380 aml_append(ctx
, aml_store(aml_buffer(1, byte_list
), retvar
));
382 * PCI Firmware Specification 3.1
383 * 4.6. _DSM Definitions for PCI
385 UUID
= aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
386 ifctx1
= aml_if(aml_lnot(aml_equal(aml_arg(0), UUID
)));
388 /* call is for unsupported UUID, bail out */
389 aml_append(ifctx1
, aml_return(retvar
));
391 aml_append(ctx
, ifctx1
);
393 ifctx1
= aml_if(aml_lless(aml_arg(1), aml_int(2)));
395 /* call is for unsupported REV, bail out */
396 aml_append(ifctx1
, aml_return(retvar
));
398 aml_append(ctx
, ifctx1
);
401 static Aml
*aml_pci_edsm(void)
404 Aml
*zero
= aml_int(0);
405 Aml
*func
= aml_arg(2);
406 Aml
*ret
= aml_local(0);
407 Aml
*aidx
= aml_local(1);
408 Aml
*params
= aml_arg(4);
410 method
= aml_method("EDSM", 5, AML_SERIALIZED
);
412 /* get supported functions */
413 ifctx
= aml_if(aml_equal(func
, zero
));
415 /* 1: have supported functions */
416 /* 7: support for function 7 */
417 const uint8_t caps
= 1 | BIT(7);
418 build_append_pci_dsm_func0_common(ifctx
, ret
);
419 aml_append(ifctx
, aml_store(aml_int(caps
), aml_index(ret
, zero
)));
420 aml_append(ifctx
, aml_return(ret
));
422 aml_append(method
, ifctx
);
424 /* handle specific functions requests */
426 * PCI Firmware Specification 3.1
427 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
430 ifctx
= aml_if(aml_equal(func
, aml_int(7)));
432 Aml
*pkg
= aml_package(2);
433 aml_append(pkg
, zero
);
434 /* optional, if not impl. should return null string */
435 aml_append(pkg
, aml_string("%s", ""));
436 aml_append(ifctx
, aml_store(pkg
, ret
));
439 * IASL is fine when initializing Package with computational data,
440 * however it makes guest unhappy /it fails to process such AML/.
441 * So use runtime assignment to set acpi-index after initializer
442 * to make OSPM happy.
445 aml_store(aml_derefof(aml_index(params
, aml_int(0))), aidx
));
446 aml_append(ifctx
, aml_store(aidx
, aml_index(ret
, zero
)));
447 aml_append(ifctx
, aml_return(ret
));
449 aml_append(method
, ifctx
);
454 static Aml
*aml_pci_static_endpoint_dsm(PCIDevice
*pdev
)
458 g_assert(pdev
->acpi_index
!= 0);
459 method
= aml_method("_DSM", 4, AML_SERIALIZED
);
461 Aml
*params
= aml_local(0);
462 Aml
*pkg
= aml_package(1);
463 aml_append(pkg
, aml_int(pdev
->acpi_index
));
464 aml_append(method
, aml_store(pkg
, params
));
466 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1),
467 aml_arg(2), aml_arg(3), params
))
473 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
476 int32_t devfn
= PCI_DEVFN(slot
, 0);
478 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
479 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
480 aml_append(method
, if_ctx
);
483 static bool is_devfn_ignored_generic(const int devfn
, const PCIBus
*bus
)
485 const PCIDevice
*pdev
= bus
->devices
[devfn
];
487 if (PCI_FUNC(devfn
)) {
488 if (IS_PCI_BRIDGE(pdev
)) {
490 * Ignore only hotplugged PCI bridges on !0 functions, but
491 * allow describing cold plugged bridges on all functions
493 if (DEVICE(pdev
)->hotplugged
) {
501 static bool is_devfn_ignored_hotplug(const int devfn
, const PCIBus
*bus
)
503 PCIDevice
*pdev
= bus
->devices
[devfn
];
505 return is_devfn_ignored_generic(devfn
, bus
) ||
506 !DEVICE_GET_CLASS(pdev
)->hotpluggable
||
507 /* Cold plugged bridges aren't themselves hot-pluggable */
508 (IS_PCI_BRIDGE(pdev
) && !DEVICE(pdev
)->hotplugged
);
509 } else { /* non populated slots */
511 * hotplug is supported only for non-multifunction device
512 * so generate device description only for function 0
514 if (PCI_FUNC(devfn
) ||
515 (pci_bus_is_express(bus
) && PCI_SLOT(devfn
) > 0)) {
522 void build_append_pcihp_slots(Aml
*parent_scope
, PCIBus
*bus
)
525 Aml
*dev
, *notify_method
= NULL
, *method
;
526 QObject
*bsel
= object_property_get_qobject(OBJECT(bus
),
527 ACPI_PCIHP_PROP_BSEL
, NULL
);
528 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
531 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
532 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
534 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
535 int slot
= PCI_SLOT(devfn
);
536 int adr
= slot
<< 16 | PCI_FUNC(devfn
);
538 if (is_devfn_ignored_hotplug(devfn
, bus
)) {
542 if (bus
->devices
[devfn
]) {
543 dev
= aml_scope("S%.02X", devfn
);
545 dev
= aml_device("S%.02X", devfn
);
546 aml_append(dev
, aml_name_decl("_ADR", aml_int(adr
)));
550 * Can't declare _SUN here for every device as it changes 'slot'
551 * enumeration order in linux kernel, so use another variable for it
553 aml_append(dev
, aml_name_decl("ASUN", aml_int(slot
)));
554 aml_append(dev
, aml_pci_device_dsm());
556 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
557 /* add _EJ0 to make slot hotpluggable */
558 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
560 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
562 aml_append(dev
, method
);
564 build_append_pcihp_notify_entry(notify_method
, slot
);
566 /* device descriptor has been composed, add it into parent context */
567 aml_append(parent_scope
, dev
);
569 aml_append(parent_scope
, notify_method
);
572 void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
)
577 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
578 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
579 int adr
= PCI_SLOT(devfn
) << 16 | PCI_FUNC(devfn
);
580 PCIDevice
*pdev
= bus
->devices
[devfn
];
582 if (!pdev
|| is_devfn_ignored_generic(devfn
, bus
)) {
586 /* start to compose PCI device descriptor */
587 dev
= aml_device("S%.02X", devfn
);
588 aml_append(dev
, aml_name_decl("_ADR", aml_int(adr
)));
590 call_dev_aml_func(DEVICE(bus
->devices
[devfn
]), dev
);
591 /* add _DSM if device has acpi-index set */
592 if (pdev
->acpi_index
&&
593 !object_property_get_bool(OBJECT(pdev
), "hotpluggable",
595 aml_append(dev
, aml_pci_static_endpoint_dsm(pdev
));
598 /* device descriptor has been composed, add it into parent context */
599 aml_append(parent_scope
, dev
);
603 static bool build_append_notfication_callback(Aml
*parent_scope
,
609 int nr_notifiers
= 0;
610 GQueue
*pcnt_bus_list
= g_queue_new();
612 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
613 Aml
*br_scope
= aml_scope("S%.02X", sec
->parent_dev
->devfn
);
614 if (pci_bus_is_root(sec
)) {
617 nr_notifiers
= nr_notifiers
+
618 build_append_notfication_callback(br_scope
, sec
);
620 * add new child scope to parent
621 * and keep track of bus that have PCNT,
622 * bus list is used later to call children PCNTs from this level PCNT
625 g_queue_push_tail(pcnt_bus_list
, sec
);
626 aml_append(parent_scope
, br_scope
);
631 * Append PCNT method to notify about events on local and child buses.
632 * ps: hostbridge might not have hotplug (bsel) enabled but might have
633 * child bridges that do have bsel.
635 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
637 /* If bus supports hotplug select it and notify about local events */
638 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
640 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
642 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
643 aml_append(method
, aml_call2("DVNT", aml_name("PCIU"),
644 aml_int(1))); /* Device Check */
645 aml_append(method
, aml_call2("DVNT", aml_name("PCID"),
646 aml_int(3))); /* Eject Request */
650 /* Notify about child bus events in any case */
651 while ((sec
= g_queue_pop_head(pcnt_bus_list
))) {
652 aml_append(method
, aml_name("^S%.02X.PCNT", sec
->parent_dev
->devfn
));
655 aml_append(parent_scope
, method
);
657 g_queue_free(pcnt_bus_list
);
658 return !!nr_notifiers
;
661 static Aml
*aml_pci_pdsm(void)
663 Aml
*method
, *ifctx
, *ifctx1
;
664 Aml
*ret
= aml_local(0);
665 Aml
*caps
= aml_local(1);
666 Aml
*acpi_index
= aml_local(2);
667 Aml
*zero
= aml_int(0);
668 Aml
*one
= aml_int(1);
669 Aml
*func
= aml_arg(2);
670 Aml
*params
= aml_arg(4);
671 Aml
*bnum
= aml_derefof(aml_index(params
, aml_int(0)));
672 Aml
*sunum
= aml_derefof(aml_index(params
, aml_int(1)));
674 method
= aml_method("PDSM", 5, AML_SERIALIZED
);
676 /* get supported functions */
677 ifctx
= aml_if(aml_equal(func
, zero
));
679 build_append_pci_dsm_func0_common(ifctx
, ret
);
681 aml_append(ifctx
, aml_store(zero
, caps
));
683 aml_store(aml_call2("AIDX", bnum
, sunum
), acpi_index
));
685 * advertise function 7 if device has acpi-index
687 * 0: not present (default value)
688 * FFFFFFFF: not supported (old QEMU without PIDX reg)
689 * other: device's acpi-index
691 ifctx1
= aml_if(aml_lnot(
692 aml_or(aml_equal(acpi_index
, zero
),
693 aml_equal(acpi_index
, aml_int(0xFFFFFFFF)), NULL
)
696 /* have supported functions */
697 aml_append(ifctx1
, aml_or(caps
, one
, caps
));
698 /* support for function 7 */
700 aml_or(caps
, aml_shiftleft(one
, aml_int(7)), caps
));
702 aml_append(ifctx
, ifctx1
);
704 aml_append(ifctx
, aml_store(caps
, aml_index(ret
, zero
)));
705 aml_append(ifctx
, aml_return(ret
));
707 aml_append(method
, ifctx
);
709 /* handle specific functions requests */
711 * PCI Firmware Specification 3.1
712 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
715 ifctx
= aml_if(aml_equal(func
, aml_int(7)));
717 Aml
*pkg
= aml_package(2);
719 aml_append(pkg
, zero
);
721 * optional, if not impl. should return null string
723 aml_append(pkg
, aml_string("%s", ""));
724 aml_append(ifctx
, aml_store(pkg
, ret
));
726 aml_append(ifctx
, aml_store(aml_call2("AIDX", bnum
, sunum
), acpi_index
));
728 * update acpi-index to actual value
730 aml_append(ifctx
, aml_store(acpi_index
, aml_index(ret
, zero
)));
731 aml_append(ifctx
, aml_return(ret
));
734 aml_append(method
, ifctx
);
740 * @link_name: link name for PCI route entry
742 * build AML package containing a PCI route entry for @link_name
744 static Aml
*build_prt_entry(const char *link_name
)
746 Aml
*a_zero
= aml_int(0);
747 Aml
*pkg
= aml_package(4);
748 aml_append(pkg
, a_zero
);
749 aml_append(pkg
, a_zero
);
750 aml_append(pkg
, aml_name("%s", link_name
));
751 aml_append(pkg
, a_zero
);
756 * initialize_route - Initialize the interrupt routing rule
757 * through a specific LINK:
758 * if (lnk_idx == idx)
759 * route using link 'link_name'
761 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
762 Aml
*lnk_idx
, int idx
)
764 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
765 Aml
*pkg
= build_prt_entry(link_name
);
767 aml_append(if_ctx
, aml_store(pkg
, route
));
773 * build_prt - Define interrupt rounting rules
775 * Returns an array of 128 routes, one for each device,
776 * based on device location.
777 * The main goal is to equally distribute the interrupts
778 * over the 4 existing ACPI links (works only for i440fx).
779 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
782 static Aml
*build_prt(bool is_pci0_prt
)
784 Aml
*method
, *while_ctx
, *pin
, *res
;
786 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
789 aml_append(method
, aml_store(aml_package(128), res
));
790 aml_append(method
, aml_store(aml_int(0), pin
));
792 /* while (pin < 128) */
793 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
795 Aml
*slot
= aml_local(2);
796 Aml
*lnk_idx
= aml_local(3);
797 Aml
*route
= aml_local(4);
799 /* slot = pin >> 2 */
800 aml_append(while_ctx
,
801 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
802 /* lnk_idx = (slot + pin) & 3 */
803 aml_append(while_ctx
,
804 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
807 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
808 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
810 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
812 /* device 1 is the power-management device, needs SCI */
813 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
815 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
818 aml_store(build_prt_entry("LNKS"), route
));
820 aml_append(if_device_1
, if_pin_4
);
821 else_pin_4
= aml_else();
823 aml_append(else_pin_4
,
824 aml_store(build_prt_entry("LNKA"), route
));
826 aml_append(if_device_1
, else_pin_4
);
828 aml_append(while_ctx
, if_device_1
);
830 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
832 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
833 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
835 /* route[0] = 0x[slot]FFFF */
836 aml_append(while_ctx
,
837 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
839 aml_index(route
, aml_int(0))));
840 /* route[1] = pin & 3 */
841 aml_append(while_ctx
,
842 aml_store(aml_and(pin
, aml_int(3), NULL
),
843 aml_index(route
, aml_int(1))));
844 /* res[pin] = route */
845 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
847 aml_append(while_ctx
, aml_increment(pin
));
849 aml_append(method
, while_ctx
);
851 aml_append(method
, aml_return(res
));
856 static void build_hpet_aml(Aml
*table
)
862 Aml
*scope
= aml_scope("_SB");
863 Aml
*dev
= aml_device("HPET");
864 Aml
*zero
= aml_int(0);
865 Aml
*id
= aml_local(0);
866 Aml
*period
= aml_local(1);
868 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
869 aml_append(dev
, aml_name_decl("_UID", zero
));
872 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
874 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
875 aml_append(field
, aml_named_field("VEND", 32));
876 aml_append(field
, aml_named_field("PRD", 32));
877 aml_append(dev
, field
);
879 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
880 aml_append(method
, aml_store(aml_name("VEND"), id
));
881 aml_append(method
, aml_store(aml_name("PRD"), period
));
882 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
883 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
884 aml_equal(id
, aml_int(0xffff))));
886 aml_append(if_ctx
, aml_return(zero
));
888 aml_append(method
, if_ctx
);
890 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
891 aml_lgreater(period
, aml_int(100000000))));
893 aml_append(if_ctx
, aml_return(zero
));
895 aml_append(method
, if_ctx
);
897 aml_append(method
, aml_return(aml_int(0x0F)));
898 aml_append(dev
, method
);
900 crs
= aml_resource_template();
901 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
902 aml_append(dev
, aml_name_decl("_CRS", crs
));
904 aml_append(scope
, dev
);
905 aml_append(table
, scope
);
908 static Aml
*build_vmbus_device_aml(VMBusBridge
*vmbus_bridge
)
914 dev
= aml_device("VMBS");
915 aml_append(dev
, aml_name_decl("STA", aml_int(0xF)));
916 aml_append(dev
, aml_name_decl("_HID", aml_string("VMBus")));
917 aml_append(dev
, aml_name_decl("_UID", aml_int(0x0)));
918 aml_append(dev
, aml_name_decl("_DDN", aml_string("VMBUS")));
920 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
921 aml_append(method
, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL
),
923 aml_append(dev
, method
);
925 method
= aml_method("_PS0", 0, AML_NOTSERIALIZED
);
926 aml_append(method
, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL
),
928 aml_append(dev
, method
);
930 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
931 aml_append(method
, aml_return(aml_name("STA")));
932 aml_append(dev
, method
);
934 aml_append(dev
, aml_name_decl("_PS3", aml_int(0x0)));
936 crs
= aml_resource_template();
937 aml_append(crs
, aml_irq_no_flags(vmbus_bridge
->irq
));
938 aml_append(dev
, aml_name_decl("_CRS", crs
));
943 static void build_dbg_aml(Aml
*table
)
948 Aml
*scope
= aml_scope("\\");
949 Aml
*buf
= aml_local(0);
950 Aml
*len
= aml_local(1);
951 Aml
*idx
= aml_local(2);
954 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
955 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
956 aml_append(field
, aml_named_field("DBGB", 8));
957 aml_append(scope
, field
);
959 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
961 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
962 aml_append(method
, aml_to_buffer(buf
, buf
));
963 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
964 aml_append(method
, aml_store(aml_int(0), idx
));
966 while_ctx
= aml_while(aml_lless(idx
, len
));
967 aml_append(while_ctx
,
968 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
969 aml_append(while_ctx
, aml_increment(idx
));
970 aml_append(method
, while_ctx
);
972 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
973 aml_append(scope
, method
);
975 aml_append(table
, scope
);
978 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
983 uint32_t irqs
[] = {5, 10, 11};
985 dev
= aml_device("%s", name
);
986 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
987 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
989 crs
= aml_resource_template();
990 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
991 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
992 aml_append(dev
, aml_name_decl("_PRS", crs
));
994 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
995 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
996 aml_append(dev
, method
);
998 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
999 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1000 aml_append(dev
, method
);
1002 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1003 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1004 aml_append(dev
, method
);
1006 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1007 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1008 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1009 aml_append(dev
, method
);
1014 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1021 dev
= aml_device("%s", name
);
1022 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1023 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1025 crs
= aml_resource_template();
1027 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1028 AML_SHARED
, &irqs
, 1));
1029 aml_append(dev
, aml_name_decl("_PRS", crs
));
1031 aml_append(dev
, aml_name_decl("_CRS", crs
));
1034 * _DIS can be no-op because the interrupt cannot be disabled.
1036 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1037 aml_append(dev
, method
);
1039 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1040 aml_append(dev
, method
);
1045 /* _CRS method - get current settings */
1046 static Aml
*build_iqcr_method(bool is_piix4
)
1050 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1051 Aml
*crs
= aml_resource_template();
1054 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1055 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1056 aml_append(method
, aml_name_decl("PRR0", crs
));
1059 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1062 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1063 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1064 aml_append(method
, if_ctx
);
1067 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1071 aml_append(method
, aml_return(aml_name("PRR0")));
1075 /* _STA method - get status */
1076 static Aml
*build_irq_status_method(void)
1079 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1081 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1082 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1083 aml_append(method
, if_ctx
);
1084 aml_append(method
, aml_return(aml_int(0x0B)));
1088 static void build_piix4_pci0_int(Aml
*table
)
1094 Aml
*sb_scope
= aml_scope("_SB");
1095 Aml
*pci0_scope
= aml_scope("PCI0");
1097 aml_append(pci0_scope
, build_prt(true));
1098 aml_append(sb_scope
, pci0_scope
);
1100 aml_append(sb_scope
, build_irq_status_method());
1101 aml_append(sb_scope
, build_iqcr_method(true));
1103 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1104 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1105 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1106 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1108 dev
= aml_device("LNKS");
1110 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1111 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1113 crs
= aml_resource_template();
1115 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1116 AML_ACTIVE_HIGH
, AML_SHARED
,
1118 aml_append(dev
, aml_name_decl("_PRS", crs
));
1120 /* The SCI cannot be disabled and is always attached to GSI 9,
1121 * so these are no-ops. We only need this link to override the
1122 * polarity to active high and match the content of the MADT.
1124 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1125 aml_append(method
, aml_return(aml_int(0x0b)));
1126 aml_append(dev
, method
);
1128 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1129 aml_append(dev
, method
);
1131 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1132 aml_append(method
, aml_return(aml_name("_PRS")));
1133 aml_append(dev
, method
);
1135 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1136 aml_append(dev
, method
);
1138 aml_append(sb_scope
, dev
);
1140 aml_append(table
, sb_scope
);
1143 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1148 char base
= name
[3] < 'E' ? 'A' : 'E';
1149 char *s
= g_strdup(name
);
1150 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1152 assert(strlen(s
) == 4);
1154 head
= name
[3] - base
;
1155 for (i
= 0; i
< 4; i
++) {
1159 s
[3] = base
+ head
+ i
;
1160 pkg
= aml_package(4);
1161 aml_append(pkg
, a_nr
);
1162 aml_append(pkg
, aml_int(i
));
1163 aml_append(pkg
, aml_name("%s", s
));
1164 aml_append(pkg
, aml_int(0));
1165 aml_append(ctx
, pkg
);
1170 static Aml
*build_q35_routing_table(const char *str
)
1174 char *name
= g_strdup_printf("%s ", str
);
1176 pkg
= aml_package(128);
1177 for (i
= 0; i
< 0x18; i
++) {
1178 name
[3] = 'E' + (i
& 0x3);
1179 append_q35_prt_entry(pkg
, i
, name
);
1183 append_q35_prt_entry(pkg
, 0x18, name
);
1185 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1186 for (i
= 0x0019; i
< 0x1e; i
++) {
1188 append_q35_prt_entry(pkg
, i
, name
);
1191 /* PCIe->PCI bridge. use PIRQ[E-H] */
1193 append_q35_prt_entry(pkg
, 0x1e, name
);
1195 append_q35_prt_entry(pkg
, 0x1f, name
);
1201 static void build_q35_pci0_int(Aml
*table
)
1204 Aml
*sb_scope
= aml_scope("_SB");
1205 Aml
*pci0_scope
= aml_scope("PCI0");
1207 /* Zero => PIC mode, One => APIC Mode */
1208 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1209 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1211 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1213 aml_append(table
, method
);
1215 aml_append(pci0_scope
,
1216 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1217 aml_append(pci0_scope
,
1218 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1220 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1225 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1227 /* Note: we provide the same info as the PCI routing
1228 table of the Bochs BIOS */
1229 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1230 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1231 aml_append(method
, if_ctx
);
1232 else_ctx
= aml_else();
1233 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1234 aml_append(method
, else_ctx
);
1236 aml_append(pci0_scope
, method
);
1237 aml_append(sb_scope
, pci0_scope
);
1239 aml_append(sb_scope
, build_irq_status_method());
1240 aml_append(sb_scope
, build_iqcr_method(false));
1242 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1243 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1244 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1245 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1246 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1247 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1248 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1249 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1251 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1252 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1253 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1254 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1255 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1256 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1257 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1258 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1260 aml_append(table
, sb_scope
);
1263 static Aml
*build_q35_dram_controller(const AcpiMcfgInfo
*mcfg
)
1266 Aml
*resource_template
;
1268 /* DRAM controller */
1269 dev
= aml_device("DRAC");
1270 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0C01")));
1272 resource_template
= aml_resource_template();
1273 if (mcfg
->base
+ mcfg
->size
- 1 >= (1ULL << 32)) {
1274 aml_append(resource_template
,
1275 aml_qword_memory(AML_POS_DECODE
,
1282 mcfg
->base
+ mcfg
->size
- 1,
1286 aml_append(resource_template
,
1287 aml_dword_memory(AML_POS_DECODE
,
1294 mcfg
->base
+ mcfg
->size
- 1,
1298 aml_append(dev
, aml_name_decl("_CRS", resource_template
));
1303 static void build_x86_acpi_pci_hotplug(Aml
*table
, uint64_t pcihp_addr
)
1309 scope
= aml_scope("_SB.PCI0");
1312 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(pcihp_addr
), 0x08));
1313 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1314 aml_append(field
, aml_named_field("PCIU", 32));
1315 aml_append(field
, aml_named_field("PCID", 32));
1316 aml_append(scope
, field
);
1319 aml_operation_region("SEJ", AML_SYSTEM_IO
,
1320 aml_int(pcihp_addr
+ ACPI_PCIHP_SEJ_BASE
), 0x04));
1321 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1322 aml_append(field
, aml_named_field("B0EJ", 32));
1323 aml_append(scope
, field
);
1326 aml_operation_region("BNMR", AML_SYSTEM_IO
,
1327 aml_int(pcihp_addr
+ ACPI_PCIHP_BNMR_BASE
), 0x08));
1328 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1329 aml_append(field
, aml_named_field("BNUM", 32));
1330 aml_append(field
, aml_named_field("PIDX", 32));
1331 aml_append(scope
, field
);
1333 aml_append(scope
, aml_mutex("BLCK", 0));
1335 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1336 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1337 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1339 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1340 aml_append(method
, aml_release(aml_name("BLCK")));
1341 aml_append(method
, aml_return(aml_int(0)));
1342 aml_append(scope
, method
);
1344 method
= aml_method("AIDX", 2, AML_NOTSERIALIZED
);
1345 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1346 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1348 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1349 aml_append(method
, aml_store(aml_name("PIDX"), aml_local(0)));
1350 aml_append(method
, aml_release(aml_name("BLCK")));
1351 aml_append(method
, aml_return(aml_local(0)));
1352 aml_append(scope
, method
);
1354 aml_append(scope
, aml_pci_pdsm());
1356 aml_append(table
, scope
);
1359 static Aml
*build_q35_osc_method(bool enable_native_pcie_hotplug
)
1365 Aml
*a_cwd1
= aml_name("CDW1");
1366 Aml
*a_ctrl
= aml_local(0);
1368 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1369 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1371 if_ctx
= aml_if(aml_equal(
1372 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1373 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1374 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1376 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1379 * Always allow native PME, AER (no dependencies)
1380 * Allow SHPC (PCI bridges can have SHPC controller)
1381 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1383 aml_append(if_ctx
, aml_and(a_ctrl
,
1384 aml_int(0x1E | (enable_native_pcie_hotplug
? 0x1 : 0x0)), a_ctrl
));
1386 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1387 /* Unknown revision */
1388 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1389 aml_append(if_ctx
, if_ctx2
);
1391 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1392 /* Capabilities bits were masked */
1393 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1394 aml_append(if_ctx
, if_ctx2
);
1396 /* Update DWORD3 in the buffer */
1397 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1398 aml_append(method
, if_ctx
);
1400 else_ctx
= aml_else();
1401 /* Unrecognized UUID */
1402 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1403 aml_append(method
, else_ctx
);
1405 aml_append(method
, aml_return(aml_arg(3)));
1409 static void build_acpi0017(Aml
*table
)
1411 Aml
*dev
, *scope
, *method
;
1413 scope
= aml_scope("_SB");
1414 dev
= aml_device("CXLM");
1415 aml_append(dev
, aml_name_decl("_HID", aml_string("ACPI0017")));
1417 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1418 aml_append(method
, aml_return(aml_int(0x0B)));
1419 aml_append(dev
, method
);
1420 build_cxl_dsm_method(dev
);
1422 aml_append(scope
, dev
);
1423 aml_append(table
, scope
);
1427 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1428 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1429 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1431 Object
*i440fx
= object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE
);
1432 Object
*q35
= object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE
);
1433 CrsRangeEntry
*entry
;
1434 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1435 CrsRangeSet crs_range_set
;
1436 PCMachineState
*pcms
= PC_MACHINE(machine
);
1437 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1438 X86MachineState
*x86ms
= X86_MACHINE(machine
);
1440 bool mcfg_valid
= !!acpi_get_mcfg(&mcfg
);
1441 uint32_t nr_mem
= machine
->ram_slots
;
1442 int root_bus_limit
= 0xFF;
1445 TPMIf
*tpm
= tpm_find();
1447 bool cxl_present
= false;
1449 VMBusBridge
*vmbus_bridge
= vmbus_bridge_find();
1450 AcpiTable table
= { .sig
= "DSDT", .rev
= 1, .oem_id
= x86ms
->oem_id
,
1451 .oem_table_id
= x86ms
->oem_table_id
};
1453 assert(!!i440fx
!= !!q35
);
1455 acpi_table_begin(&table
, table_data
);
1456 dsdt
= init_aml_allocator();
1458 build_dbg_aml(dsdt
);
1460 sb_scope
= aml_scope("_SB");
1461 dev
= aml_device("PCI0");
1462 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1463 aml_append(dev
, aml_name_decl("_UID", aml_int(pcmc
->pci_root_uid
)));
1464 aml_append(dev
, aml_pci_edsm());
1465 aml_append(sb_scope
, dev
);
1466 aml_append(dsdt
, sb_scope
);
1468 if (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
) {
1469 build_x86_acpi_pci_hotplug(dsdt
, pm
->pcihp_io_base
);
1471 build_piix4_pci0_int(dsdt
);
1473 sb_scope
= aml_scope("_SB");
1474 dev
= aml_device("PCI0");
1475 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1476 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1477 aml_append(dev
, aml_name_decl("_UID", aml_int(pcmc
->pci_root_uid
)));
1478 aml_append(dev
, build_q35_osc_method(!pm
->pcihp_bridge_en
));
1479 aml_append(dev
, aml_pci_edsm());
1480 aml_append(sb_scope
, dev
);
1482 aml_append(sb_scope
, build_q35_dram_controller(&mcfg
));
1485 if (pm
->smi_on_cpuhp
) {
1486 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1487 dev
= aml_device("PCI0.SMI0");
1488 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1489 aml_append(dev
, aml_name_decl("_UID", aml_string("SMI resources")));
1490 crs
= aml_resource_template();
1499 aml_append(dev
, aml_name_decl("_CRS", crs
));
1500 aml_append(dev
, aml_operation_region("SMIR", AML_SYSTEM_IO
,
1501 aml_int(pm
->fadt
.smi_cmd
), 2));
1502 field
= aml_field("SMIR", AML_BYTE_ACC
, AML_NOLOCK
,
1503 AML_WRITE_AS_ZEROS
);
1504 aml_append(field
, aml_named_field("SMIC", 8));
1505 aml_append(field
, aml_reserved_field(8));
1506 aml_append(dev
, field
);
1507 aml_append(sb_scope
, dev
);
1510 aml_append(dsdt
, sb_scope
);
1512 if (pm
->pcihp_bridge_en
) {
1513 build_x86_acpi_pci_hotplug(dsdt
, pm
->pcihp_io_base
);
1515 build_q35_pci0_int(dsdt
);
1518 if (misc
->has_hpet
) {
1519 build_hpet_aml(dsdt
);
1523 sb_scope
= aml_scope("_SB");
1524 aml_append(sb_scope
, build_vmbus_device_aml(vmbus_bridge
));
1525 aml_append(dsdt
, sb_scope
);
1528 scope
= aml_scope("_GPE");
1530 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1531 if (machine
->nvdimms_state
->is_enabled
) {
1532 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1533 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1535 aml_append(scope
, method
);
1538 aml_append(dsdt
, scope
);
1540 if (pcmc
->legacy_cpu_hotplug
) {
1541 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1543 CPUHotplugFeatures opts
= {
1544 .acpi_1_compatible
= true, .has_legacy_cphp
= true,
1545 .smi_path
= pm
->smi_on_cpuhp
? "\\_SB.PCI0.SMI0.SMIC" : NULL
,
1546 .fw_unplugs_cpu
= pm
->smi_on_cpu_unplug
,
1548 build_cpus_aml(dsdt
, machine
, opts
, pc_madt_cpu_entry
,
1549 pm
->cpu_hp_io_base
, "\\_SB.PCI0", "\\_GPE._E02");
1552 if (pcms
->memhp_io_base
&& nr_mem
) {
1553 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0",
1554 "\\_GPE._E03", AML_SYSTEM_IO
,
1555 pcms
->memhp_io_base
);
1558 crs_range_set_init(&crs_range_set
);
1559 bus
= PC_MACHINE(machine
)->bus
;
1561 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1562 uint8_t bus_num
= pci_bus_num(bus
);
1563 uint8_t numa_node
= pci_bus_numa_node(bus
);
1565 /* look only for expander root buses */
1566 if (!pci_bus_is_root(bus
)) {
1570 if (bus_num
< root_bus_limit
) {
1571 root_bus_limit
= bus_num
- 1;
1574 scope
= aml_scope("\\_SB");
1576 if (pci_bus_is_cxl(bus
)) {
1577 dev
= aml_device("CL%.02X", bus_num
);
1579 dev
= aml_device("PC%.02X", bus_num
);
1581 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1582 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1583 if (pci_bus_is_cxl(bus
)) {
1584 struct Aml
*aml_pkg
= aml_package(2);
1586 aml_append(dev
, aml_name_decl("_HID", aml_string("ACPI0016")));
1587 aml_append(aml_pkg
, aml_eisaid("PNP0A08"));
1588 aml_append(aml_pkg
, aml_eisaid("PNP0A03"));
1589 aml_append(dev
, aml_name_decl("_CID", aml_pkg
));
1590 build_cxl_osc_method(dev
);
1591 } else if (pci_bus_is_express(bus
)) {
1592 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1593 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1595 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1596 aml_append(dev
, build_q35_osc_method(true));
1598 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1601 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1602 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1605 aml_append(dev
, build_prt(false));
1606 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
,
1608 aml_append(dev
, aml_name_decl("_CRS", crs
));
1609 aml_append(scope
, dev
);
1610 aml_append(dsdt
, scope
);
1612 /* Handle the ranges for the PXB expanders */
1613 if (pci_bus_is_cxl(bus
)) {
1614 MemoryRegion
*mr
= &pcms
->cxl_devices_state
.host_mr
;
1615 uint64_t base
= mr
->addr
;
1618 crs_range_insert(crs_range_set
.mem_ranges
, base
,
1619 base
+ memory_region_size(mr
) - 1);
1625 build_acpi0017(dsdt
);
1629 * At this point crs_range_set has all the ranges used by pci
1630 * busses *other* than PCI0. These ranges will be excluded from
1631 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1635 crs_range_insert(crs_range_set
.mem_ranges
,
1636 mcfg
.base
, mcfg
.base
+ mcfg
.size
- 1);
1639 scope
= aml_scope("\\_SB.PCI0");
1640 /* build PCI0._CRS */
1641 crs
= aml_resource_template();
1643 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1644 0x0000, 0x0, root_bus_limit
,
1645 0x0000, root_bus_limit
+ 1));
1646 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
1649 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1650 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1651 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1653 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
1654 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
1655 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
1657 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1658 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1659 0x0000, entry
->base
, entry
->limit
,
1660 0x0000, entry
->limit
- entry
->base
+ 1));
1664 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1665 AML_CACHEABLE
, AML_READ_WRITE
,
1666 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1668 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
1669 range_lob(pci_hole
),
1670 range_upb(pci_hole
));
1671 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
1672 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
1674 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1675 AML_NON_CACHEABLE
, AML_READ_WRITE
,
1676 0, entry
->base
, entry
->limit
,
1677 0, entry
->limit
- entry
->base
+ 1));
1680 if (!range_is_empty(pci_hole64
)) {
1681 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
1682 range_lob(pci_hole64
),
1683 range_upb(pci_hole64
));
1684 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
1685 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
1687 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1689 AML_CACHEABLE
, AML_READ_WRITE
,
1690 0, entry
->base
, entry
->limit
,
1691 0, entry
->limit
- entry
->base
+ 1));
1696 if (TPM_IS_TIS_ISA(tpm_find())) {
1697 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
1698 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
1701 aml_append(scope
, aml_name_decl("_CRS", crs
));
1703 /* reserve GPE0 block resources */
1704 dev
= aml_device("GPE0");
1705 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1706 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
1707 /* device present, functioning, decoding, not shown in UI */
1708 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1709 crs
= aml_resource_template();
1713 pm
->fadt
.gpe0_blk
.address
,
1714 pm
->fadt
.gpe0_blk
.address
,
1716 pm
->fadt
.gpe0_blk
.bit_width
/ 8)
1718 aml_append(dev
, aml_name_decl("_CRS", crs
));
1719 aml_append(scope
, dev
);
1721 crs_range_set_free(&crs_range_set
);
1723 /* reserve PCIHP resources */
1724 if (pm
->pcihp_io_len
&& (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
)) {
1725 dev
= aml_device("PHPR");
1726 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1728 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1729 /* device present, functioning, decoding, not shown in UI */
1730 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1731 crs
= aml_resource_template();
1733 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
1736 aml_append(dev
, aml_name_decl("_CRS", crs
));
1737 aml_append(scope
, dev
);
1739 aml_append(dsdt
, scope
);
1741 /* create S3_ / S4_ / S5_ packages if necessary */
1742 scope
= aml_scope("\\");
1743 if (!pm
->s3_disabled
) {
1744 pkg
= aml_package(4);
1745 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1746 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1747 aml_append(pkg
, aml_int(0)); /* reserved */
1748 aml_append(pkg
, aml_int(0)); /* reserved */
1749 aml_append(scope
, aml_name_decl("_S3", pkg
));
1752 if (!pm
->s4_disabled
) {
1753 pkg
= aml_package(4);
1754 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
1755 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1756 aml_append(pkg
, aml_int(pm
->s4_val
));
1757 aml_append(pkg
, aml_int(0)); /* reserved */
1758 aml_append(pkg
, aml_int(0)); /* reserved */
1759 aml_append(scope
, aml_name_decl("_S4", pkg
));
1762 pkg
= aml_package(4);
1763 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1764 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1765 aml_append(pkg
, aml_int(0)); /* reserved */
1766 aml_append(pkg
, aml_int(0)); /* reserved */
1767 aml_append(scope
, aml_name_decl("_S5", pkg
));
1768 aml_append(dsdt
, scope
);
1770 /* create fw_cfg node, unconditionally */
1772 scope
= aml_scope("\\_SB.PCI0");
1773 fw_cfg_add_acpi_dsdt(scope
, x86ms
->fw_cfg
);
1774 aml_append(dsdt
, scope
);
1777 sb_scope
= aml_scope("\\_SB");
1779 Object
*pci_host
= acpi_get_i386_pci_host();
1782 PCIBus
*pbus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
1783 Aml
*ascope
= aml_scope("PCI0");
1784 /* Scan all PCI buses. Generate tables to support hotplug. */
1785 build_append_pci_bus_devices(ascope
, pbus
);
1786 if (object_property_find(OBJECT(pbus
), ACPI_PCIHP_PROP_BSEL
)) {
1787 build_append_pcihp_slots(ascope
, pbus
);
1789 aml_append(sb_scope
, ascope
);
1794 if (TPM_IS_CRB(tpm
)) {
1795 dev
= aml_device("TPM");
1796 aml_append(dev
, aml_name_decl("_HID", aml_string("MSFT0101")));
1797 aml_append(dev
, aml_name_decl("_STR",
1798 aml_string("TPM 2.0 Device")));
1799 crs
= aml_resource_template();
1800 aml_append(crs
, aml_memory32_fixed(TPM_CRB_ADDR_BASE
,
1801 TPM_CRB_ADDR_SIZE
, AML_READ_WRITE
));
1802 aml_append(dev
, aml_name_decl("_CRS", crs
));
1804 aml_append(dev
, aml_name_decl("_STA", aml_int(0xf)));
1805 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1807 tpm_build_ppi_acpi(tpm
, dev
);
1809 aml_append(sb_scope
, dev
);
1813 if (pcms
->sgx_epc
.size
!= 0) {
1814 uint64_t epc_base
= pcms
->sgx_epc
.base
;
1815 uint64_t epc_size
= pcms
->sgx_epc
.size
;
1817 dev
= aml_device("EPC");
1818 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1819 aml_append(dev
, aml_name_decl("_STR",
1820 aml_unicode("Enclave Page Cache 1.0")));
1821 crs
= aml_resource_template();
1823 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1824 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1825 AML_READ_WRITE
, 0, epc_base
,
1826 epc_base
+ epc_size
- 1, 0, epc_size
));
1827 aml_append(dev
, aml_name_decl("_CRS", crs
));
1829 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1830 aml_append(method
, aml_return(aml_int(0x0f)));
1831 aml_append(dev
, method
);
1833 aml_append(sb_scope
, dev
);
1835 aml_append(dsdt
, sb_scope
);
1837 if (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
) {
1840 Object
*pci_host
= acpi_get_i386_pci_host();
1841 PCIBus
*b
= PCI_HOST_BRIDGE(pci_host
)->bus
;
1843 scope
= aml_scope("\\_SB.PCI0");
1844 has_pcnt
= build_append_notfication_callback(scope
, b
);
1846 aml_append(dsdt
, scope
);
1849 scope
= aml_scope("_GPE");
1851 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1854 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1855 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1856 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1858 aml_append(scope
, method
);
1860 aml_append(dsdt
, scope
);
1863 /* copy AML table into ACPI tables blob and patch header there */
1864 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
1865 acpi_table_end(linker
, &table
);
1866 free_aml_allocator();
1870 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1871 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1874 build_hpet(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
1875 const char *oem_table_id
)
1877 AcpiTable table
= { .sig
= "HPET", .rev
= 1,
1878 .oem_id
= oem_id
, .oem_table_id
= oem_table_id
};
1880 acpi_table_begin(&table
, table_data
);
1881 /* Note timer_block_id value must be kept in sync with value advertised by
1884 /* Event Timer Block ID */
1885 build_append_int_noprefix(table_data
, 0x8086a201, 4);
1887 build_append_gas(table_data
, AML_AS_SYSTEM_MEMORY
, 0, 0, 0, HPET_BASE
);
1889 build_append_int_noprefix(table_data
, 0, 1);
1890 /* Main Counter Minimum Clock_tick in Periodic Mode */
1891 build_append_int_noprefix(table_data
, 0, 2);
1892 /* Page Protection And OEM Attribute */
1893 build_append_int_noprefix(table_data
, 0, 1);
1894 acpi_table_end(linker
, &table
);
1899 * TCPA Description Table
1901 * Following Level 00, Rev 00.37 of specs:
1902 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1903 * 7.1.2 ACPI Table Layout
1906 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
,
1907 const char *oem_id
, const char *oem_table_id
)
1909 unsigned log_addr_offset
;
1910 AcpiTable table
= { .sig
= "TCPA", .rev
= 2,
1911 .oem_id
= oem_id
, .oem_table_id
= oem_table_id
};
1913 acpi_table_begin(&table
, table_data
);
1914 /* Platform Class */
1915 build_append_int_noprefix(table_data
, TPM_TCPA_ACPI_CLASS_CLIENT
, 2);
1916 /* Log Area Minimum Length (LAML) */
1917 build_append_int_noprefix(table_data
, TPM_LOG_AREA_MINIMUM_SIZE
, 4);
1918 /* Log Area Start Address (LASA) */
1919 log_addr_offset
= table_data
->len
;
1920 build_append_int_noprefix(table_data
, 0, 8);
1922 /* allocate/reserve space for TPM log area */
1923 acpi_data_push(tcpalog
, TPM_LOG_AREA_MINIMUM_SIZE
);
1924 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
1925 false /* high memory */);
1926 /* log area start address to be filled by Guest linker */
1927 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
1928 log_addr_offset
, 8, ACPI_BUILD_TPMLOG_FILE
, 0);
1930 acpi_table_end(linker
, &table
);
1934 #define HOLE_640K_START (640 * KiB)
1935 #define HOLE_640K_END (1 * MiB)
1938 * ACPI spec, Revision 3.0
1939 * 5.2.15 System Resource Affinity Table (SRAT)
1942 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
1945 int numa_mem_start
, slots
;
1946 uint64_t mem_len
, mem_base
, next_base
;
1947 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1948 X86MachineState
*x86ms
= X86_MACHINE(machine
);
1949 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
1950 int nb_numa_nodes
= machine
->numa_state
->num_nodes
;
1951 NodeInfo
*numa_info
= machine
->numa_state
->nodes
;
1952 AcpiTable table
= { .sig
= "SRAT", .rev
= 1, .oem_id
= x86ms
->oem_id
,
1953 .oem_table_id
= x86ms
->oem_table_id
};
1955 acpi_table_begin(&table
, table_data
);
1956 build_append_int_noprefix(table_data
, 1, 4); /* Reserved */
1957 build_append_int_noprefix(table_data
, 0, 8); /* Reserved */
1959 for (i
= 0; i
< apic_ids
->len
; i
++) {
1960 int node_id
= apic_ids
->cpus
[i
].props
.node_id
;
1961 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
1963 if (apic_id
< 255) {
1964 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1965 build_append_int_noprefix(table_data
, 0, 1); /* Type */
1966 build_append_int_noprefix(table_data
, 16, 1); /* Length */
1967 /* Proximity Domain [7:0] */
1968 build_append_int_noprefix(table_data
, node_id
, 1);
1969 build_append_int_noprefix(table_data
, apic_id
, 1); /* APIC ID */
1970 /* Flags, Table 5-36 */
1971 build_append_int_noprefix(table_data
, 1, 4);
1972 build_append_int_noprefix(table_data
, 0, 1); /* Local SAPIC EID */
1973 /* Proximity Domain [31:8] */
1974 build_append_int_noprefix(table_data
, 0, 3);
1975 build_append_int_noprefix(table_data
, 0, 4); /* Reserved */
1978 * ACPI spec, Revision 4.0
1979 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1981 build_append_int_noprefix(table_data
, 2, 1); /* Type */
1982 build_append_int_noprefix(table_data
, 24, 1); /* Length */
1983 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
1984 /* Proximity Domain */
1985 build_append_int_noprefix(table_data
, node_id
, 4);
1986 build_append_int_noprefix(table_data
, apic_id
, 4); /* X2APIC ID */
1987 /* Flags, Table 5-39 */
1988 build_append_int_noprefix(table_data
, 1 /* Enabled */, 4);
1989 build_append_int_noprefix(table_data
, 0, 4); /* Clock Domain */
1990 build_append_int_noprefix(table_data
, 0, 4); /* Reserved */
1994 /* the memory map is a bit tricky, it contains at least one hole
1995 * from 640k-1M and possibly another one from 3.5G-4G.
1998 numa_mem_start
= table_data
->len
;
2000 for (i
= 1; i
< nb_numa_nodes
+ 1; ++i
) {
2001 mem_base
= next_base
;
2002 mem_len
= numa_info
[i
- 1].node_mem
;
2003 next_base
= mem_base
+ mem_len
;
2005 /* Cut out the 640K hole */
2006 if (mem_base
<= HOLE_640K_START
&&
2007 next_base
> HOLE_640K_START
) {
2008 mem_len
-= next_base
- HOLE_640K_START
;
2010 build_srat_memory(table_data
, mem_base
, mem_len
, i
- 1,
2011 MEM_AFFINITY_ENABLED
);
2014 /* Check for the rare case: 640K < RAM < 1M */
2015 if (next_base
<= HOLE_640K_END
) {
2016 next_base
= HOLE_640K_END
;
2019 mem_base
= HOLE_640K_END
;
2020 mem_len
= next_base
- HOLE_640K_END
;
2023 /* Cut out the ACPI_PCI hole */
2024 if (mem_base
<= x86ms
->below_4g_mem_size
&&
2025 next_base
> x86ms
->below_4g_mem_size
) {
2026 mem_len
-= next_base
- x86ms
->below_4g_mem_size
;
2028 build_srat_memory(table_data
, mem_base
, mem_len
, i
- 1,
2029 MEM_AFFINITY_ENABLED
);
2031 mem_base
= x86ms
->above_4g_mem_start
;
2032 mem_len
= next_base
- x86ms
->below_4g_mem_size
;
2033 next_base
= mem_base
+ mem_len
;
2037 build_srat_memory(table_data
, mem_base
, mem_len
, i
- 1,
2038 MEM_AFFINITY_ENABLED
);
2042 if (machine
->nvdimms_state
->is_enabled
) {
2043 nvdimm_build_srat(table_data
);
2046 sgx_epc_build_srat(table_data
);
2049 * TODO: this part is not in ACPI spec and current linux kernel boots fine
2050 * without these entries. But I recall there were issues the last time I
2051 * tried to remove it with some ancient guest OS, however I can't remember
2052 * what that was so keep this around for now
2054 slots
= (table_data
->len
- numa_mem_start
) / 40 /* mem affinity len */;
2055 for (; slots
< nb_numa_nodes
+ 2; slots
++) {
2056 build_srat_memory(table_data
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2060 * Entry is required for Windows to enable memory hotplug in OS
2061 * and for Linux to enable SWIOTLB when booted with less than
2062 * 4G of RAM. Windows works better if the entry sets proximity
2063 * to the highest NUMA node in the machine.
2064 * Memory devices may override proximity set by this entry,
2065 * providing _PXM method if necessary.
2067 if (machine
->device_memory
) {
2068 build_srat_memory(table_data
, machine
->device_memory
->base
,
2069 memory_region_size(&machine
->device_memory
->mr
),
2071 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2074 acpi_table_end(linker
, &table
);
2078 * Insert DMAR scope for PCI bridges and endpoint devices
2081 insert_scope(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
2083 const size_t device_scope_size
= 6 /* device scope structure */ +
2084 2 /* 1 path entry */;
2085 GArray
*scope_blob
= opaque
;
2087 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_BRIDGE
)) {
2088 /* Dmar Scope Type: 0x02 for PCI Bridge */
2089 build_append_int_noprefix(scope_blob
, 0x02, 1);
2091 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2092 build_append_int_noprefix(scope_blob
, 0x01, 1);
2096 build_append_int_noprefix(scope_blob
, device_scope_size
, 1);
2098 build_append_int_noprefix(scope_blob
, 0, 2);
2099 /* enumeration_id */
2100 build_append_int_noprefix(scope_blob
, 0, 1);
2102 build_append_int_noprefix(scope_blob
, pci_bus_num(bus
), 1);
2104 build_append_int_noprefix(scope_blob
, PCI_SLOT(dev
->devfn
), 1);
2106 build_append_int_noprefix(scope_blob
, PCI_FUNC(dev
->devfn
), 1);
2109 /* For a given PCI host bridge, walk and insert DMAR scope */
2111 dmar_host_bridges(Object
*obj
, void *opaque
)
2113 GArray
*scope_blob
= opaque
;
2115 if (object_dynamic_cast(obj
, TYPE_PCI_HOST_BRIDGE
)) {
2116 PCIBus
*bus
= PCI_HOST_BRIDGE(obj
)->bus
;
2118 if (bus
&& !pci_bus_bypass_iommu(bus
)) {
2119 pci_for_each_device_under_bus(bus
, insert_scope
, scope_blob
);
2127 * Intel ® Virtualization Technology for Directed I/O
2128 * Architecture Specification. Revision 3.3
2129 * 8.1 DMA Remapping Reporting Structure
2132 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
2133 const char *oem_table_id
)
2135 uint8_t dmar_flags
= 0;
2136 uint8_t rsvd10
[10] = {};
2137 /* Root complex IOAPIC uses one path only */
2138 const size_t ioapic_scope_size
= 6 /* device scope structure */ +
2139 2 /* 1 path entry */;
2140 X86IOMMUState
*iommu
= x86_iommu_get_default();
2141 IntelIOMMUState
*intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
2142 GArray
*scope_blob
= g_array_new(false, true, 1);
2144 AcpiTable table
= { .sig
= "DMAR", .rev
= 1, .oem_id
= oem_id
,
2145 .oem_table_id
= oem_table_id
};
2148 * A PCI bus walk, for each PCI host bridge.
2149 * Insert scope for each PCI bridge and endpoint device which
2150 * is attached to a bus with iommu enabled.
2152 object_child_foreach_recursive(object_get_root(),
2153 dmar_host_bridges
, scope_blob
);
2156 if (x86_iommu_ir_supported(iommu
)) {
2157 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2160 acpi_table_begin(&table
, table_data
);
2161 /* Host Address Width */
2162 build_append_int_noprefix(table_data
, intel_iommu
->aw_bits
- 1, 1);
2163 build_append_int_noprefix(table_data
, dmar_flags
, 1); /* Flags */
2164 g_array_append_vals(table_data
, rsvd10
, sizeof(rsvd10
)); /* Reserved */
2166 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2167 build_append_int_noprefix(table_data
, 0, 2); /* Type */
2169 build_append_int_noprefix(table_data
,
2170 16 + ioapic_scope_size
+ scope_blob
->len
, 2);
2172 build_append_int_noprefix(table_data
, 0 /* Don't include all pci device */ ,
2174 build_append_int_noprefix(table_data
, 0 , 1); /* Reserved */
2175 build_append_int_noprefix(table_data
, 0 , 2); /* Segment Number */
2176 /* Register Base Address */
2177 build_append_int_noprefix(table_data
, Q35_HOST_BRIDGE_IOMMU_ADDR
, 8);
2179 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2180 * 8.3.1 (version Oct. 2014 or later). */
2181 build_append_int_noprefix(table_data
, 0x03 /* IOAPIC */, 1); /* Type */
2182 build_append_int_noprefix(table_data
, ioapic_scope_size
, 1); /* Length */
2183 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
2184 /* Enumeration ID */
2185 build_append_int_noprefix(table_data
, ACPI_BUILD_IOAPIC_ID
, 1);
2186 /* Start Bus Number */
2187 build_append_int_noprefix(table_data
, Q35_PSEUDO_BUS_PLATFORM
, 1);
2188 /* Path, {Device, Function} pair */
2189 build_append_int_noprefix(table_data
, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
), 1);
2190 build_append_int_noprefix(table_data
, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
), 1);
2192 /* Add scope found above */
2193 g_array_append_vals(table_data
, scope_blob
->data
, scope_blob
->len
);
2194 g_array_free(scope_blob
, true);
2196 if (iommu
->dt_supported
) {
2197 /* 8.5 Root Port ATS Capability Reporting Structure */
2198 build_append_int_noprefix(table_data
, 2, 2); /* Type */
2199 build_append_int_noprefix(table_data
, 8, 2); /* Length */
2200 build_append_int_noprefix(table_data
, 1 /* ALL_PORTS */, 1); /* Flags */
2201 build_append_int_noprefix(table_data
, 0, 1); /* Reserved */
2202 build_append_int_noprefix(table_data
, 0, 2); /* Segment Number */
2205 acpi_table_end(linker
, &table
);
2209 * Windows ACPI Emulated Devices Table
2210 * (Version 1.0 - April 6, 2009)
2211 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2213 * Helpful to speedup Windows guests and ignored by others.
2216 build_waet(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
2217 const char *oem_table_id
)
2219 AcpiTable table
= { .sig
= "WAET", .rev
= 1, .oem_id
= oem_id
,
2220 .oem_table_id
= oem_table_id
};
2222 acpi_table_begin(&table
, table_data
);
2224 * Set "ACPI PM timer good" flag.
2226 * Tells Windows guests that our ACPI PM timer is reliable in the
2227 * sense that guest can read it only once to obtain a reliable value.
2228 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2230 build_append_int_noprefix(table_data
, 1 << 1 /* ACPI PM timer good */, 4);
2231 acpi_table_end(linker
, &table
);
2235 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2236 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2238 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2241 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2242 * necessary for the PCI topology.
2245 insert_ivhd(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
2247 GArray
*table_data
= opaque
;
2250 /* "Select" IVHD entry, type 0x2 */
2251 entry
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
) << 8 | 0x2;
2252 build_append_int_noprefix(table_data
, entry
, 4);
2254 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_BRIDGE
)) {
2255 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
2256 uint8_t sec
= pci_bus_num(sec_bus
);
2257 uint8_t sub
= dev
->config
[PCI_SUBORDINATE_BUS
];
2259 if (pci_bus_is_express(sec_bus
)) {
2261 * Walk the bus if there are subordinates, otherwise use a range
2262 * to cover an entire leaf bus. We could potentially also use a
2263 * range for traversed buses, but we'd need to take care not to
2264 * create both Select and Range entries covering the same device.
2265 * This is easier and potentially more compact.
2267 * An example bare metal system seems to use Select entries for
2268 * root ports without a slot (ie. built-ins) and Range entries
2269 * when there is a slot. The same system also only hard-codes
2270 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2271 * making no effort to support nested bridges. We attempt to
2272 * be more thorough here.
2274 if (sec
== sub
) { /* leaf bus */
2275 /* "Start of Range" IVHD entry, type 0x3 */
2276 entry
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0)) << 8 | 0x3;
2277 build_append_int_noprefix(table_data
, entry
, 4);
2278 /* "End of Range" IVHD entry, type 0x4 */
2279 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2280 build_append_int_noprefix(table_data
, entry
, 4);
2282 pci_for_each_device(sec_bus
, sec
, insert_ivhd
, table_data
);
2286 * If the secondary bus is conventional, then we need to create an
2287 * Alias range for everything downstream. The range covers the
2288 * first devfn on the secondary bus to the last devfn on the
2289 * subordinate bus. The alias target depends on legacy versus
2290 * express bridges, just as in pci_device_iommu_address_space().
2291 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2293 uint16_t dev_id_a
, dev_id_b
;
2295 dev_id_a
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0));
2297 if (pci_is_express(dev
) &&
2298 pcie_cap_get_type(dev
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2299 dev_id_b
= dev_id_a
;
2301 dev_id_b
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
);
2304 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2305 build_append_int_noprefix(table_data
, dev_id_a
<< 8 | 0x43, 4);
2306 build_append_int_noprefix(table_data
, dev_id_b
<< 8 | 0x0, 4);
2308 /* "End of Range" IVHD entry, type 0x4 */
2309 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2310 build_append_int_noprefix(table_data
, entry
, 4);
2315 /* For all PCI host bridges, walk and insert IVHD entries */
2317 ivrs_host_bridges(Object
*obj
, void *opaque
)
2319 GArray
*ivhd_blob
= opaque
;
2321 if (object_dynamic_cast(obj
, TYPE_PCI_HOST_BRIDGE
)) {
2322 PCIBus
*bus
= PCI_HOST_BRIDGE(obj
)->bus
;
2324 if (bus
&& !pci_bus_bypass_iommu(bus
)) {
2325 pci_for_each_device_under_bus(bus
, insert_ivhd
, ivhd_blob
);
2333 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
2334 const char *oem_table_id
)
2336 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2337 GArray
*ivhd_blob
= g_array_new(false, true, 1);
2338 AcpiTable table
= { .sig
= "IVRS", .rev
= 1, .oem_id
= oem_id
,
2339 .oem_table_id
= oem_table_id
};
2340 uint64_t feature_report
;
2342 acpi_table_begin(&table
, table_data
);
2343 /* IVinfo - IO virtualization information common to all
2344 * IOMMU units in a system
2346 build_append_int_noprefix(table_data
,
2347 (1UL << 0) | /* EFRSup */
2348 (40UL << 8), /* PASize */
2351 build_append_int_noprefix(table_data
, 0, 8);
2354 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2355 * complete set of IVHD entries. Do this into a separate blob so that we
2356 * can calculate the total IVRS table length here and then append the new
2357 * blob further below. Fall back to an entry covering all devices, which
2358 * is sufficient when no aliases are present.
2360 object_child_foreach_recursive(object_get_root(),
2361 ivrs_host_bridges
, ivhd_blob
);
2363 if (!ivhd_blob
->len
) {
2365 * Type 1 device entry reporting all devices
2366 * These are 4-byte device entries currently reporting the range of
2367 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2369 build_append_int_noprefix(ivhd_blob
, 0x0000001, 4);
2373 * When interrupt remapping is supported, we add a special IVHD device
2375 * Refer to spec - Table 95: IVHD device entry type codes
2377 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2378 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2380 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2381 build_append_int_noprefix(ivhd_blob
,
2382 (0x1ull
<< 56) | /* type IOAPIC */
2383 (IOAPIC_SB_DEVID
<< 40) | /* IOAPIC devid */
2384 0x48, /* special device */
2388 /* IVHD definition - type 10h */
2389 build_append_int_noprefix(table_data
, 0x10, 1);
2390 /* virtualization flags */
2391 build_append_int_noprefix(table_data
,
2392 (1UL << 0) | /* HtTunEn */
2393 (1UL << 4) | /* iotblSup */
2394 (1UL << 6) | /* PrefSup */
2395 (1UL << 7), /* PPRSup */
2399 build_append_int_noprefix(table_data
, ivhd_blob
->len
+ 24, 2);
2401 build_append_int_noprefix(table_data
,
2402 object_property_get_int(OBJECT(&s
->pci
), "addr",
2404 /* Capability offset */
2405 build_append_int_noprefix(table_data
, s
->pci
.capab_offset
, 2);
2406 /* IOMMU base address */
2407 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2408 /* PCI Segment Group */
2409 build_append_int_noprefix(table_data
, 0, 2);
2411 build_append_int_noprefix(table_data
, 0, 2);
2412 /* IOMMU Feature Reporting */
2413 feature_report
= (48UL << 30) | /* HATS */
2414 (48UL << 28) | /* GATS */
2415 (1UL << 2) | /* GTSup */
2416 (1UL << 6); /* GASup */
2418 feature_report
|= (1UL << 0); /* XTSup */
2420 build_append_int_noprefix(table_data
, feature_report
, 4);
2422 /* IVHD entries as found above */
2423 g_array_append_vals(table_data
, ivhd_blob
->data
, ivhd_blob
->len
);
2425 /* IVHD definition - type 11h */
2426 build_append_int_noprefix(table_data
, 0x11, 1);
2427 /* virtualization flags */
2428 build_append_int_noprefix(table_data
,
2429 (1UL << 0) | /* HtTunEn */
2430 (1UL << 4), /* iotblSup */
2434 build_append_int_noprefix(table_data
, ivhd_blob
->len
+ 40, 2);
2436 build_append_int_noprefix(table_data
,
2437 object_property_get_int(OBJECT(&s
->pci
), "addr",
2439 /* Capability offset */
2440 build_append_int_noprefix(table_data
, s
->pci
.capab_offset
, 2);
2441 /* IOMMU base address */
2442 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2443 /* PCI Segment Group */
2444 build_append_int_noprefix(table_data
, 0, 2);
2446 build_append_int_noprefix(table_data
, 0, 2);
2447 /* IOMMU Attributes */
2448 build_append_int_noprefix(table_data
, 0, 4);
2449 /* EFR Register Image */
2450 build_append_int_noprefix(table_data
,
2451 amdvi_extended_feature_register(s
),
2453 /* EFR Register Image 2 */
2454 build_append_int_noprefix(table_data
, 0, 8);
2456 /* IVHD entries as found above */
2457 g_array_append_vals(table_data
, ivhd_blob
->data
, ivhd_blob
->len
);
2459 g_array_free(ivhd_blob
, TRUE
);
2460 acpi_table_end(linker
, &table
);
2464 struct AcpiBuildState
{
2465 /* Copy of table in RAM (for patching). */
2466 MemoryRegion
*table_mr
;
2467 /* Is table patched? */
2470 MemoryRegion
*rsdp_mr
;
2471 MemoryRegion
*linker_mr
;
2474 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2479 pci_host
= acpi_get_i386_pci_host();
2484 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2488 mcfg
->base
= qnum_get_uint(qobject_to(QNum
, o
));
2490 if (mcfg
->base
== PCIE_BASE_ADDR_UNMAPPED
) {
2494 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2496 mcfg
->size
= qnum_get_uint(qobject_to(QNum
, o
));
2502 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2504 PCMachineState
*pcms
= PC_MACHINE(machine
);
2505 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2506 X86MachineState
*x86ms
= X86_MACHINE(machine
);
2507 DeviceState
*iommu
= pcms
->iommu
;
2508 GArray
*table_offsets
;
2509 unsigned facs
, dsdt
, rsdt
, fadt
;
2513 Range pci_hole
= {}, pci_hole64
= {};
2516 GArray
*tables_blob
= tables
->table_data
;
2517 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2518 Object
*vmgenid_dev
;
2522 acpi_get_pm_info(machine
, &pm
);
2523 acpi_get_misc_info(&misc
);
2524 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2525 acpi_get_slic_oem(&slic_oem
);
2528 oem_id
= slic_oem
.id
;
2530 oem_id
= x86ms
->oem_id
;
2533 if (slic_oem
.table_id
) {
2534 oem_table_id
= slic_oem
.table_id
;
2536 oem_table_id
= x86ms
->oem_table_id
;
2539 table_offsets
= g_array_new(false, true /* clear */,
2541 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2543 bios_linker_loader_alloc(tables
->linker
,
2544 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2545 64 /* Ensure FACS is aligned */,
2546 false /* high memory */);
2549 * FACS is pointed to by FADT.
2550 * We place it first since it's the only table that has alignment
2553 facs
= tables_blob
->len
;
2554 build_facs(tables_blob
);
2556 /* DSDT is pointed to by FADT */
2557 dsdt
= tables_blob
->len
;
2558 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2559 &pci_hole
, &pci_hole64
, machine
);
2561 /* Count the size of the DSDT and SSDT, we will need it for legacy
2562 * sizing of ACPI tables.
2564 aml_len
+= tables_blob
->len
- dsdt
;
2566 /* ACPI tables pointed to by RSDT */
2567 fadt
= tables_blob
->len
;
2568 acpi_add_table(table_offsets
, tables_blob
);
2569 pm
.fadt
.facs_tbl_offset
= &facs
;
2570 pm
.fadt
.dsdt_tbl_offset
= &dsdt
;
2571 pm
.fadt
.xdsdt_tbl_offset
= &dsdt
;
2572 build_fadt(tables_blob
, tables
->linker
, &pm
.fadt
, oem_id
, oem_table_id
);
2573 aml_len
+= tables_blob
->len
- fadt
;
2575 acpi_add_table(table_offsets
, tables_blob
);
2576 acpi_build_madt(tables_blob
, tables
->linker
, x86ms
,
2577 x86ms
->oem_id
, x86ms
->oem_table_id
);
2579 #ifdef CONFIG_ACPI_ERST
2582 erst_dev
= find_erst_dev();
2584 acpi_add_table(table_offsets
, tables_blob
);
2585 build_erst(tables_blob
, tables
->linker
, erst_dev
,
2586 x86ms
->oem_id
, x86ms
->oem_table_id
);
2591 vmgenid_dev
= find_vmgenid_dev();
2593 acpi_add_table(table_offsets
, tables_blob
);
2594 vmgenid_build_acpi(VMGENID(vmgenid_dev
), tables_blob
,
2595 tables
->vmgenid
, tables
->linker
, x86ms
->oem_id
);
2598 if (misc
.has_hpet
) {
2599 acpi_add_table(table_offsets
, tables_blob
);
2600 build_hpet(tables_blob
, tables
->linker
, x86ms
->oem_id
,
2601 x86ms
->oem_table_id
);
2604 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2605 if (misc
.tpm_version
== TPM_VERSION_1_2
) {
2606 acpi_add_table(table_offsets
, tables_blob
);
2607 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
,
2608 x86ms
->oem_id
, x86ms
->oem_table_id
);
2609 } else { /* TPM_VERSION_2_0 */
2610 acpi_add_table(table_offsets
, tables_blob
);
2611 build_tpm2(tables_blob
, tables
->linker
, tables
->tcpalog
,
2612 x86ms
->oem_id
, x86ms
->oem_table_id
);
2616 if (machine
->numa_state
->num_nodes
) {
2617 acpi_add_table(table_offsets
, tables_blob
);
2618 build_srat(tables_blob
, tables
->linker
, machine
);
2619 if (machine
->numa_state
->have_numa_distance
) {
2620 acpi_add_table(table_offsets
, tables_blob
);
2621 build_slit(tables_blob
, tables
->linker
, machine
, x86ms
->oem_id
,
2622 x86ms
->oem_table_id
);
2624 if (machine
->numa_state
->hmat_enabled
) {
2625 acpi_add_table(table_offsets
, tables_blob
);
2626 build_hmat(tables_blob
, tables
->linker
, machine
->numa_state
,
2627 x86ms
->oem_id
, x86ms
->oem_table_id
);
2630 if (acpi_get_mcfg(&mcfg
)) {
2631 acpi_add_table(table_offsets
, tables_blob
);
2632 build_mcfg(tables_blob
, tables
->linker
, &mcfg
, x86ms
->oem_id
,
2633 x86ms
->oem_table_id
);
2635 if (object_dynamic_cast(OBJECT(iommu
), TYPE_AMD_IOMMU_DEVICE
)) {
2636 acpi_add_table(table_offsets
, tables_blob
);
2637 build_amd_iommu(tables_blob
, tables
->linker
, x86ms
->oem_id
,
2638 x86ms
->oem_table_id
);
2639 } else if (object_dynamic_cast(OBJECT(iommu
), TYPE_INTEL_IOMMU_DEVICE
)) {
2640 acpi_add_table(table_offsets
, tables_blob
);
2641 build_dmar_q35(tables_blob
, tables
->linker
, x86ms
->oem_id
,
2642 x86ms
->oem_table_id
);
2643 } else if (object_dynamic_cast(OBJECT(iommu
), TYPE_VIRTIO_IOMMU_PCI
)) {
2644 PCIDevice
*pdev
= PCI_DEVICE(iommu
);
2646 acpi_add_table(table_offsets
, tables_blob
);
2647 build_viot(machine
, tables_blob
, tables
->linker
, pci_get_bdf(pdev
),
2648 x86ms
->oem_id
, x86ms
->oem_table_id
);
2650 if (machine
->nvdimms_state
->is_enabled
) {
2651 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2652 machine
->nvdimms_state
, machine
->ram_slots
,
2653 x86ms
->oem_id
, x86ms
->oem_table_id
);
2655 if (pcms
->cxl_devices_state
.is_enabled
) {
2656 cxl_build_cedt(table_offsets
, tables_blob
, tables
->linker
,
2657 x86ms
->oem_id
, x86ms
->oem_table_id
, &pcms
->cxl_devices_state
);
2660 acpi_add_table(table_offsets
, tables_blob
);
2661 build_waet(tables_blob
, tables
->linker
, x86ms
->oem_id
, x86ms
->oem_table_id
);
2663 /* Add tables supplied by user (if any) */
2664 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2665 unsigned len
= acpi_table_len(u
);
2667 acpi_add_table(table_offsets
, tables_blob
);
2668 g_array_append_vals(tables_blob
, u
, len
);
2671 /* RSDT is pointed to by RSDP */
2672 rsdt
= tables_blob
->len
;
2673 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2674 oem_id
, oem_table_id
);
2676 /* RSDP is in FSEG memory, so allocate it separately */
2678 AcpiRsdpData rsdp_data
= {
2680 .oem_id
= x86ms
->oem_id
,
2681 .xsdt_tbl_offset
= NULL
,
2682 .rsdt_tbl_offset
= &rsdt
,
2684 build_rsdp(tables
->rsdp
, tables
->linker
, &rsdp_data
);
2685 if (!pcmc
->rsdp_in_ram
) {
2686 /* We used to allocate some extra space for RSDP revision 2 but
2687 * only used the RSDP revision 0 space. The extra bytes were
2688 * zeroed out and not used.
2689 * Here we continue wasting those extra 16 bytes to make sure we
2690 * don't break migration for machine types 2.2 and older due to
2691 * RSDP blob size mismatch.
2693 build_append_int_noprefix(tables
->rsdp
, 0, 16);
2697 /* We'll expose it all to Guest so we want to reduce
2698 * chance of size changes.
2700 * We used to align the tables to 4k, but of course this would
2701 * too simple to be enough. 4k turned out to be too small an
2702 * alignment very soon, and in fact it is almost impossible to
2703 * keep the table size stable for all (max_cpus, max_memory_slots)
2704 * combinations. So the table size is always 64k for pc-i440fx-2.1
2705 * and we give an error if the table grows beyond that limit.
2707 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2708 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2709 * than 2.0 and we can always pad the smaller tables with zeros. We can
2710 * then use the exact size of the 2.0 tables.
2712 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2714 if (pcmc
->legacy_acpi_table_size
) {
2715 /* Subtracting aml_len gives the size of fixed tables. Then add the
2716 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2718 int legacy_aml_len
=
2719 pcmc
->legacy_acpi_table_size
+
2720 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* x86ms
->apic_id_limit
;
2721 int legacy_table_size
=
2722 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2723 ACPI_BUILD_ALIGN_SIZE
);
2724 if ((tables_blob
->len
> legacy_table_size
) &&
2725 !pcmc
->resizable_acpi_blob
) {
2726 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2727 warn_report("ACPI table size %u exceeds %d bytes,"
2728 " migration may not work",
2729 tables_blob
->len
, legacy_table_size
);
2730 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2731 " or PCI bridges.\n");
2733 g_array_set_size(tables_blob
, legacy_table_size
);
2735 /* Make sure we have a buffer in case we need to resize the tables. */
2736 if ((tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) &&
2737 !pcmc
->resizable_acpi_blob
) {
2738 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2739 warn_report("ACPI table size %u exceeds %d bytes,"
2740 " migration may not work",
2741 tables_blob
->len
, ACPI_BUILD_TABLE_SIZE
/ 2);
2742 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2743 " or PCI bridges.\n");
2745 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2748 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2750 /* Cleanup memory that's no longer used. */
2751 g_array_free(table_offsets
, true);
2752 g_free(slic_oem
.id
);
2753 g_free(slic_oem
.table_id
);
2756 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2758 uint32_t size
= acpi_data_len(data
);
2760 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2761 memory_region_ram_resize(mr
, size
, &error_abort
);
2763 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2764 memory_region_set_dirty(mr
, 0, size
);
2767 static void acpi_build_update(void *build_opaque
)
2769 AcpiBuildState
*build_state
= build_opaque
;
2770 AcpiBuildTables tables
;
2772 /* No state to update or already patched? Nothing to do. */
2773 if (!build_state
|| build_state
->patched
) {
2776 build_state
->patched
= 1;
2778 acpi_build_tables_init(&tables
);
2780 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2782 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2784 if (build_state
->rsdp
) {
2785 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2787 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2790 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2791 acpi_build_tables_cleanup(&tables
, true);
2794 static void acpi_build_reset(void *build_opaque
)
2796 AcpiBuildState
*build_state
= build_opaque
;
2797 build_state
->patched
= 0;
2800 static const VMStateDescription vmstate_acpi_build
= {
2801 .name
= "acpi_build",
2803 .minimum_version_id
= 1,
2804 .fields
= (const VMStateField
[]) {
2805 VMSTATE_UINT8(patched
, AcpiBuildState
),
2806 VMSTATE_END_OF_LIST()
2810 void acpi_setup(void)
2812 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2813 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2814 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
2815 AcpiBuildTables tables
;
2816 AcpiBuildState
*build_state
;
2817 Object
*vmgenid_dev
;
2820 static FwCfgTPMConfig tpm_config
;
2823 if (!x86ms
->fw_cfg
) {
2824 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2828 if (!pcms
->acpi_build_enabled
) {
2829 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2833 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms
))) {
2834 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2838 build_state
= g_malloc0(sizeof *build_state
);
2840 acpi_build_tables_init(&tables
);
2841 acpi_build(&tables
, MACHINE(pcms
));
2843 /* Now expose it all to Guest */
2844 build_state
->table_mr
= acpi_add_rom_blob(acpi_build_update
,
2845 build_state
, tables
.table_data
,
2846 ACPI_BUILD_TABLE_FILE
);
2847 assert(build_state
->table_mr
!= NULL
);
2849 build_state
->linker_mr
=
2850 acpi_add_rom_blob(acpi_build_update
, build_state
,
2851 tables
.linker
->cmd_blob
, ACPI_BUILD_LOADER_FILE
);
2854 fw_cfg_add_file(x86ms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2855 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2858 if (tpm
&& object_property_get_bool(OBJECT(tpm
), "ppi", &error_abort
)) {
2859 tpm_config
= (FwCfgTPMConfig
) {
2860 .tpmppi_address
= cpu_to_le32(TPM_PPI_ADDR_BASE
),
2861 .tpm_version
= tpm_get_version(tpm
),
2862 .tpmppi_version
= TPM_PPI_VERSION_1_30
2864 fw_cfg_add_file(x86ms
->fw_cfg
, "etc/tpm/config",
2865 &tpm_config
, sizeof tpm_config
);
2869 vmgenid_dev
= find_vmgenid_dev();
2871 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev
), x86ms
->fw_cfg
,
2875 if (!pcmc
->rsdp_in_ram
) {
2877 * Keep for compatibility with old machine types.
2878 * Though RSDP is small, its contents isn't immutable, so
2879 * we'll update it along with the rest of tables on guest access.
2881 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2883 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2884 fw_cfg_add_file_callback(x86ms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2885 acpi_build_update
, NULL
, build_state
,
2886 build_state
->rsdp
, rsdp_size
, true);
2887 build_state
->rsdp_mr
= NULL
;
2889 build_state
->rsdp
= NULL
;
2890 build_state
->rsdp_mr
= acpi_add_rom_blob(acpi_build_update
,
2891 build_state
, tables
.rsdp
,
2892 ACPI_BUILD_RSDP_FILE
);
2895 qemu_register_reset(acpi_build_reset
, build_state
);
2896 acpi_build_reset(build_state
);
2897 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2899 /* Cleanup tables but don't free the memory: we track it
2902 acpi_build_tables_cleanup(&tables
, false);