2 * QEMU Firmware configuration device emulation
4 * Copyright (c) 2008 Gleb Natapov
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "sysemu/sysemu.h"
26 #include "sysemu/dma.h"
27 #include "hw/isa/isa.h"
28 #include "hw/nvram/fw_cfg.h"
29 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/config-file.h"
34 #define FW_CFG_CTL_SIZE 2
35 #define FW_CFG_NAME "fw_cfg"
36 #define FW_CFG_PATH "/machine/" FW_CFG_NAME
38 #define TYPE_FW_CFG "fw_cfg"
39 #define TYPE_FW_CFG_IO "fw_cfg_io"
40 #define TYPE_FW_CFG_MEM "fw_cfg_mem"
42 #define FW_CFG(obj) OBJECT_CHECK(FWCfgState, (obj), TYPE_FW_CFG)
43 #define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_IO)
44 #define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM)
46 /* FW_CFG_VERSION bits */
47 #define FW_CFG_VERSION 0x01
48 #define FW_CFG_VERSION_DMA 0x02
50 /* FW_CFG_DMA_CONTROL bits */
51 #define FW_CFG_DMA_CTL_ERROR 0x01
52 #define FW_CFG_DMA_CTL_READ 0x02
53 #define FW_CFG_DMA_CTL_SKIP 0x04
54 #define FW_CFG_DMA_CTL_SELECT 0x08
56 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
58 typedef struct FWCfgEntry
{
61 void *callback_opaque
;
62 FWCfgReadCallback read_callback
;
67 SysBusDevice parent_obj
;
70 FWCfgEntry entries
[2][FW_CFG_MAX_ENTRY
];
74 Notifier machine_ready
;
79 MemoryRegion dma_iomem
;
84 FWCfgState parent_obj
;
87 MemoryRegion comb_iomem
;
88 uint32_t iobase
, dma_iobase
;
91 struct FWCfgMemState
{
93 FWCfgState parent_obj
;
96 MemoryRegion ctl_iomem
, data_iomem
;
98 MemoryRegionOps wide_data_ops
;
104 static char *read_splashfile(char *filename
, gsize
*file_sizep
,
111 unsigned int filehead
;
114 res
= g_file_get_contents(filename
, &content
, file_sizep
, &err
);
116 error_report("failed to read splash file '%s'", filename
);
121 /* check file size */
122 if (*file_sizep
< 30) {
127 filehead
= ((content
[0] & 0xff) + (content
[1] << 8)) & 0xffff;
128 if (filehead
== 0xd8ff) {
129 file_type
= JPG_FILE
;
130 } else if (filehead
== 0x4d42) {
131 file_type
= BMP_FILE
;
137 if (file_type
== BMP_FILE
) {
138 bmp_bpp
= (content
[28] + (content
[29] << 8)) & 0xffff;
145 *file_typep
= file_type
;
150 error_report("splash file '%s' format not recognized; must be JPEG "
151 "or 24 bit BMP", filename
);
156 static void fw_cfg_bootsplash(FWCfgState
*s
)
158 int boot_splash_time
= -1;
159 const char *boot_splash_filename
= NULL
;
161 char *filename
, *file_data
;
166 /* get user configuration */
167 QemuOptsList
*plist
= qemu_find_opts("boot-opts");
168 QemuOpts
*opts
= QTAILQ_FIRST(&plist
->head
);
170 temp
= qemu_opt_get(opts
, "splash");
172 boot_splash_filename
= temp
;
174 temp
= qemu_opt_get(opts
, "splash-time");
177 boot_splash_time
= strtol(p
, (char **)&p
, 10);
181 /* insert splash time if user configurated */
182 if (boot_splash_time
>= 0) {
183 /* validate the input */
184 if (boot_splash_time
> 0xffff) {
185 error_report("splash time is big than 65535, force it to 65535.");
186 boot_splash_time
= 0xffff;
188 /* use little endian format */
189 qemu_extra_params_fw
[0] = (uint8_t)(boot_splash_time
& 0xff);
190 qemu_extra_params_fw
[1] = (uint8_t)((boot_splash_time
>> 8) & 0xff);
191 fw_cfg_add_file(s
, "etc/boot-menu-wait", qemu_extra_params_fw
, 2);
194 /* insert splash file if user configurated */
195 if (boot_splash_filename
!= NULL
) {
196 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, boot_splash_filename
);
197 if (filename
== NULL
) {
198 error_report("failed to find file '%s'.", boot_splash_filename
);
202 /* loading file data */
203 file_data
= read_splashfile(filename
, &file_size
, &file_type
);
204 if (file_data
== NULL
) {
208 g_free(boot_splash_filedata
);
209 boot_splash_filedata
= (uint8_t *)file_data
;
210 boot_splash_filedata_size
= file_size
;
213 if (file_type
== JPG_FILE
) {
214 fw_cfg_add_file(s
, "bootsplash.jpg",
215 boot_splash_filedata
, boot_splash_filedata_size
);
217 fw_cfg_add_file(s
, "bootsplash.bmp",
218 boot_splash_filedata
, boot_splash_filedata_size
);
224 static void fw_cfg_reboot(FWCfgState
*s
)
226 int reboot_timeout
= -1;
230 /* get user configuration */
231 QemuOptsList
*plist
= qemu_find_opts("boot-opts");
232 QemuOpts
*opts
= QTAILQ_FIRST(&plist
->head
);
234 temp
= qemu_opt_get(opts
, "reboot-timeout");
237 reboot_timeout
= strtol(p
, (char **)&p
, 10);
240 /* validate the input */
241 if (reboot_timeout
> 0xffff) {
242 error_report("reboot timeout is larger than 65535, force it to 65535.");
243 reboot_timeout
= 0xffff;
245 fw_cfg_add_file(s
, "etc/boot-fail-wait", g_memdup(&reboot_timeout
, 4), 4);
248 static void fw_cfg_write(FWCfgState
*s
, uint8_t value
)
250 /* nothing, write support removed in QEMU v2.4+ */
253 static int fw_cfg_select(FWCfgState
*s
, uint16_t key
)
259 if ((key
& FW_CFG_ENTRY_MASK
) >= FW_CFG_MAX_ENTRY
) {
260 s
->cur_entry
= FW_CFG_INVALID
;
265 /* entry successfully selected, now run callback if present */
266 arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
267 e
= &s
->entries
[arch
][key
& FW_CFG_ENTRY_MASK
];
268 if (e
->read_callback
) {
269 e
->read_callback(e
->callback_opaque
);
273 trace_fw_cfg_select(s
, key
, ret
);
277 static uint64_t fw_cfg_data_read(void *opaque
, hwaddr addr
, unsigned size
)
279 FWCfgState
*s
= opaque
;
280 int arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
281 FWCfgEntry
*e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
282 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
285 assert(size
> 0 && size
<= sizeof(value
));
286 if (s
->cur_entry
!= FW_CFG_INVALID
&& e
->data
&& s
->cur_offset
< e
->len
) {
287 /* The least significant 'size' bytes of the return value are
288 * expected to contain a string preserving portion of the item
289 * data, padded with zeros on the right in case we run out early.
290 * In technical terms, we're composing the host-endian representation
291 * of the big endian interpretation of the fw_cfg string.
294 value
= (value
<< 8) | e
->data
[s
->cur_offset
++];
295 } while (--size
&& s
->cur_offset
< e
->len
);
296 /* If size is still not zero, we *did* run out early, so continue
297 * left-shifting, to add the appropriate number of padding zeros
303 trace_fw_cfg_read(s
, value
);
307 static void fw_cfg_data_mem_write(void *opaque
, hwaddr addr
,
308 uint64_t value
, unsigned size
)
310 FWCfgState
*s
= opaque
;
314 fw_cfg_write(s
, value
>> (8 * --i
));
318 static void fw_cfg_dma_transfer(FWCfgState
*s
)
327 /* Reset the address before the next access */
328 dma_addr
= s
->dma_addr
;
331 if (dma_memory_read(s
->dma_as
, dma_addr
, &dma
, sizeof(dma
))) {
332 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
333 FW_CFG_DMA_CTL_ERROR
);
337 dma
.address
= be64_to_cpu(dma
.address
);
338 dma
.length
= be32_to_cpu(dma
.length
);
339 dma
.control
= be32_to_cpu(dma
.control
);
341 if (dma
.control
& FW_CFG_DMA_CTL_SELECT
) {
342 fw_cfg_select(s
, dma
.control
>> 16);
345 arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
346 e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
347 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
349 if (dma
.control
& FW_CFG_DMA_CTL_READ
) {
351 } else if (dma
.control
& FW_CFG_DMA_CTL_SKIP
) {
359 while (dma
.length
> 0 && !(dma
.control
& FW_CFG_DMA_CTL_ERROR
)) {
360 if (s
->cur_entry
== FW_CFG_INVALID
|| !e
->data
||
361 s
->cur_offset
>= e
->len
) {
364 /* If the access is not a read access, it will be a skip access,
368 if (dma_memory_set(s
->dma_as
, dma
.address
, 0, len
)) {
369 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
374 if (dma
.length
<= (e
->len
- s
->cur_offset
)) {
377 len
= (e
->len
- s
->cur_offset
);
380 /* If the access is not a read access, it will be a skip access,
384 if (dma_memory_write(s
->dma_as
, dma
.address
,
385 &e
->data
[s
->cur_offset
], len
)) {
386 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
390 s
->cur_offset
+= len
;
398 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
401 trace_fw_cfg_read(s
, 0);
404 static uint64_t fw_cfg_dma_mem_read(void *opaque
, hwaddr addr
,
407 /* Return a signature value (and handle various read sizes) */
408 return extract64(FW_CFG_DMA_SIGNATURE
, (8 - addr
- size
) * 8, size
* 8);
411 static void fw_cfg_dma_mem_write(void *opaque
, hwaddr addr
,
412 uint64_t value
, unsigned size
)
414 FWCfgState
*s
= opaque
;
418 /* FWCfgDmaAccess high address */
419 s
->dma_addr
= value
<< 32;
420 } else if (addr
== 4) {
421 /* FWCfgDmaAccess low address */
422 s
->dma_addr
|= value
;
423 fw_cfg_dma_transfer(s
);
425 } else if (size
== 8 && addr
== 0) {
427 fw_cfg_dma_transfer(s
);
431 static bool fw_cfg_dma_mem_valid(void *opaque
, hwaddr addr
,
432 unsigned size
, bool is_write
)
434 return !is_write
|| ((size
== 4 && (addr
== 0 || addr
== 4)) ||
435 (size
== 8 && addr
== 0));
438 static bool fw_cfg_data_mem_valid(void *opaque
, hwaddr addr
,
439 unsigned size
, bool is_write
)
444 static void fw_cfg_ctl_mem_write(void *opaque
, hwaddr addr
,
445 uint64_t value
, unsigned size
)
447 fw_cfg_select(opaque
, (uint16_t)value
);
450 static bool fw_cfg_ctl_mem_valid(void *opaque
, hwaddr addr
,
451 unsigned size
, bool is_write
)
453 return is_write
&& size
== 2;
456 static void fw_cfg_comb_write(void *opaque
, hwaddr addr
,
457 uint64_t value
, unsigned size
)
461 fw_cfg_write(opaque
, (uint8_t)value
);
464 fw_cfg_select(opaque
, (uint16_t)value
);
469 static bool fw_cfg_comb_valid(void *opaque
, hwaddr addr
,
470 unsigned size
, bool is_write
)
472 return (size
== 1) || (is_write
&& size
== 2);
475 static const MemoryRegionOps fw_cfg_ctl_mem_ops
= {
476 .write
= fw_cfg_ctl_mem_write
,
477 .endianness
= DEVICE_BIG_ENDIAN
,
478 .valid
.accepts
= fw_cfg_ctl_mem_valid
,
481 static const MemoryRegionOps fw_cfg_data_mem_ops
= {
482 .read
= fw_cfg_data_read
,
483 .write
= fw_cfg_data_mem_write
,
484 .endianness
= DEVICE_BIG_ENDIAN
,
486 .min_access_size
= 1,
487 .max_access_size
= 1,
488 .accepts
= fw_cfg_data_mem_valid
,
492 static const MemoryRegionOps fw_cfg_comb_mem_ops
= {
493 .read
= fw_cfg_data_read
,
494 .write
= fw_cfg_comb_write
,
495 .endianness
= DEVICE_LITTLE_ENDIAN
,
496 .valid
.accepts
= fw_cfg_comb_valid
,
499 static const MemoryRegionOps fw_cfg_dma_mem_ops
= {
500 .read
= fw_cfg_dma_mem_read
,
501 .write
= fw_cfg_dma_mem_write
,
502 .endianness
= DEVICE_BIG_ENDIAN
,
503 .valid
.accepts
= fw_cfg_dma_mem_valid
,
504 .valid
.max_access_size
= 8,
505 .impl
.max_access_size
= 8,
508 static void fw_cfg_reset(DeviceState
*d
)
510 FWCfgState
*s
= FW_CFG(d
);
512 /* we never register a read callback for FW_CFG_SIGNATURE */
513 fw_cfg_select(s
, FW_CFG_SIGNATURE
);
516 /* Save restore 32 bit int as uint16_t
517 This is a Big hack, but it is how the old state did it.
518 Or we broke compatibility in the state, or we can't use struct tm
521 static int get_uint32_as_uint16(QEMUFile
*f
, void *pv
, size_t size
)
524 *v
= qemu_get_be16(f
);
528 static void put_unused(QEMUFile
*f
, void *pv
, size_t size
)
530 fprintf(stderr
, "uint32_as_uint16 is only used for backward compatibility.\n");
531 fprintf(stderr
, "This functions shouldn't be called.\n");
534 static const VMStateInfo vmstate_hack_uint32_as_uint16
= {
535 .name
= "int32_as_uint16",
536 .get
= get_uint32_as_uint16
,
540 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
541 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
544 static bool is_version_1(void *opaque
, int version_id
)
546 return version_id
== 1;
549 static bool fw_cfg_dma_enabled(void *opaque
)
551 FWCfgState
*s
= opaque
;
553 return s
->dma_enabled
;
556 static const VMStateDescription vmstate_fw_cfg_dma
= {
557 .name
= "fw_cfg/dma",
558 .needed
= fw_cfg_dma_enabled
,
559 .fields
= (VMStateField
[]) {
560 VMSTATE_UINT64(dma_addr
, FWCfgState
),
561 VMSTATE_END_OF_LIST()
565 static const VMStateDescription vmstate_fw_cfg
= {
568 .minimum_version_id
= 1,
569 .fields
= (VMStateField
[]) {
570 VMSTATE_UINT16(cur_entry
, FWCfgState
),
571 VMSTATE_UINT16_HACK(cur_offset
, FWCfgState
, is_version_1
),
572 VMSTATE_UINT32_V(cur_offset
, FWCfgState
, 2),
573 VMSTATE_END_OF_LIST()
575 .subsections
= (const VMStateDescription
*[]) {
581 static void fw_cfg_add_bytes_read_callback(FWCfgState
*s
, uint16_t key
,
582 FWCfgReadCallback callback
,
583 void *callback_opaque
,
584 void *data
, size_t len
)
586 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
588 key
&= FW_CFG_ENTRY_MASK
;
590 assert(key
< FW_CFG_MAX_ENTRY
&& len
< UINT32_MAX
);
591 assert(s
->entries
[arch
][key
].data
== NULL
); /* avoid key conflict */
593 s
->entries
[arch
][key
].data
= data
;
594 s
->entries
[arch
][key
].len
= (uint32_t)len
;
595 s
->entries
[arch
][key
].read_callback
= callback
;
596 s
->entries
[arch
][key
].callback_opaque
= callback_opaque
;
599 static void *fw_cfg_modify_bytes_read(FWCfgState
*s
, uint16_t key
,
600 void *data
, size_t len
)
603 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
605 key
&= FW_CFG_ENTRY_MASK
;
607 assert(key
< FW_CFG_MAX_ENTRY
&& len
< UINT32_MAX
);
609 /* return the old data to the function caller, avoid memory leak */
610 ptr
= s
->entries
[arch
][key
].data
;
611 s
->entries
[arch
][key
].data
= data
;
612 s
->entries
[arch
][key
].len
= len
;
613 s
->entries
[arch
][key
].callback_opaque
= NULL
;
618 void fw_cfg_add_bytes(FWCfgState
*s
, uint16_t key
, void *data
, size_t len
)
620 fw_cfg_add_bytes_read_callback(s
, key
, NULL
, NULL
, data
, len
);
623 void fw_cfg_add_string(FWCfgState
*s
, uint16_t key
, const char *value
)
625 size_t sz
= strlen(value
) + 1;
627 fw_cfg_add_bytes(s
, key
, g_memdup(value
, sz
), sz
);
630 void fw_cfg_add_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
634 copy
= g_malloc(sizeof(value
));
635 *copy
= cpu_to_le16(value
);
636 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
639 void fw_cfg_modify_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
641 uint16_t *copy
, *old
;
643 copy
= g_malloc(sizeof(value
));
644 *copy
= cpu_to_le16(value
);
645 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
649 void fw_cfg_add_i32(FWCfgState
*s
, uint16_t key
, uint32_t value
)
653 copy
= g_malloc(sizeof(value
));
654 *copy
= cpu_to_le32(value
);
655 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
658 void fw_cfg_add_i64(FWCfgState
*s
, uint16_t key
, uint64_t value
)
662 copy
= g_malloc(sizeof(value
));
663 *copy
= cpu_to_le64(value
);
664 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
667 void fw_cfg_add_file_callback(FWCfgState
*s
, const char *filename
,
668 FWCfgReadCallback callback
, void *callback_opaque
,
669 void *data
, size_t len
)
675 dsize
= sizeof(uint32_t) + sizeof(FWCfgFile
) * FW_CFG_FILE_SLOTS
;
676 s
->files
= g_malloc0(dsize
);
677 fw_cfg_add_bytes(s
, FW_CFG_FILE_DIR
, s
->files
, dsize
);
680 index
= be32_to_cpu(s
->files
->count
);
681 assert(index
< FW_CFG_FILE_SLOTS
);
683 pstrcpy(s
->files
->f
[index
].name
, sizeof(s
->files
->f
[index
].name
),
685 for (i
= 0; i
< index
; i
++) {
686 if (strcmp(s
->files
->f
[index
].name
, s
->files
->f
[i
].name
) == 0) {
687 error_report("duplicate fw_cfg file name: %s",
688 s
->files
->f
[index
].name
);
693 fw_cfg_add_bytes_read_callback(s
, FW_CFG_FILE_FIRST
+ index
,
694 callback
, callback_opaque
, data
, len
);
696 s
->files
->f
[index
].size
= cpu_to_be32(len
);
697 s
->files
->f
[index
].select
= cpu_to_be16(FW_CFG_FILE_FIRST
+ index
);
698 trace_fw_cfg_add_file(s
, index
, s
->files
->f
[index
].name
, len
);
700 s
->files
->count
= cpu_to_be32(index
+1);
703 void fw_cfg_add_file(FWCfgState
*s
, const char *filename
,
704 void *data
, size_t len
)
706 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, data
, len
);
709 void *fw_cfg_modify_file(FWCfgState
*s
, const char *filename
,
710 void *data
, size_t len
)
717 index
= be32_to_cpu(s
->files
->count
);
718 assert(index
< FW_CFG_FILE_SLOTS
);
720 for (i
= 0; i
< index
; i
++) {
721 if (strcmp(filename
, s
->files
->f
[i
].name
) == 0) {
722 ptr
= fw_cfg_modify_bytes_read(s
, FW_CFG_FILE_FIRST
+ i
,
724 s
->files
->f
[i
].size
= cpu_to_be32(len
);
729 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, data
, len
);
733 static void fw_cfg_machine_reset(void *opaque
)
737 FWCfgState
*s
= opaque
;
738 char *bootindex
= get_boot_devices_list(&len
, false);
740 ptr
= fw_cfg_modify_file(s
, "bootorder", (uint8_t *)bootindex
, len
);
744 static void fw_cfg_machine_ready(struct Notifier
*n
, void *data
)
746 FWCfgState
*s
= container_of(n
, FWCfgState
, machine_ready
);
747 qemu_register_reset(fw_cfg_machine_reset
, s
);
752 static void fw_cfg_init1(DeviceState
*dev
)
754 FWCfgState
*s
= FW_CFG(dev
);
756 assert(!object_resolve_path(FW_CFG_PATH
, NULL
));
758 object_property_add_child(qdev_get_machine(), FW_CFG_NAME
, OBJECT(s
), NULL
);
760 qdev_init_nofail(dev
);
762 fw_cfg_add_bytes(s
, FW_CFG_SIGNATURE
, (char *)"QEMU", 4);
763 fw_cfg_add_bytes(s
, FW_CFG_UUID
, qemu_uuid
, 16);
764 fw_cfg_add_i16(s
, FW_CFG_NOGRAPHIC
, (uint16_t)(display_type
== DT_NOGRAPHIC
));
765 fw_cfg_add_i16(s
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
766 fw_cfg_add_i16(s
, FW_CFG_BOOT_MENU
, (uint16_t)boot_menu
);
767 fw_cfg_bootsplash(s
);
770 s
->machine_ready
.notify
= fw_cfg_machine_ready
;
771 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
774 FWCfgState
*fw_cfg_init_io_dma(uint32_t iobase
, uint32_t dma_iobase
,
775 AddressSpace
*dma_as
)
779 uint32_t version
= FW_CFG_VERSION
;
780 bool dma_enabled
= dma_iobase
&& dma_as
;
782 dev
= qdev_create(NULL
, TYPE_FW_CFG_IO
);
783 qdev_prop_set_uint32(dev
, "iobase", iobase
);
784 qdev_prop_set_uint32(dev
, "dma_iobase", dma_iobase
);
785 qdev_prop_set_bit(dev
, "dma_enabled", dma_enabled
);
791 /* 64 bits for the address field */
795 version
|= FW_CFG_VERSION_DMA
;
798 fw_cfg_add_i32(s
, FW_CFG_ID
, version
);
803 FWCfgState
*fw_cfg_init_io(uint32_t iobase
)
805 return fw_cfg_init_io_dma(iobase
, 0, NULL
);
808 FWCfgState
*fw_cfg_init_mem_wide(hwaddr ctl_addr
,
809 hwaddr data_addr
, uint32_t data_width
,
810 hwaddr dma_addr
, AddressSpace
*dma_as
)
815 uint32_t version
= FW_CFG_VERSION
;
816 bool dma_enabled
= dma_addr
&& dma_as
;
818 dev
= qdev_create(NULL
, TYPE_FW_CFG_MEM
);
819 qdev_prop_set_uint32(dev
, "data_width", data_width
);
820 qdev_prop_set_bit(dev
, "dma_enabled", dma_enabled
);
824 sbd
= SYS_BUS_DEVICE(dev
);
825 sysbus_mmio_map(sbd
, 0, ctl_addr
);
826 sysbus_mmio_map(sbd
, 1, data_addr
);
833 sysbus_mmio_map(sbd
, 2, dma_addr
);
834 version
|= FW_CFG_VERSION_DMA
;
837 fw_cfg_add_i32(s
, FW_CFG_ID
, version
);
842 FWCfgState
*fw_cfg_init_mem(hwaddr ctl_addr
, hwaddr data_addr
)
844 return fw_cfg_init_mem_wide(ctl_addr
, data_addr
,
845 fw_cfg_data_mem_ops
.valid
.max_access_size
,
850 FWCfgState
*fw_cfg_find(void)
852 return FW_CFG(object_resolve_path(FW_CFG_PATH
, NULL
));
855 static void fw_cfg_class_init(ObjectClass
*klass
, void *data
)
857 DeviceClass
*dc
= DEVICE_CLASS(klass
);
859 dc
->reset
= fw_cfg_reset
;
860 dc
->vmsd
= &vmstate_fw_cfg
;
863 static const TypeInfo fw_cfg_info
= {
865 .parent
= TYPE_SYS_BUS_DEVICE
,
866 .instance_size
= sizeof(FWCfgState
),
867 .class_init
= fw_cfg_class_init
,
871 static Property fw_cfg_io_properties
[] = {
872 DEFINE_PROP_UINT32("iobase", FWCfgIoState
, iobase
, -1),
873 DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState
, dma_iobase
, -1),
874 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState
, parent_obj
.dma_enabled
,
876 DEFINE_PROP_END_OF_LIST(),
879 static void fw_cfg_io_realize(DeviceState
*dev
, Error
**errp
)
881 FWCfgIoState
*s
= FW_CFG_IO(dev
);
882 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
884 memory_region_init_io(&s
->comb_iomem
, OBJECT(s
), &fw_cfg_comb_mem_ops
,
885 FW_CFG(s
), "fwcfg", FW_CFG_CTL_SIZE
);
886 sysbus_add_io(sbd
, s
->iobase
, &s
->comb_iomem
);
888 if (FW_CFG(s
)->dma_enabled
) {
889 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
890 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
892 sysbus_add_io(sbd
, s
->dma_iobase
, &FW_CFG(s
)->dma_iomem
);
896 static void fw_cfg_io_class_init(ObjectClass
*klass
, void *data
)
898 DeviceClass
*dc
= DEVICE_CLASS(klass
);
900 dc
->realize
= fw_cfg_io_realize
;
901 dc
->props
= fw_cfg_io_properties
;
904 static const TypeInfo fw_cfg_io_info
= {
905 .name
= TYPE_FW_CFG_IO
,
906 .parent
= TYPE_FW_CFG
,
907 .instance_size
= sizeof(FWCfgIoState
),
908 .class_init
= fw_cfg_io_class_init
,
912 static Property fw_cfg_mem_properties
[] = {
913 DEFINE_PROP_UINT32("data_width", FWCfgMemState
, data_width
, -1),
914 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState
, parent_obj
.dma_enabled
,
916 DEFINE_PROP_END_OF_LIST(),
919 static void fw_cfg_mem_realize(DeviceState
*dev
, Error
**errp
)
921 FWCfgMemState
*s
= FW_CFG_MEM(dev
);
922 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
923 const MemoryRegionOps
*data_ops
= &fw_cfg_data_mem_ops
;
925 memory_region_init_io(&s
->ctl_iomem
, OBJECT(s
), &fw_cfg_ctl_mem_ops
,
926 FW_CFG(s
), "fwcfg.ctl", FW_CFG_CTL_SIZE
);
927 sysbus_init_mmio(sbd
, &s
->ctl_iomem
);
929 if (s
->data_width
> data_ops
->valid
.max_access_size
) {
930 /* memberwise copy because the "old_mmio" member is const */
931 s
->wide_data_ops
.read
= data_ops
->read
;
932 s
->wide_data_ops
.write
= data_ops
->write
;
933 s
->wide_data_ops
.endianness
= data_ops
->endianness
;
934 s
->wide_data_ops
.valid
= data_ops
->valid
;
935 s
->wide_data_ops
.impl
= data_ops
->impl
;
937 s
->wide_data_ops
.valid
.max_access_size
= s
->data_width
;
938 s
->wide_data_ops
.impl
.max_access_size
= s
->data_width
;
939 data_ops
= &s
->wide_data_ops
;
941 memory_region_init_io(&s
->data_iomem
, OBJECT(s
), data_ops
, FW_CFG(s
),
942 "fwcfg.data", data_ops
->valid
.max_access_size
);
943 sysbus_init_mmio(sbd
, &s
->data_iomem
);
945 if (FW_CFG(s
)->dma_enabled
) {
946 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
947 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
949 sysbus_init_mmio(sbd
, &FW_CFG(s
)->dma_iomem
);
953 static void fw_cfg_mem_class_init(ObjectClass
*klass
, void *data
)
955 DeviceClass
*dc
= DEVICE_CLASS(klass
);
957 dc
->realize
= fw_cfg_mem_realize
;
958 dc
->props
= fw_cfg_mem_properties
;
961 static const TypeInfo fw_cfg_mem_info
= {
962 .name
= TYPE_FW_CFG_MEM
,
963 .parent
= TYPE_FW_CFG
,
964 .instance_size
= sizeof(FWCfgMemState
),
965 .class_init
= fw_cfg_mem_class_init
,
969 static void fw_cfg_register_types(void)
971 type_register_static(&fw_cfg_info
);
972 type_register_static(&fw_cfg_io_info
);
973 type_register_static(&fw_cfg_mem_info
);
976 type_init(fw_cfg_register_types
)