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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / linux-user / main.c
blob91b3f8cfd2f389c4ad8bf682c1806369f6d11316
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <sys/mman.h>
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qemu.h"
25 #include "qemu-common.h"
26 #include "cpu.h"
27 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
28 #include "vsyscall.h"
29 #endif
30 #include "tcg.h"
31 #include "qemu/timer.h"
32 #include "qemu/envlist.h"
33 #include "elf.h"
34
35 char *exec_path;
36
37 int singlestep;
38 const char *filename;
39 const char *argv0;
40 int gdbstub_port;
41 envlist_t *envlist;
42 static const char *cpu_model;
43 unsigned long mmap_min_addr;
44 #if defined(CONFIG_USE_GUEST_BASE)
45 uintptr_t guest_base;
46 int have_guest_base;
47 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
48 /*
49 * When running 32-on-64 we should make sure we can fit all of the possible
50 * guest address space into a contiguous chunk of virtual host memory.
51 *
52 * This way we will never overlap with our own libraries or binaries or stack
53 * or anything else that QEMU maps.
54 */
55 # ifdef TARGET_MIPS
56 /* MIPS only supports 31 bits of virtual address space for user space */
57 uintptr_t reserved_va = 0x77000000;
58 # else
59 uintptr_t reserved_va = 0xf7000000;
60 # endif
61 #else
62 uintptr_t reserved_va;
63 #endif
64 #endif
65
66 static void usage(void);
67
68 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
69 const char *qemu_uname_release;
70
71 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
72 we allocate a bigger stack. Need a better solution, for example
73 by remapping the process stack directly at the right place */
74 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
75
76 void gemu_log(const char *fmt, ...)
77 {
78 va_list ap;
79
80 va_start(ap, fmt);
81 vfprintf(stderr, fmt, ap);
82 va_end(ap);
83 }
84
85 #if defined(TARGET_I386)
86 int cpu_get_pic_interrupt(CPUX86State *env)
87 {
88 return -1;
89 }
90 #endif
91
92 /***********************************************************/
93 /* Helper routines for implementing atomic operations. */
94
95 /* To implement exclusive operations we force all cpus to syncronise.
96 We don't require a full sync, only that no cpus are executing guest code.
97 The alternative is to map target atomic ops onto host equivalents,
98 which requires quite a lot of per host/target work. */
99 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
100 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
101 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
102 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
103 static int pending_cpus;
104
105 /* Make sure everything is in a consistent state for calling fork(). */
106 void fork_start(void)
107 {
108 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
109 pthread_mutex_lock(&exclusive_lock);
110 mmap_fork_start();
111 }
112
113 void fork_end(int child)
114 {
115 mmap_fork_end(child);
116 if (child) {
117 CPUState *cpu, *next_cpu;
118 /* Child processes created by fork() only have a single thread.
119 Discard information about the parent threads. */
120 CPU_FOREACH_SAFE(cpu, next_cpu) {
121 if (cpu != thread_cpu) {
122 QTAILQ_REMOVE(&cpus, thread_cpu, node);
123 }
124 }
125 pending_cpus = 0;
126 pthread_mutex_init(&exclusive_lock, NULL);
127 pthread_mutex_init(&cpu_list_mutex, NULL);
128 pthread_cond_init(&exclusive_cond, NULL);
129 pthread_cond_init(&exclusive_resume, NULL);
130 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
131 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
132 } else {
133 pthread_mutex_unlock(&exclusive_lock);
134 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
135 }
136 }
137
138 /* Wait for pending exclusive operations to complete. The exclusive lock
139 must be held. */
140 static inline void exclusive_idle(void)
141 {
142 while (pending_cpus) {
143 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
144 }
145 }
146
147 /* Start an exclusive operation.
148 Must only be called from outside cpu_arm_exec. */
149 static inline void start_exclusive(void)
150 {
151 CPUState *other_cpu;
152
153 pthread_mutex_lock(&exclusive_lock);
154 exclusive_idle();
155
156 pending_cpus = 1;
157 /* Make all other cpus stop executing. */
158 CPU_FOREACH(other_cpu) {
159 if (other_cpu->running) {
160 pending_cpus++;
161 cpu_exit(other_cpu);
162 }
163 }
164 if (pending_cpus > 1) {
165 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
166 }
167 }
168
169 /* Finish an exclusive operation. */
170 static inline void end_exclusive(void)
171 {
172 pending_cpus = 0;
173 pthread_cond_broadcast(&exclusive_resume);
174 pthread_mutex_unlock(&exclusive_lock);
175 }
176
177 /* Wait for exclusive ops to finish, and begin cpu execution. */
178 static inline void cpu_exec_start(CPUState *cpu)
179 {
180 pthread_mutex_lock(&exclusive_lock);
181 exclusive_idle();
182 cpu->running = true;
183 pthread_mutex_unlock(&exclusive_lock);
184 }
185
186 /* Mark cpu as not executing, and release pending exclusive ops. */
187 static inline void cpu_exec_end(CPUState *cpu)
188 {
189 pthread_mutex_lock(&exclusive_lock);
190 cpu->running = false;
191 if (pending_cpus > 1) {
192 pending_cpus--;
193 if (pending_cpus == 1) {
194 pthread_cond_signal(&exclusive_cond);
195 }
196 }
197 exclusive_idle();
198 pthread_mutex_unlock(&exclusive_lock);
199 }
200
201 void cpu_list_lock(void)
202 {
203 pthread_mutex_lock(&cpu_list_mutex);
204 }
205
206 void cpu_list_unlock(void)
207 {
208 pthread_mutex_unlock(&cpu_list_mutex);
209 }
210
211
212 #ifdef TARGET_I386
213 /***********************************************************/
214 /* CPUX86 core interface */
215
216 void cpu_smm_update(CPUX86State *env)
217 {
218 }
219
220 uint64_t cpu_get_tsc(CPUX86State *env)
221 {
222 return cpu_get_real_ticks();
223 }
224
225 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
226 int flags)
227 {
228 unsigned int e1, e2;
229 uint32_t *p;
230 e1 = (addr << 16) | (limit & 0xffff);
231 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
232 e2 |= flags;
233 p = ptr;
234 p[0] = tswap32(e1);
235 p[1] = tswap32(e2);
236 }
237
238 static uint64_t *idt_table;
239 #ifdef TARGET_X86_64
240 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
241 uint64_t addr, unsigned int sel)
242 {
243 uint32_t *p, e1, e2;
244 e1 = (addr & 0xffff) | (sel << 16);
245 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
246 p = ptr;
247 p[0] = tswap32(e1);
248 p[1] = tswap32(e2);
249 p[2] = tswap32(addr >> 32);
250 p[3] = 0;
251 }
252 /* only dpl matters as we do only user space emulation */
253 static void set_idt(int n, unsigned int dpl)
254 {
255 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
256 }
257 #else
258 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
259 uint32_t addr, unsigned int sel)
260 {
261 uint32_t *p, e1, e2;
262 e1 = (addr & 0xffff) | (sel << 16);
263 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
264 p = ptr;
265 p[0] = tswap32(e1);
266 p[1] = tswap32(e2);
267 }
268
269 /* only dpl matters as we do only user space emulation */
270 static void set_idt(int n, unsigned int dpl)
271 {
272 set_gate(idt_table + n, 0, dpl, 0, 0);
273 }
274 #endif
275
276 void cpu_loop(CPUX86State *env)
277 {
278 CPUState *cs = CPU(x86_env_get_cpu(env));
279 int trapnr;
280 abi_ulong pc;
281 target_siginfo_t info;
282 #ifdef TARGET_X86_64
283 int syscall_num;
284 #endif
285
286 for(;;) {
287 trapnr = cpu_x86_exec(env);
288 switch(trapnr) {
289 case 0x80:
290 /* linux syscall from int $0x80 */
291 env->regs[R_EAX] = do_syscall(env,
292 env->regs[R_EAX],
293 env->regs[R_EBX],
294 env->regs[R_ECX],
295 env->regs[R_EDX],
296 env->regs[R_ESI],
297 env->regs[R_EDI],
298 env->regs[R_EBP],
299 0, 0);
300 break;
301 #ifndef TARGET_ABI32
302 case EXCP_SYSCALL:
303 /* linux syscall from syscall instruction */
304 env->regs[R_EAX] = do_syscall(env,
305 env->regs[R_EAX],
306 env->regs[R_EDI],
307 env->regs[R_ESI],
308 env->regs[R_EDX],
309 env->regs[10],
310 env->regs[8],
311 env->regs[9],
312 0, 0);
313 break;
314 #endif
315 #ifdef TARGET_X86_64
316 case EXCP_VSYSCALL:
317 switch (env->eip) {
318 case TARGET_VSYSCALL_ADDR(__NR_vgettimeofday):
319 syscall_num = __NR_gettimeofday;
320 break;
321 case TARGET_VSYSCALL_ADDR(__NR_vtime):
322 #ifdef __NR_time
323 syscall_num = __NR_time;
324 #else
325 /* XXX: not yet implemented (arm eabi host) */
326 cpu_abort(cs, "Unimplemented vsyscall vtime");
327 #endif
328 break;
329 case TARGET_VSYSCALL_ADDR(__NR_vgetcpu):
330 /* XXX: not yet implemented */
331 cpu_abort(cs, "Unimplemented vsyscall vgetcpu");
332 break;
333 default:
334 cpu_abort(cs,
335 "Invalid vsyscall to address " TARGET_FMT_lx "\n",
336 env->eip);
337 }
338 env->regs[R_EAX] = do_syscall(env,
339 syscall_num,
340 env->regs[R_EDI],
341 env->regs[R_ESI],
342 env->regs[R_EDX],
343 env->regs[10],
344 env->regs[8],
345 env->regs[9],
346 0, 0);
347 /* simulate a ret */
348 env->eip = ldq(env->regs[R_ESP]);
349 env->regs[R_ESP] += 8;
350 break;
351 #endif
352 case EXCP0B_NOSEG:
353 case EXCP0C_STACK:
354 info.si_signo = SIGBUS;
355 info.si_errno = 0;
356 info.si_code = TARGET_SI_KERNEL;
357 info._sifields._sigfault._addr = 0;
358 queue_signal(env, info.si_signo, &info);
359 break;
360 case EXCP0D_GPF:
361 /* XXX: potential problem if ABI32 */
362 #ifndef TARGET_X86_64
363 if (env->eflags & VM_MASK) {
364 handle_vm86_fault(env);
365 } else
366 #endif
367 {
368 info.si_signo = SIGSEGV;
369 info.si_errno = 0;
370 info.si_code = TARGET_SI_KERNEL;
371 info._sifields._sigfault._addr = 0;
372 queue_signal(env, info.si_signo, &info);
373 }
374 break;
375 case EXCP0E_PAGE:
376 info.si_signo = SIGSEGV;
377 info.si_errno = 0;
378 if (!(env->error_code & 1))
379 info.si_code = TARGET_SEGV_MAPERR;
380 else
381 info.si_code = TARGET_SEGV_ACCERR;
382 info._sifields._sigfault._addr = env->cr[2];
383 queue_signal(env, info.si_signo, &info);
384 break;
385 case EXCP00_DIVZ:
386 #ifndef TARGET_X86_64
387 if (env->eflags & VM_MASK) {
388 handle_vm86_trap(env, trapnr);
389 } else
390 #endif
391 {
392 /* division by zero */
393 info.si_signo = SIGFPE;
394 info.si_errno = 0;
395 info.si_code = TARGET_FPE_INTDIV;
396 info._sifields._sigfault._addr = env->eip;
397 queue_signal(env, info.si_signo, &info);
398 }
399 break;
400 case EXCP01_DB:
401 case EXCP03_INT3:
402 #ifndef TARGET_X86_64
403 if (env->eflags & VM_MASK) {
404 handle_vm86_trap(env, trapnr);
405 } else
406 #endif
407 {
408 info.si_signo = SIGTRAP;
409 info.si_errno = 0;
410 if (trapnr == EXCP01_DB) {
411 info.si_code = TARGET_TRAP_BRKPT;
412 info._sifields._sigfault._addr = env->eip;
413 } else {
414 info.si_code = TARGET_SI_KERNEL;
415 info._sifields._sigfault._addr = 0;
416 }
417 queue_signal(env, info.si_signo, &info);
418 }
419 break;
420 case EXCP04_INTO:
421 case EXCP05_BOUND:
422 #ifndef TARGET_X86_64
423 if (env->eflags & VM_MASK) {
424 handle_vm86_trap(env, trapnr);
425 } else
426 #endif
427 {
428 info.si_signo = SIGSEGV;
429 info.si_errno = 0;
430 info.si_code = TARGET_SI_KERNEL;
431 info._sifields._sigfault._addr = 0;
432 queue_signal(env, info.si_signo, &info);
433 }
434 break;
435 case EXCP06_ILLOP:
436 info.si_signo = SIGILL;
437 info.si_errno = 0;
438 info.si_code = TARGET_ILL_ILLOPN;
439 info._sifields._sigfault._addr = env->eip;
440 queue_signal(env, info.si_signo, &info);
441 break;
442 case EXCP_INTERRUPT:
443 /* just indicate that signals should be handled asap */
444 break;
445 case EXCP_DEBUG:
446 {
447 int sig;
448
449 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
450 if (sig)
451 {
452 info.si_signo = sig;
453 info.si_errno = 0;
454 info.si_code = TARGET_TRAP_BRKPT;
455 queue_signal(env, info.si_signo, &info);
456 }
457 }
458 break;
459 default:
460 pc = env->segs[R_CS].base + env->eip;
461 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
462 (long)pc, trapnr);
463 abort();
464 }
465 process_pending_signals(env);
466 }
467 }
468 #endif
469
470 #ifdef TARGET_ARM
471
472 #define get_user_code_u32(x, gaddr, env) \
473 ({ abi_long __r = get_user_u32((x), (gaddr)); \
474 if (!__r && bswap_code(arm_sctlr_b(env))) { \
475 (x) = bswap32(x); \
476 } \
477 __r; \
478 })
479
480 #define get_user_code_u16(x, gaddr, env) \
481 ({ abi_long __r = get_user_u16((x), (gaddr)); \
482 if (!__r && bswap_code(arm_sctlr_b(env))) { \
483 (x) = bswap16(x); \
484 } \
485 __r; \
486 })
487
488 #define get_user_data_u32(x, gaddr, env) \
489 ({ abi_long __r = get_user_u32((x), (gaddr)); \
490 if (!__r && arm_cpu_bswap_data(env)) { \
491 (x) = bswap32(x); \
492 } \
493 __r; \
494 })
495
496 #define get_user_data_u16(x, gaddr, env) \
497 ({ abi_long __r = get_user_u16((x), (gaddr)); \
498 if (!__r && arm_cpu_bswap_data(env)) { \
499 (x) = bswap16(x); \
500 } \
501 __r; \
502 })
503
504 #define put_user_data_u32(x, gaddr, env) \
505 ({ typeof(x) __x = (x); \
506 if (arm_cpu_bswap_data(env)) { \
507 __x = bswap32(__x); \
508 } \
509 put_user_u32(__x, (gaddr)); \
510 })
511
512 #define put_user_data_u16(x, gaddr, env) \
513 ({ typeof(x) __x = (x); \
514 if (arm_cpu_bswap_data(env)) { \
515 __x = bswap16(__x); \
516 } \
517 put_user_u16(__x, (gaddr)); \
518 })
519
520 #ifdef TARGET_ABI32
521 /* Commpage handling -- there is no commpage for AArch64 */
522
523 /*
524 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
525 * Input:
526 * r0 = pointer to oldval
527 * r1 = pointer to newval
528 * r2 = pointer to target value
529 *
530 * Output:
531 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
532 * C set if *ptr was changed, clear if no exchange happened
533 *
534 * Note segv's in kernel helpers are a bit tricky, we can set the
535 * data address sensibly but the PC address is just the entry point.
536 */
537 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
538 {
539 uint64_t oldval, newval, val;
540 uint32_t addr, cpsr;
541 target_siginfo_t info;
542
543 /* Based on the 32 bit code in do_kernel_trap */
544
545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552
553 if (get_user_u64(oldval, env->regs[0])) {
554 env->exception.vaddress = env->regs[0];
555 goto segv;
556 };
557
558 if (get_user_u64(newval, env->regs[1])) {
559 env->exception.vaddress = env->regs[1];
560 goto segv;
561 };
562
563 if (get_user_u64(val, addr)) {
564 env->exception.vaddress = addr;
565 goto segv;
566 }
567
568 if (val == oldval) {
569 val = newval;
570
571 if (put_user_u64(val, addr)) {
572 env->exception.vaddress = addr;
573 goto segv;
574 };
575
576 env->regs[0] = 0;
577 cpsr |= CPSR_C;
578 } else {
579 env->regs[0] = -1;
580 cpsr &= ~CPSR_C;
581 }
582 cpsr_write(env, cpsr, CPSR_C);
583 end_exclusive();
584 return;
585
586 segv:
587 end_exclusive();
588 /* We get the PC of the entry address - which is as good as anything,
589 on a real kernel what you get depends on which mode it uses. */
590 info.si_signo = SIGSEGV;
591 info.si_errno = 0;
592 /* XXX: check env->error_code */
593 info.si_code = TARGET_SEGV_MAPERR;
594 info._sifields._sigfault._addr = env->exception.vaddress;
595 queue_signal(env, info.si_signo, &info);
596
597 end_exclusive();
598 }
599
600 /* Handle a jump to the kernel code page. */
601 static int
602 do_kernel_trap(CPUARMState *env)
603 {
604 uint32_t addr;
605 uint32_t cpsr;
606 uint32_t val;
607
608 switch (env->regs[15]) {
609 case 0xffff0fa0: /* __kernel_memory_barrier */
610 /* ??? No-op. Will need to do better for SMP. */
611 break;
612 case 0xffff0fc0: /* __kernel_cmpxchg */
613 /* XXX: This only works between threads, not between processes.
614 It's probably possible to implement this with native host
615 operations. However things like ldrex/strex are much harder so
616 there's not much point trying. */
617 start_exclusive();
618 cpsr = cpsr_read(env);
619 addr = env->regs[2];
620 /* FIXME: This should SEGV if the access fails. */
621 if (get_user_u32(val, addr))
622 val = ~env->regs[0];
623 if (val == env->regs[0]) {
624 val = env->regs[1];
625 /* FIXME: Check for segfaults. */
626 put_user_u32(val, addr);
627 env->regs[0] = 0;
628 cpsr |= CPSR_C;
629 } else {
630 env->regs[0] = -1;
631 cpsr &= ~CPSR_C;
632 }
633 cpsr_write(env, cpsr, CPSR_C);
634 end_exclusive();
635 break;
636 case 0xffff0fe0: /* __kernel_get_tls */
637 env->regs[0] = env->cp15.tpidrro_el0;
638 break;
639 case 0xffff0f60: /* __kernel_cmpxchg64 */
640 arm_kernel_cmpxchg64_helper(env);
641 break;
642
643 default:
644 return 1;
645 }
646 /* Jump back to the caller. */
647 addr = env->regs[14];
648 if (addr & 1) {
649 env->thumb = 1;
650 addr &= ~1;
651 }
652 env->regs[15] = addr;
653
654 return 0;
655 }
656
657 /* Store exclusive handling for AArch32 */
658 static int do_strex(CPUARMState *env)
659 {
660 uint64_t val;
661 int size;
662 int rc = 1;
663 int segv = 0;
664 uint32_t addr;
665 start_exclusive();
666 if (env->exclusive_addr != env->exclusive_test) {
667 goto fail;
668 }
669 /* We know we're always AArch32 so the address is in uint32_t range
670 * unless it was the -1 exclusive-monitor-lost value (which won't
671 * match exclusive_test above).
672 */
673 assert(extract64(env->exclusive_addr, 32, 32) == 0);
674 addr = env->exclusive_addr;
675 size = env->exclusive_info & 0xf;
676 switch (size) {
677 case 0:
678 segv = get_user_u8(val, addr);
679 break;
680 case 1:
681 segv = get_user_data_u16(val, addr, env);
682 break;
683 case 2:
684 case 3:
685 segv = get_user_data_u32(val, addr, env);
686 break;
687 default:
688 abort();
689 }
690 if (segv) {
691 env->exception.vaddress = addr;
692 goto done;
693 }
694 if (size == 3) {
695 uint32_t valhi;
696 segv = get_user_data_u32(valhi, addr + 4, env);
697 if (segv) {
698 env->exception.vaddress = addr + 4;
699 goto done;
700 }
701 if (arm_cpu_bswap_data(env)) {
702 val = deposit64((uint64_t)valhi, 32, 32, val);
703 } else {
704 val = deposit64(val, 32, 32, valhi);
705 }
706 }
707 if (val != env->exclusive_val) {
708 goto fail;
709 }
710
711 val = env->regs[(env->exclusive_info >> 8) & 0xf];
712 switch (size) {
713 case 0:
714 segv = put_user_u8(val, addr);
715 break;
716 case 1:
717 segv = put_user_data_u16(val, addr, env);
718 break;
719 case 2:
720 case 3:
721 segv = put_user_data_u32(val, addr, env);
722 break;
723 }
724 if (segv) {
725 env->exception.vaddress = addr;
726 goto done;
727 }
728 if (size == 3) {
729 val = env->regs[(env->exclusive_info >> 12) & 0xf];
730 segv = put_user_data_u32(val, addr + 4, env);
731 if (segv) {
732 env->exception.vaddress = addr + 4;
733 goto done;
734 }
735 }
736 rc = 0;
737 fail:
738 env->regs[15] += 4;
739 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
740 done:
741 end_exclusive();
742 return segv;
743 }
744
745 void cpu_loop(CPUARMState *env)
746 {
747 CPUState *cs = CPU(arm_env_get_cpu(env));
748 int trapnr;
749 unsigned int n, insn;
750 target_siginfo_t info;
751 uint32_t addr;
752
753 for(;;) {
754 cpu_exec_start(cs);
755 trapnr = cpu_arm_exec(env);
756 cpu_exec_end(cs);
757 switch(trapnr) {
758 case EXCP_UDEF:
759 {
760 TaskState *ts = cs->opaque;
761 uint32_t opcode;
762 int rc;
763
764 /* we handle the FPU emulation here, as Linux */
765 /* we get the opcode */
766 /* FIXME - what to do if get_user() fails? */
767 get_user_code_u32(opcode, env->regs[15], env);
768
769 rc = EmulateAll(opcode, &ts->fpa, env);
770 if (rc == 0) { /* illegal instruction */
771 info.si_signo = SIGILL;
772 info.si_errno = 0;
773 info.si_code = TARGET_ILL_ILLOPN;
774 info._sifields._sigfault._addr = env->regs[15];
775 queue_signal(env, info.si_signo, &info);
776 } else if (rc < 0) { /* FP exception */
777 int arm_fpe=0;
778
779 /* translate softfloat flags to FPSR flags */
780 if (-rc & float_flag_invalid)
781 arm_fpe |= BIT_IOC;
782 if (-rc & float_flag_divbyzero)
783 arm_fpe |= BIT_DZC;
784 if (-rc & float_flag_overflow)
785 arm_fpe |= BIT_OFC;
786 if (-rc & float_flag_underflow)
787 arm_fpe |= BIT_UFC;
788 if (-rc & float_flag_inexact)
789 arm_fpe |= BIT_IXC;
790
791 FPSR fpsr = ts->fpa.fpsr;
792 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
793
794 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
795 info.si_signo = SIGFPE;
796 info.si_errno = 0;
797
798 /* ordered by priority, least first */
799 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
800 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
801 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
802 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
803 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
804
805 info._sifields._sigfault._addr = env->regs[15];
806 queue_signal(env, info.si_signo, &info);
807 } else {
808 env->regs[15] += 4;
809 }
810
811 /* accumulate unenabled exceptions */
812 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
813 fpsr |= BIT_IXC;
814 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
815 fpsr |= BIT_UFC;
816 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
817 fpsr |= BIT_OFC;
818 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
819 fpsr |= BIT_DZC;
820 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
821 fpsr |= BIT_IOC;
822 ts->fpa.fpsr=fpsr;
823 } else { /* everything OK */
824 /* increment PC */
825 env->regs[15] += 4;
826 }
827 }
828 break;
829 case EXCP_SWI:
830 case EXCP_BKPT:
831 {
832 env->eabi = 1;
833 /* system call */
834 if (trapnr == EXCP_BKPT) {
835 if (env->thumb) {
836 /* FIXME - what to do if get_user() fails? */
837 get_user_code_u16(insn, env->regs[15], env);
838 n = insn & 0xff;
839 env->regs[15] += 2;
840 } else {
841 /* FIXME - what to do if get_user() fails? */
842 get_user_code_u32(insn, env->regs[15], env);
843 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
844 env->regs[15] += 4;
845 }
846 } else {
847 if (env->thumb) {
848 /* FIXME - what to do if get_user() fails? */
849 get_user_code_u16(insn, env->regs[15] - 2, env);
850 n = insn & 0xff;
851 } else {
852 /* FIXME - what to do if get_user() fails? */
853 get_user_code_u32(insn, env->regs[15] - 4, env);
854 n = insn & 0xffffff;
855 }
856 }
857
858 if (n == ARM_NR_cacheflush) {
859 /* nop */
860 } else if (n == ARM_NR_semihosting
861 || n == ARM_NR_thumb_semihosting) {
862 env->regs[0] = do_arm_semihosting (env);
863 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
864 /* linux syscall */
865 if (env->thumb || n == 0) {
866 n = env->regs[7];
867 } else {
868 n -= ARM_SYSCALL_BASE;
869 env->eabi = 0;
870 }
871 if ( n > ARM_NR_BASE) {
872 switch (n) {
873 case ARM_NR_cacheflush:
874 /* nop */
875 break;
876 case ARM_NR_set_tls:
877 cpu_set_tls(env, env->regs[0]);
878 env->regs[0] = 0;
879 break;
880 case ARM_NR_breakpoint:
881 env->regs[15] -= env->thumb ? 2 : 4;
882 goto excp_debug;
883 default:
884 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
885 n);
886 env->regs[0] = -TARGET_ENOSYS;
887 break;
888 }
889 } else {
890 env->regs[0] = do_syscall(env,
891 n,
892 env->regs[0],
893 env->regs[1],
894 env->regs[2],
895 env->regs[3],
896 env->regs[4],
897 env->regs[5],
898 0, 0);
899 }
900 } else {
901 goto error;
902 }
903 }
904 break;
905 case EXCP_INTERRUPT:
906 /* just indicate that signals should be handled asap */
907 break;
908 case EXCP_STREX:
909 if (!do_strex(env)) {
910 break;
911 }
912 /* fall through for segv */
913 case EXCP_PREFETCH_ABORT:
914 case EXCP_DATA_ABORT:
915 addr = env->exception.vaddress;
916 {
917 info.si_signo = SIGSEGV;
918 info.si_errno = 0;
919 /* XXX: check env->error_code */
920 info.si_code = TARGET_SEGV_MAPERR;
921 info._sifields._sigfault._addr = addr;
922 queue_signal(env, info.si_signo, &info);
923 }
924 break;
925 case EXCP_DEBUG:
926 excp_debug:
927 {
928 int sig;
929
930 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
931 if (sig)
932 {
933 info.si_signo = sig;
934 info.si_errno = 0;
935 info.si_code = TARGET_TRAP_BRKPT;
936 queue_signal(env, info.si_signo, &info);
937 }
938 }
939 break;
940 case EXCP_KERNEL_TRAP:
941 if (do_kernel_trap(env))
942 goto error;
943 break;
944 default:
945 error:
946 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
947 trapnr);
948 cpu_dump_state(cs, stderr, fprintf, 0);
949 abort();
950 }
951 process_pending_signals(env);
952 }
953 }
954
955 #else
956
957 /*
958 * Handle AArch64 store-release exclusive
959 *
960 * rs = gets the status result of store exclusive
961 * rt = is the register that is stored
962 * rt2 = is the second register store (in STP)
963 *
964 */
965 static int do_strex_a64(CPUARMState *env)
966 {
967 uint64_t val;
968 int size;
969 bool is_pair;
970 int rc = 1;
971 int segv = 0;
972 uint64_t addr;
973 int rs, rt, rt2;
974
975 start_exclusive();
976 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
977 size = extract32(env->exclusive_info, 0, 2);
978 is_pair = extract32(env->exclusive_info, 2, 1);
979 rs = extract32(env->exclusive_info, 4, 5);
980 rt = extract32(env->exclusive_info, 9, 5);
981 rt2 = extract32(env->exclusive_info, 14, 5);
982
983 addr = env->exclusive_addr;
984
985 if (addr != env->exclusive_test) {
986 goto finish;
987 }
988
989 switch (size) {
990 case 0:
991 segv = get_user_u8(val, addr);
992 break;
993 case 1:
994 segv = get_user_u16(val, addr);
995 break;
996 case 2:
997 segv = get_user_u32(val, addr);
998 break;
999 case 3:
1000 segv = get_user_u64(val, addr);
1001 break;
1002 default:
1003 abort();
1004 }
1005 if (segv) {
1006 env->exception.vaddress = addr;
1007 goto error;
1008 }
1009 if (val != env->exclusive_val) {
1010 goto finish;
1011 }
1012 if (is_pair) {
1013 if (size == 2) {
1014 segv = get_user_u32(val, addr + 4);
1015 } else {
1016 segv = get_user_u64(val, addr + 8);
1017 }
1018 if (segv) {
1019 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1020 goto error;
1021 }
1022 if (val != env->exclusive_high) {
1023 goto finish;
1024 }
1025 }
1026 /* handle the zero register */
1027 val = rt == 31 ? 0 : env->xregs[rt];
1028 switch (size) {
1029 case 0:
1030 segv = put_user_u8(val, addr);
1031 break;
1032 case 1:
1033 segv = put_user_u16(val, addr);
1034 break;
1035 case 2:
1036 segv = put_user_u32(val, addr);
1037 break;
1038 case 3:
1039 segv = put_user_u64(val, addr);
1040 break;
1041 }
1042 if (segv) {
1043 goto error;
1044 }
1045 if (is_pair) {
1046 /* handle the zero register */
1047 val = rt2 == 31 ? 0 : env->xregs[rt2];
1048 if (size == 2) {
1049 segv = put_user_u32(val, addr + 4);
1050 } else {
1051 segv = put_user_u64(val, addr + 8);
1052 }
1053 if (segv) {
1054 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1055 goto error;
1056 }
1057 }
1058 rc = 0;
1059 finish:
1060 env->pc += 4;
1061 /* rs == 31 encodes a write to the ZR, thus throwing away
1062 * the status return. This is rather silly but valid.
1063 */
1064 if (rs < 31) {
1065 env->xregs[rs] = rc;
1066 }
1067 error:
1068 /* instruction faulted, PC does not advance */
1069 /* either way a strex releases any exclusive lock we have */
1070 env->exclusive_addr = -1;
1071 end_exclusive();
1072 return segv;
1073 }
1074
1075 /* AArch64 main loop */
1076 void cpu_loop(CPUARMState *env)
1077 {
1078 CPUState *cs = CPU(arm_env_get_cpu(env));
1079 int trapnr, sig;
1080 target_siginfo_t info;
1081
1082 for (;;) {
1083 cpu_exec_start(cs);
1084 trapnr = cpu_arm_exec(env);
1085 cpu_exec_end(cs);
1086
1087 switch (trapnr) {
1088 case EXCP_SWI:
1089 env->xregs[0] = do_syscall(env,
1090 env->xregs[8],
1091 env->xregs[0],
1092 env->xregs[1],
1093 env->xregs[2],
1094 env->xregs[3],
1095 env->xregs[4],
1096 env->xregs[5],
1097 0, 0);
1098 break;
1099 case EXCP_INTERRUPT:
1100 /* just indicate that signals should be handled asap */
1101 break;
1102 case EXCP_UDEF:
1103 info.si_signo = SIGILL;
1104 info.si_errno = 0;
1105 info.si_code = TARGET_ILL_ILLOPN;
1106 info._sifields._sigfault._addr = env->pc;
1107 queue_signal(env, info.si_signo, &info);
1108 break;
1109 case EXCP_STREX:
1110 if (!do_strex_a64(env)) {
1111 break;
1112 }
1113 /* fall through for segv */
1114 case EXCP_PREFETCH_ABORT:
1115 case EXCP_DATA_ABORT:
1116 info.si_signo = SIGSEGV;
1117 info.si_errno = 0;
1118 /* XXX: check env->error_code */
1119 info.si_code = TARGET_SEGV_MAPERR;
1120 info._sifields._sigfault._addr = env->exception.vaddress;
1121 queue_signal(env, info.si_signo, &info);
1122 break;
1123 case EXCP_DEBUG:
1124 case EXCP_BKPT:
1125 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1126 if (sig) {
1127 info.si_signo = sig;
1128 info.si_errno = 0;
1129 info.si_code = TARGET_TRAP_BRKPT;
1130 queue_signal(env, info.si_signo, &info);
1131 }
1132 break;
1133 default:
1134 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1135 trapnr);
1136 cpu_dump_state(cs, stderr, fprintf, 0);
1137 abort();
1138 }
1139 process_pending_signals(env);
1140 /* Exception return on AArch64 always clears the exclusive monitor,
1141 * so any return to running guest code implies this.
1142 * A strex (successful or otherwise) also clears the monitor, so
1143 * we don't need to specialcase EXCP_STREX.
1144 */
1145 env->exclusive_addr = -1;
1146 }
1147 }
1148 #endif /* ndef TARGET_ABI32 */
1149
1150 #endif
1151
1152 #ifdef TARGET_UNICORE32
1153
1154 void cpu_loop(CPUUniCore32State *env)
1155 {
1156 CPUState *cs = CPU(uc32_env_get_cpu(env));
1157 int trapnr;
1158 unsigned int n, insn;
1159 target_siginfo_t info;
1160
1161 for (;;) {
1162 cpu_exec_start(cs);
1163 trapnr = uc32_cpu_exec(env);
1164 cpu_exec_end(cs);
1165 switch (trapnr) {
1166 case UC32_EXCP_PRIV:
1167 {
1168 /* system call */
1169 get_user_u32(insn, env->regs[31] - 4);
1170 n = insn & 0xffffff;
1171
1172 if (n >= UC32_SYSCALL_BASE) {
1173 /* linux syscall */
1174 n -= UC32_SYSCALL_BASE;
1175 if (n == UC32_SYSCALL_NR_set_tls) {
1176 cpu_set_tls(env, env->regs[0]);
1177 env->regs[0] = 0;
1178 } else {
1179 env->regs[0] = do_syscall(env,
1180 n,
1181 env->regs[0],
1182 env->regs[1],
1183 env->regs[2],
1184 env->regs[3],
1185 env->regs[4],
1186 env->regs[5],
1187 0, 0);
1188 }
1189 } else {
1190 goto error;
1191 }
1192 }
1193 break;
1194 case UC32_EXCP_DTRAP:
1195 case UC32_EXCP_ITRAP:
1196 info.si_signo = SIGSEGV;
1197 info.si_errno = 0;
1198 /* XXX: check env->error_code */
1199 info.si_code = TARGET_SEGV_MAPERR;
1200 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1201 queue_signal(env, info.si_signo, &info);
1202 break;
1203 case EXCP_INTERRUPT:
1204 /* just indicate that signals should be handled asap */
1205 break;
1206 case EXCP_DEBUG:
1207 {
1208 int sig;
1209
1210 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1211 if (sig) {
1212 info.si_signo = sig;
1213 info.si_errno = 0;
1214 info.si_code = TARGET_TRAP_BRKPT;
1215 queue_signal(env, info.si_signo, &info);
1216 }
1217 }
1218 break;
1219 default:
1220 goto error;
1221 }
1222 process_pending_signals(env);
1223 }
1224
1225 error:
1226 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1227 cpu_dump_state(cs, stderr, fprintf, 0);
1228 abort();
1229 }
1230 #endif
1231
1232 #ifdef TARGET_SPARC
1233 #define SPARC64_STACK_BIAS 2047
1234
1235 //#define DEBUG_WIN
1236
1237 /* WARNING: dealing with register windows _is_ complicated. More info
1238 can be found at http://www.sics.se/~psm/sparcstack.html */
1239 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1240 {
1241 index = (index + cwp * 16) % (16 * env->nwindows);
1242 /* wrap handling : if cwp is on the last window, then we use the
1243 registers 'after' the end */
1244 if (index < 8 && env->cwp == env->nwindows - 1)
1245 index += 16 * env->nwindows;
1246 return index;
1247 }
1248
1249 /* save the register window 'cwp1' */
1250 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1251 {
1252 unsigned int i;
1253 abi_ulong sp_ptr;
1254
1255 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1256 #ifdef TARGET_SPARC64
1257 if (sp_ptr & 3)
1258 sp_ptr += SPARC64_STACK_BIAS;
1259 #endif
1260 #if defined(DEBUG_WIN)
1261 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1262 sp_ptr, cwp1);
1263 #endif
1264 for(i = 0; i < 16; i++) {
1265 /* FIXME - what to do if put_user() fails? */
1266 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1267 sp_ptr += sizeof(abi_ulong);
1268 }
1269 }
1270
1271 static void save_window(CPUSPARCState *env)
1272 {
1273 #ifndef TARGET_SPARC64
1274 unsigned int new_wim;
1275 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1276 ((1LL << env->nwindows) - 1);
1277 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1278 env->wim = new_wim;
1279 #else
1280 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1281 env->cansave++;
1282 env->canrestore--;
1283 #endif
1284 }
1285
1286 static void restore_window(CPUSPARCState *env)
1287 {
1288 #ifndef TARGET_SPARC64
1289 unsigned int new_wim;
1290 #endif
1291 unsigned int i, cwp1;
1292 abi_ulong sp_ptr;
1293
1294 #ifndef TARGET_SPARC64
1295 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1296 ((1LL << env->nwindows) - 1);
1297 #endif
1298
1299 /* restore the invalid window */
1300 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1301 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1302 #ifdef TARGET_SPARC64
1303 if (sp_ptr & 3)
1304 sp_ptr += SPARC64_STACK_BIAS;
1305 #endif
1306 #if defined(DEBUG_WIN)
1307 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1308 sp_ptr, cwp1);
1309 #endif
1310 for(i = 0; i < 16; i++) {
1311 /* FIXME - what to do if get_user() fails? */
1312 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1313 sp_ptr += sizeof(abi_ulong);
1314 }
1315 #ifdef TARGET_SPARC64
1316 env->canrestore++;
1317 if (env->cleanwin < env->nwindows - 1)
1318 env->cleanwin++;
1319 env->cansave--;
1320 #else
1321 env->wim = new_wim;
1322 #endif
1323 }
1324
1325 static void flush_windows(CPUSPARCState *env)
1326 {
1327 int offset, cwp1;
1328
1329 offset = 1;
1330 for(;;) {
1331 /* if restore would invoke restore_window(), then we can stop */
1332 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1333 #ifndef TARGET_SPARC64
1334 if (env->wim & (1 << cwp1))
1335 break;
1336 #else
1337 if (env->canrestore == 0)
1338 break;
1339 env->cansave++;
1340 env->canrestore--;
1341 #endif
1342 save_window_offset(env, cwp1);
1343 offset++;
1344 }
1345 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1346 #ifndef TARGET_SPARC64
1347 /* set wim so that restore will reload the registers */
1348 env->wim = 1 << cwp1;
1349 #endif
1350 #if defined(DEBUG_WIN)
1351 printf("flush_windows: nb=%d\n", offset - 1);
1352 #endif
1353 }
1354
1355 void cpu_loop (CPUSPARCState *env)
1356 {
1357 CPUState *cs = CPU(sparc_env_get_cpu(env));
1358 int trapnr;
1359 abi_long ret;
1360 target_siginfo_t info;
1361
1362 while (1) {
1363 trapnr = cpu_sparc_exec (env);
1364
1365 /* Compute PSR before exposing state. */
1366 if (env->cc_op != CC_OP_FLAGS) {
1367 cpu_get_psr(env);
1368 }
1369
1370 switch (trapnr) {
1371 #ifndef TARGET_SPARC64
1372 case 0x88:
1373 case 0x90:
1374 #else
1375 case 0x110:
1376 case 0x16d:
1377 #endif
1378 ret = do_syscall (env, env->gregs[1],
1379 env->regwptr[0], env->regwptr[1],
1380 env->regwptr[2], env->regwptr[3],
1381 env->regwptr[4], env->regwptr[5],
1382 0, 0);
1383 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1384 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1385 env->xcc |= PSR_CARRY;
1386 #else
1387 env->psr |= PSR_CARRY;
1388 #endif
1389 ret = -ret;
1390 } else {
1391 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1392 env->xcc &= ~PSR_CARRY;
1393 #else
1394 env->psr &= ~PSR_CARRY;
1395 #endif
1396 }
1397 env->regwptr[0] = ret;
1398 /* next instruction */
1399 env->pc = env->npc;
1400 env->npc = env->npc + 4;
1401 break;
1402 case 0x83: /* flush windows */
1403 #ifdef TARGET_ABI32
1404 case 0x103:
1405 #endif
1406 flush_windows(env);
1407 /* next instruction */
1408 env->pc = env->npc;
1409 env->npc = env->npc + 4;
1410 break;
1411 #ifndef TARGET_SPARC64
1412 case TT_WIN_OVF: /* window overflow */
1413 save_window(env);
1414 break;
1415 case TT_WIN_UNF: /* window underflow */
1416 restore_window(env);
1417 break;
1418 case TT_TFAULT:
1419 case TT_DFAULT:
1420 {
1421 info.si_signo = TARGET_SIGSEGV;
1422 info.si_errno = 0;
1423 /* XXX: check env->error_code */
1424 info.si_code = TARGET_SEGV_MAPERR;
1425 info._sifields._sigfault._addr = env->mmuregs[4];
1426 queue_signal(env, info.si_signo, &info);
1427 }
1428 break;
1429 #else
1430 case TT_SPILL: /* window overflow */
1431 save_window(env);
1432 break;
1433 case TT_FILL: /* window underflow */
1434 restore_window(env);
1435 break;
1436 case TT_TFAULT:
1437 case TT_DFAULT:
1438 {
1439 info.si_signo = TARGET_SIGSEGV;
1440 info.si_errno = 0;
1441 /* XXX: check env->error_code */
1442 info.si_code = TARGET_SEGV_MAPERR;
1443 if (trapnr == TT_DFAULT)
1444 info._sifields._sigfault._addr = env->dmmuregs[4];
1445 else
1446 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1447 queue_signal(env, info.si_signo, &info);
1448 }
1449 break;
1450 #ifndef TARGET_ABI32
1451 case 0x16e:
1452 flush_windows(env);
1453 sparc64_get_context(env);
1454 break;
1455 case 0x16f:
1456 flush_windows(env);
1457 sparc64_set_context(env);
1458 break;
1459 #endif
1460 #endif
1461 case EXCP_INTERRUPT:
1462 /* just indicate that signals should be handled asap */
1463 break;
1464 case TT_ILL_INSN:
1465 {
1466 info.si_signo = TARGET_SIGILL;
1467 info.si_errno = 0;
1468 info.si_code = TARGET_ILL_ILLOPC;
1469 info._sifields._sigfault._addr = env->pc;
1470 queue_signal(env, info.si_signo, &info);
1471 }
1472 break;
1473 case EXCP_DEBUG:
1474 {
1475 int sig;
1476
1477 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1478 if (sig)
1479 {
1480 info.si_signo = sig;
1481 info.si_errno = 0;
1482 info.si_code = TARGET_TRAP_BRKPT;
1483 queue_signal(env, info.si_signo, &info);
1484 }
1485 }
1486 break;
1487 default:
1488 printf ("Unhandled trap: 0x%x\n", trapnr);
1489 cpu_dump_state(cs, stderr, fprintf, 0);
1490 exit (1);
1491 }
1492 process_pending_signals (env);
1493 }
1494 }
1495
1496 #endif
1497
1498 #ifdef TARGET_PPC
1499 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1500 {
1501 /* TO FIX */
1502 return 0;
1503 }
1504
1505 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1506 {
1507 return cpu_ppc_get_tb(env);
1508 }
1509
1510 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1511 {
1512 return cpu_ppc_get_tb(env) >> 32;
1513 }
1514
1515 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1516 {
1517 return cpu_ppc_get_tb(env);
1518 }
1519
1520 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1521 {
1522 return cpu_ppc_get_tb(env) >> 32;
1523 }
1524
1525 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1526 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1527
1528 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1529 {
1530 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1531 }
1532
1533 /* XXX: to be fixed */
1534 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1535 {
1536 return -1;
1537 }
1538
1539 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1540 {
1541 return -1;
1542 }
1543
1544 #define EXCP_DUMP(env, fmt, ...) \
1545 do { \
1546 CPUState *cs = ENV_GET_CPU(env); \
1547 fprintf(stderr, fmt , ## __VA_ARGS__); \
1548 cpu_dump_state(cs, stderr, fprintf, 0); \
1549 qemu_log(fmt, ## __VA_ARGS__); \
1550 if (qemu_log_enabled()) { \
1551 log_cpu_state(cs, 0); \
1552 } \
1553 } while (0)
1554
1555 static int do_store_exclusive(CPUPPCState *env)
1556 {
1557 target_ulong addr;
1558 target_ulong page_addr;
1559 target_ulong val, val2 __attribute__((unused)) = 0;
1560 int flags;
1561 int segv = 0;
1562
1563 addr = env->reserve_ea;
1564 page_addr = addr & TARGET_PAGE_MASK;
1565 start_exclusive();
1566 mmap_lock();
1567 flags = page_get_flags(page_addr);
1568 if ((flags & PAGE_READ) == 0) {
1569 segv = 1;
1570 } else {
1571 int reg = env->reserve_info & 0x1f;
1572 int size = env->reserve_info >> 5;
1573 int stored = 0;
1574
1575 if (addr == env->reserve_addr) {
1576 switch (size) {
1577 case 1: segv = get_user_u8(val, addr); break;
1578 case 2: segv = get_user_u16(val, addr); break;
1579 case 4: segv = get_user_u32(val, addr); break;
1580 #if defined(TARGET_PPC64)
1581 case 8: segv = get_user_u64(val, addr); break;
1582 case 16: {
1583 segv = get_user_u64(val, addr);
1584 if (!segv) {
1585 segv = get_user_u64(val2, addr + 8);
1586 }
1587 break;
1588 }
1589 #endif
1590 default: abort();
1591 }
1592 if (!segv && val == env->reserve_val) {
1593 val = env->gpr[reg];
1594 switch (size) {
1595 case 1: segv = put_user_u8(val, addr); break;
1596 case 2: segv = put_user_u16(val, addr); break;
1597 case 4: segv = put_user_u32(val, addr); break;
1598 #if defined(TARGET_PPC64)
1599 case 8: segv = put_user_u64(val, addr); break;
1600 case 16: {
1601 if (val2 == env->reserve_val2) {
1602 if (msr_le) {
1603 val2 = val;
1604 val = env->gpr[reg+1];
1605 } else {
1606 val2 = env->gpr[reg+1];
1607 }
1608 segv = put_user_u64(val, addr);
1609 if (!segv) {
1610 segv = put_user_u64(val2, addr + 8);
1611 }
1612 }
1613 break;
1614 }
1615 #endif
1616 default: abort();
1617 }
1618 if (!segv) {
1619 stored = 1;
1620 }
1621 }
1622 }
1623 env->crf[0] = (stored << 1) | xer_so;
1624 env->reserve_addr = (target_ulong)-1;
1625 }
1626 if (!segv) {
1627 env->nip += 4;
1628 }
1629 mmap_unlock();
1630 end_exclusive();
1631 return segv;
1632 }
1633
1634 void cpu_loop(CPUPPCState *env)
1635 {
1636 CPUState *cs = CPU(ppc_env_get_cpu(env));
1637 target_siginfo_t info;
1638 int trapnr;
1639 target_ulong ret;
1640
1641 for(;;) {
1642 cpu_exec_start(cs);
1643 trapnr = cpu_ppc_exec(env);
1644 cpu_exec_end(cs);
1645 switch(trapnr) {
1646 case POWERPC_EXCP_NONE:
1647 /* Just go on */
1648 break;
1649 case POWERPC_EXCP_CRITICAL: /* Critical input */
1650 cpu_abort(cs, "Critical interrupt while in user mode. "
1651 "Aborting\n");
1652 break;
1653 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1654 cpu_abort(cs, "Machine check exception while in user mode. "
1655 "Aborting\n");
1656 break;
1657 case POWERPC_EXCP_DSI: /* Data storage exception */
1658 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1659 env->spr[SPR_DAR]);
1660 /* XXX: check this. Seems bugged */
1661 switch (env->error_code & 0xFF000000) {
1662 case 0x40000000:
1663 info.si_signo = TARGET_SIGSEGV;
1664 info.si_errno = 0;
1665 info.si_code = TARGET_SEGV_MAPERR;
1666 break;
1667 case 0x04000000:
1668 info.si_signo = TARGET_SIGILL;
1669 info.si_errno = 0;
1670 info.si_code = TARGET_ILL_ILLADR;
1671 break;
1672 case 0x08000000:
1673 info.si_signo = TARGET_SIGSEGV;
1674 info.si_errno = 0;
1675 info.si_code = TARGET_SEGV_ACCERR;
1676 break;
1677 default:
1678 /* Let's send a regular segfault... */
1679 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1680 env->error_code);
1681 info.si_signo = TARGET_SIGSEGV;
1682 info.si_errno = 0;
1683 info.si_code = TARGET_SEGV_MAPERR;
1684 break;
1685 }
1686 info._sifields._sigfault._addr = env->nip;
1687 queue_signal(env, info.si_signo, &info);
1688 break;
1689 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1690 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1691 "\n", env->spr[SPR_SRR0]);
1692 /* XXX: check this */
1693 switch (env->error_code & 0xFF000000) {
1694 case 0x40000000:
1695 info.si_signo = TARGET_SIGSEGV;
1696 info.si_errno = 0;
1697 info.si_code = TARGET_SEGV_MAPERR;
1698 break;
1699 case 0x10000000:
1700 case 0x08000000:
1701 info.si_signo = TARGET_SIGSEGV;
1702 info.si_errno = 0;
1703 info.si_code = TARGET_SEGV_ACCERR;
1704 break;
1705 default:
1706 /* Let's send a regular segfault... */
1707 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1708 env->error_code);
1709 info.si_signo = TARGET_SIGSEGV;
1710 info.si_errno = 0;
1711 info.si_code = TARGET_SEGV_MAPERR;
1712 break;
1713 }
1714 info._sifields._sigfault._addr = env->nip - 4;
1715 queue_signal(env, info.si_signo, &info);
1716 break;
1717 case POWERPC_EXCP_EXTERNAL: /* External input */
1718 cpu_abort(cs, "External interrupt while in user mode. "
1719 "Aborting\n");
1720 break;
1721 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1722 EXCP_DUMP(env, "Unaligned memory access\n");
1723 /* XXX: check this */
1724 info.si_signo = TARGET_SIGBUS;
1725 info.si_errno = 0;
1726 info.si_code = TARGET_BUS_ADRALN;
1727 info._sifields._sigfault._addr = env->nip - 4;
1728 queue_signal(env, info.si_signo, &info);
1729 break;
1730 case POWERPC_EXCP_PROGRAM: /* Program exception */
1731 /* XXX: check this */
1732 switch (env->error_code & ~0xF) {
1733 case POWERPC_EXCP_FP:
1734 EXCP_DUMP(env, "Floating point program exception\n");
1735 info.si_signo = TARGET_SIGFPE;
1736 info.si_errno = 0;
1737 switch (env->error_code & 0xF) {
1738 case POWERPC_EXCP_FP_OX:
1739 info.si_code = TARGET_FPE_FLTOVF;
1740 break;
1741 case POWERPC_EXCP_FP_UX:
1742 info.si_code = TARGET_FPE_FLTUND;
1743 break;
1744 case POWERPC_EXCP_FP_ZX:
1745 case POWERPC_EXCP_FP_VXZDZ:
1746 info.si_code = TARGET_FPE_FLTDIV;
1747 break;
1748 case POWERPC_EXCP_FP_XX:
1749 info.si_code = TARGET_FPE_FLTRES;
1750 break;
1751 case POWERPC_EXCP_FP_VXSOFT:
1752 info.si_code = TARGET_FPE_FLTINV;
1753 break;
1754 case POWERPC_EXCP_FP_VXSNAN:
1755 case POWERPC_EXCP_FP_VXISI:
1756 case POWERPC_EXCP_FP_VXIDI:
1757 case POWERPC_EXCP_FP_VXIMZ:
1758 case POWERPC_EXCP_FP_VXVC:
1759 case POWERPC_EXCP_FP_VXSQRT:
1760 case POWERPC_EXCP_FP_VXCVI:
1761 info.si_code = TARGET_FPE_FLTSUB;
1762 break;
1763 default:
1764 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1765 env->error_code);
1766 break;
1767 }
1768 break;
1769 case POWERPC_EXCP_INVAL:
1770 EXCP_DUMP(env, "Invalid instruction\n");
1771 info.si_signo = TARGET_SIGILL;
1772 info.si_errno = 0;
1773 switch (env->error_code & 0xF) {
1774 case POWERPC_EXCP_INVAL_INVAL:
1775 info.si_code = TARGET_ILL_ILLOPC;
1776 break;
1777 case POWERPC_EXCP_INVAL_LSWX:
1778 info.si_code = TARGET_ILL_ILLOPN;
1779 break;
1780 case POWERPC_EXCP_INVAL_SPR:
1781 info.si_code = TARGET_ILL_PRVREG;
1782 break;
1783 case POWERPC_EXCP_INVAL_FP:
1784 info.si_code = TARGET_ILL_COPROC;
1785 break;
1786 default:
1787 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1788 env->error_code & 0xF);
1789 info.si_code = TARGET_ILL_ILLADR;
1790 break;
1791 }
1792 break;
1793 case POWERPC_EXCP_PRIV:
1794 EXCP_DUMP(env, "Privilege violation\n");
1795 info.si_signo = TARGET_SIGILL;
1796 info.si_errno = 0;
1797 switch (env->error_code & 0xF) {
1798 case POWERPC_EXCP_PRIV_OPC:
1799 info.si_code = TARGET_ILL_PRVOPC;
1800 break;
1801 case POWERPC_EXCP_PRIV_REG:
1802 info.si_code = TARGET_ILL_PRVREG;
1803 break;
1804 default:
1805 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1806 env->error_code & 0xF);
1807 info.si_code = TARGET_ILL_PRVOPC;
1808 break;
1809 }
1810 break;
1811 case POWERPC_EXCP_TRAP:
1812 cpu_abort(cs, "Tried to call a TRAP\n");
1813 break;
1814 default:
1815 /* Should not happen ! */
1816 cpu_abort(cs, "Unknown program exception (%02x)\n",
1817 env->error_code);
1818 break;
1819 }
1820 info._sifields._sigfault._addr = env->nip - 4;
1821 queue_signal(env, info.si_signo, &info);
1822 break;
1823 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1824 EXCP_DUMP(env, "No floating point allowed\n");
1825 info.si_signo = TARGET_SIGILL;
1826 info.si_errno = 0;
1827 info.si_code = TARGET_ILL_COPROC;
1828 info._sifields._sigfault._addr = env->nip - 4;
1829 queue_signal(env, info.si_signo, &info);
1830 break;
1831 case POWERPC_EXCP_SYSCALL: /* System call exception */
1832 cpu_abort(cs, "Syscall exception while in user mode. "
1833 "Aborting\n");
1834 break;
1835 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1836 EXCP_DUMP(env, "No APU instruction allowed\n");
1837 info.si_signo = TARGET_SIGILL;
1838 info.si_errno = 0;
1839 info.si_code = TARGET_ILL_COPROC;
1840 info._sifields._sigfault._addr = env->nip - 4;
1841 queue_signal(env, info.si_signo, &info);
1842 break;
1843 case POWERPC_EXCP_DECR: /* Decrementer exception */
1844 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1845 "Aborting\n");
1846 break;
1847 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1848 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1849 "Aborting\n");
1850 break;
1851 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1852 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1853 "Aborting\n");
1854 break;
1855 case POWERPC_EXCP_DTLB: /* Data TLB error */
1856 cpu_abort(cs, "Data TLB exception while in user mode. "
1857 "Aborting\n");
1858 break;
1859 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1860 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1861 "Aborting\n");
1862 break;
1863 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1864 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1865 info.si_signo = TARGET_SIGILL;
1866 info.si_errno = 0;
1867 info.si_code = TARGET_ILL_COPROC;
1868 info._sifields._sigfault._addr = env->nip - 4;
1869 queue_signal(env, info.si_signo, &info);
1870 break;
1871 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1872 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1873 break;
1874 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1875 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1876 break;
1877 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1878 cpu_abort(cs, "Performance monitor exception not handled\n");
1879 break;
1880 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1881 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1882 "Aborting\n");
1883 break;
1884 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1885 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1886 "Aborting\n");
1887 break;
1888 case POWERPC_EXCP_RESET: /* System reset exception */
1889 cpu_abort(cs, "Reset interrupt while in user mode. "
1890 "Aborting\n");
1891 break;
1892 case POWERPC_EXCP_DSEG: /* Data segment exception */
1893 cpu_abort(cs, "Data segment exception while in user mode. "
1894 "Aborting\n");
1895 break;
1896 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1897 cpu_abort(cs, "Instruction segment exception "
1898 "while in user mode. Aborting\n");
1899 break;
1900 /* PowerPC 64 with hypervisor mode support */
1901 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1902 cpu_abort(cs, "Hypervisor decrementer interrupt "
1903 "while in user mode. Aborting\n");
1904 break;
1905 case POWERPC_EXCP_TRACE: /* Trace exception */
1906 /* Nothing to do:
1907 * we use this exception to emulate step-by-step execution mode.
1908 */
1909 break;
1910 /* PowerPC 64 with hypervisor mode support */
1911 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1912 cpu_abort(cs, "Hypervisor data storage exception "
1913 "while in user mode. Aborting\n");
1914 break;
1915 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1916 cpu_abort(cs, "Hypervisor instruction storage exception "
1917 "while in user mode. Aborting\n");
1918 break;
1919 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1920 cpu_abort(cs, "Hypervisor data segment exception "
1921 "while in user mode. Aborting\n");
1922 break;
1923 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1924 cpu_abort(cs, "Hypervisor instruction segment exception "
1925 "while in user mode. Aborting\n");
1926 break;
1927 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1928 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1929 info.si_signo = TARGET_SIGILL;
1930 info.si_errno = 0;
1931 info.si_code = TARGET_ILL_COPROC;
1932 info._sifields._sigfault._addr = env->nip - 4;
1933 queue_signal(env, info.si_signo, &info);
1934 break;
1935 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1936 cpu_abort(cs, "Programmable interval timer interrupt "
1937 "while in user mode. Aborting\n");
1938 break;
1939 case POWERPC_EXCP_IO: /* IO error exception */
1940 cpu_abort(cs, "IO error exception while in user mode. "
1941 "Aborting\n");
1942 break;
1943 case POWERPC_EXCP_RUNM: /* Run mode exception */
1944 cpu_abort(cs, "Run mode exception while in user mode. "
1945 "Aborting\n");
1946 break;
1947 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1948 cpu_abort(cs, "Emulation trap exception not handled\n");
1949 break;
1950 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1951 cpu_abort(cs, "Instruction fetch TLB exception "
1952 "while in user-mode. Aborting");
1953 break;
1954 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1955 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1956 "Aborting");
1957 break;
1958 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1959 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1960 "Aborting");
1961 break;
1962 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1963 cpu_abort(cs, "Floating-point assist exception not handled\n");
1964 break;
1965 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1966 cpu_abort(cs, "Instruction address breakpoint exception "
1967 "not handled\n");
1968 break;
1969 case POWERPC_EXCP_SMI: /* System management interrupt */
1970 cpu_abort(cs, "System management interrupt while in user mode. "
1971 "Aborting\n");
1972 break;
1973 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1974 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1975 "Aborting\n");
1976 break;
1977 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1978 cpu_abort(cs, "Performance monitor exception not handled\n");
1979 break;
1980 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1981 cpu_abort(cs, "Vector assist exception not handled\n");
1982 break;
1983 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1984 cpu_abort(cs, "Soft patch exception not handled\n");
1985 break;
1986 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1987 cpu_abort(cs, "Maintenance exception while in user mode. "
1988 "Aborting\n");
1989 break;
1990 case POWERPC_EXCP_STOP: /* stop translation */
1991 /* We did invalidate the instruction cache. Go on */
1992 break;
1993 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1994 /* We just stopped because of a branch. Go on */
1995 break;
1996 case POWERPC_EXCP_SYSCALL_USER:
1997 /* system call in user-mode emulation */
1998 /* WARNING:
1999 * PPC ABI uses overflow flag in cr0 to signal an error
2000 * in syscalls.
2001 */
2002 env->crf[0] &= ~0x1;
2003 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
2004 env->gpr[5], env->gpr[6], env->gpr[7],
2005 env->gpr[8], 0, 0);
2006 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
2007 /* Returning from a successful sigreturn syscall.
2008 Avoid corrupting register state. */
2009 break;
2010 }
2011 if (ret > (target_ulong)(-515)) {
2012 env->crf[0] |= 0x1;
2013 ret = -ret;
2014 }
2015 env->gpr[3] = ret;
2016 break;
2017 case POWERPC_EXCP_STCX:
2018 if (do_store_exclusive(env)) {
2019 info.si_signo = TARGET_SIGSEGV;
2020 info.si_errno = 0;
2021 info.si_code = TARGET_SEGV_MAPERR;
2022 info._sifields._sigfault._addr = env->nip;
2023 queue_signal(env, info.si_signo, &info);
2024 }
2025 break;
2026 case EXCP_DEBUG:
2027 {
2028 int sig;
2029
2030 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2031 if (sig) {
2032 info.si_signo = sig;
2033 info.si_errno = 0;
2034 info.si_code = TARGET_TRAP_BRKPT;
2035 queue_signal(env, info.si_signo, &info);
2036 }
2037 }
2038 break;
2039 case EXCP_INTERRUPT:
2040 /* just indicate that signals should be handled asap */
2041 break;
2042 default:
2043 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
2044 break;
2045 }
2046 process_pending_signals(env);
2047 }
2048 }
2049 #endif
2050
2051 #ifdef TARGET_MIPS
2052
2053 # ifdef TARGET_ABI_MIPSO32
2054 # define MIPS_SYS(name, args) args,
2055 static const uint8_t mips_syscall_args[] = {
2056 MIPS_SYS(sys_syscall , 8) /* 4000 */
2057 MIPS_SYS(sys_exit , 1)
2058 MIPS_SYS(sys_fork , 0)
2059 MIPS_SYS(sys_read , 3)
2060 MIPS_SYS(sys_write , 3)
2061 MIPS_SYS(sys_open , 3) /* 4005 */
2062 MIPS_SYS(sys_close , 1)
2063 MIPS_SYS(sys_waitpid , 3)
2064 MIPS_SYS(sys_creat , 2)
2065 MIPS_SYS(sys_link , 2)
2066 MIPS_SYS(sys_unlink , 1) /* 4010 */
2067 MIPS_SYS(sys_execve , 0)
2068 MIPS_SYS(sys_chdir , 1)
2069 MIPS_SYS(sys_time , 1)
2070 MIPS_SYS(sys_mknod , 3)
2071 MIPS_SYS(sys_chmod , 2) /* 4015 */
2072 MIPS_SYS(sys_lchown , 3)
2073 MIPS_SYS(sys_ni_syscall , 0)
2074 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2075 MIPS_SYS(sys_lseek , 3)
2076 MIPS_SYS(sys_getpid , 0) /* 4020 */
2077 MIPS_SYS(sys_mount , 5)
2078 MIPS_SYS(sys_umount , 1)
2079 MIPS_SYS(sys_setuid , 1)
2080 MIPS_SYS(sys_getuid , 0)
2081 MIPS_SYS(sys_stime , 1) /* 4025 */
2082 MIPS_SYS(sys_ptrace , 4)
2083 MIPS_SYS(sys_alarm , 1)
2084 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2085 MIPS_SYS(sys_pause , 0)
2086 MIPS_SYS(sys_utime , 2) /* 4030 */
2087 MIPS_SYS(sys_ni_syscall , 0)
2088 MIPS_SYS(sys_ni_syscall , 0)
2089 MIPS_SYS(sys_access , 2)
2090 MIPS_SYS(sys_nice , 1)
2091 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2092 MIPS_SYS(sys_sync , 0)
2093 MIPS_SYS(sys_kill , 2)
2094 MIPS_SYS(sys_rename , 2)
2095 MIPS_SYS(sys_mkdir , 2)
2096 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2097 MIPS_SYS(sys_dup , 1)
2098 MIPS_SYS(sys_pipe , 0)
2099 MIPS_SYS(sys_times , 1)
2100 MIPS_SYS(sys_ni_syscall , 0)
2101 MIPS_SYS(sys_brk , 1) /* 4045 */
2102 MIPS_SYS(sys_setgid , 1)
2103 MIPS_SYS(sys_getgid , 0)
2104 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2105 MIPS_SYS(sys_geteuid , 0)
2106 MIPS_SYS(sys_getegid , 0) /* 4050 */
2107 MIPS_SYS(sys_acct , 0)
2108 MIPS_SYS(sys_umount2 , 2)
2109 MIPS_SYS(sys_ni_syscall , 0)
2110 MIPS_SYS(sys_ioctl , 3)
2111 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2112 MIPS_SYS(sys_ni_syscall , 2)
2113 MIPS_SYS(sys_setpgid , 2)
2114 MIPS_SYS(sys_ni_syscall , 0)
2115 MIPS_SYS(sys_olduname , 1)
2116 MIPS_SYS(sys_umask , 1) /* 4060 */
2117 MIPS_SYS(sys_chroot , 1)
2118 MIPS_SYS(sys_ustat , 2)
2119 MIPS_SYS(sys_dup2 , 2)
2120 MIPS_SYS(sys_getppid , 0)
2121 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2122 MIPS_SYS(sys_setsid , 0)
2123 MIPS_SYS(sys_sigaction , 3)
2124 MIPS_SYS(sys_sgetmask , 0)
2125 MIPS_SYS(sys_ssetmask , 1)
2126 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2127 MIPS_SYS(sys_setregid , 2)
2128 MIPS_SYS(sys_sigsuspend , 0)
2129 MIPS_SYS(sys_sigpending , 1)
2130 MIPS_SYS(sys_sethostname , 2)
2131 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2132 MIPS_SYS(sys_getrlimit , 2)
2133 MIPS_SYS(sys_getrusage , 2)
2134 MIPS_SYS(sys_gettimeofday, 2)
2135 MIPS_SYS(sys_settimeofday, 2)
2136 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2137 MIPS_SYS(sys_setgroups , 2)
2138 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2139 MIPS_SYS(sys_symlink , 2)
2140 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2141 MIPS_SYS(sys_readlink , 3) /* 4085 */
2142 MIPS_SYS(sys_uselib , 1)
2143 MIPS_SYS(sys_swapon , 2)
2144 MIPS_SYS(sys_reboot , 3)
2145 MIPS_SYS(old_readdir , 3)
2146 MIPS_SYS(old_mmap , 6) /* 4090 */
2147 MIPS_SYS(sys_munmap , 2)
2148 MIPS_SYS(sys_truncate , 2)
2149 MIPS_SYS(sys_ftruncate , 2)
2150 MIPS_SYS(sys_fchmod , 2)
2151 MIPS_SYS(sys_fchown , 3) /* 4095 */
2152 MIPS_SYS(sys_getpriority , 2)
2153 MIPS_SYS(sys_setpriority , 3)
2154 MIPS_SYS(sys_ni_syscall , 0)
2155 MIPS_SYS(sys_statfs , 2)
2156 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2157 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2158 MIPS_SYS(sys_socketcall , 2)
2159 MIPS_SYS(sys_syslog , 3)
2160 MIPS_SYS(sys_setitimer , 3)
2161 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2162 MIPS_SYS(sys_newstat , 2)
2163 MIPS_SYS(sys_newlstat , 2)
2164 MIPS_SYS(sys_newfstat , 2)
2165 MIPS_SYS(sys_uname , 1)
2166 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2167 MIPS_SYS(sys_vhangup , 0)
2168 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2169 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2170 MIPS_SYS(sys_wait4 , 4)
2171 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2172 MIPS_SYS(sys_sysinfo , 1)
2173 MIPS_SYS(sys_ipc , 6)
2174 MIPS_SYS(sys_fsync , 1)
2175 MIPS_SYS(sys_sigreturn , 0)
2176 MIPS_SYS(sys_clone , 6) /* 4120 */
2177 MIPS_SYS(sys_setdomainname, 2)
2178 MIPS_SYS(sys_newuname , 1)
2179 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2180 MIPS_SYS(sys_adjtimex , 1)
2181 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2182 MIPS_SYS(sys_sigprocmask , 3)
2183 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2184 MIPS_SYS(sys_init_module , 5)
2185 MIPS_SYS(sys_delete_module, 1)
2186 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2187 MIPS_SYS(sys_quotactl , 0)
2188 MIPS_SYS(sys_getpgid , 1)
2189 MIPS_SYS(sys_fchdir , 1)
2190 MIPS_SYS(sys_bdflush , 2)
2191 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2192 MIPS_SYS(sys_personality , 1)
2193 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2194 MIPS_SYS(sys_setfsuid , 1)
2195 MIPS_SYS(sys_setfsgid , 1)
2196 MIPS_SYS(sys_llseek , 5) /* 4140 */
2197 MIPS_SYS(sys_getdents , 3)
2198 MIPS_SYS(sys_select , 5)
2199 MIPS_SYS(sys_flock , 2)
2200 MIPS_SYS(sys_msync , 3)
2201 MIPS_SYS(sys_readv , 3) /* 4145 */
2202 MIPS_SYS(sys_writev , 3)
2203 MIPS_SYS(sys_cacheflush , 3)
2204 MIPS_SYS(sys_cachectl , 3)
2205 MIPS_SYS(sys_sysmips , 4)
2206 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2207 MIPS_SYS(sys_getsid , 1)
2208 MIPS_SYS(sys_fdatasync , 0)
2209 MIPS_SYS(sys_sysctl , 1)
2210 MIPS_SYS(sys_mlock , 2)
2211 MIPS_SYS(sys_munlock , 2) /* 4155 */
2212 MIPS_SYS(sys_mlockall , 1)
2213 MIPS_SYS(sys_munlockall , 0)
2214 MIPS_SYS(sys_sched_setparam, 2)
2215 MIPS_SYS(sys_sched_getparam, 2)
2216 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2217 MIPS_SYS(sys_sched_getscheduler, 1)
2218 MIPS_SYS(sys_sched_yield , 0)
2219 MIPS_SYS(sys_sched_get_priority_max, 1)
2220 MIPS_SYS(sys_sched_get_priority_min, 1)
2221 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2222 MIPS_SYS(sys_nanosleep, 2)
2223 MIPS_SYS(sys_mremap , 5)
2224 MIPS_SYS(sys_accept , 3)
2225 MIPS_SYS(sys_bind , 3)
2226 MIPS_SYS(sys_connect , 3) /* 4170 */
2227 MIPS_SYS(sys_getpeername , 3)
2228 MIPS_SYS(sys_getsockname , 3)
2229 MIPS_SYS(sys_getsockopt , 5)
2230 MIPS_SYS(sys_listen , 2)
2231 MIPS_SYS(sys_recv , 4) /* 4175 */
2232 MIPS_SYS(sys_recvfrom , 6)
2233 MIPS_SYS(sys_recvmsg , 3)
2234 MIPS_SYS(sys_send , 4)
2235 MIPS_SYS(sys_sendmsg , 3)
2236 MIPS_SYS(sys_sendto , 6) /* 4180 */
2237 MIPS_SYS(sys_setsockopt , 5)
2238 MIPS_SYS(sys_shutdown , 2)
2239 MIPS_SYS(sys_socket , 3)
2240 MIPS_SYS(sys_socketpair , 4)
2241 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2242 MIPS_SYS(sys_getresuid , 3)
2243 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2244 MIPS_SYS(sys_poll , 3)
2245 MIPS_SYS(sys_nfsservctl , 3)
2246 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2247 MIPS_SYS(sys_getresgid , 3)
2248 MIPS_SYS(sys_prctl , 5)
2249 MIPS_SYS(sys_rt_sigreturn, 0)
2250 MIPS_SYS(sys_rt_sigaction, 4)
2251 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2252 MIPS_SYS(sys_rt_sigpending, 2)
2253 MIPS_SYS(sys_rt_sigtimedwait, 4)
2254 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2255 MIPS_SYS(sys_rt_sigsuspend, 0)
2256 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2257 MIPS_SYS(sys_pwrite64 , 6)
2258 MIPS_SYS(sys_chown , 3)
2259 MIPS_SYS(sys_getcwd , 2)
2260 MIPS_SYS(sys_capget , 2)
2261 MIPS_SYS(sys_capset , 2) /* 4205 */
2262 MIPS_SYS(sys_sigaltstack , 2)
2263 MIPS_SYS(sys_sendfile , 4)
2264 MIPS_SYS(sys_ni_syscall , 0)
2265 MIPS_SYS(sys_ni_syscall , 0)
2266 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2267 MIPS_SYS(sys_truncate64 , 4)
2268 MIPS_SYS(sys_ftruncate64 , 4)
2269 MIPS_SYS(sys_stat64 , 2)
2270 MIPS_SYS(sys_lstat64 , 2)
2271 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2272 MIPS_SYS(sys_pivot_root , 2)
2273 MIPS_SYS(sys_mincore , 3)
2274 MIPS_SYS(sys_madvise , 3)
2275 MIPS_SYS(sys_getdents64 , 3)
2276 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2277 MIPS_SYS(sys_ni_syscall , 0)
2278 MIPS_SYS(sys_gettid , 0)
2279 MIPS_SYS(sys_readahead , 5)
2280 MIPS_SYS(sys_setxattr , 5)
2281 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2282 MIPS_SYS(sys_fsetxattr , 5)
2283 MIPS_SYS(sys_getxattr , 4)
2284 MIPS_SYS(sys_lgetxattr , 4)
2285 MIPS_SYS(sys_fgetxattr , 4)
2286 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2287 MIPS_SYS(sys_llistxattr , 3)
2288 MIPS_SYS(sys_flistxattr , 3)
2289 MIPS_SYS(sys_removexattr , 2)
2290 MIPS_SYS(sys_lremovexattr, 2)
2291 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2292 MIPS_SYS(sys_tkill , 2)
2293 MIPS_SYS(sys_sendfile64 , 5)
2294 MIPS_SYS(sys_futex , 6)
2295 MIPS_SYS(sys_sched_setaffinity, 3)
2296 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2297 MIPS_SYS(sys_io_setup , 2)
2298 MIPS_SYS(sys_io_destroy , 1)
2299 MIPS_SYS(sys_io_getevents, 5)
2300 MIPS_SYS(sys_io_submit , 3)
2301 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2302 MIPS_SYS(sys_exit_group , 1)
2303 MIPS_SYS(sys_lookup_dcookie, 3)
2304 MIPS_SYS(sys_epoll_create, 1)
2305 MIPS_SYS(sys_epoll_ctl , 4)
2306 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2307 MIPS_SYS(sys_remap_file_pages, 5)
2308 MIPS_SYS(sys_set_tid_address, 1)
2309 MIPS_SYS(sys_restart_syscall, 0)
2310 MIPS_SYS(sys_fadvise64_64, 7)
2311 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2312 MIPS_SYS(sys_fstatfs64 , 2)
2313 MIPS_SYS(sys_timer_create, 3)
2314 MIPS_SYS(sys_timer_settime, 4)
2315 MIPS_SYS(sys_timer_gettime, 2)
2316 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2317 MIPS_SYS(sys_timer_delete, 1)
2318 MIPS_SYS(sys_clock_settime, 2)
2319 MIPS_SYS(sys_clock_gettime, 2)
2320 MIPS_SYS(sys_clock_getres, 2)
2321 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2322 MIPS_SYS(sys_tgkill , 3)
2323 MIPS_SYS(sys_utimes , 2)
2324 MIPS_SYS(sys_mbind , 4)
2325 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2326 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2327 MIPS_SYS(sys_mq_open , 4)
2328 MIPS_SYS(sys_mq_unlink , 1)
2329 MIPS_SYS(sys_mq_timedsend, 5)
2330 MIPS_SYS(sys_mq_timedreceive, 5)
2331 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2332 MIPS_SYS(sys_mq_getsetattr, 3)
2333 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2334 MIPS_SYS(sys_waitid , 4)
2335 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2336 MIPS_SYS(sys_add_key , 5)
2337 MIPS_SYS(sys_request_key, 4)
2338 MIPS_SYS(sys_keyctl , 5)
2339 MIPS_SYS(sys_set_thread_area, 1)
2340 MIPS_SYS(sys_inotify_init, 0)
2341 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2342 MIPS_SYS(sys_inotify_rm_watch, 2)
2343 MIPS_SYS(sys_migrate_pages, 4)
2344 MIPS_SYS(sys_openat, 4)
2345 MIPS_SYS(sys_mkdirat, 3)
2346 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2347 MIPS_SYS(sys_fchownat, 5)
2348 MIPS_SYS(sys_futimesat, 3)
2349 MIPS_SYS(sys_fstatat64, 4)
2350 MIPS_SYS(sys_unlinkat, 3)
2351 MIPS_SYS(sys_renameat, 4) /* 4295 */
2352 MIPS_SYS(sys_linkat, 5)
2353 MIPS_SYS(sys_symlinkat, 3)
2354 MIPS_SYS(sys_readlinkat, 4)
2355 MIPS_SYS(sys_fchmodat, 3)
2356 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2357 MIPS_SYS(sys_pselect6, 6)
2358 MIPS_SYS(sys_ppoll, 5)
2359 MIPS_SYS(sys_unshare, 1)
2360 MIPS_SYS(sys_splice, 6)
2361 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2362 MIPS_SYS(sys_tee, 4)
2363 MIPS_SYS(sys_vmsplice, 4)
2364 MIPS_SYS(sys_move_pages, 6)
2365 MIPS_SYS(sys_set_robust_list, 2)
2366 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2367 MIPS_SYS(sys_kexec_load, 4)
2368 MIPS_SYS(sys_getcpu, 3)
2369 MIPS_SYS(sys_epoll_pwait, 6)
2370 MIPS_SYS(sys_ioprio_set, 3)
2371 MIPS_SYS(sys_ioprio_get, 2)
2372 MIPS_SYS(sys_utimensat, 4)
2373 MIPS_SYS(sys_signalfd, 3)
2374 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2375 MIPS_SYS(sys_eventfd, 1)
2376 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2377 MIPS_SYS(sys_timerfd_create, 2)
2378 MIPS_SYS(sys_timerfd_gettime, 2)
2379 MIPS_SYS(sys_timerfd_settime, 4)
2380 MIPS_SYS(sys_signalfd4, 4)
2381 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2382 MIPS_SYS(sys_epoll_create1, 1)
2383 MIPS_SYS(sys_dup3, 3)
2384 MIPS_SYS(sys_pipe2, 2)
2385 MIPS_SYS(sys_inotify_init1, 1)
2386 MIPS_SYS(sys_preadv, 6) /* 4330 */
2387 MIPS_SYS(sys_pwritev, 6)
2388 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2389 MIPS_SYS(sys_perf_event_open, 5)
2390 MIPS_SYS(sys_accept4, 4)
2391 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2392 MIPS_SYS(sys_fanotify_init, 2)
2393 MIPS_SYS(sys_fanotify_mark, 6)
2394 MIPS_SYS(sys_prlimit64, 4)
2395 MIPS_SYS(sys_name_to_handle_at, 5)
2396 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2397 MIPS_SYS(sys_clock_adjtime, 2)
2398 MIPS_SYS(sys_syncfs, 1)
2399 };
2400 # undef MIPS_SYS
2401 # endif /* O32 */
2402
2403 static int do_store_exclusive(CPUMIPSState *env)
2404 {
2405 target_ulong addr;
2406 target_ulong page_addr;
2407 target_ulong val;
2408 int flags;
2409 int segv = 0;
2410 int reg;
2411 int d;
2412
2413 addr = env->lladdr;
2414 page_addr = addr & TARGET_PAGE_MASK;
2415 start_exclusive();
2416 mmap_lock();
2417 flags = page_get_flags(page_addr);
2418 if ((flags & PAGE_READ) == 0) {
2419 segv = 1;
2420 } else {
2421 reg = env->llreg & 0x1f;
2422 d = (env->llreg & 0x20) != 0;
2423 if (d) {
2424 segv = get_user_s64(val, addr);
2425 } else {
2426 segv = get_user_s32(val, addr);
2427 }
2428 if (!segv) {
2429 if (val != env->llval) {
2430 env->active_tc.gpr[reg] = 0;
2431 } else {
2432 if (d) {
2433 segv = put_user_u64(env->llnewval, addr);
2434 } else {
2435 segv = put_user_u32(env->llnewval, addr);
2436 }
2437 if (!segv) {
2438 env->active_tc.gpr[reg] = 1;
2439 }
2440 }
2441 }
2442 }
2443 env->lladdr = -1;
2444 if (!segv) {
2445 env->active_tc.PC += 4;
2446 }
2447 mmap_unlock();
2448 end_exclusive();
2449 return segv;
2450 }
2451
2452 /* Break codes */
2453 enum {
2454 BRK_OVERFLOW = 6,
2455 BRK_DIVZERO = 7
2456 };
2457
2458 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2459 unsigned int code)
2460 {
2461 int ret = -1;
2462
2463 switch (code) {
2464 case BRK_OVERFLOW:
2465 case BRK_DIVZERO:
2466 info->si_signo = TARGET_SIGFPE;
2467 info->si_errno = 0;
2468 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2469 queue_signal(env, info->si_signo, &*info);
2470 ret = 0;
2471 break;
2472 default:
2473 info->si_signo = TARGET_SIGTRAP;
2474 info->si_errno = 0;
2475 queue_signal(env, info->si_signo, &*info);
2476 ret = 0;
2477 break;
2478 }
2479
2480 return ret;
2481 }
2482
2483 void cpu_loop(CPUMIPSState *env)
2484 {
2485 CPUState *cs = CPU(mips_env_get_cpu(env));
2486 target_siginfo_t info;
2487 int trapnr;
2488 abi_long ret;
2489 # ifdef TARGET_ABI_MIPSO32
2490 unsigned int syscall_num;
2491 # endif
2492
2493 for(;;) {
2494 cpu_exec_start(cs);
2495 trapnr = cpu_mips_exec(env);
2496 cpu_exec_end(cs);
2497 switch(trapnr) {
2498 case EXCP_SYSCALL:
2499 env->active_tc.PC += 4;
2500 # ifdef TARGET_ABI_MIPSO32
2501 syscall_num = env->active_tc.gpr[2] - 4000;
2502 if (syscall_num >= sizeof(mips_syscall_args)) {
2503 ret = -TARGET_ENOSYS;
2504 } else {
2505 int nb_args;
2506 abi_ulong sp_reg;
2507 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2508
2509 nb_args = mips_syscall_args[syscall_num];
2510 sp_reg = env->active_tc.gpr[29];
2511 switch (nb_args) {
2512 /* these arguments are taken from the stack */
2513 case 8:
2514 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2515 goto done_syscall;
2516 }
2517 case 7:
2518 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2519 goto done_syscall;
2520 }
2521 case 6:
2522 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2523 goto done_syscall;
2524 }
2525 case 5:
2526 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2527 goto done_syscall;
2528 }
2529 default:
2530 break;
2531 }
2532 ret = do_syscall(env, env->active_tc.gpr[2],
2533 env->active_tc.gpr[4],
2534 env->active_tc.gpr[5],
2535 env->active_tc.gpr[6],
2536 env->active_tc.gpr[7],
2537 arg5, arg6, arg7, arg8);
2538 }
2539 done_syscall:
2540 # else
2541 ret = do_syscall(env, env->active_tc.gpr[2],
2542 env->active_tc.gpr[4], env->active_tc.gpr[5],
2543 env->active_tc.gpr[6], env->active_tc.gpr[7],
2544 env->active_tc.gpr[8], env->active_tc.gpr[9],
2545 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2546 # endif /* O32 */
2547 if (ret == -TARGET_QEMU_ESIGRETURN) {
2548 /* Returning from a successful sigreturn syscall.
2549 Avoid clobbering register state. */
2550 break;
2551 }
2552 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2553 env->active_tc.gpr[7] = 1; /* error flag */
2554 ret = -ret;
2555 } else {
2556 env->active_tc.gpr[7] = 0; /* error flag */
2557 }
2558 env->active_tc.gpr[2] = ret;
2559 break;
2560 case EXCP_TLBL:
2561 case EXCP_TLBS:
2562 case EXCP_AdEL:
2563 case EXCP_AdES:
2564 info.si_signo = TARGET_SIGSEGV;
2565 info.si_errno = 0;
2566 /* XXX: check env->error_code */
2567 info.si_code = TARGET_SEGV_MAPERR;
2568 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2569 queue_signal(env, info.si_signo, &info);
2570 break;
2571 case EXCP_CpU:
2572 case EXCP_RI:
2573 info.si_signo = TARGET_SIGILL;
2574 info.si_errno = 0;
2575 info.si_code = 0;
2576 queue_signal(env, info.si_signo, &info);
2577 break;
2578 case EXCP_INTERRUPT:
2579 /* just indicate that signals should be handled asap */
2580 break;
2581 case EXCP_DEBUG:
2582 {
2583 int sig;
2584
2585 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2586 if (sig)
2587 {
2588 info.si_signo = sig;
2589 info.si_errno = 0;
2590 info.si_code = TARGET_TRAP_BRKPT;
2591 queue_signal(env, info.si_signo, &info);
2592 }
2593 }
2594 break;
2595 case EXCP_SC:
2596 if (do_store_exclusive(env)) {
2597 info.si_signo = TARGET_SIGSEGV;
2598 info.si_errno = 0;
2599 info.si_code = TARGET_SEGV_MAPERR;
2600 info._sifields._sigfault._addr = env->active_tc.PC;
2601 queue_signal(env, info.si_signo, &info);
2602 }
2603 break;
2604 case EXCP_DSPDIS:
2605 info.si_signo = TARGET_SIGILL;
2606 info.si_errno = 0;
2607 info.si_code = TARGET_ILL_ILLOPC;
2608 queue_signal(env, info.si_signo, &info);
2609 break;
2610 /* The code below was inspired by the MIPS Linux kernel trap
2611 * handling code in arch/mips/kernel/traps.c.
2612 */
2613 case EXCP_BREAK:
2614 {
2615 abi_ulong trap_instr;
2616 unsigned int code;
2617
2618 if (env->hflags & MIPS_HFLAG_M16) {
2619 if (env->insn_flags & ASE_MICROMIPS) {
2620 /* microMIPS mode */
2621 ret = get_user_u16(trap_instr, env->active_tc.PC);
2622 if (ret != 0) {
2623 goto error;
2624 }
2625
2626 if ((trap_instr >> 10) == 0x11) {
2627 /* 16-bit instruction */
2628 code = trap_instr & 0xf;
2629 } else {
2630 /* 32-bit instruction */
2631 abi_ulong instr_lo;
2632
2633 ret = get_user_u16(instr_lo,
2634 env->active_tc.PC + 2);
2635 if (ret != 0) {
2636 goto error;
2637 }
2638 trap_instr = (trap_instr << 16) | instr_lo;
2639 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2640 /* Unfortunately, microMIPS also suffers from
2641 the old assembler bug... */
2642 if (code >= (1 << 10)) {
2643 code >>= 10;
2644 }
2645 }
2646 } else {
2647 /* MIPS16e mode */
2648 ret = get_user_u16(trap_instr, env->active_tc.PC);
2649 if (ret != 0) {
2650 goto error;
2651 }
2652 code = (trap_instr >> 6) & 0x3f;
2653 }
2654 } else {
2655 ret = get_user_ual(trap_instr, env->active_tc.PC);
2656 if (ret != 0) {
2657 goto error;
2658 }
2659
2660 /* As described in the original Linux kernel code, the
2661 * below checks on 'code' are to work around an old
2662 * assembly bug.
2663 */
2664 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2665 if (code >= (1 << 10)) {
2666 code >>= 10;
2667 }
2668 }
2669
2670 if (do_break(env, &info, code) != 0) {
2671 goto error;
2672 }
2673 }
2674 break;
2675 case EXCP_TRAP:
2676 {
2677 abi_ulong trap_instr;
2678 unsigned int code = 0;
2679
2680 if (env->hflags & MIPS_HFLAG_M16) {
2681 /* microMIPS mode */
2682 abi_ulong instr[2];
2683
2684 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2685 get_user_u16(instr[1], env->active_tc.PC + 2);
2686
2687 trap_instr = (instr[0] << 16) | instr[1];
2688 } else {
2689 ret = get_user_ual(trap_instr, env->active_tc.PC);
2690 }
2691
2692 if (ret != 0) {
2693 goto error;
2694 }
2695
2696 /* The immediate versions don't provide a code. */
2697 if (!(trap_instr & 0xFC000000)) {
2698 if (env->hflags & MIPS_HFLAG_M16) {
2699 /* microMIPS mode */
2700 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2701 } else {
2702 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2703 }
2704 }
2705
2706 if (do_break(env, &info, code) != 0) {
2707 goto error;
2708 }
2709 }
2710 break;
2711 default:
2712 error:
2713 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2714 trapnr);
2715 cpu_dump_state(cs, stderr, fprintf, 0);
2716 abort();
2717 }
2718 process_pending_signals(env);
2719 }
2720 }
2721 #endif
2722
2723 #ifdef TARGET_OPENRISC
2724
2725 void cpu_loop(CPUOpenRISCState *env)
2726 {
2727 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2728 int trapnr, gdbsig;
2729
2730 for (;;) {
2731 trapnr = cpu_exec(env);
2732 gdbsig = 0;
2733
2734 switch (trapnr) {
2735 case EXCP_RESET:
2736 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2737 exit(1);
2738 break;
2739 case EXCP_BUSERR:
2740 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2741 gdbsig = SIGBUS;
2742 break;
2743 case EXCP_DPF:
2744 case EXCP_IPF:
2745 cpu_dump_state(cs, stderr, fprintf, 0);
2746 gdbsig = TARGET_SIGSEGV;
2747 break;
2748 case EXCP_TICK:
2749 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2750 break;
2751 case EXCP_ALIGN:
2752 qemu_log("\nAlignment pc is %#x\n", env->pc);
2753 gdbsig = SIGBUS;
2754 break;
2755 case EXCP_ILLEGAL:
2756 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2757 gdbsig = SIGILL;
2758 break;
2759 case EXCP_INT:
2760 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2761 break;
2762 case EXCP_DTLBMISS:
2763 case EXCP_ITLBMISS:
2764 qemu_log("\nTLB miss\n");
2765 break;
2766 case EXCP_RANGE:
2767 qemu_log("\nRange\n");
2768 gdbsig = SIGSEGV;
2769 break;
2770 case EXCP_SYSCALL:
2771 env->pc += 4; /* 0xc00; */
2772 env->gpr[11] = do_syscall(env,
2773 env->gpr[11], /* return value */
2774 env->gpr[3], /* r3 - r7 are params */
2775 env->gpr[4],
2776 env->gpr[5],
2777 env->gpr[6],
2778 env->gpr[7],
2779 env->gpr[8], 0, 0);
2780 break;
2781 case EXCP_FPE:
2782 qemu_log("\nFloating point error\n");
2783 break;
2784 case EXCP_TRAP:
2785 qemu_log("\nTrap\n");
2786 gdbsig = SIGTRAP;
2787 break;
2788 case EXCP_NR:
2789 qemu_log("\nNR\n");
2790 break;
2791 default:
2792 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2793 trapnr);
2794 cpu_dump_state(cs, stderr, fprintf, 0);
2795 gdbsig = TARGET_SIGILL;
2796 break;
2797 }
2798 if (gdbsig) {
2799 gdb_handlesig(cs, gdbsig);
2800 if (gdbsig != TARGET_SIGTRAP) {
2801 exit(1);
2802 }
2803 }
2804
2805 process_pending_signals(env);
2806 }
2807 }
2808
2809 #endif /* TARGET_OPENRISC */
2810
2811 #ifdef TARGET_SH4
2812 void cpu_loop(CPUSH4State *env)
2813 {
2814 CPUState *cs = CPU(sh_env_get_cpu(env));
2815 int trapnr, ret;
2816 target_siginfo_t info;
2817
2818 while (1) {
2819 trapnr = cpu_sh4_exec (env);
2820
2821 switch (trapnr) {
2822 case 0x160:
2823 env->pc += 2;
2824 ret = do_syscall(env,
2825 env->gregs[3],
2826 env->gregs[4],
2827 env->gregs[5],
2828 env->gregs[6],
2829 env->gregs[7],
2830 env->gregs[0],
2831 env->gregs[1],
2832 0, 0);
2833 env->gregs[0] = ret;
2834 break;
2835 case EXCP_INTERRUPT:
2836 /* just indicate that signals should be handled asap */
2837 break;
2838 case EXCP_DEBUG:
2839 {
2840 int sig;
2841
2842 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2843 if (sig)
2844 {
2845 info.si_signo = sig;
2846 info.si_errno = 0;
2847 info.si_code = TARGET_TRAP_BRKPT;
2848 queue_signal(env, info.si_signo, &info);
2849 }
2850 }
2851 break;
2852 case 0xa0:
2853 case 0xc0:
2854 info.si_signo = SIGSEGV;
2855 info.si_errno = 0;
2856 info.si_code = TARGET_SEGV_MAPERR;
2857 info._sifields._sigfault._addr = env->tea;
2858 queue_signal(env, info.si_signo, &info);
2859 break;
2860
2861 default:
2862 printf ("Unhandled trap: 0x%x\n", trapnr);
2863 cpu_dump_state(cs, stderr, fprintf, 0);
2864 exit (1);
2865 }
2866 process_pending_signals (env);
2867 }
2868 }
2869 #endif
2870
2871 #ifdef TARGET_CRIS
2872 void cpu_loop(CPUCRISState *env)
2873 {
2874 CPUState *cs = CPU(cris_env_get_cpu(env));
2875 int trapnr, ret;
2876 target_siginfo_t info;
2877
2878 while (1) {
2879 trapnr = cpu_cris_exec (env);
2880 switch (trapnr) {
2881 case 0xaa:
2882 {
2883 info.si_signo = SIGSEGV;
2884 info.si_errno = 0;
2885 /* XXX: check env->error_code */
2886 info.si_code = TARGET_SEGV_MAPERR;
2887 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2888 queue_signal(env, info.si_signo, &info);
2889 }
2890 break;
2891 case EXCP_INTERRUPT:
2892 /* just indicate that signals should be handled asap */
2893 break;
2894 case EXCP_BREAK:
2895 ret = do_syscall(env,
2896 env->regs[9],
2897 env->regs[10],
2898 env->regs[11],
2899 env->regs[12],
2900 env->regs[13],
2901 env->pregs[7],
2902 env->pregs[11],
2903 0, 0);
2904 env->regs[10] = ret;
2905 break;
2906 case EXCP_DEBUG:
2907 {
2908 int sig;
2909
2910 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2911 if (sig)
2912 {
2913 info.si_signo = sig;
2914 info.si_errno = 0;
2915 info.si_code = TARGET_TRAP_BRKPT;
2916 queue_signal(env, info.si_signo, &info);
2917 }
2918 }
2919 break;
2920 default:
2921 printf ("Unhandled trap: 0x%x\n", trapnr);
2922 cpu_dump_state(cs, stderr, fprintf, 0);
2923 exit (1);
2924 }
2925 process_pending_signals (env);
2926 }
2927 }
2928 #endif
2929
2930 #ifdef TARGET_MICROBLAZE
2931 void cpu_loop(CPUMBState *env)
2932 {
2933 CPUState *cs = CPU(mb_env_get_cpu(env));
2934 int trapnr, ret;
2935 target_siginfo_t info;
2936
2937 while (1) {
2938 trapnr = cpu_mb_exec (env);
2939 switch (trapnr) {
2940 case 0xaa:
2941 {
2942 info.si_signo = SIGSEGV;
2943 info.si_errno = 0;
2944 /* XXX: check env->error_code */
2945 info.si_code = TARGET_SEGV_MAPERR;
2946 info._sifields._sigfault._addr = 0;
2947 queue_signal(env, info.si_signo, &info);
2948 }
2949 break;
2950 case EXCP_INTERRUPT:
2951 /* just indicate that signals should be handled asap */
2952 break;
2953 case EXCP_BREAK:
2954 /* Return address is 4 bytes after the call. */
2955 env->regs[14] += 4;
2956 env->sregs[SR_PC] = env->regs[14];
2957 ret = do_syscall(env,
2958 env->regs[12],
2959 env->regs[5],
2960 env->regs[6],
2961 env->regs[7],
2962 env->regs[8],
2963 env->regs[9],
2964 env->regs[10],
2965 0, 0);
2966 env->regs[3] = ret;
2967 break;
2968 case EXCP_HW_EXCP:
2969 env->regs[17] = env->sregs[SR_PC] + 4;
2970 if (env->iflags & D_FLAG) {
2971 env->sregs[SR_ESR] |= 1 << 12;
2972 env->sregs[SR_PC] -= 4;
2973 /* FIXME: if branch was immed, replay the imm as well. */
2974 }
2975
2976 env->iflags &= ~(IMM_FLAG | D_FLAG);
2977
2978 switch (env->sregs[SR_ESR] & 31) {
2979 case ESR_EC_DIVZERO:
2980 info.si_signo = SIGFPE;
2981 info.si_errno = 0;
2982 info.si_code = TARGET_FPE_FLTDIV;
2983 info._sifields._sigfault._addr = 0;
2984 queue_signal(env, info.si_signo, &info);
2985 break;
2986 case ESR_EC_FPU:
2987 info.si_signo = SIGFPE;
2988 info.si_errno = 0;
2989 if (env->sregs[SR_FSR] & FSR_IO) {
2990 info.si_code = TARGET_FPE_FLTINV;
2991 }
2992 if (env->sregs[SR_FSR] & FSR_DZ) {
2993 info.si_code = TARGET_FPE_FLTDIV;
2994 }
2995 info._sifields._sigfault._addr = 0;
2996 queue_signal(env, info.si_signo, &info);
2997 break;
2998 default:
2999 printf ("Unhandled hw-exception: 0x%x\n",
3000 env->sregs[SR_ESR] & ESR_EC_MASK);
3001 cpu_dump_state(cs, stderr, fprintf, 0);
3002 exit (1);
3003 break;
3004 }
3005 break;
3006 case EXCP_DEBUG:
3007 {
3008 int sig;
3009
3010 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3011 if (sig)
3012 {
3013 info.si_signo = sig;
3014 info.si_errno = 0;
3015 info.si_code = TARGET_TRAP_BRKPT;
3016 queue_signal(env, info.si_signo, &info);
3017 }
3018 }
3019 break;
3020 default:
3021 printf ("Unhandled trap: 0x%x\n", trapnr);
3022 cpu_dump_state(cs, stderr, fprintf, 0);
3023 exit (1);
3024 }
3025 process_pending_signals (env);
3026 }
3027 }
3028 #endif
3029
3030 #ifdef TARGET_M68K
3031
3032 void cpu_loop(CPUM68KState *env)
3033 {
3034 CPUState *cs = CPU(m68k_env_get_cpu(env));
3035 int trapnr;
3036 unsigned int n;
3037 target_siginfo_t info;
3038 TaskState *ts = cs->opaque;
3039
3040 for(;;) {
3041 trapnr = cpu_m68k_exec(env);
3042 switch(trapnr) {
3043 case EXCP_ILLEGAL:
3044 {
3045 if (ts->sim_syscalls) {
3046 uint16_t nr;
3047 nr = lduw(env->pc + 2);
3048 env->pc += 4;
3049 do_m68k_simcall(env, nr);
3050 } else {
3051 goto do_sigill;
3052 }
3053 }
3054 break;
3055 case EXCP_HALT_INSN:
3056 /* Semihosing syscall. */
3057 env->pc += 4;
3058 do_m68k_semihosting(env, env->dregs[0]);
3059 break;
3060 case EXCP_LINEA:
3061 case EXCP_LINEF:
3062 case EXCP_UNSUPPORTED:
3063 do_sigill:
3064 info.si_signo = SIGILL;
3065 info.si_errno = 0;
3066 info.si_code = TARGET_ILL_ILLOPN;
3067 info._sifields._sigfault._addr = env->pc;
3068 queue_signal(env, info.si_signo, &info);
3069 break;
3070 case EXCP_TRAP0:
3071 {
3072 ts->sim_syscalls = 0;
3073 n = env->dregs[0];
3074 env->pc += 2;
3075 env->dregs[0] = do_syscall(env,
3076 n,
3077 env->dregs[1],
3078 env->dregs[2],
3079 env->dregs[3],
3080 env->dregs[4],
3081 env->dregs[5],
3082 env->aregs[0],
3083 0, 0);
3084 }
3085 break;
3086 case EXCP_INTERRUPT:
3087 /* just indicate that signals should be handled asap */
3088 break;
3089 case EXCP_ACCESS:
3090 {
3091 info.si_signo = SIGSEGV;
3092 info.si_errno = 0;
3093 /* XXX: check env->error_code */
3094 info.si_code = TARGET_SEGV_MAPERR;
3095 info._sifields._sigfault._addr = env->mmu.ar;
3096 queue_signal(env, info.si_signo, &info);
3097 }
3098 break;
3099 case EXCP_DEBUG:
3100 {
3101 int sig;
3102
3103 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3104 if (sig)
3105 {
3106 info.si_signo = sig;
3107 info.si_errno = 0;
3108 info.si_code = TARGET_TRAP_BRKPT;
3109 queue_signal(env, info.si_signo, &info);
3110 }
3111 }
3112 break;
3113 default:
3114 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
3115 trapnr);
3116 cpu_dump_state(cs, stderr, fprintf, 0);
3117 abort();
3118 }
3119 process_pending_signals(env);
3120 }
3121 }
3122 #endif /* TARGET_M68K */
3123
3124 #ifdef TARGET_ALPHA
3125 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3126 {
3127 target_ulong addr, val, tmp;
3128 target_siginfo_t info;
3129 int ret = 0;
3130
3131 addr = env->lock_addr;
3132 tmp = env->lock_st_addr;
3133 env->lock_addr = -1;
3134 env->lock_st_addr = 0;
3135
3136 start_exclusive();
3137 mmap_lock();
3138
3139 if (addr == tmp) {
3140 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3141 goto do_sigsegv;
3142 }
3143
3144 if (val == env->lock_value) {
3145 tmp = env->ir[reg];
3146 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3147 goto do_sigsegv;
3148 }
3149 ret = 1;
3150 }
3151 }
3152 env->ir[reg] = ret;
3153 env->pc += 4;
3154
3155 mmap_unlock();
3156 end_exclusive();
3157 return;
3158
3159 do_sigsegv:
3160 mmap_unlock();
3161 end_exclusive();
3162
3163 info.si_signo = TARGET_SIGSEGV;
3164 info.si_errno = 0;
3165 info.si_code = TARGET_SEGV_MAPERR;
3166 info._sifields._sigfault._addr = addr;
3167 queue_signal(env, TARGET_SIGSEGV, &info);
3168 }
3169
3170 void cpu_loop(CPUAlphaState *env)
3171 {
3172 CPUState *cs = CPU(alpha_env_get_cpu(env));
3173 int trapnr;
3174 target_siginfo_t info;
3175 abi_long sysret;
3176
3177 while (1) {
3178 trapnr = cpu_alpha_exec (env);
3179
3180 /* All of the traps imply a transition through PALcode, which
3181 implies an REI instruction has been executed. Which means
3182 that the intr_flag should be cleared. */
3183 env->intr_flag = 0;
3184
3185 switch (trapnr) {
3186 case EXCP_RESET:
3187 fprintf(stderr, "Reset requested. Exit\n");
3188 exit(1);
3189 break;
3190 case EXCP_MCHK:
3191 fprintf(stderr, "Machine check exception. Exit\n");
3192 exit(1);
3193 break;
3194 case EXCP_SMP_INTERRUPT:
3195 case EXCP_CLK_INTERRUPT:
3196 case EXCP_DEV_INTERRUPT:
3197 fprintf(stderr, "External interrupt. Exit\n");
3198 exit(1);
3199 break;
3200 case EXCP_MMFAULT:
3201 env->lock_addr = -1;
3202 info.si_signo = TARGET_SIGSEGV;
3203 info.si_errno = 0;
3204 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3205 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3206 info._sifields._sigfault._addr = env->trap_arg0;
3207 queue_signal(env, info.si_signo, &info);
3208 break;
3209 case EXCP_UNALIGN:
3210 env->lock_addr = -1;
3211 info.si_signo = TARGET_SIGBUS;
3212 info.si_errno = 0;
3213 info.si_code = TARGET_BUS_ADRALN;
3214 info._sifields._sigfault._addr = env->trap_arg0;
3215 queue_signal(env, info.si_signo, &info);
3216 break;
3217 case EXCP_OPCDEC:
3218 do_sigill:
3219 env->lock_addr = -1;
3220 info.si_signo = TARGET_SIGILL;
3221 info.si_errno = 0;
3222 info.si_code = TARGET_ILL_ILLOPC;
3223 info._sifields._sigfault._addr = env->pc;
3224 queue_signal(env, info.si_signo, &info);
3225 break;
3226 case EXCP_ARITH:
3227 env->lock_addr = -1;
3228 info.si_signo = TARGET_SIGFPE;
3229 info.si_errno = 0;
3230 info.si_code = TARGET_FPE_FLTINV;
3231 info._sifields._sigfault._addr = env->pc;
3232 queue_signal(env, info.si_signo, &info);
3233 break;
3234 case EXCP_FEN:
3235 /* No-op. Linux simply re-enables the FPU. */
3236 break;
3237 case EXCP_CALL_PAL:
3238 env->lock_addr = -1;
3239 switch (env->error_code) {
3240 case 0x80:
3241 /* BPT */
3242 info.si_signo = TARGET_SIGTRAP;
3243 info.si_errno = 0;
3244 info.si_code = TARGET_TRAP_BRKPT;
3245 info._sifields._sigfault._addr = env->pc;
3246 queue_signal(env, info.si_signo, &info);
3247 break;
3248 case 0x81:
3249 /* BUGCHK */
3250 info.si_signo = TARGET_SIGTRAP;
3251 info.si_errno = 0;
3252 info.si_code = 0;
3253 info._sifields._sigfault._addr = env->pc;
3254 queue_signal(env, info.si_signo, &info);
3255 break;
3256 case 0x83:
3257 /* CALLSYS */
3258 trapnr = env->ir[IR_V0];
3259 sysret = do_syscall(env, trapnr,
3260 env->ir[IR_A0], env->ir[IR_A1],
3261 env->ir[IR_A2], env->ir[IR_A3],
3262 env->ir[IR_A4], env->ir[IR_A5],
3263 0, 0);
3264 if (trapnr == TARGET_NR_sigreturn
3265 || trapnr == TARGET_NR_rt_sigreturn) {
3266 break;
3267 }
3268 /* Syscall writes 0 to V0 to bypass error check, similar
3269 to how this is handled internal to Linux kernel.
3270 (Ab)use trapnr temporarily as boolean indicating error. */
3271 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3272 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3273 env->ir[IR_A3] = trapnr;
3274 break;
3275 case 0x86:
3276 /* IMB */
3277 /* ??? We can probably elide the code using page_unprotect
3278 that is checking for self-modifying code. Instead we
3279 could simply call tb_flush here. Until we work out the
3280 changes required to turn off the extra write protection,
3281 this can be a no-op. */
3282 break;
3283 case 0x9E:
3284 /* RDUNIQUE */
3285 /* Handled in the translator for usermode. */
3286 abort();
3287 case 0x9F:
3288 /* WRUNIQUE */
3289 /* Handled in the translator for usermode. */
3290 abort();
3291 case 0xAA:
3292 /* GENTRAP */
3293 info.si_signo = TARGET_SIGFPE;
3294 switch (env->ir[IR_A0]) {
3295 case TARGET_GEN_INTOVF:
3296 info.si_code = TARGET_FPE_INTOVF;
3297 break;
3298 case TARGET_GEN_INTDIV:
3299 info.si_code = TARGET_FPE_INTDIV;
3300 break;
3301 case TARGET_GEN_FLTOVF:
3302 info.si_code = TARGET_FPE_FLTOVF;
3303 break;
3304 case TARGET_GEN_FLTUND:
3305 info.si_code = TARGET_FPE_FLTUND;
3306 break;
3307 case TARGET_GEN_FLTINV:
3308 info.si_code = TARGET_FPE_FLTINV;
3309 break;
3310 case TARGET_GEN_FLTINE:
3311 info.si_code = TARGET_FPE_FLTRES;
3312 break;
3313 case TARGET_GEN_ROPRAND:
3314 info.si_code = 0;
3315 break;
3316 default:
3317 info.si_signo = TARGET_SIGTRAP;
3318 info.si_code = 0;
3319 break;
3320 }
3321 info.si_errno = 0;
3322 info._sifields._sigfault._addr = env->pc;
3323 queue_signal(env, info.si_signo, &info);
3324 break;
3325 default:
3326 goto do_sigill;
3327 }
3328 break;
3329 case EXCP_DEBUG:
3330 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3331 if (info.si_signo) {
3332 env->lock_addr = -1;
3333 info.si_errno = 0;
3334 info.si_code = TARGET_TRAP_BRKPT;
3335 queue_signal(env, info.si_signo, &info);
3336 }
3337 break;
3338 case EXCP_STL_C:
3339 case EXCP_STQ_C:
3340 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3341 break;
3342 case EXCP_INTERRUPT:
3343 /* Just indicate that signals should be handled asap. */
3344 break;
3345 default:
3346 printf ("Unhandled trap: 0x%x\n", trapnr);
3347 cpu_dump_state(cs, stderr, fprintf, 0);
3348 exit (1);
3349 }
3350 process_pending_signals (env);
3351 }
3352 }
3353 #endif /* TARGET_ALPHA */
3354
3355 #ifdef TARGET_S390X
3356 void cpu_loop(CPUS390XState *env)
3357 {
3358 CPUState *cs = CPU(s390_env_get_cpu(env));
3359 int trapnr, n, sig;
3360 target_siginfo_t info;
3361 target_ulong addr;
3362
3363 while (1) {
3364 trapnr = cpu_s390x_exec(env);
3365 switch (trapnr) {
3366 case EXCP_INTERRUPT:
3367 /* Just indicate that signals should be handled asap. */
3368 break;
3369
3370 case EXCP_SVC:
3371 n = env->int_svc_code;
3372 if (!n) {
3373 /* syscalls > 255 */
3374 n = env->regs[1];
3375 }
3376 env->psw.addr += env->int_svc_ilen;
3377 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3378 env->regs[4], env->regs[5],
3379 env->regs[6], env->regs[7], 0, 0);
3380 break;
3381
3382 case EXCP_DEBUG:
3383 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3384 if (sig) {
3385 n = TARGET_TRAP_BRKPT;
3386 goto do_signal_pc;
3387 }
3388 break;
3389 case EXCP_PGM:
3390 n = env->int_pgm_code;
3391 switch (n) {
3392 case PGM_OPERATION:
3393 case PGM_PRIVILEGED:
3394 sig = SIGILL;
3395 n = TARGET_ILL_ILLOPC;
3396 goto do_signal_pc;
3397 case PGM_PROTECTION:
3398 case PGM_ADDRESSING:
3399 sig = SIGSEGV;
3400 /* XXX: check env->error_code */
3401 n = TARGET_SEGV_MAPERR;
3402 addr = env->__excp_addr;
3403 goto do_signal;
3404 case PGM_EXECUTE:
3405 case PGM_SPECIFICATION:
3406 case PGM_SPECIAL_OP:
3407 case PGM_OPERAND:
3408 do_sigill_opn:
3409 sig = SIGILL;
3410 n = TARGET_ILL_ILLOPN;
3411 goto do_signal_pc;
3412
3413 case PGM_FIXPT_OVERFLOW:
3414 sig = SIGFPE;
3415 n = TARGET_FPE_INTOVF;
3416 goto do_signal_pc;
3417 case PGM_FIXPT_DIVIDE:
3418 sig = SIGFPE;
3419 n = TARGET_FPE_INTDIV;
3420 goto do_signal_pc;
3421
3422 case PGM_DATA:
3423 n = (env->fpc >> 8) & 0xff;
3424 if (n == 0xff) {
3425 /* compare-and-trap */
3426 goto do_sigill_opn;
3427 } else {
3428 /* An IEEE exception, simulated or otherwise. */
3429 if (n & 0x80) {
3430 n = TARGET_FPE_FLTINV;
3431 } else if (n & 0x40) {
3432 n = TARGET_FPE_FLTDIV;
3433 } else if (n & 0x20) {
3434 n = TARGET_FPE_FLTOVF;
3435 } else if (n & 0x10) {
3436 n = TARGET_FPE_FLTUND;
3437 } else if (n & 0x08) {
3438 n = TARGET_FPE_FLTRES;
3439 } else {
3440 /* ??? Quantum exception; BFP, DFP error. */
3441 goto do_sigill_opn;
3442 }
3443 sig = SIGFPE;
3444 goto do_signal_pc;
3445 }
3446
3447 default:
3448 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3449 cpu_dump_state(cs, stderr, fprintf, 0);
3450 exit(1);
3451 }
3452 break;
3453
3454 do_signal_pc:
3455 addr = env->psw.addr;
3456 do_signal:
3457 info.si_signo = sig;
3458 info.si_errno = 0;
3459 info.si_code = n;
3460 info._sifields._sigfault._addr = addr;
3461 queue_signal(env, info.si_signo, &info);
3462 break;
3463
3464 default:
3465 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3466 cpu_dump_state(cs, stderr, fprintf, 0);
3467 exit(1);
3468 }
3469 process_pending_signals (env);
3470 }
3471 }
3472
3473 #endif /* TARGET_S390X */
3474
3475 THREAD CPUState *thread_cpu;
3476
3477 void task_settid(TaskState *ts)
3478 {
3479 if (ts->ts_tid == 0) {
3480 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3481 }
3482 }
3483
3484 void stop_all_tasks(void)
3485 {
3486 /*
3487 * We trust that when using NPTL, start_exclusive()
3488 * handles thread stopping correctly.
3489 */
3490 start_exclusive();
3491 }
3492
3493 /* Assumes contents are already zeroed. */
3494 void init_task_state(TaskState *ts)
3495 {
3496 int i;
3497
3498 ts->used = 1;
3499 ts->first_free = ts->sigqueue_table;
3500 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3501 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3502 }
3503 ts->sigqueue_table[i].next = NULL;
3504 }
3505
3506 CPUArchState *cpu_copy(CPUArchState *env)
3507 {
3508 CPUState *cpu = ENV_GET_CPU(env);
3509 CPUArchState *new_env = cpu_init(cpu_model);
3510 CPUState *new_cpu = ENV_GET_CPU(new_env);
3511 #if defined(TARGET_HAS_ICE)
3512 CPUBreakpoint *bp;
3513 CPUWatchpoint *wp;
3514 #endif
3515
3516 /* Reset non arch specific state */
3517 cpu_reset(new_cpu);
3518
3519 memcpy(new_env, env, sizeof(CPUArchState));
3520
3521 /* Clone all break/watchpoints.
3522 Note: Once we support ptrace with hw-debug register access, make sure
3523 BP_CPU break/watchpoints are handled correctly on clone. */
3524 QTAILQ_INIT(&cpu->breakpoints);
3525 QTAILQ_INIT(&cpu->watchpoints);
3526 #if defined(TARGET_HAS_ICE)
3527 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3528 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3529 }
3530 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3531 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3532 }
3533 #endif
3534
3535 return new_env;
3536 }
3537
3538 static void handle_arg_help(const char *arg)
3539 {
3540 usage();
3541 }
3542
3543 static void handle_arg_log(const char *arg)
3544 {
3545 int mask;
3546
3547 mask = qemu_str_to_log_mask(arg);
3548 if (!mask) {
3549 qemu_print_log_usage(stdout);
3550 exit(1);
3551 }
3552 qemu_set_log(mask);
3553 }
3554
3555 static void handle_arg_log_filename(const char *arg)
3556 {
3557 qemu_set_log_filename(arg);
3558 }
3559
3560 static void handle_arg_set_env(const char *arg)
3561 {
3562 char *r, *p, *token;
3563 r = p = strdup(arg);
3564 while ((token = strsep(&p, ",")) != NULL) {
3565 if (envlist_setenv(envlist, token) != 0) {
3566 usage();
3567 }
3568 }
3569 free(r);
3570 }
3571
3572 static void handle_arg_unset_env(const char *arg)
3573 {
3574 char *r, *p, *token;
3575 r = p = strdup(arg);
3576 while ((token = strsep(&p, ",")) != NULL) {
3577 if (envlist_unsetenv(envlist, token) != 0) {
3578 usage();
3579 }
3580 }
3581 free(r);
3582 }
3583
3584 static void handle_arg_argv0(const char *arg)
3585 {
3586 argv0 = strdup(arg);
3587 }
3588
3589 static void handle_arg_stack_size(const char *arg)
3590 {
3591 char *p;
3592 guest_stack_size = strtoul(arg, &p, 0);
3593 if (guest_stack_size == 0) {
3594 usage();
3595 }
3596
3597 if (*p == 'M') {
3598 guest_stack_size *= 1024 * 1024;
3599 } else if (*p == 'k' || *p == 'K') {
3600 guest_stack_size *= 1024;
3601 }
3602 }
3603
3604 static void handle_arg_ld_prefix(const char *arg)
3605 {
3606 interp_prefix = strdup(arg);
3607 }
3608
3609 static void handle_arg_pagesize(const char *arg)
3610 {
3611 qemu_host_page_size = atoi(arg);
3612 if (qemu_host_page_size == 0 ||
3613 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3614 fprintf(stderr, "page size must be a power of two\n");
3615 exit(1);
3616 }
3617 }
3618
3619 static void handle_arg_randseed(const char *arg)
3620 {
3621 unsigned long long seed;
3622
3623 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3624 fprintf(stderr, "Invalid seed number: %s\n", arg);
3625 exit(1);
3626 }
3627 srand(seed);
3628 }
3629
3630 static void handle_arg_gdb(const char *arg)
3631 {
3632 gdbstub_port = atoi(arg);
3633 }
3634
3635 static void handle_arg_uname(const char *arg)
3636 {
3637 qemu_uname_release = strdup(arg);
3638 }
3639
3640 static void handle_arg_cpu(const char *arg)
3641 {
3642 cpu_model = strdup(arg);
3643 if (cpu_model == NULL || is_help_option(cpu_model)) {
3644 /* XXX: implement xxx_cpu_list for targets that still miss it */
3645 #if defined(cpu_list_id)
3646 cpu_list_id(stdout, &fprintf, "");
3647 #elif defined(cpu_list)
3648 cpu_list(stdout, &fprintf); /* deprecated */
3649 #else
3650 /* TODO: add cpu selection for alpha, microblaze, unicore32, s390x. */
3651 printf("Target ignores cpu selection\n");
3652 #endif
3653 exit(1);
3654 }
3655 }
3656
3657 #if defined(CONFIG_USE_GUEST_BASE)
3658 static void handle_arg_guest_base(const char *arg)
3659 {
3660 guest_base = strtol(arg, NULL, 0);
3661 have_guest_base = 1;
3662 }
3663
3664 static void handle_arg_reserved_va(const char *arg)
3665 {
3666 char *p;
3667 int shift = 0;
3668 reserved_va = strtoul(arg, &p, 0);
3669 switch (*p) {
3670 case 'k':
3671 case 'K':
3672 shift = 10;
3673 break;
3674 case 'M':
3675 shift = 20;
3676 break;
3677 case 'G':
3678 shift = 30;
3679 break;
3680 }
3681 if (shift) {
3682 unsigned long unshifted = reserved_va;
3683 p++;
3684 reserved_va <<= shift;
3685 if (((reserved_va >> shift) != unshifted)
3686 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3687 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3688 #endif
3689 ) {
3690 fprintf(stderr, "Reserved virtual address too big\n");
3691 exit(1);
3692 }
3693 }
3694 if (*p) {
3695 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3696 exit(1);
3697 }
3698 }
3699 #endif
3700
3701 static void handle_arg_singlestep(const char *arg)
3702 {
3703 singlestep = 1;
3704 }
3705
3706 static void handle_arg_strace(const char *arg)
3707 {
3708 do_strace = 1;
3709 }
3710
3711 static void handle_arg_version(const char *arg)
3712 {
3713 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3714 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3715 exit(0);
3716 }
3717
3718 struct qemu_argument {
3719 const char *argv;
3720 const char *env;
3721 bool has_arg;
3722 void (*handle_opt)(const char *arg);
3723 const char *example;
3724 const char *help;
3725 };
3726
3727 static const struct qemu_argument arg_table[] = {
3728 {"h", "", false, handle_arg_help,
3729 "", "print this help"},
3730 {"g", "QEMU_GDB", true, handle_arg_gdb,
3731 "port", "wait gdb connection to 'port'"},
3732 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3733 "path", "set the elf interpreter prefix to 'path'"},
3734 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3735 "size", "set the stack size to 'size' bytes"},
3736 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3737 "model", "select CPU (-cpu help for list)"},
3738 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3739 "var=value", "sets targets environment variable (see below)"},
3740 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3741 "var", "unsets targets environment variable (see below)"},
3742 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3743 "argv0", "forces target process argv[0] to be 'argv0'"},
3744 {"r", "QEMU_UNAME", true, handle_arg_uname,
3745 "uname", "set qemu uname release string to 'uname'"},
3746 #if defined(CONFIG_USE_GUEST_BASE)
3747 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3748 "address", "set guest_base address to 'address'"},
3749 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3750 "size", "reserve 'size' bytes for guest virtual address space"},
3751 #endif
3752 {"d", "QEMU_LOG", true, handle_arg_log,
3753 "item[,...]", "enable logging of specified items "
3754 "(use '-d help' for a list of items)"},
3755 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3756 "logfile", "write logs to 'logfile' (default stderr)"},
3757 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3758 "pagesize", "set the host page size to 'pagesize'"},
3759 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3760 "", "run in singlestep mode"},
3761 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3762 "", "log system calls"},
3763 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3764 "", "Seed for pseudo-random number generator"},
3765 {"version", "QEMU_VERSION", false, handle_arg_version,
3766 "", "display version information and exit"},
3767 {NULL, NULL, false, NULL, NULL, NULL}
3768 };
3769
3770 static void QEMU_NORETURN usage(void)
3771 {
3772 const struct qemu_argument *arginfo;
3773 int maxarglen;
3774 int maxenvlen;
3775
3776 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3777 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3778 "\n"
3779 "Options and associated environment variables:\n"
3780 "\n");
3781
3782 /* Calculate column widths. We must always have at least enough space
3783 * for the column header.
3784 */
3785 maxarglen = strlen("Argument");
3786 maxenvlen = strlen("Env-variable");
3787
3788 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3789 int arglen = strlen(arginfo->argv);
3790 if (arginfo->has_arg) {
3791 arglen += strlen(arginfo->example) + 1;
3792 }
3793 if (strlen(arginfo->env) > maxenvlen) {
3794 maxenvlen = strlen(arginfo->env);
3795 }
3796 if (arglen > maxarglen) {
3797 maxarglen = arglen;
3798 }
3799 }
3800
3801 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3802 maxenvlen, "Env-variable");
3803
3804 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3805 if (arginfo->has_arg) {
3806 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3807 (int)(maxarglen - strlen(arginfo->argv) - 1),
3808 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3809 } else {
3810 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3811 maxenvlen, arginfo->env,
3812 arginfo->help);
3813 }
3814 }
3815
3816 printf("\n"
3817 "Defaults:\n"
3818 "QEMU_LD_PREFIX = %s\n"
3819 "QEMU_STACK_SIZE = %ld byte\n",
3820 interp_prefix,
3821 guest_stack_size);
3822
3823 printf("\n"
3824 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3825 "QEMU_UNSET_ENV environment variables to set and unset\n"
3826 "environment variables for the target process.\n"
3827 "It is possible to provide several variables by separating them\n"
3828 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3829 "provide the -E and -U options multiple times.\n"
3830 "The following lines are equivalent:\n"
3831 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3832 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3833 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3834 "Note that if you provide several changes to a single variable\n"
3835 "the last change will stay in effect.\n");
3836
3837 exit(1);
3838 }
3839
3840 static int parse_args(int argc, char **argv)
3841 {
3842 const char *r;
3843 int optind;
3844 const struct qemu_argument *arginfo;
3845
3846 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3847 if (arginfo->env == NULL) {
3848 continue;
3849 }
3850
3851 r = getenv(arginfo->env);
3852 if (r != NULL) {
3853 arginfo->handle_opt(r);
3854 }
3855 }
3856
3857 optind = 1;
3858 for (;;) {
3859 if (optind >= argc) {
3860 break;
3861 }
3862 r = argv[optind];
3863 if (r[0] != '-') {
3864 break;
3865 }
3866 optind++;
3867 r++;
3868 if (!strcmp(r, "-")) {
3869 break;
3870 }
3871
3872 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3873 if (!strcmp(r, arginfo->argv)) {
3874 if (arginfo->has_arg) {
3875 if (optind >= argc) {
3876 usage();
3877 }
3878 arginfo->handle_opt(argv[optind]);
3879 optind++;
3880 } else {
3881 arginfo->handle_opt(NULL);
3882 }
3883 break;
3884 }
3885 }
3886
3887 /* no option matched the current argv */
3888 if (arginfo->handle_opt == NULL) {
3889 usage();
3890 }
3891 }
3892
3893 if (optind >= argc) {
3894 usage();
3895 }
3896
3897 filename = argv[optind];
3898 exec_path = argv[optind];
3899
3900 return optind;
3901 }
3902
3903 int main(int argc, char **argv)
3904 {
3905 struct target_pt_regs regs1, *regs = &regs1;
3906 struct image_info info1, *info = &info1;
3907 struct linux_binprm bprm;
3908 TaskState *ts;
3909 CPUArchState *env;
3910 CPUState *cpu;
3911 int optind;
3912 char **target_environ, **wrk;
3913 char **target_argv;
3914 int target_argc;
3915 int i;
3916 int ret;
3917 int execfd;
3918
3919 module_call_init(MODULE_INIT_QOM);
3920
3921 if ((envlist = envlist_create()) == NULL) {
3922 (void) fprintf(stderr, "Unable to allocate envlist\n");
3923 exit(1);
3924 }
3925
3926 /* add current environment into the list */
3927 for (wrk = environ; *wrk != NULL; wrk++) {
3928 (void) envlist_setenv(envlist, *wrk);
3929 }
3930
3931 /* Read the stack limit from the kernel. If it's "unlimited",
3932 then we can do little else besides use the default. */
3933 {
3934 struct rlimit lim;
3935 if (getrlimit(RLIMIT_STACK, &lim) == 0
3936 && lim.rlim_cur != RLIM_INFINITY
3937 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3938 guest_stack_size = lim.rlim_cur;
3939 }
3940 }
3941
3942 cpu_model = NULL;
3943 #if defined(cpudef_setup)
3944 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3945 #endif
3946
3947 srand(time(NULL));
3948
3949 optind = parse_args(argc, argv);
3950
3951 /* Zero out regs */
3952 memset(regs, 0, sizeof(struct target_pt_regs));
3953
3954 /* Zero out image_info */
3955 memset(info, 0, sizeof(struct image_info));
3956
3957 memset(&bprm, 0, sizeof (bprm));
3958
3959 /* Scan interp_prefix dir for replacement files. */
3960 init_paths(interp_prefix);
3961
3962 init_qemu_uname_release();
3963
3964 if (cpu_model == NULL) {
3965 #if defined(TARGET_I386)
3966 #ifdef TARGET_X86_64
3967 cpu_model = "qemu64";
3968 #else
3969 cpu_model = "qemu32";
3970 #endif
3971 #elif defined(TARGET_ARM)
3972 cpu_model = "any";
3973 #elif defined(TARGET_UNICORE32)
3974 cpu_model = "any";
3975 #elif defined(TARGET_M68K)
3976 cpu_model = "any";
3977 #elif defined(TARGET_SPARC)
3978 #ifdef TARGET_SPARC64
3979 cpu_model = "TI UltraSparc II";
3980 #else
3981 cpu_model = "Fujitsu MB86904";
3982 #endif
3983 #elif defined(TARGET_MIPS)
3984 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3985 cpu_model = "20Kc";
3986 #else
3987 cpu_model = "24Kf";
3988 #endif
3989 #elif defined TARGET_OPENRISC
3990 cpu_model = "or1200";
3991 #elif defined(TARGET_PPC)
3992 # ifdef TARGET_PPC64
3993 cpu_model = "POWER7";
3994 # else
3995 cpu_model = "750";
3996 # endif
3997 #else
3998 cpu_model = "any";
3999 #endif
4000 }
4001 tcg_exec_init(0);
4002 cpu_exec_init_all();
4003 /* NOTE: we need to init the CPU at this stage to get
4004 qemu_host_page_size */
4005 env = cpu_init(cpu_model);
4006 if (!env) {
4007 fprintf(stderr, "Unable to find CPU definition\n");
4008 exit(1);
4009 }
4010 cpu = ENV_GET_CPU(env);
4011 cpu_reset(cpu);
4012
4013 thread_cpu = cpu;
4014
4015 if (getenv("QEMU_STRACE")) {
4016 do_strace = 1;
4017 }
4018
4019 if (getenv("QEMU_RAND_SEED")) {
4020 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4021 }
4022
4023 target_environ = envlist_to_environ(envlist, NULL);
4024 envlist_free(envlist);
4025
4026 #if defined(CONFIG_USE_GUEST_BASE)
4027 /*
4028 * Now that page sizes are configured in cpu_init() we can do
4029 * proper page alignment for guest_base.
4030 */
4031 guest_base = HOST_PAGE_ALIGN(guest_base);
4032
4033 if (reserved_va || have_guest_base) {
4034 guest_base = init_guest_space(guest_base, reserved_va, 0,
4035 have_guest_base);
4036 if (guest_base == (unsigned long)-1) {
4037 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4038 "space for use as guest address space (check your virtual "
4039 "memory ulimit setting or reserve less using -R option)\n",
4040 reserved_va);
4041 exit(1);
4042 }
4043
4044 if (reserved_va) {
4045 mmap_next_start = reserved_va;
4046 }
4047 }
4048 #endif /* CONFIG_USE_GUEST_BASE */
4049
4050 /*
4051 * Read in mmap_min_addr kernel parameter. This value is used
4052 * When loading the ELF image to determine whether guest_base
4053 * is needed. It is also used in mmap_find_vma.
4054 */
4055 {
4056 FILE *fp;
4057
4058 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4059 unsigned long tmp;
4060 if (fscanf(fp, "%lu", &tmp) == 1) {
4061 mmap_min_addr = tmp;
4062 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
4063 }
4064 fclose(fp);
4065 }
4066 }
4067
4068 /*
4069 * Prepare copy of argv vector for target.
4070 */
4071 target_argc = argc - optind;
4072 target_argv = calloc(target_argc + 1, sizeof (char *));
4073 if (target_argv == NULL) {
4074 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4075 exit(1);
4076 }
4077
4078 /*
4079 * If argv0 is specified (using '-0' switch) we replace
4080 * argv[0] pointer with the given one.
4081 */
4082 i = 0;
4083 if (argv0 != NULL) {
4084 target_argv[i++] = strdup(argv0);
4085 }
4086 for (; i < target_argc; i++) {
4087 target_argv[i] = strdup(argv[optind + i]);
4088 }
4089 target_argv[target_argc] = NULL;
4090
4091 ts = g_malloc0 (sizeof(TaskState));
4092 init_task_state(ts);
4093 /* build Task State */
4094 ts->info = info;
4095 ts->bprm = &bprm;
4096 cpu->opaque = ts;
4097 task_settid(ts);
4098
4099 execfd = qemu_getauxval(AT_EXECFD);
4100 if (execfd == 0) {
4101 execfd = open(filename, O_RDONLY);
4102 if (execfd < 0) {
4103 printf("Error while loading %s: %s\n", filename, strerror(errno));
4104 _exit(1);
4105 }
4106 }
4107
4108 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4109 info, &bprm);
4110 if (ret != 0) {
4111 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4112 _exit(1);
4113 }
4114
4115 for (wrk = target_environ; *wrk; wrk++) {
4116 free(*wrk);
4117 }
4118
4119 free(target_environ);
4120
4121 if (qemu_log_enabled()) {
4122 #if defined(CONFIG_USE_GUEST_BASE)
4123 qemu_log("guest_base 0x%" PRIxPTR "\n", guest_base);
4124 #endif
4125 log_page_dump();
4126
4127 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4128 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4129 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4130 info->start_code);
4131 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4132 info->start_data);
4133 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4134 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4135 info->start_stack);
4136 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4137 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4138 }
4139
4140 target_set_brk(info->brk);
4141 syscall_init();
4142 signal_init();
4143
4144 #if defined(CONFIG_USE_GUEST_BASE)
4145 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4146 generating the prologue until now so that the prologue can take
4147 the real value of GUEST_BASE into account. */
4148 tcg_prologue_init(&tcg_ctx);
4149 #endif
4150
4151 #if defined(TARGET_I386)
4152 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4153 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4154 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4155 env->cr[4] |= CR4_OSFXSR_MASK;
4156 env->hflags |= HF_OSFXSR_MASK;
4157 }
4158 #ifndef TARGET_ABI32
4159 /* enable 64 bit mode if possible */
4160 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4161 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4162 exit(1);
4163 }
4164 env->cr[4] |= CR4_PAE_MASK;
4165 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4166 env->hflags |= HF_LMA_MASK;
4167 #endif
4168
4169 /* flags setup : we activate the IRQs by default as in user mode */
4170 env->eflags |= IF_MASK;
4171
4172 /* linux register setup */
4173 #ifndef TARGET_ABI32
4174 env->regs[R_EAX] = regs->rax;
4175 env->regs[R_EBX] = regs->rbx;
4176 env->regs[R_ECX] = regs->rcx;
4177 env->regs[R_EDX] = regs->rdx;
4178 env->regs[R_ESI] = regs->rsi;
4179 env->regs[R_EDI] = regs->rdi;
4180 env->regs[R_EBP] = regs->rbp;
4181 env->regs[R_ESP] = regs->rsp;
4182 env->eip = regs->rip;
4183 #else
4184 env->regs[R_EAX] = regs->eax;
4185 env->regs[R_EBX] = regs->ebx;
4186 env->regs[R_ECX] = regs->ecx;
4187 env->regs[R_EDX] = regs->edx;
4188 env->regs[R_ESI] = regs->esi;
4189 env->regs[R_EDI] = regs->edi;
4190 env->regs[R_EBP] = regs->ebp;
4191 env->regs[R_ESP] = regs->esp;
4192 env->eip = regs->eip;
4193 #endif
4194
4195 /* linux interrupt setup */
4196 #ifndef TARGET_ABI32
4197 env->idt.limit = 511;
4198 #else
4199 env->idt.limit = 255;
4200 #endif
4201 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4202 PROT_READ|PROT_WRITE,
4203 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4204 idt_table = g2h(env->idt.base);
4205 set_idt(0, 0);
4206 set_idt(1, 0);
4207 set_idt(2, 0);
4208 set_idt(3, 3);
4209 set_idt(4, 3);
4210 set_idt(5, 0);
4211 set_idt(6, 0);
4212 set_idt(7, 0);
4213 set_idt(8, 0);
4214 set_idt(9, 0);
4215 set_idt(10, 0);
4216 set_idt(11, 0);
4217 set_idt(12, 0);
4218 set_idt(13, 0);
4219 set_idt(14, 0);
4220 set_idt(15, 0);
4221 set_idt(16, 0);
4222 set_idt(17, 0);
4223 set_idt(18, 0);
4224 set_idt(19, 0);
4225 set_idt(0x80, 3);
4226
4227 /* linux segment setup */
4228 {
4229 uint64_t *gdt_table;
4230 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4231 PROT_READ|PROT_WRITE,
4232 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4233 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4234 gdt_table = g2h(env->gdt.base);
4235 #ifdef TARGET_ABI32
4236 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4237 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4238 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4239 #else
4240 /* 64 bit code segment */
4241 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4242 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4243 DESC_L_MASK |
4244 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4245 #endif
4246 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4247 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4248 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4249 }
4250 cpu_x86_load_seg(env, R_CS, __USER_CS);
4251 cpu_x86_load_seg(env, R_SS, __USER_DS);
4252 #ifdef TARGET_ABI32
4253 cpu_x86_load_seg(env, R_DS, __USER_DS);
4254 cpu_x86_load_seg(env, R_ES, __USER_DS);
4255 cpu_x86_load_seg(env, R_FS, __USER_DS);
4256 cpu_x86_load_seg(env, R_GS, __USER_DS);
4257 /* This hack makes Wine work... */
4258 env->segs[R_FS].selector = 0;
4259 #else
4260 cpu_x86_load_seg(env, R_DS, 0);
4261 cpu_x86_load_seg(env, R_ES, 0);
4262 cpu_x86_load_seg(env, R_FS, 0);
4263 cpu_x86_load_seg(env, R_GS, 0);
4264 #endif
4265 #elif defined(TARGET_AARCH64)
4266 {
4267 int i;
4268
4269 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4270 fprintf(stderr,
4271 "The selected ARM CPU does not support 64 bit mode\n");
4272 exit(1);
4273 }
4274
4275 for (i = 0; i < 31; i++) {
4276 env->xregs[i] = regs->regs[i];
4277 }
4278 env->pc = regs->pc;
4279 env->xregs[31] = regs->sp;
4280 }
4281 #elif defined(TARGET_ARM)
4282 {
4283 int i;
4284 cpsr_write(env, regs->uregs[16], 0xffffffff);
4285 for(i = 0; i < 16; i++) {
4286 env->regs[i] = regs->uregs[i];
4287 }
4288 #ifdef TARGET_WORDS_BIGENDIAN
4289 /* Enable BE8. */
4290 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4291 && (info->elf_flags & EF_ARM_BE8)) {
4292 env->uncached_cpsr |= CPSR_E;
4293 env->signal_cpsr_e = CPSR_E;
4294 } else {
4295 if (arm_feature(env, ARM_FEATURE_V7)) {
4296 fprintf(stderr, "BE32 binaries only supported until ARMv6\n");
4297 exit(1);
4298 }
4299 env->cp15.c1_sys |= SCTLR_B;
4300 }
4301 #endif
4302 }
4303 #elif defined(TARGET_UNICORE32)
4304 {
4305 int i;
4306 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4307 for (i = 0; i < 32; i++) {
4308 env->regs[i] = regs->uregs[i];
4309 }
4310 }
4311 #elif defined(TARGET_SPARC)
4312 {
4313 int i;
4314 env->pc = regs->pc;
4315 env->npc = regs->npc;
4316 env->y = regs->y;
4317 for(i = 0; i < 8; i++)
4318 env->gregs[i] = regs->u_regs[i];
4319 for(i = 0; i < 8; i++)
4320 env->regwptr[i] = regs->u_regs[i + 8];
4321 }
4322 #elif defined(TARGET_PPC)
4323 {
4324 int i;
4325
4326 #if defined(TARGET_PPC64)
4327 #if defined(TARGET_ABI32)
4328 env->msr &= ~((target_ulong)1 << MSR_SF);
4329 #else
4330 env->msr |= (target_ulong)1 << MSR_SF;
4331 #endif
4332 #endif
4333 env->nip = regs->nip;
4334 for(i = 0; i < 32; i++) {
4335 env->gpr[i] = regs->gpr[i];
4336 }
4337 }
4338 #elif defined(TARGET_M68K)
4339 {
4340 env->pc = regs->pc;
4341 env->dregs[0] = regs->d0;
4342 env->dregs[1] = regs->d1;
4343 env->dregs[2] = regs->d2;
4344 env->dregs[3] = regs->d3;
4345 env->dregs[4] = regs->d4;
4346 env->dregs[5] = regs->d5;
4347 env->dregs[6] = regs->d6;
4348 env->dregs[7] = regs->d7;
4349 env->aregs[0] = regs->a0;
4350 env->aregs[1] = regs->a1;
4351 env->aregs[2] = regs->a2;
4352 env->aregs[3] = regs->a3;
4353 env->aregs[4] = regs->a4;
4354 env->aregs[5] = regs->a5;
4355 env->aregs[6] = regs->a6;
4356 env->aregs[7] = regs->usp;
4357 env->sr = regs->sr;
4358 ts->sim_syscalls = 1;
4359 }
4360 #elif defined(TARGET_MICROBLAZE)
4361 {
4362 env->regs[0] = regs->r0;
4363 env->regs[1] = regs->r1;
4364 env->regs[2] = regs->r2;
4365 env->regs[3] = regs->r3;
4366 env->regs[4] = regs->r4;
4367 env->regs[5] = regs->r5;
4368 env->regs[6] = regs->r6;
4369 env->regs[7] = regs->r7;
4370 env->regs[8] = regs->r8;
4371 env->regs[9] = regs->r9;
4372 env->regs[10] = regs->r10;
4373 env->regs[11] = regs->r11;
4374 env->regs[12] = regs->r12;
4375 env->regs[13] = regs->r13;
4376 env->regs[14] = regs->r14;
4377 env->regs[15] = regs->r15;
4378 env->regs[16] = regs->r16;
4379 env->regs[17] = regs->r17;
4380 env->regs[18] = regs->r18;
4381 env->regs[19] = regs->r19;
4382 env->regs[20] = regs->r20;
4383 env->regs[21] = regs->r21;
4384 env->regs[22] = regs->r22;
4385 env->regs[23] = regs->r23;
4386 env->regs[24] = regs->r24;
4387 env->regs[25] = regs->r25;
4388 env->regs[26] = regs->r26;
4389 env->regs[27] = regs->r27;
4390 env->regs[28] = regs->r28;
4391 env->regs[29] = regs->r29;
4392 env->regs[30] = regs->r30;
4393 env->regs[31] = regs->r31;
4394 env->sregs[SR_PC] = regs->pc;
4395 }
4396 #elif defined(TARGET_MIPS)
4397 {
4398 int i;
4399
4400 for(i = 0; i < 32; i++) {
4401 env->active_tc.gpr[i] = regs->regs[i];
4402 }
4403 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4404 if (regs->cp0_epc & 1) {
4405 env->hflags |= MIPS_HFLAG_M16;
4406 }
4407 }
4408 #elif defined(TARGET_OPENRISC)
4409 {
4410 int i;
4411
4412 for (i = 0; i < 32; i++) {
4413 env->gpr[i] = regs->gpr[i];
4414 }
4415
4416 env->sr = regs->sr;
4417 env->pc = regs->pc;
4418 }
4419 #elif defined(TARGET_SH4)
4420 {
4421 int i;
4422
4423 for(i = 0; i < 16; i++) {
4424 env->gregs[i] = regs->regs[i];
4425 }
4426 env->pc = regs->pc;
4427 }
4428 #elif defined(TARGET_ALPHA)
4429 {
4430 int i;
4431
4432 for(i = 0; i < 28; i++) {
4433 env->ir[i] = ((abi_ulong *)regs)[i];
4434 }
4435 env->ir[IR_SP] = regs->usp;
4436 env->pc = regs->pc;
4437 }
4438 #elif defined(TARGET_CRIS)
4439 {
4440 env->regs[0] = regs->r0;
4441 env->regs[1] = regs->r1;
4442 env->regs[2] = regs->r2;
4443 env->regs[3] = regs->r3;
4444 env->regs[4] = regs->r4;
4445 env->regs[5] = regs->r5;
4446 env->regs[6] = regs->r6;
4447 env->regs[7] = regs->r7;
4448 env->regs[8] = regs->r8;
4449 env->regs[9] = regs->r9;
4450 env->regs[10] = regs->r10;
4451 env->regs[11] = regs->r11;
4452 env->regs[12] = regs->r12;
4453 env->regs[13] = regs->r13;
4454 env->regs[14] = info->start_stack;
4455 env->regs[15] = regs->acr;
4456 env->pc = regs->erp;
4457 }
4458 #elif defined(TARGET_S390X)
4459 {
4460 int i;
4461 for (i = 0; i < 16; i++) {
4462 env->regs[i] = regs->gprs[i];
4463 }
4464 env->psw.mask = regs->psw.mask;
4465 env->psw.addr = regs->psw.addr;
4466 }
4467 #else
4468 #error unsupported target CPU
4469 #endif
4470
4471 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4472 ts->stack_base = info->start_stack;
4473 ts->heap_base = info->brk;
4474 /* This will be filled in on the first SYS_HEAPINFO call. */
4475 ts->heap_limit = 0;
4476 #endif
4477
4478 if (gdbstub_port) {
4479 if (gdbserver_start(gdbstub_port) < 0) {
4480 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4481 gdbstub_port);
4482 exit(1);
4483 }
4484 gdb_handlesig(cpu, 0);
4485 }
4486 cpu_loop(env);
4487 /* never exits */
4488 return 0;
4489 }
AR7 emulation for QEMU