hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "hw/hw.h"
  29 #include "trace.h"
  30 #include "qemu/timer.h"
  31 #include "hw/ppc/spapr.h"
  32 #include "hw/ppc/xics.h"
  33 #include "qemu/error-report.h"
  34 #include "qapi/visitor.h"
  35
  36 static int get_cpu_index_by_dt_id(int cpu_dt_id)
  37 {
  38     PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
  39
  40     if (cpu) {
  41         return cpu->parent_obj.cpu_index;
  42     }
  43
  44     return -1;
  45 }
  46
  47 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
  48 {
  49     CPUState *cs = CPU(cpu);
  50     CPUPPCState *env = &cpu->env;
  51     ICPState *ss = &icp->ss[cs->cpu_index];
  52     XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
  53
  54     assert(cs->cpu_index < icp->nr_servers);
  55
  56     if (info->cpu_setup) {
  57         info->cpu_setup(icp, cpu);
  58     }
  59
  60     switch (PPC_INPUT(env)) {
  61     case PPC_FLAGS_INPUT_POWER7:
  62         ss->output = env->irq_inputs[POWER7_INPUT_INT];
  63         break;
  64
  65     case PPC_FLAGS_INPUT_970:
  66         ss->output = env->irq_inputs[PPC970_INPUT_INT];
  67         break;
  68
  69     default:
  70         error_report("XICS interrupt controller does not support this CPU "
  71                      "bus model");
  72         abort();
  73     }
  74 }
  75
  76 /*
  77  * XICS Common class - parent for emulated XICS and KVM-XICS
  78  */
  79 static void xics_common_reset(DeviceState *d)
  80 {
  81     XICSState *icp = XICS_COMMON(d);
  82     int i;
  83
  84     for (i = 0; i < icp->nr_servers; i++) {
  85         device_reset(DEVICE(&icp->ss[i]));
  86     }
  87
  88     device_reset(DEVICE(icp->ics));
  89 }
  90
  91 static void xics_prop_get_nr_irqs(Object *obj, Visitor *v,
  92                                   void *opaque, const char *name, Error **errp)
  93 {
  94     XICSState *icp = XICS_COMMON(obj);
  95     int64_t value = icp->nr_irqs;
  96
  97     visit_type_int(v, &value, name, errp);
  98 }
  99
 100 static void xics_prop_set_nr_irqs(Object *obj, Visitor *v,
 101                                   void *opaque, const char *name, Error **errp)
 102 {
 103     XICSState *icp = XICS_COMMON(obj);
 104     XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
 105     Error *error = NULL;
 106     int64_t value;
 107
 108     visit_type_int(v, &value, name, &error);
 109     if (error) {
 110         error_propagate(errp, error);
 111         return;
 112     }
 113     if (icp->nr_irqs) {
 114         error_setg(errp, "Number of interrupts is already set to %u",
 115                    icp->nr_irqs);
 116         return;
 117     }
 118
 119     assert(info->set_nr_irqs);
 120     assert(icp->ics);
 121     info->set_nr_irqs(icp, value, errp);
 122 }
 123
 124 static void xics_prop_get_nr_servers(Object *obj, Visitor *v,
 125                                      void *opaque, const char *name,
 126                                      Error **errp)
 127 {
 128     XICSState *icp = XICS_COMMON(obj);
 129     int64_t value = icp->nr_servers;
 130
 131     visit_type_int(v, &value, name, errp);
 132 }
 133
 134 static void xics_prop_set_nr_servers(Object *obj, Visitor *v,
 135                                      void *opaque, const char *name,
 136                                      Error **errp)
 137 {
 138     XICSState *icp = XICS_COMMON(obj);
 139     XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
 140     Error *error = NULL;
 141     int64_t value;
 142
 143     visit_type_int(v, &value, name, &error);
 144     if (error) {
 145         error_propagate(errp, error);
 146         return;
 147     }
 148     if (icp->nr_servers) {
 149         error_setg(errp, "Number of servers is already set to %u",
 150                    icp->nr_servers);
 151         return;
 152     }
 153
 154     assert(info->set_nr_servers);
 155     info->set_nr_servers(icp, value, errp);
 156 }
 157
 158 static void xics_common_initfn(Object *obj)
 159 {
 160     object_property_add(obj, "nr_irqs", "int",
 161                         xics_prop_get_nr_irqs, xics_prop_set_nr_irqs,
 162                         NULL, NULL, NULL);
 163     object_property_add(obj, "nr_servers", "int",
 164                         xics_prop_get_nr_servers, xics_prop_set_nr_servers,
 165                         NULL, NULL, NULL);
 166 }
 167
 168 static void xics_common_class_init(ObjectClass *oc, void *data)
 169 {
 170     DeviceClass *dc = DEVICE_CLASS(oc);
 171
 172     dc->reset = xics_common_reset;
 173 }
 174
 175 static const TypeInfo xics_common_info = {
 176     .name          = TYPE_XICS_COMMON,
 177     .parent        = TYPE_SYS_BUS_DEVICE,
 178     .instance_size = sizeof(XICSState),
 179     .class_size    = sizeof(XICSStateClass),
 180     .instance_init = xics_common_initfn,
 181     .class_init    = xics_common_class_init,
 182 };
 183
 184 /*
 185  * ICP: Presentation layer
 186  */
 187
 188 #define XISR_MASK  0x00ffffff
 189 #define CPPR_MASK  0xff000000
 190
 191 #define XISR(ss)   (((ss)->xirr) & XISR_MASK)
 192 #define CPPR(ss)   (((ss)->xirr) >> 24)
 193
 194 static void ics_reject(ICSState *ics, int nr);
 195 static void ics_resend(ICSState *ics);
 196 static void ics_eoi(ICSState *ics, int nr);
 197
 198 static void icp_check_ipi(XICSState *icp, int server)
 199 {
 200     ICPState *ss = icp->ss + server;
 201
 202     if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
 203         return;
 204     }
 205
 206     trace_xics_icp_check_ipi(server, ss->mfrr);
 207
 208     if (XISR(ss)) {
 209         ics_reject(icp->ics, XISR(ss));
 210     }
 211
 212     ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
 213     ss->pending_priority = ss->mfrr;
 214     qemu_irq_raise(ss->output);
 215 }
 216
 217 static void icp_resend(XICSState *icp, int server)
 218 {
 219     ICPState *ss = icp->ss + server;
 220
 221     if (ss->mfrr < CPPR(ss)) {
 222         icp_check_ipi(icp, server);
 223     }
 224     ics_resend(icp->ics);
 225 }
 226
 227 static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
 228 {
 229     ICPState *ss = icp->ss + server;
 230     uint8_t old_cppr;
 231     uint32_t old_xisr;
 232
 233     old_cppr = CPPR(ss);
 234     ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);
 235
 236     if (cppr < old_cppr) {
 237         if (XISR(ss) && (cppr <= ss->pending_priority)) {
 238             old_xisr = XISR(ss);
 239             ss->xirr &= ~XISR_MASK; /* Clear XISR */
 240             ss->pending_priority = 0xff;
 241             qemu_irq_lower(ss->output);
 242             ics_reject(icp->ics, old_xisr);
 243         }
 244     } else {
 245         if (!XISR(ss)) {
 246             icp_resend(icp, server);
 247         }
 248     }
 249 }
 250
 251 static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
 252 {
 253     ICPState *ss = icp->ss + server;
 254
 255     ss->mfrr = mfrr;
 256     if (mfrr < CPPR(ss)) {
 257         icp_check_ipi(icp, server);
 258     }
 259 }
 260
 261 static uint32_t icp_accept(ICPState *ss)
 262 {
 263     uint32_t xirr = ss->xirr;
 264
 265     qemu_irq_lower(ss->output);
 266     ss->xirr = ss->pending_priority << 24;
 267     ss->pending_priority = 0xff;
 268
 269     trace_xics_icp_accept(xirr, ss->xirr);
 270
 271     return xirr;
 272 }
 273
 274 static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
 275 {
 276     ICPState *ss = icp->ss + server;
 277
 278     /* Send EOI -> ICS */
 279     ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 280     trace_xics_icp_eoi(server, xirr, ss->xirr);
 281     ics_eoi(icp->ics, xirr & XISR_MASK);
 282     if (!XISR(ss)) {
 283         icp_resend(icp, server);
 284     }
 285 }
 286
 287 static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)
 288 {
 289     ICPState *ss = icp->ss + server;
 290
 291     trace_xics_icp_irq(server, nr, priority);
 292
 293     if ((priority >= CPPR(ss))
 294         || (XISR(ss) && (ss->pending_priority <= priority))) {
 295         ics_reject(icp->ics, nr);
 296     } else {
 297         if (XISR(ss)) {
 298             ics_reject(icp->ics, XISR(ss));
 299         }
 300         ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 301         ss->pending_priority = priority;
 302         trace_xics_icp_raise(ss->xirr, ss->pending_priority);
 303         qemu_irq_raise(ss->output);
 304     }
 305 }
 306
 307 static void icp_dispatch_pre_save(void *opaque)
 308 {
 309     ICPState *ss = opaque;
 310     ICPStateClass *info = ICP_GET_CLASS(ss);
 311
 312     if (info->pre_save) {
 313         info->pre_save(ss);
 314     }
 315 }
 316
 317 static int icp_dispatch_post_load(void *opaque, int version_id)
 318 {
 319     ICPState *ss = opaque;
 320     ICPStateClass *info = ICP_GET_CLASS(ss);
 321
 322     if (info->post_load) {
 323         return info->post_load(ss, version_id);
 324     }
 325
 326     return 0;
 327 }
 328
 329 static const VMStateDescription vmstate_icp_server = {
 330     .name = "icp/server",
 331     .version_id = 1,
 332     .minimum_version_id = 1,
 333     .pre_save = icp_dispatch_pre_save,
 334     .post_load = icp_dispatch_post_load,
 335     .fields = (VMStateField[]) {
 336         /* Sanity check */
 337         VMSTATE_UINT32(xirr, ICPState),
 338         VMSTATE_UINT8(pending_priority, ICPState),
 339         VMSTATE_UINT8(mfrr, ICPState),
 340         VMSTATE_END_OF_LIST()
 341     },
 342 };
 343
 344 static void icp_reset(DeviceState *dev)
 345 {
 346     ICPState *icp = ICP(dev);
 347
 348     icp->xirr = 0;
 349     icp->pending_priority = 0xff;
 350     icp->mfrr = 0xff;
 351
 352     /* Make all outputs are deasserted */
 353     qemu_set_irq(icp->output, 0);
 354 }
 355
 356 static void icp_class_init(ObjectClass *klass, void *data)
 357 {
 358     DeviceClass *dc = DEVICE_CLASS(klass);
 359
 360     dc->reset = icp_reset;
 361     dc->vmsd = &vmstate_icp_server;
 362 }
 363
 364 static const TypeInfo icp_info = {
 365     .name = TYPE_ICP,
 366     .parent = TYPE_DEVICE,
 367     .instance_size = sizeof(ICPState),
 368     .class_init = icp_class_init,
 369     .class_size = sizeof(ICPStateClass),
 370 };
 371
 372 /*
 373  * ICS: Source layer
 374  */
 375 static int ics_valid_irq(ICSState *ics, uint32_t nr)
 376 {
 377     return (nr >= ics->offset)
 378         && (nr < (ics->offset + ics->nr_irqs));
 379 }
 380
 381 static void resend_msi(ICSState *ics, int srcno)
 382 {
 383     ICSIRQState *irq = ics->irqs + srcno;
 384
 385     /* FIXME: filter by server#? */
 386     if (irq->status & XICS_STATUS_REJECTED) {
 387         irq->status &= ~XICS_STATUS_REJECTED;
 388         if (irq->priority != 0xff) {
 389             icp_irq(ics->icp, irq->server, srcno + ics->offset,
 390                     irq->priority);
 391         }
 392     }
 393 }
 394
 395 static void resend_lsi(ICSState *ics, int srcno)
 396 {
 397     ICSIRQState *irq = ics->irqs + srcno;
 398
 399     if ((irq->priority != 0xff)
 400         && (irq->status & XICS_STATUS_ASSERTED)
 401         && !(irq->status & XICS_STATUS_SENT)) {
 402         irq->status |= XICS_STATUS_SENT;
 403         icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
 404     }
 405 }
 406
 407 static void set_irq_msi(ICSState *ics, int srcno, int val)
 408 {
 409     ICSIRQState *irq = ics->irqs + srcno;
 410
 411     trace_xics_set_irq_msi(srcno, srcno + ics->offset);
 412
 413     if (val) {
 414         if (irq->priority == 0xff) {
 415             irq->status |= XICS_STATUS_MASKED_PENDING;
 416             trace_xics_masked_pending();
 417         } else  {
 418             icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
 419         }
 420     }
 421 }
 422
 423 static void set_irq_lsi(ICSState *ics, int srcno, int val)
 424 {
 425     ICSIRQState *irq = ics->irqs + srcno;
 426
 427     trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
 428     if (val) {
 429         irq->status |= XICS_STATUS_ASSERTED;
 430     } else {
 431         irq->status &= ~XICS_STATUS_ASSERTED;
 432     }
 433     resend_lsi(ics, srcno);
 434 }
 435
 436 static void ics_set_irq(void *opaque, int srcno, int val)
 437 {
 438     ICSState *ics = (ICSState *)opaque;
 439
 440     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 441         set_irq_lsi(ics, srcno, val);
 442     } else {
 443         set_irq_msi(ics, srcno, val);
 444     }
 445 }
 446
 447 static void write_xive_msi(ICSState *ics, int srcno)
 448 {
 449     ICSIRQState *irq = ics->irqs + srcno;
 450
 451     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 452         || (irq->priority == 0xff)) {
 453         return;
 454     }
 455
 456     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 457     icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
 458 }
 459
 460 static void write_xive_lsi(ICSState *ics, int srcno)
 461 {
 462     resend_lsi(ics, srcno);
 463 }
 464
 465 static void ics_write_xive(ICSState *ics, int nr, int server,
 466                            uint8_t priority, uint8_t saved_priority)
 467 {
 468     int srcno = nr - ics->offset;
 469     ICSIRQState *irq = ics->irqs + srcno;
 470
 471     irq->server = server;
 472     irq->priority = priority;
 473     irq->saved_priority = saved_priority;
 474
 475     trace_xics_ics_write_xive(nr, srcno, server, priority);
 476
 477     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 478         write_xive_lsi(ics, srcno);
 479     } else {
 480         write_xive_msi(ics, srcno);
 481     }
 482 }
 483
 484 static void ics_reject(ICSState *ics, int nr)
 485 {
 486     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 487
 488     trace_xics_ics_reject(nr, nr - ics->offset);
 489     irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
 490     irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
 491 }
 492
 493 static void ics_resend(ICSState *ics)
 494 {
 495     int i;
 496
 497     for (i = 0; i < ics->nr_irqs; i++) {
 498         /* FIXME: filter by server#? */
 499         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 500             resend_lsi(ics, i);
 501         } else {
 502             resend_msi(ics, i);
 503         }
 504     }
 505 }
 506
 507 static void ics_eoi(ICSState *ics, int nr)
 508 {
 509     int srcno = nr - ics->offset;
 510     ICSIRQState *irq = ics->irqs + srcno;
 511
 512     trace_xics_ics_eoi(nr);
 513
 514     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 515         irq->status &= ~XICS_STATUS_SENT;
 516     }
 517 }
 518
 519 static void ics_reset(DeviceState *dev)
 520 {
 521     ICSState *ics = ICS(dev);
 522     int i;
 523     uint8_t flags[ics->nr_irqs];
 524
 525     for (i = 0; i < ics->nr_irqs; i++) {
 526         flags[i] = ics->irqs[i].flags;
 527     }
 528
 529     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 530
 531     for (i = 0; i < ics->nr_irqs; i++) {
 532         ics->irqs[i].priority = 0xff;
 533         ics->irqs[i].saved_priority = 0xff;
 534         ics->irqs[i].flags = flags[i];
 535     }
 536 }
 537
 538 static int ics_post_load(ICSState *ics, int version_id)
 539 {
 540     int i;
 541
 542     for (i = 0; i < ics->icp->nr_servers; i++) {
 543         icp_resend(ics->icp, i);
 544     }
 545
 546     return 0;
 547 }
 548
 549 static void ics_dispatch_pre_save(void *opaque)
 550 {
 551     ICSState *ics = opaque;
 552     ICSStateClass *info = ICS_GET_CLASS(ics);
 553
 554     if (info->pre_save) {
 555         info->pre_save(ics);
 556     }
 557 }
 558
 559 static int ics_dispatch_post_load(void *opaque, int version_id)
 560 {
 561     ICSState *ics = opaque;
 562     ICSStateClass *info = ICS_GET_CLASS(ics);
 563
 564     if (info->post_load) {
 565         return info->post_load(ics, version_id);
 566     }
 567
 568     return 0;
 569 }
 570
 571 static const VMStateDescription vmstate_ics_irq = {
 572     .name = "ics/irq",
 573     .version_id = 2,
 574     .minimum_version_id = 1,
 575     .fields = (VMStateField[]) {
 576         VMSTATE_UINT32(server, ICSIRQState),
 577         VMSTATE_UINT8(priority, ICSIRQState),
 578         VMSTATE_UINT8(saved_priority, ICSIRQState),
 579         VMSTATE_UINT8(status, ICSIRQState),
 580         VMSTATE_UINT8(flags, ICSIRQState),
 581         VMSTATE_END_OF_LIST()
 582     },
 583 };
 584
 585 static const VMStateDescription vmstate_ics = {
 586     .name = "ics",
 587     .version_id = 1,
 588     .minimum_version_id = 1,
 589     .pre_save = ics_dispatch_pre_save,
 590     .post_load = ics_dispatch_post_load,
 591     .fields = (VMStateField[]) {
 592         /* Sanity check */
 593         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
 594
 595         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 596                                              vmstate_ics_irq, ICSIRQState),
 597         VMSTATE_END_OF_LIST()
 598     },
 599 };
 600
 601 static void ics_initfn(Object *obj)
 602 {
 603     ICSState *ics = ICS(obj);
 604
 605     ics->offset = XICS_IRQ_BASE;
 606 }
 607
 608 static void ics_realize(DeviceState *dev, Error **errp)
 609 {
 610     ICSState *ics = ICS(dev);
 611
 612     if (!ics->nr_irqs) {
 613         error_setg(errp, "Number of interrupts needs to be greater 0");
 614         return;
 615     }
 616     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 617     ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
 618 }
 619
 620 static void ics_class_init(ObjectClass *klass, void *data)
 621 {
 622     DeviceClass *dc = DEVICE_CLASS(klass);
 623     ICSStateClass *isc = ICS_CLASS(klass);
 624
 625     dc->realize = ics_realize;
 626     dc->vmsd = &vmstate_ics;
 627     dc->reset = ics_reset;
 628     isc->post_load = ics_post_load;
 629 }
 630
 631 static const TypeInfo ics_info = {
 632     .name = TYPE_ICS,
 633     .parent = TYPE_DEVICE,
 634     .instance_size = sizeof(ICSState),
 635     .class_init = ics_class_init,
 636     .class_size = sizeof(ICSStateClass),
 637     .instance_init = ics_initfn,
 638 };
 639
 640 /*
 641  * Exported functions
 642  */
 643 static int xics_find_source(XICSState *icp, int irq)
 644 {
 645     int sources = 1;
 646     int src;
 647
 648     /* FIXME: implement multiple sources */
 649     for (src = 0; src < sources; ++src) {
 650         ICSState *ics = &icp->ics[src];
 651         if (ics_valid_irq(ics, irq)) {
 652             return src;
 653         }
 654     }
 655
 656     return -1;
 657 }
 658
 659 qemu_irq xics_get_qirq(XICSState *icp, int irq)
 660 {
 661     int src = xics_find_source(icp, irq);
 662
 663     if (src >= 0) {
 664         ICSState *ics = &icp->ics[src];
 665         return ics->qirqs[irq - ics->offset];
 666     }
 667
 668     return NULL;
 669 }
 670
 671 static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 672 {
 673     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 674
 675     ics->irqs[srcno].flags |=
 676         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 677 }
 678
 679 void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
 680 {
 681     int src = xics_find_source(icp, irq);
 682     ICSState *ics;
 683
 684     assert(src >= 0);
 685
 686     ics = &icp->ics[src];
 687     ics_set_irq_type(ics, irq - ics->offset, lsi);
 688 }
 689
 690 #define ICS_IRQ_FREE(ics, srcno)   \
 691     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
 692
 693 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
 694 {
 695     int first, i;
 696
 697     for (first = 0; first < ics->nr_irqs; first += alignnum) {
 698         if (num > (ics->nr_irqs - first)) {
 699             return -1;
 700         }
 701         for (i = first; i < first + num; ++i) {
 702             if (!ICS_IRQ_FREE(ics, i)) {
 703                 break;
 704             }
 705         }
 706         if (i == (first + num)) {
 707             return first;
 708         }
 709     }
 710
 711     return -1;
 712 }
 713
 714 int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi)
 715 {
 716     ICSState *ics = &icp->ics[src];
 717     int irq;
 718
 719     if (irq_hint) {
 720         assert(src == xics_find_source(icp, irq_hint));
 721         if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
 722             trace_xics_alloc_failed_hint(src, irq_hint);
 723             return -1;
 724         }
 725         irq = irq_hint;
 726     } else {
 727         irq = ics_find_free_block(ics, 1, 1);
 728         if (irq < 0) {
 729             trace_xics_alloc_failed_no_left(src);
 730             return -1;
 731         }
 732         irq += ics->offset;
 733     }
 734
 735     ics_set_irq_type(ics, irq - ics->offset, lsi);
 736     trace_xics_alloc(src, irq);
 737
 738     return irq;
 739 }
 740
 741 /*
 742  * Allocate block of consequtive IRQs, returns a number of the first.
 743  * If align==true, aligns the first IRQ number to num.
 744  */
 745 int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align)
 746 {
 747     int i, first = -1;
 748     ICSState *ics = &icp->ics[src];
 749
 750     assert(src == 0);
 751     /*
 752      * MSIMesage::data is used for storing VIRQ so
 753      * it has to be aligned to num to support multiple
 754      * MSI vectors. MSI-X is not affected by this.
 755      * The hint is used for the first IRQ, the rest should
 756      * be allocated continuously.
 757      */
 758     if (align) {
 759         assert((num == 1) || (num == 2) || (num == 4) ||
 760                (num == 8) || (num == 16) || (num == 32));
 761         first = ics_find_free_block(ics, num, num);
 762     } else {
 763         first = ics_find_free_block(ics, num, 1);
 764     }
 765
 766     if (first >= 0) {
 767         for (i = first; i < first + num; ++i) {
 768             ics_set_irq_type(ics, i, lsi);
 769         }
 770     }
 771     first += ics->offset;
 772
 773     trace_xics_alloc_block(src, first, num, lsi, align);
 774
 775     return first;
 776 }
 777
 778 static void ics_free(ICSState *ics, int srcno, int num)
 779 {
 780     int i;
 781
 782     for (i = srcno; i < srcno + num; ++i) {
 783         if (ICS_IRQ_FREE(ics, i)) {
 784             trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
 785         }
 786         memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
 787     }
 788 }
 789
 790 void xics_free(XICSState *icp, int irq, int num)
 791 {
 792     int src = xics_find_source(icp, irq);
 793
 794     if (src >= 0) {
 795         ICSState *ics = &icp->ics[src];
 796
 797         /* FIXME: implement multiple sources */
 798         assert(src == 0);
 799
 800         trace_xics_ics_free(ics - icp->ics, irq, num);
 801         ics_free(ics, irq - ics->offset, num);
 802     }
 803 }
 804
 805 /*
 806  * Guest interfaces
 807  */
 808
 809 static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 810                            target_ulong opcode, target_ulong *args)
 811 {
 812     CPUState *cs = CPU(cpu);
 813     target_ulong cppr = args[0];
 814
 815     icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
 816     return H_SUCCESS;
 817 }
 818
 819 static target_ulong h_ipi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 820                           target_ulong opcode, target_ulong *args)
 821 {
 822     target_ulong server = get_cpu_index_by_dt_id(args[0]);
 823     target_ulong mfrr = args[1];
 824
 825     if (server >= spapr->icp->nr_servers) {
 826         return H_PARAMETER;
 827     }
 828
 829     icp_set_mfrr(spapr->icp, server, mfrr);
 830     return H_SUCCESS;
 831 }
 832
 833 static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 834                            target_ulong opcode, target_ulong *args)
 835 {
 836     CPUState *cs = CPU(cpu);
 837     uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
 838
 839     args[0] = xirr;
 840     return H_SUCCESS;
 841 }
 842
 843 static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 844                              target_ulong opcode, target_ulong *args)
 845 {
 846     CPUState *cs = CPU(cpu);
 847     ICPState *ss = &spapr->icp->ss[cs->cpu_index];
 848     uint32_t xirr = icp_accept(ss);
 849
 850     args[0] = xirr;
 851     args[1] = cpu_get_real_ticks();
 852     return H_SUCCESS;
 853 }
 854
 855 static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 856                           target_ulong opcode, target_ulong *args)
 857 {
 858     CPUState *cs = CPU(cpu);
 859     target_ulong xirr = args[0];
 860
 861     icp_eoi(spapr->icp, cs->cpu_index, xirr);
 862     return H_SUCCESS;
 863 }
 864
 865 static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 866                             target_ulong opcode, target_ulong *args)
 867 {
 868     CPUState *cs = CPU(cpu);
 869     ICPState *ss = &spapr->icp->ss[cs->cpu_index];
 870
 871     args[0] = ss->xirr;
 872     args[1] = ss->mfrr;
 873
 874     return H_SUCCESS;
 875 }
 876
 877 static void rtas_set_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 878                           uint32_t token,
 879                           uint32_t nargs, target_ulong args,
 880                           uint32_t nret, target_ulong rets)
 881 {
 882     ICSState *ics = spapr->icp->ics;
 883     uint32_t nr, server, priority;
 884
 885     if ((nargs != 3) || (nret != 1)) {
 886         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 887         return;
 888     }
 889
 890     nr = rtas_ld(args, 0);
 891     server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
 892     priority = rtas_ld(args, 2);
 893
 894     if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
 895         || (priority > 0xff)) {
 896         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 897         return;
 898     }
 899
 900     ics_write_xive(ics, nr, server, priority, priority);
 901
 902     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 903 }
 904
 905 static void rtas_get_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 906                           uint32_t token,
 907                           uint32_t nargs, target_ulong args,
 908                           uint32_t nret, target_ulong rets)
 909 {
 910     ICSState *ics = spapr->icp->ics;
 911     uint32_t nr;
 912
 913     if ((nargs != 1) || (nret != 3)) {
 914         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 915         return;
 916     }
 917
 918     nr = rtas_ld(args, 0);
 919
 920     if (!ics_valid_irq(ics, nr)) {
 921         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 922         return;
 923     }
 924
 925     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 926     rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
 927     rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
 928 }
 929
 930 static void rtas_int_off(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 931                          uint32_t token,
 932                          uint32_t nargs, target_ulong args,
 933                          uint32_t nret, target_ulong rets)
 934 {
 935     ICSState *ics = spapr->icp->ics;
 936     uint32_t nr;
 937
 938     if ((nargs != 1) || (nret != 1)) {
 939         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 940         return;
 941     }
 942
 943     nr = rtas_ld(args, 0);
 944
 945     if (!ics_valid_irq(ics, nr)) {
 946         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 947         return;
 948     }
 949
 950     ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
 951                    ics->irqs[nr - ics->offset].priority);
 952
 953     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 954 }
 955
 956 static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 957                         uint32_t token,
 958                         uint32_t nargs, target_ulong args,
 959                         uint32_t nret, target_ulong rets)
 960 {
 961     ICSState *ics = spapr->icp->ics;
 962     uint32_t nr;
 963
 964     if ((nargs != 1) || (nret != 1)) {
 965         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 966         return;
 967     }
 968
 969     nr = rtas_ld(args, 0);
 970
 971     if (!ics_valid_irq(ics, nr)) {
 972         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 973         return;
 974     }
 975
 976     ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
 977                    ics->irqs[nr - ics->offset].saved_priority,
 978                    ics->irqs[nr - ics->offset].saved_priority);
 979
 980     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 981 }
 982
 983 /*
 984  * XICS
 985  */
 986
 987 static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
 988 {
 989     icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
 990 }
 991
 992 static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,
 993                                 Error **errp)
 994 {
 995     int i;
 996
 997     icp->nr_servers = nr_servers;
 998
 999     icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
1000     for (i = 0; i < icp->nr_servers; i++) {
1001         char buffer[32];
1002         object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
1003         snprintf(buffer, sizeof(buffer), "icp[%d]", i);
1004         object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
1005                                   errp);
1006     }
1007 }
1008
1009 static void xics_realize(DeviceState *dev, Error **errp)
1010 {
1011     XICSState *icp = XICS(dev);
1012     Error *error = NULL;
1013     int i;
1014
1015     if (!icp->nr_servers) {
1016         error_setg(errp, "Number of servers needs to be greater 0");
1017         return;
1018     }
1019
1020     /* Registration of global state belongs into realize */
1021     spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
1022     spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
1023     spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
1024     spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
1025
1026     spapr_register_hypercall(H_CPPR, h_cppr);
1027     spapr_register_hypercall(H_IPI, h_ipi);
1028     spapr_register_hypercall(H_XIRR, h_xirr);
1029     spapr_register_hypercall(H_XIRR_X, h_xirr_x);
1030     spapr_register_hypercall(H_EOI, h_eoi);
1031     spapr_register_hypercall(H_IPOLL, h_ipoll);
1032
1033     object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
1034     if (error) {
1035         error_propagate(errp, error);
1036         return;
1037     }
1038
1039     for (i = 0; i < icp->nr_servers; i++) {
1040         object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
1041         if (error) {
1042             error_propagate(errp, error);
1043             return;
1044         }
1045     }
1046 }
1047
1048 static void xics_initfn(Object *obj)
1049 {
1050     XICSState *xics = XICS(obj);
1051
1052     xics->ics = ICS(object_new(TYPE_ICS));
1053     object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
1054     xics->ics->icp = xics;
1055 }
1056
1057 static void xics_class_init(ObjectClass *oc, void *data)
1058 {
1059     DeviceClass *dc = DEVICE_CLASS(oc);
1060     XICSStateClass *xsc = XICS_CLASS(oc);
1061
1062     dc->realize = xics_realize;
1063     xsc->set_nr_irqs = xics_set_nr_irqs;
1064     xsc->set_nr_servers = xics_set_nr_servers;
1065 }
1066
1067 static const TypeInfo xics_info = {
1068     .name          = TYPE_XICS,
1069     .parent        = TYPE_XICS_COMMON,
1070     .instance_size = sizeof(XICSState),
1071     .class_size = sizeof(XICSStateClass),
1072     .class_init    = xics_class_init,
1073     .instance_init = xics_initfn,
1074 };
1075
1076 static void xics_register_types(void)
1077 {
1078     type_register_static(&xics_common_info);
1079     type_register_static(&xics_info);
1080     type_register_static(&ics_info);
1081     type_register_static(&icp_info);
1082 }
1083
1084 type_init(xics_register_types)